1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_utils.c
4 * @author MCD Application Team
5 * @brief UTILS LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 /* Includes ------------------------------------------------------------------*/
19 #include "stm32h5xx_ll_utils.h"
20 #include "stm32h5xx_ll_rcc.h"
21 #include "stm32h5xx_ll_system.h"
22 #include "stm32h5xx_ll_pwr.h"
23 #ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25 #else
26 #define assert_param(expr) ((void)0U)
27 #endif /* USE_FULL_ASSERT */
28
29 /** @addtogroup STM32H5xx_LL_Driver
30 * @{
31 */
32
33 /** @addtogroup UTILS_LL
34 * @{
35 */
36
37 /* Private types -------------------------------------------------------------*/
38 /* Private variables ---------------------------------------------------------*/
39 /* Private constants ---------------------------------------------------------*/
40 /** @addtogroup UTILS_LL_Private_Constants
41 * @{
42 */
43 #define UTILS_MAX_FREQUENCY_SCALE0 240000000U /*!< Maximum frequency for system clock at power scale0, in Hz */
44 #define UTILS_MAX_FREQUENCY_SCALE1 180000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
45 #define UTILS_MAX_FREQUENCY_SCALE2 130000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
46 #define UTILS_MAX_FREQUENCY_SCALE3 80000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
47
48 /* Defines used for PLL range */
49 #define UTILS_PLLVCO_INPUT_MIN1 1000000U /*!< Frequency min for the low range PLLVCO input, in Hz */
50 #define UTILS_PLLVCO_INPUT_MAX1 2000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */
51 #define UTILS_PLLVCO_INPUT_MIN2 2000000U /*!< Frequency min for the low range PLLVCO input, in Hz */
52 #define UTILS_PLLVCO_INPUT_MAX2 4000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */
53 #define UTILS_PLLVCO_INPUT_MIN3 4000000U /*!< Frequency min for the low range PLLVCO input, in Hz */
54 #define UTILS_PLLVCO_INPUT_MAX3 8000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */
55 #define UTILS_PLLVCO_INPUT_MIN4 8000000U /*!< Frequency min for the low range PLLVCO input, in Hz */
56 #define UTILS_PLLVCO_INPUT_MAX4 16000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */
57
58 #define UTILS_PLLVCO_MEDIUM_OUTPUT_MIN 150000000U /*!< Frequency min for the medium range PLLVCO output, in Hz */
59 #define UTILS_PLLVCO_WIDE_OUTPUT_MIN 192000000U /*!< Frequency min for the wide range PLLVCO output, in Hz */
60 #define UTILS_PLLVCO_MEDIUM_OUTPUT_MAX 420000000U /*!< Frequency max for the medium range PLLVCO output, in Hz */
61 #define UTILS_PLLVCO_WIDE_OUTPUT_MAX 836000000U /*!< Frequency max for the wide range PLLVCO output, in Hz */
62 /* Defines used for HSE range */
63 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
64 #define UTILS_HSE_FREQUENCY_MAX 50000000U /*!< Frequency max for HSE frequency, in Hz */
65
66 /* Defines used for FLASH latency according to HCLK Frequency */
67 #define UTILS_SCALE0_LATENCY0_FREQ 38000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 0 */
68 #define UTILS_SCALE0_LATENCY1_FREQ 76000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 0 */
69 #define UTILS_SCALE0_LATENCY2_FREQ 114000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 0 */
70 #define UTILS_SCALE0_LATENCY3_FREQ 152000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 0 */
71 #define UTILS_SCALE0_LATENCY4_FREQ 190000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 0 */
72 #define UTILS_SCALE0_LATENCY5_FREQ 240000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 0 */
73
74 #define UTILS_SCALE1_LATENCY0_FREQ 32000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */
75 #define UTILS_SCALE1_LATENCY1_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
76 #define UTILS_SCALE1_LATENCY2_FREQ 96000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
77 #define UTILS_SCALE1_LATENCY3_FREQ 128000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
78 #define UTILS_SCALE1_LATENCY4_FREQ 160000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
79 #define UTILS_SCALE1_LATENCY5_FREQ 180000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
80
81 #define UTILS_SCALE2_LATENCY0_FREQ 26000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 2 */
82 #define UTILS_SCALE2_LATENCY1_FREQ 50000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
83 #define UTILS_SCALE2_LATENCY2_FREQ 80000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
84 #define UTILS_SCALE2_LATENCY3_FREQ 106000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
85 #define UTILS_SCALE2_LATENCY4_FREQ 130000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
86
87 #define UTILS_SCALE3_LATENCY0_FREQ 16000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 3 */
88 #define UTILS_SCALE3_LATENCY1_FREQ 32000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
89 #define UTILS_SCALE3_LATENCY2_FREQ 50000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
90 #define UTILS_SCALE3_LATENCY3_FREQ 65000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
91 #define UTILS_SCALE3_LATENCY4_FREQ 80000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */
92 /**
93 * @}
94 */
95
96 /* Private macros ------------------------------------------------------------*/
97 /** @addtogroup UTILS_LL_Private_Macros
98 * @{
99 */
100 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
101 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
102 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
103 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
104 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
105 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
106 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
107 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
108 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
109
110 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
111 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
112 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
113 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
114 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
115
116 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
117 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
118 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
119 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
120 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
121
122 #define IS_LL_UTILS_APB3_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB3_DIV_1) \
123 || ((__VALUE__) == LL_RCC_APB3_DIV_2) \
124 || ((__VALUE__) == LL_RCC_APB3_DIV_4) \
125 || ((__VALUE__) == LL_RCC_APB3_DIV_8) \
126 || ((__VALUE__) == LL_RCC_APB3_DIV_16))
127
128 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U))
129
130 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((4U <= (__VALUE__)) && ((__VALUE__) <= 512U))
131
132 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) ((2U <= (__VALUE__)) && ((__VALUE__) <= 128U))
133
134 #define IS_LL_UTILS_FRACN_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU)
135
136 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__, __RANGE__) ( \
137 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_1_2) && \
138 (UTILS_PLLVCO_INPUT_MIN1 <= (__VALUE__)) && \
139 ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX1)) || \
140 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_2_4) && \
141 (UTILS_PLLVCO_INPUT_MIN2 <= (__VALUE__)) && \
142 ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX2)) || \
143 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_4_8) && \
144 (UTILS_PLLVCO_INPUT_MIN3 <= (__VALUE__)) && \
145 ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX3)) || \
146 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_8_16) && \
147 (UTILS_PLLVCO_INPUT_MIN4 <= (__VALUE__)) && \
148 ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX4)))
149
150 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__, __RANGE__) ( \
151 (((__RANGE__) == LL_RCC_PLLVCORANGE_MEDIUM) && \
152 (UTILS_PLLVCO_MEDIUM_OUTPUT_MIN <= (__VALUE__)) && \
153 ((__VALUE__) <= UTILS_PLLVCO_MEDIUM_OUTPUT_MAX)) || \
154 (((__RANGE__) == LL_RCC_PLLVCORANGE_WIDE) && \
155 (UTILS_PLLVCO_WIDE_OUTPUT_MIN <= (__VALUE__)) && \
156 ((__VALUE__) <= UTILS_PLLVCO_WIDE_OUTPUT_MAX)))
157
158 #define IS_LL_UTILS_CHECK_VCO_RANGES(__RANGEIN__, __RANGEOUT__) ( \
159 (((__RANGEIN__) == LL_RCC_PLLINPUTRANGE_1_2) && \
160 ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_MEDIUM)) || \
161 (((__RANGEIN__) != LL_RCC_PLLINPUTRANGE_1_2) && \
162 ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_WIDE)))
163
164 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0) ? \
165 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE0) : \
166 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? \
167 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
168 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? \
169 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
170 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
171
172 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
173 || ((__STATE__) == LL_UTILS_HSEBYPASS_DIGITAL_ON) \
174 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
175
176 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) &&\
177 ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
178 /**
179 * @}
180 */
181 /* Private function prototypes -----------------------------------------------*/
182 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
183 * @{
184 */
185 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
186 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
187 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency,
188 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
189 static ErrorStatus UTILS_PLL_IsBusy(void);
190 /**
191 * @}
192 */
193
194 /* Exported functions --------------------------------------------------------*/
195 /** @addtogroup UTILS_LL_Exported_Functions
196 * @{
197 */
198
199 /** @addtogroup UTILS_LL_EF_DELAY
200 * @{
201 */
202
203 /**
204 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
205 * @note When a RTOS is used, it is recommended to avoid changing the Systick
206 * configuration by calling this function, for a delay use rather osDelay RTOS service.
207 * @param HCLKFrequency HCLK frequency in Hz
208 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
209 * @retval None
210 */
LL_Init1msTick(uint32_t HCLKFrequency)211 void LL_Init1msTick(uint32_t HCLKFrequency)
212 {
213 /* Use frequency provided in argument */
214 LL_InitTick(HCLKFrequency, 1000U);
215 }
216
217 /**
218 * @brief This function provides accurate delay (in milliseconds) based
219 * on SysTick counter flag
220 * @note When a RTOS is used, it is recommended to avoid using blocking delay
221 * and use rather osDelay service.
222 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
223 * will configure Systick to 1ms
224 * @param Delay specifies the delay time length, in milliseconds.
225 * @retval None
226 */
227
LL_mDelay(uint32_t Delay)228 void LL_mDelay(uint32_t Delay)
229 {
230 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
231 uint32_t tmpDelay = Delay;
232
233 /* Add this code to indicate that local variable is not used */
234 ((void)tmp);
235
236 /* Add a period to guaranty minimum wait */
237 if (tmpDelay < LL_MAX_DELAY)
238 {
239 tmpDelay++;
240 }
241
242 while (tmpDelay != 0U)
243 {
244 if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
245 {
246 tmpDelay--;
247 }
248 }
249 }
250
251 /**
252 * @}
253 */
254
255 /** @addtogroup UTILS_EF_SYSTEM
256 * @brief System Configuration functions
257 *
258 @verbatim
259 ===============================================================================
260 ##### System Configuration functions #####
261 ===============================================================================
262 [..]
263 System, AHB and APB buses clocks configuration
264
265 (+) The maximum frequency of the SYSCLK is 240 MHz and HCLK is 240 MHz.
266 (+) The maximum frequency of the PCLK1, PCLK2 and PCLK3 is 240 MHz.
267 @endverbatim
268 @internal
269 Depending on the device voltage range, the maximum frequency should be
270 adapted accordingly:
271
272 (++) Table 1. HCLK clock frequency for STM32H5 devices
273 (++) +-----------------------------------------------------------------------------------------------+
274 (++) | Latency | HCLK clock frequency (MHz) |
275 (++) | |-----------------------------------------------------------------------------|
276 (++) | | voltage range 0 | voltage range 1 | voltage range 2 | voltage range 3 |
277 (++) | | 1.26 - 1.35V | 1.15 - 1.26V | 1.05 - 1.15V | 0,95 - 1,05V |
278 (++) |-----------------|-------------------|------------------|------------------|-------------------|
279 (++) |0WS(1 CPU cycles)| 0 < HCLK <= 38 | 0 < HCLK <= 32 | 0 < HCLK <= 26 | 0 < HCLK <= 16 |
280 (++) |-----------------|-------------------|------------------|------------------|-------------------|
281 (++) |1WS(2 CPU cycles)| 38 < HCLK <= 76 | 32 < HCLK <= 64 | 26 < HCLK <= 50 | 16 < HCLK <= 32 |
282 (++) |-----------------|-------------------|------------------|------------------|-------------------|
283 (++) |2WS(3 CPU cycles)| 76 < HCLK <= 114 | 64 < HCLK <= 96 | 50 < HCLK <= 80 | 32 < HCLK <= 50 |
284 (++) |-----------------|-------------------|------------------|------------------|-------------------|
285 (++) |3WS(4 CPU cycles)| 114 < HCLK <= 152 | 96 < HCLK <= 128 | 80 < HCLK <= 106 | 50 < HCLK <= 65 |
286 (++) |-----------------|-------------------|------------------|------------------|-------------------|
287 (++) |4WS(5 CPU cycles)| 152 < HCLK <= 190| 128 < HCLK <= 160| 106 < HCLK <= 130| 65 < HCLK <= 80 |
288 (++) |-----------------|-------------------|------------------|------------------|-------------------|
289 (++) |5WS(6 CPU cycles)| 190 < HCLK <= 240| 160 < HCLK <= 180| NA | NA |
290 (++) +-----------------+-------------------+------------------+------------------+-------------------+
291
292 @endinternal
293 * @{
294 */
295
296 /**
297 * @brief This function sets directly SystemCoreClock CMSIS variable.
298 * @note Variable can be calculated also through SystemCoreClockUpdate function.
299 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
300 * @retval None
301 */
LL_SetSystemCoreClock(uint32_t HCLKFrequency)302 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
303 {
304 /* HCLK clock frequency */
305 SystemCoreClock = HCLKFrequency;
306 }
307
308 /**
309 * @brief This function configures system clock at maximum frequency with CSI as clock source of the PLL1
310 * @note The application needs to ensure that all PLLs is disabled.
311 * @note Function is based on the following formula:
312 * - PLL1 output frequency = (((CSI frequency / PLL1M) * PLL1N) / PLL1P)
313 * - PLL1M: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLL1VCO_input = CSI frequency / PLL1M)
314 * - PLL1N: ensure that the VCO output frequency is between 192 and 836 MHz
315 * (PLL1VCO_output = PLL1VCO_input * PLL1N)
316 * - PLL1P: ensure that max frequency at 240 MHz is reached (PLL1VCO_output / PLL1P)
317 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
318 * the configuration information for the PLL.
319 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
320 * the configuration information for the BUS prescalers.
321 * @retval An ErrorStatus enumeration value:
322 * - SUCCESS: Max frequency configuration done
323 * - ERROR: Max frequency configuration not done
324 */
LL_PLL_ConfigSystemClock_CSI(LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)325 ErrorStatus LL_PLL_ConfigSystemClock_CSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
326 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
327 {
328 ErrorStatus status = SUCCESS;
329 #ifdef USE_FULL_ASSERT
330 uint32_t vcoinput_freq;
331 uint32_t vcooutput_freq;
332 #endif /* USE_FULL_ASSERT */
333 uint32_t pllfreq;
334
335 /* Check the parameters */
336 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
337 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
338 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
339 assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
340
341 /* Check VCO Input frequency */
342 #ifdef USE_FULL_ASSERT
343 vcoinput_freq = CSI_VALUE / UTILS_PLLInitStruct->PLLM;
344 #endif /* USE_FULL_ASSERT */
345 assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input));
346
347 /* Check VCO Input ranges */
348 assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output));
349
350 /* Check VCO Output frequency */
351 #ifdef USE_FULL_ASSERT
352 vcooutput_freq = LL_RCC_CalcPLLClockFreq(CSI_VALUE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
353 UTILS_PLLInitStruct->FRACN, 1U);
354 /* PLL1P Set to 1 to check the assert param (VCO_output)*/
355 #endif /* USE_FULL_ASSERT */
356 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
357
358 /* Check if the main PLL is enabled */
359 if (UTILS_PLL_IsBusy() == SUCCESS)
360 {
361 /* Calculate the new PLL output frequency */
362 pllfreq = UTILS_GetPLLOutputFrequency(CSI_VALUE, UTILS_PLLInitStruct);
363
364 /* Enable CSI if not enabled */
365 if (LL_RCC_CSI_IsReady() != 1U)
366 {
367 LL_RCC_CSI_Enable();
368 while (LL_RCC_CSI_IsReady() != 1U)
369 {
370 /* Wait for CSI ready */
371 }
372 }
373
374 /* Configure PLL */
375 LL_RCC_PLL1_ConfigDomain_SYS(LL_RCC_PLL1SOURCE_CSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
376 UTILS_PLLInitStruct->PLLP);
377 LL_RCC_PLL1FRACN_Disable();
378 LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN);
379 LL_RCC_PLL1FRACN_Enable();
380 LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input);
381 LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output);
382
383 /* Enable PLL and switch system clock to PLL */
384 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
385 }
386 else
387 {
388 /* Current PLL configuration cannot be modified */
389 status = ERROR;
390 }
391
392 return status;
393 }
394
395
396 /**
397 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL1
398 * @note The application need to ensure that all PLLs are disabled.
399 * @note Function is based on the following formula:
400 * - PLL1 output frequency = (((HSI frequency / PLL1M) * PLL1N) / PLL1P)
401 * - PLL1M: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLL1VCO_input = HSI frequency / PLL1M)
402 * - PLL1N: ensure that the VCO output frequency is between 150 and 836 MHz
403 * (PLL1VCO_output = PLL1VCO_input * PLL1N)
404 * - PLL1P: ensure that max frequency at 240 MHz is reach (PLL1VCO_output / PLL1P)
405 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
406 * the configuration information for the PLL1.
407 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
408 * the configuration information for the BUS prescalers.
409 * @retval An ErrorStatus enumeration value:
410 * - SUCCESS: Max frequency configuration done
411 * - ERROR: Max frequency configuration not done
412 *
413 *
414 */
LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)415 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
416 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
417 {
418 ErrorStatus status = SUCCESS;
419 #ifdef USE_FULL_ASSERT
420 uint32_t vcoinput_freq;
421 uint32_t vcooutput_freq;
422 #endif /* USE_FULL_ASSERT */
423 uint32_t pllfreq;
424 uint32_t hsi_clk;
425
426 /* Check the parameters */
427 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
428 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
429 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
430 assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
431
432 hsi_clk = (HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos));
433
434 /* Check VCO Input frequency */
435 #ifdef USE_FULL_ASSERT
436 vcoinput_freq = hsi_clk / UTILS_PLLInitStruct->PLLM;
437 #endif /* USE_FULL_ASSERT */
438 assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input));
439
440 /* Check VCO Input ranges */
441 assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output));
442
443 /* Check VCO Output frequency */
444 #ifdef USE_FULL_ASSERT
445 vcooutput_freq = LL_RCC_CalcPLLClockFreq(hsi_clk, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
446 UTILS_PLLInitStruct->FRACN, 1UL);
447 /* PLL1P Set to 1 to check the assert param (VCO_output)*/
448 #endif /* USE_FULL_ASSERT */
449 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
450
451 /* Check if the main PLL is enabled */
452 if (UTILS_PLL_IsBusy() == SUCCESS)
453 {
454 /* Calculate the new PLL output frequency */
455 pllfreq = UTILS_GetPLLOutputFrequency(hsi_clk, UTILS_PLLInitStruct);
456
457 /* Enable HSI if not enabled */
458 if (LL_RCC_HSI_IsReady() != 1U)
459 {
460 LL_RCC_HSI_Enable();
461 while (LL_RCC_HSI_IsReady() != 1U)
462 {
463 /* Wait for HSI ready */
464 }
465 }
466
467 /* Configure PLL */
468 LL_RCC_PLL1_ConfigDomain_SYS(LL_RCC_PLL1SOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
469 UTILS_PLLInitStruct->PLLP);
470 LL_RCC_PLL1FRACN_Disable();
471 LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN);
472 LL_RCC_PLL1FRACN_Enable();
473 LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input);
474 LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output);
475
476 /* Enable PLL and switch system clock to PLL */
477 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
478 }
479 else
480 {
481 /* Current PLL configuration cannot be modified */
482 status = ERROR;
483 }
484
485 return status;
486 }
487
488 /**
489 * @brief This function configures system clock with HSE as clock source of the PLL1
490 * @note The application needs to ensure that the PLL1 is disabled.
491 * @note Function is based on the following formula:
492 * - PLL1 output frequency = (((HSE frequency / PLL1M) * PLL1N) / PLL1P)
493 * - PLL1M: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLL1VCO_input = HSE frequency / PLL1M)
494 * - PLL1N: ensure that the VCO output frequency is between 192 and 836 MHz
495 * (PLL1VCO_output = PLL1VCO_input * PLL1N)
496 * - PLL1P: ensure that max frequency at 240 MHz is reached (PLL1VCO_output / PLL1P)
497 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 50000000
498 * @param HSEBypass This parameter can be one of the following values:
499 * @arg @ref LL_UTILS_HSEBYPASS_ON
500 * @arg @ref LL_UTILS_HSEBYPASS_OFF
501 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
502 * the configuration information for the PLL.
503 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
504 * the configuration information for the BUS prescalers.
505 * @retval An ErrorStatus enumeration value:
506 * - SUCCESS: Max frequency configuration done
507 * - ERROR: Max frequency configuration not done
508 */
LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,uint32_t HSEBypass,LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)509 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
510 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
511 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
512 {
513 ErrorStatus status = SUCCESS;
514 #ifdef USE_FULL_ASSERT
515 uint32_t vcoinput_freq;
516 uint32_t vcooutput_freq;
517 #endif /* USE_FULL_ASSERT */
518 uint32_t pllfreq;
519
520 /* Check the parameters */
521 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
522 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
523 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
524 assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
525 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
526 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
527
528 /* Check VCO Input frequency */
529 #ifdef USE_FULL_ASSERT
530 vcoinput_freq = HSEFrequency / UTILS_PLLInitStruct->PLLM;
531 #endif /* USE_FULL_ASSERT */
532 assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input));
533
534 /* Check VCO Input/output ranges compatibility */
535 assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output));
536
537 /* Check VCO output frequency */
538 #ifdef USE_FULL_ASSERT
539 vcooutput_freq = LL_RCC_CalcPLLClockFreq(HSEFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
540 UTILS_PLLInitStruct->FRACN, 1U);
541 /* PLL1P Set to 1 to check the assert param (VCO_output)*/
542 #endif /* USE_FULL_ASSERT */
543 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
544
545 /* Check if the main PLL is enabled */
546 if (UTILS_PLL_IsBusy() == SUCCESS)
547 {
548 /* Calculate the new PLL output frequency */
549 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
550
551 /* Enable HSE if not enabled */
552 if (LL_RCC_HSE_IsReady() != 1U)
553 {
554 /* Check if need to enable HSE bypass feature or not */
555 if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
556 {
557 LL_RCC_HSE_EnableBypass();
558 LL_RCC_HSE_SetExternalClockType(LL_RCC_HSE_ANALOG_TYPE);
559 }
560 else if (HSEBypass == LL_UTILS_HSEBYPASS_DIGITAL_ON)
561 {
562 LL_RCC_HSE_EnableBypass();
563 LL_RCC_HSE_SetExternalClockType(LL_RCC_HSE_DIGITAL_TYPE);
564 }
565 else
566 {
567 LL_RCC_HSE_DisableBypass();
568 }
569
570 /* Enable HSE */
571 LL_RCC_HSE_Enable();
572 while (LL_RCC_HSE_IsReady() != 1U)
573 {
574 /* Wait for HSE ready */
575 }
576 }
577
578 /* Configure PLL */
579 LL_RCC_PLL1_ConfigDomain_SYS(LL_RCC_PLL1SOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
580 UTILS_PLLInitStruct->PLLP);
581 LL_RCC_PLL1FRACN_Disable();
582 LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN);
583 LL_RCC_PLL1FRACN_Enable();
584 LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input);
585 LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output);
586
587 /* Enable PLL and switch system clock to PLL */
588 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
589 }
590 else
591 {
592 /* Current PLL configuration cannot be modified */
593 status = ERROR;
594 }
595
596 return status;
597 }
598
599 /**
600 * @}
601 */
602
603 /**
604 * @}
605 */
606
607 /**
608 * @brief Update number of Flash wait states in line with new frequency and current
609 voltage range.
610 * @param HCLK_Frequency HCLK frequency
611 * @retval An ErrorStatus enumeration value:
612 * - SUCCESS: Latency has been modified
613 * - ERROR: Latency cannot be modified
614 */
LL_SetFlashLatency(uint32_t HCLK_Frequency)615 ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
616 {
617 ErrorStatus status = SUCCESS;
618 uint32_t timeout;
619 uint32_t getlatency;
620 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
621
622 /* Frequency cannot be equal to 0 */
623 if (HCLK_Frequency == 0U)
624 {
625 status = ERROR;
626 }
627 else
628 {
629 if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0)
630 {
631 if (HCLK_Frequency <= UTILS_SCALE0_LATENCY0_FREQ)
632 {
633 /* 0 < HCLK <= 38 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */
634 }
635 else if ((HCLK_Frequency <= UTILS_SCALE0_LATENCY1_FREQ))
636 {
637 /* 38 < HCLK <=76 => 1WS (2 CPU cycles) */
638 latency = LL_FLASH_LATENCY_1;
639 }
640 else if (HCLK_Frequency <= UTILS_SCALE0_LATENCY2_FREQ)
641 {
642 /* 76 < HCLK <= 114 => 2WS (3 CPU cycles) */
643 latency = LL_FLASH_LATENCY_2;
644 }
645 else if (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ)
646 {
647 /* 114 < HCLK <= 152 => 3WS (4 CPU cycles) */
648 latency = LL_FLASH_LATENCY_3;
649 }
650 else if (HCLK_Frequency <= UTILS_SCALE0_LATENCY4_FREQ)
651 {
652 /* 152 < HCLK <= 190 => 4WS (5 CPU cycles) */
653 latency = LL_FLASH_LATENCY_4;
654 }
655 else if (HCLK_Frequency <= UTILS_SCALE0_LATENCY5_FREQ)
656 {
657 /* 190 < HCLK <= 240 => 5WS (6 CPU cycles) */
658 latency = LL_FLASH_LATENCY_5;
659 }
660 else
661 {
662 status = ERROR;
663 }
664 }
665 else if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
666 {
667 if (HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ)
668 {
669 /* 0 < HCLK <= 32 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */
670 }
671 else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ)
672 {
673 /* 32 < HCLK <=64 => 1WS (2 CPU cycles) */
674 latency = LL_FLASH_LATENCY_1;
675 }
676 else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ)
677 {
678 /* 64 < HCLK <= 96 => 2WS (3 CPU cycles) */
679 latency = LL_FLASH_LATENCY_2;
680 }
681 else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY3_FREQ)
682 {
683 /* 96 < HCLK <= 128 => 3WS (4 CPU cycles) */
684 latency = LL_FLASH_LATENCY_3;
685 }
686 else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY4_FREQ)
687 {
688 /* 128 < HCLK <= 160 => 4WS (5 CPU cycles) */
689 latency = LL_FLASH_LATENCY_4;
690 }
691 else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY5_FREQ)
692 {
693 /* 160 < HCLK <= 150 => 5WS (6 CPU cycles) */
694 latency = LL_FLASH_LATENCY_5;
695 }
696 else
697 {
698 status = ERROR;
699 }
700 }
701 else if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
702 {
703 if (HCLK_Frequency <= UTILS_SCALE2_LATENCY0_FREQ)
704 {
705 /* 0 < HCLK <= 26 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */
706 }
707 else if (HCLK_Frequency <= UTILS_SCALE2_LATENCY1_FREQ)
708 {
709 /* 26 < HCLK <= 50 => 1WS (2 CPU cycles) */
710 latency = LL_FLASH_LATENCY_1;
711 }
712 else if (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ)
713 {
714 /* 50 < HCLK <= 80 => 2WS (3 CPU cycles) */
715 latency = LL_FLASH_LATENCY_2;
716 }
717 else if (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ)
718 {
719 /* 80 < HCLK <= 106 => 3WS (4 CPU cycles) */
720 latency = LL_FLASH_LATENCY_3;
721 }
722 else if (HCLK_Frequency <= UTILS_SCALE2_LATENCY4_FREQ)
723 {
724 /* 106 < HCLK <= 130 => 4WS (5 CPU cycles) */
725 latency = LL_FLASH_LATENCY_4;
726 }
727 else
728 {
729 status = ERROR;
730 }
731 }
732 else /* Voltage Scale 3 */
733 {
734 if (HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ)
735 {
736 /* 0 < HCLK <= 16 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */
737 }
738 else if (HCLK_Frequency <= UTILS_SCALE3_LATENCY1_FREQ)
739 {
740 /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */
741 latency = LL_FLASH_LATENCY_1;
742 }
743 else if (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ)
744 {
745 /* 32 < HCLK <= 50 => 2WS (3 CPU cycles) */
746 latency = LL_FLASH_LATENCY_2;
747 }
748 else if (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ)
749 {
750 /* 50 < HCLK <= 65 => 3WS (4 CPU cycles) */
751 latency = LL_FLASH_LATENCY_3;
752 }
753 else if (HCLK_Frequency <= UTILS_SCALE3_LATENCY4_FREQ)
754 {
755 /* 65 < HCLK <= 80 => 4WS (5 CPU cycles) */
756 latency = LL_FLASH_LATENCY_4;
757 }
758 else
759 {
760 status = ERROR;
761 }
762 }
763 }
764
765 if (status == SUCCESS)
766 {
767 LL_FLASH_SetLatency(latency);
768
769 /* Check that the new number of wait states is taken into account to access the Flash
770 memory by reading the FLASH_ACR register */
771 timeout = 2;
772 do
773 {
774 /* Wait for Flash latency to be updated */
775 getlatency = LL_FLASH_GetLatency();
776 timeout--;
777 } while ((getlatency != latency) && (timeout > 0U));
778
779 if (getlatency != latency)
780 {
781 status = ERROR;
782 }
783 }
784 return status;
785 }
786
787 /** @addtogroup UTILS_LL_Private_Functions
788 * @{
789 */
790 /**
791 * @brief Function to Get PLL1 Output frequency
792 * @param PLL_InputFrequency PLL1 input frequency (in Hz)
793 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
794 * the configuration information for the PLL.
795 * @retval PLL output frequency (in Hz)
796 */
UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct)797 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
798 {
799 uint32_t pllfreq;
800
801 /* Check the parameters */
802 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
803 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
804 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
805 assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
806
807 /* Check different PLL parameters according to RM */
808 /* - PLLM: ensure that the VCO input frequency is in the correct range. */
809 pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM);
810 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq, UTILS_PLLInitStruct->VCO_Input));
811
812 /* - PLLN: ensure that the VCO output frequency is in the correct range. */
813 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN);
814 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq, UTILS_PLLInitStruct->VCO_Output));
815
816 /* - PLLP: ensure that PLL1P output frequency does not exceed the corresponding maximum voltage scale frequency. */
817 pllfreq = pllfreq / (UTILS_PLLInitStruct->PLLP);
818 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
819
820 return pllfreq;
821 }
822
823 /**
824 * @brief Function to check that main PLL can be modified
825 * @retval An ErrorStatus enumeration value:
826 * - SUCCESS: Main PLL modification can be done
827 * - ERROR: Main PLL is busy
828 */
UTILS_PLL_IsBusy(void)829 static ErrorStatus UTILS_PLL_IsBusy(void)
830 {
831 ErrorStatus status = SUCCESS;
832
833 /* Check if PLL1 is busy*/
834 if (LL_RCC_PLL1_IsReady() != 0U)
835 {
836 /* PLL configuration cannot be modified */
837 status = ERROR;
838 }
839
840 return status;
841 }
842
843 /**
844 * @brief Function to enable PLL1 and switch system clock to PLL1
845 * @param SYSCLK_Frequency SYSCLK frequency
846 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
847 * the configuration information for the BUS prescalers.
848 * @retval An ErrorStatus enumeration value:
849 * - SUCCESS: No problem to switch system to PLL1
850 * - ERROR: Problem to switch system to PLL1
851 */
UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)852 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency,
853 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
854 {
855 ErrorStatus status = SUCCESS;
856 uint32_t hclk_frequency;
857
858 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->SYSCLKDivider));
859 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
860 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
861 assert_param(IS_LL_UTILS_APB3_DIV(UTILS_ClkInitStruct->APB3CLKDivider));
862
863 /* Calculate HCLK frequency */
864 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->SYSCLKDivider);
865
866 /* Increasing the number of wait states because of higher CPU frequency */
867 if (SystemCoreClock < hclk_frequency)
868 {
869 /* Set FLASH latency to highest latency */
870 status = LL_SetFlashLatency(hclk_frequency);
871 }
872
873 /* Update system clock configuration */
874 if (status == SUCCESS)
875 {
876 /* Enable PLL1 */
877 LL_RCC_PLL1_Enable();
878 LL_RCC_PLL1P_Enable();
879 while (LL_RCC_PLL1_IsReady() != 1U)
880 {
881 /* Wait for PLL ready */
882 }
883
884 /* Set All APBxPrescaler to the Highest Divider */
885 LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16);
886 LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16);
887 LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16);
888
889 /* Set AHB prescaler*/
890 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->SYSCLKDivider);
891
892 /* Sysclk activation on the main PLL */
893 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
894 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
895 {
896 /* Wait for system clock switch to PLL */
897 }
898
899 /* Set APB1, APB2 & APB3 prescaler*/
900 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
901 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
902 LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider);
903 }
904
905 /* Decreasing the number of wait states because of lower CPU frequency */
906 if (SystemCoreClock > hclk_frequency)
907 {
908 /* Set FLASH latency to lowest latency */
909 status = LL_SetFlashLatency(hclk_frequency);
910 }
911
912 /* Update SystemCoreClock variable */
913 if (status == SUCCESS)
914 {
915 LL_SetSystemCoreClock(hclk_frequency);
916 }
917
918 return status;
919 }
920
921 /**
922 * @}
923 */
924
925 /**
926 * @}
927 */
928
929 /**
930 * @}
931 */
932
