1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_spi.c
4 * @author MCD Application Team
5 * @brief SPI LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32h5xx_ll_spi.h"
22 #include "stm32h5xx_ll_bus.h"
23 #include "stm32h5xx_ll_rcc.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
35
36 /** @addtogroup SPI_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup SPI_LL_Private_Macros
45 * @{
46 */
47
48 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) || \
49 ((__VALUE__) == LL_SPI_MODE_SLAVE))
50
51 #define IS_LL_SPI_SS_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE) || \
52 ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE) || \
53 ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE) || \
54 ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE) || \
55 ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE) || \
56 ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE) || \
57 ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE) || \
58 ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE) || \
59 ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE) || \
60 ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE) || \
61 ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE) || \
62 ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE) || \
63 ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE) || \
64 ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE) || \
65 ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE) || \
66 ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE))
67
68 #define IS_LL_SPI_ID_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE) || \
69 ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE) || \
70 ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE) || \
71 ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE) || \
72 ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE) || \
73 ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE) || \
74 ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE) || \
75 ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE) || \
76 ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE) || \
77 ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE) || \
78 ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE) || \
79 ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE) || \
80 ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE) || \
81 ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE) || \
82 ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE) || \
83 ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE))
84
85 #define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN) || \
86 ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN))
87
88 #define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN) || \
89 ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN))
90
91 #define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__) (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) || \
92 ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED) || \
93 ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED))
94
95 #define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__) (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) || \
96 ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME) || \
97 ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS))
98
99 #define IS_LL_SPI_PROTOCOL(__VALUE__) (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA) || \
100 ((__VALUE__) == LL_SPI_PROTOCOL_TI))
101
102 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) || \
103 ((__VALUE__) == LL_SPI_PHASE_2EDGE))
104
105 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) || \
106 ((__VALUE__) == LL_SPI_POLARITY_HIGH))
107
108 #define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_BYPASS) || \
109 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) || \
110 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) || \
111 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) || \
112 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) || \
113 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) || \
114 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) || \
115 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) || \
116 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
117
118 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) || \
119 ((__VALUE__) == LL_SPI_MSB_FIRST))
120
121 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) || \
122 ((__VALUE__) == LL_SPI_SIMPLEX_TX) || \
123 ((__VALUE__) == LL_SPI_SIMPLEX_RX) || \
124 ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) || \
125 ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
126
127 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) || \
128 ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) || \
129 ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) || \
130 ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) || \
131 ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) || \
132 ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) || \
133 ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) || \
134 ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) || \
135 ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) || \
136 ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) || \
137 ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) || \
138 ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) || \
139 ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT) || \
140 ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT) || \
141 ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT) || \
142 ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT) || \
143 ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT) || \
144 ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT) || \
145 ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT) || \
146 ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT) || \
147 ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT) || \
148 ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT) || \
149 ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT) || \
150 ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT) || \
151 ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT) || \
152 ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT) || \
153 ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT) || \
154 ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT) || \
155 ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT))
156
157 #define IS_LL_SPI_FIFO_TH(__VALUE__) (((__VALUE__) == LL_SPI_FIFO_TH_01DATA) || \
158 ((__VALUE__) == LL_SPI_FIFO_TH_02DATA) || \
159 ((__VALUE__) == LL_SPI_FIFO_TH_03DATA) || \
160 ((__VALUE__) == LL_SPI_FIFO_TH_04DATA) || \
161 ((__VALUE__) == LL_SPI_FIFO_TH_05DATA) || \
162 ((__VALUE__) == LL_SPI_FIFO_TH_06DATA) || \
163 ((__VALUE__) == LL_SPI_FIFO_TH_07DATA) || \
164 ((__VALUE__) == LL_SPI_FIFO_TH_08DATA) || \
165 ((__VALUE__) == LL_SPI_FIFO_TH_09DATA) || \
166 ((__VALUE__) == LL_SPI_FIFO_TH_10DATA) || \
167 ((__VALUE__) == LL_SPI_FIFO_TH_11DATA) || \
168 ((__VALUE__) == LL_SPI_FIFO_TH_12DATA) || \
169 ((__VALUE__) == LL_SPI_FIFO_TH_13DATA) || \
170 ((__VALUE__) == LL_SPI_FIFO_TH_14DATA) || \
171 ((__VALUE__) == LL_SPI_FIFO_TH_15DATA) || \
172 ((__VALUE__) == LL_SPI_FIFO_TH_16DATA))
173
174 #define IS_LL_SPI_CRC(__VALUE__) (((__VALUE__) == LL_SPI_CRC_4BIT) || \
175 ((__VALUE__) == LL_SPI_CRC_5BIT) || \
176 ((__VALUE__) == LL_SPI_CRC_6BIT) || \
177 ((__VALUE__) == LL_SPI_CRC_7BIT) || \
178 ((__VALUE__) == LL_SPI_CRC_8BIT) || \
179 ((__VALUE__) == LL_SPI_CRC_9BIT) || \
180 ((__VALUE__) == LL_SPI_CRC_10BIT) || \
181 ((__VALUE__) == LL_SPI_CRC_11BIT) || \
182 ((__VALUE__) == LL_SPI_CRC_12BIT) || \
183 ((__VALUE__) == LL_SPI_CRC_13BIT) || \
184 ((__VALUE__) == LL_SPI_CRC_14BIT) || \
185 ((__VALUE__) == LL_SPI_CRC_15BIT) || \
186 ((__VALUE__) == LL_SPI_CRC_16BIT) || \
187 ((__VALUE__) == LL_SPI_CRC_17BIT) || \
188 ((__VALUE__) == LL_SPI_CRC_18BIT) || \
189 ((__VALUE__) == LL_SPI_CRC_19BIT) || \
190 ((__VALUE__) == LL_SPI_CRC_20BIT) || \
191 ((__VALUE__) == LL_SPI_CRC_21BIT) || \
192 ((__VALUE__) == LL_SPI_CRC_22BIT) || \
193 ((__VALUE__) == LL_SPI_CRC_23BIT) || \
194 ((__VALUE__) == LL_SPI_CRC_24BIT) || \
195 ((__VALUE__) == LL_SPI_CRC_25BIT) || \
196 ((__VALUE__) == LL_SPI_CRC_26BIT) || \
197 ((__VALUE__) == LL_SPI_CRC_27BIT) || \
198 ((__VALUE__) == LL_SPI_CRC_28BIT) || \
199 ((__VALUE__) == LL_SPI_CRC_29BIT) || \
200 ((__VALUE__) == LL_SPI_CRC_30BIT) || \
201 ((__VALUE__) == LL_SPI_CRC_31BIT) || \
202 ((__VALUE__) == LL_SPI_CRC_32BIT))
203
204 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) || \
205 ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) || \
206 ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
207
208 #define IS_LL_SPI_RX_FIFO(__VALUE__) (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET) || \
209 ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET) || \
210 ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET) || \
211 ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET))
212
213 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) || \
214 ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
215
216 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1UL)
217
218 /**
219 * @}
220 */
221
222 /* Private function prototypes -----------------------------------------------*/
223
224 /* Exported functions --------------------------------------------------------*/
225 /** @addtogroup SPI_LL_Exported_Functions
226 * @{
227 */
228
229 /** @addtogroup SPI_LL_EF_Init
230 * @{
231 */
232
233 /**
234 * @brief De-initialize the SPI registers to their default reset values.
235 * @param SPIx SPI Instance
236 * @retval An ErrorStatus enumeration value:
237 * - SUCCESS: SPI registers are de-initialized
238 * - ERROR: SPI registers are not de-initialized
239 */
LL_SPI_DeInit(SPI_TypeDef * SPIx)240 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
241 {
242 ErrorStatus status = ERROR;
243
244 /* Check the parameters */
245 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
246
247 #if defined(SPI1)
248 if (SPIx == SPI1)
249 {
250 /* Force reset of SPI clock */
251 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
252
253 /* Release reset of SPI clock */
254 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
255
256 /* Update the return status */
257 status = SUCCESS;
258 }
259 #endif /* SPI1 */
260 #if defined(SPI2)
261 if (SPIx == SPI2)
262 {
263 /* Force reset of SPI clock */
264 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
265
266 /* Release reset of SPI clock */
267 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
268
269 /* Update the return status */
270 status = SUCCESS;
271 }
272 #endif /* SPI2 */
273 #if defined(SPI3)
274 if (SPIx == SPI3)
275 {
276 /* Force reset of SPI clock */
277 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
278
279 /* Release reset of SPI clock */
280 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
281
282 /* Update the return status */
283 status = SUCCESS;
284 }
285 #endif /* SPI3 */
286 #if defined(SPI4)
287 if (SPIx == SPI4)
288 {
289 /* Force reset of SPI clock */
290 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
291
292 /* Release reset of SPI clock */
293 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
294
295 /* Update the return status */
296 status = SUCCESS;
297 }
298 #endif /* SPI4 */
299 #if defined(SPI5)
300 if (SPIx == SPI5)
301 {
302 /* Force reset of SPI clock */
303 LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_SPI5);
304
305 /* Release reset of SPI clock */
306 LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_SPI5);
307
308 /* Update the return status */
309 status = SUCCESS;
310 }
311 #endif /* SPI5 */
312 #if defined(SPI6)
313 if (SPIx == SPI6)
314 {
315 /* Force reset of SPI clock */
316 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6);
317
318 /* Release reset of SPI clock */
319 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6);
320
321 /* Update the return status */
322 status = SUCCESS;
323 }
324 #endif /* SPI6 */
325
326 return status;
327 }
328
329 /**
330 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
331 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled
332 * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function.
333 * Otherwise, ERROR result will be returned.
334 * @param SPIx SPI Instance
335 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
336 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
337 */
LL_SPI_Init(SPI_TypeDef * SPIx,LL_SPI_InitTypeDef * SPI_InitStruct)338 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
339 {
340 ErrorStatus status = ERROR;
341 uint32_t tmp_nss;
342 uint32_t tmp_mode;
343 uint32_t tmp_nss_polarity;
344
345 /* Check the SPI Instance SPIx*/
346 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
347
348 /* Check the SPI parameters from SPI_InitStruct*/
349 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
350 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
351 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
352 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
353 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
354 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
355 assert_param(IS_LL_SPI_BAUDRATEPRESCALER(SPI_InitStruct->BaudRate));
356 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
357 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
358
359 /* Check the SPI instance is not enabled */
360 if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
361 {
362 /*---------------------------- SPIx CFG1 Configuration ------------------------
363 * Configure SPIx CFG1 with parameters:
364 * - Master Baud Rate : SPI_CFG1_MBR[2:0] bits & SPI_CFG1_BPASS bit
365 * - CRC Computation Enable : SPI_CFG1_CRCEN bit
366 * - Length of data frame : SPI_CFG1_DSIZE[4:0] bits
367 */
368 MODIFY_REG(SPIx->CFG1, SPI_CFG1_BPASS | SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE,
369 SPI_InitStruct->BaudRate | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth);
370
371 tmp_nss = SPI_InitStruct->NSS;
372 tmp_mode = SPI_InitStruct->Mode;
373 tmp_nss_polarity = LL_SPI_GetNSSPolarity(SPIx);
374
375 /* Checks to setup Internal SS signal level and avoid a MODF Error */
376 if ((tmp_nss == LL_SPI_NSS_SOFT) && (((tmp_nss_polarity == LL_SPI_NSS_POLARITY_LOW) && \
377 (tmp_mode == LL_SPI_MODE_MASTER)) || \
378 ((tmp_nss_polarity == LL_SPI_NSS_POLARITY_HIGH) && \
379 (tmp_mode == LL_SPI_MODE_SLAVE))))
380 {
381 LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH);
382 }
383
384 /*---------------------------- SPIx CFG2 Configuration ------------------------
385 * Configure SPIx CFG2 with parameters:
386 * - NSS management : SPI_CFG2_SSM, SPI_CFG2_SSOE bits
387 * - ClockPolarity : SPI_CFG2_CPOL bit
388 * - ClockPhase : SPI_CFG2_CPHA bit
389 * - BitOrder : SPI_CFG2_LSBFRST bit
390 * - Master/Slave Mode : SPI_CFG2_MASTER bit
391 * - SPI Mode : SPI_CFG2_COMM[1:0] bits
392 */
393 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE |
394 SPI_CFG2_CPOL | SPI_CFG2_CPHA |
395 SPI_CFG2_LSBFRST | SPI_CFG2_MASTER | SPI_CFG2_COMM,
396 SPI_InitStruct->NSS | SPI_InitStruct->ClockPolarity |
397 SPI_InitStruct->ClockPhase | SPI_InitStruct->BitOrder |
398 SPI_InitStruct->Mode | (SPI_InitStruct->TransferDirection & SPI_CFG2_COMM));
399
400 /*---------------------------- SPIx CR1 Configuration ------------------------
401 * Configure SPIx CR1 with parameter:
402 * - Half Duplex Direction : SPI_CR1_HDDIR bit
403 */
404 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, SPI_InitStruct->TransferDirection & SPI_CR1_HDDIR);
405
406 /*---------------------------- SPIx CRCPOLY Configuration ----------------------
407 * Configure SPIx CRCPOLY with parameter:
408 * - CRCPoly : CRCPOLY[31:0] bits
409 */
410 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
411 {
412 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
413 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
414 }
415
416 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
417 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
418
419 status = SUCCESS;
420 }
421
422 return status;
423 }
424
425 /**
426 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
427 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
428 * whose fields will be set to default values.
429 * @retval None
430 */
LL_SPI_StructInit(LL_SPI_InitTypeDef * SPI_InitStruct)431 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
432 {
433 /* Set SPI_InitStruct fields to default values */
434 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
435 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
436 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
437 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
438 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
439 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
440 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
441 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
442 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
443 SPI_InitStruct->CRCPoly = 7UL;
444 }
445
446 /**
447 * @}
448 */
449
450 /**
451 * @}
452 */
453
454 /**
455 * @}
456 */
457 /** @addtogroup I2S_LL
458 * @{
459 */
460
461 /* Private types -------------------------------------------------------------*/
462 /* Private variables ---------------------------------------------------------*/
463 /* Private constants ---------------------------------------------------------*/
464 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
465 * @{
466 */
467 /* I2S registers Masks */
468 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
469 SPI_I2SCFGR_DATFMT | SPI_I2SCFGR_CKPOL | \
470 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_MCKOE | \
471 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
472
473 /**
474 * @}
475 */
476 /* Private macros ------------------------------------------------------------*/
477 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
478 * @{
479 */
480
481 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) || \
482 ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) || \
483 ((__VALUE__) == LL_I2S_DATAFORMAT_24B) || \
484 ((__VALUE__) == LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED) || \
485 ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
486
487 #define IS_LL_I2S_CHANNEL_LENGTH_TYPE (__VALUE__) (((__VALUE__) == LL_I2S_SLAVE_VARIABLE_CH_LENGTH) || \
488 ((__VALUE__) == LL_I2S_SLAVE_FIXED_CH_LENGTH))
489
490 #define IS_LL_I2S_CKPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) || \
491 ((__VALUE__) == LL_I2S_POLARITY_HIGH))
492
493 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) || \
494 ((__VALUE__) == LL_I2S_STANDARD_MSB) || \
495 ((__VALUE__) == LL_I2S_STANDARD_LSB) || \
496 ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) || \
497 ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
498
499 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) || \
500 ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) || \
501 ((__VALUE__) == LL_I2S_MODE_SLAVE_FULL_DUPLEX) || \
502 ((__VALUE__) == LL_I2S_MODE_MASTER_TX) || \
503 ((__VALUE__) == LL_I2S_MODE_MASTER_RX) || \
504 ((__VALUE__) == LL_I2S_MODE_MASTER_FULL_DUPLEX))
505
506 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) || \
507 ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
508
509 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) && \
510 ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) || \
511 ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
512
513 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) <= 0xFFUL)
514
515 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) || \
516 ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
517
518 #define IS_LL_I2S_FIFO_TH (__VALUE__) (((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_01DATA) || \
519 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_02DATA) || \
520 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_03DATA) || \
521 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_04DATA) || \
522 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_05DATA) || \
523 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_06DATA) || \
524 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_07DATA) || \
525 ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_08DATA))
526
527 #define IS_LL_I2S_BIT_ORDER(__VALUE__) (((__VALUE__) == LL_I2S_LSB_FIRST) || \
528 ((__VALUE__) == LL_I2S_MSB_FIRST))
529 /**
530 * @}
531 */
532
533 /* Private function prototypes -----------------------------------------------*/
534
535 /* Exported functions --------------------------------------------------------*/
536 /** @addtogroup I2S_LL_Exported_Functions
537 * @{
538 */
539
540 /** @addtogroup I2S_LL_EF_Init
541 * @{
542 */
543
544 /**
545 * @brief De-initialize the SPI/I2S registers to their default reset values.
546 * @param SPIx SPI Instance
547 * @retval An ErrorStatus enumeration value:
548 * - SUCCESS: SPI registers are de-initialized
549 * - ERROR: SPI registers are not de-initialized
550 */
LL_I2S_DeInit(SPI_TypeDef * SPIx)551 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
552 {
553 return LL_SPI_DeInit(SPIx);
554 }
555
556 /**
557 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
558 * @note As some bits in I2S configuration registers can only be written when the SPI is disabled
559 * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function.
560 * Otherwise, ERROR result will be returned.
561 * @note I2S (SPI) source clock must be ready before calling this function. Otherwise will results
562 * in wrong programming.
563 * @param SPIx SPI Instance
564 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
565 * @retval An ErrorStatus enumeration value:
566 * - SUCCESS: SPI registers are Initialized
567 * - ERROR: SPI registers are not Initialized
568 */
LL_I2S_Init(SPI_TypeDef * SPIx,LL_I2S_InitTypeDef * I2S_InitStruct)569 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
570 {
571 uint32_t i2sdiv = 0UL;
572 uint32_t i2sodd = 0UL;
573 uint32_t packetlength = 1UL;
574 uint32_t ispcm = 0UL;
575 uint32_t tmp;
576 uint32_t sourceclock = 0;
577
578 ErrorStatus status = ERROR;
579
580 /* Check the I2S parameters */
581 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
582 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
583 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
584 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
585 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
586 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
587 assert_param(IS_LL_I2S_CKPOL(I2S_InitStruct->ClockPolarity));
588
589 /* Check that SPE bit is set to 0 in order to be sure that SPI/I2S block is disabled.
590 * In this case, it is useless to check if the I2SMOD bit is set to 0 because
591 * this bit I2SMOD only serves to select the desired mode.
592 */
593 if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
594 {
595 /*---------------------------- SPIx I2SCFGR Configuration --------------------
596 * Configure SPIx I2SCFGR with parameters:
597 * - Mode : SPI_I2SCFGR_I2SCFG[2:0] bits
598 * - Standard : SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
599 * - DataFormat : SPI_I2SCFGR_CHLEN, SPI_I2SCFGR_DATFMT and SPI_I2SCFGR_DATLEN[1:0] bits
600 * - ClockPolarity : SPI_I2SCFGR_CKPOL bit
601 * - MCLKOutput : SPI_I2SPR_MCKOE bit
602 * - I2S mode : SPI_I2SCFGR_I2SMOD bit
603 */
604
605 /* Write to SPIx I2SCFGR */
606 MODIFY_REG(SPIx->I2SCFGR,
607 I2S_I2SCFGR_CLEAR_MASK,
608 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
609 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
610 I2S_InitStruct->MCLKOutput | SPI_I2SCFGR_I2SMOD);
611
612 /*---------------------------- SPIx I2SCFGR Configuration ----------------------
613 * Configure SPIx I2SCFGR with parameters:
614 * - AudioFreq : SPI_I2SCFGR_I2SDIV[7:0] and SPI_I2SCFGR_ODD bits
615 */
616
617 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
618 * else, default values are used: i2sodd = 0U, i2sdiv = 0U.
619 */
620 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
621 {
622 /* Check the frame length (For the Prescaler computing)
623 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
624 */
625 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
626 {
627 /* Packet length is 32 bits */
628 packetlength = 2UL;
629 }
630
631 /* Check if PCM standard is used */
632 if ((I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_SHORT) ||
633 (I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_LONG))
634 {
635 ispcm = 1UL;
636 }
637
638 /* Get the I2S (SPI) source clock value */
639 #if defined(SPI1)
640 if (SPIx == SPI1)
641 {
642 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI1_CLKSOURCE);
643 }
644 #endif /* SPI1 */
645 #if defined(SPI2)
646 if (SPIx == SPI2)
647 {
648 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI2_CLKSOURCE);
649 }
650 #endif /* SPI2 */
651 #if defined(SPI3)
652 if (SPIx == SPI3)
653 {
654 sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI3_CLKSOURCE);
655 }
656 #endif /* SPI3 */
657
658 /* Compute the Real divider depending on the MCLK output state with a fixed point */
659 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
660 {
661 /* MCLK output is enabled */
662 tmp = (((sourceclock / (256UL >> ispcm)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL;
663 }
664 else
665 {
666 /* MCLK output is disabled */
667 tmp = (((sourceclock / ((32UL >> ispcm) * packetlength)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL;
668 }
669
670 /* Remove the fixed point */
671 tmp = tmp / 16UL;
672
673 /* Check the parity of the divider */
674 i2sodd = tmp & 0x1UL;
675
676 /* Compute the i2sdiv prescaler */
677 i2sdiv = tmp / 2UL;
678 }
679
680 /* Test if the obtain values are forbidden or out of range */
681 if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL))
682 {
683 /* Set the default values */
684 i2sdiv = 0UL;
685 i2sodd = 0UL;
686 }
687
688 /* Write to SPIx I2SCFGR register the computed value */
689 MODIFY_REG(SPIx->I2SCFGR,
690 SPI_I2SCFGR_ODD | SPI_I2SCFGR_I2SDIV,
691 (i2sodd << SPI_I2SCFGR_ODD_Pos) | (i2sdiv << SPI_I2SCFGR_I2SDIV_Pos));
692
693 status = SUCCESS;
694 }
695
696 return status;
697 }
698
699 /**
700 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
701 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
702 * whose fields will be set to default values.
703 * @retval None
704 */
LL_I2S_StructInit(LL_I2S_InitTypeDef * I2S_InitStruct)705 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
706 {
707 /*--------------- Reset I2S init structure parameters values -----------------*/
708 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
709 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
710 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
711 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
712 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
713 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
714 }
715
716 /**
717 * @brief Set linear and parity prescaler.
718 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
719 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
720 * @param SPIx SPI Instance
721 * @param PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
722 * @note PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
723 * @param PrescalerParity This parameter can be one of the following values:
724 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
725 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
726 * @retval None
727 */
LL_I2S_ConfigPrescaler(SPI_TypeDef * SPIx,uint32_t PrescalerLinear,uint32_t PrescalerParity)728 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
729 {
730 /* Check the I2S parameters */
731 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
732 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
733 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
734
735 /* Write to SPIx I2SPR */
736 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos) |
737 (PrescalerParity << SPI_I2SCFGR_ODD_Pos));
738 }
739
740 /**
741 * @}
742 */
743
744 /**
745 * @}
746 */
747
748 /**
749 * @}
750 */
751
752 #endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
753
754 /**
755 * @}
756 */
757 #endif /* USE_FULL_LL_DRIVER */
758
