1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32h5xx_ll_rcc.h"
22 #ifdef USE_FULL_ASSERT
23 #include "stm32_assert.h"
24 #else
25 #define assert_param(expr) ((void)0U)
26 #endif /* USE_FULL_ASSERT */
27 /** @addtogroup STM32H5xx_LL_Driver
28 * @{
29 */
30
31 #if defined(RCC)
32
33 /** @addtogroup RCC_LL
34 * @{
35 */
36
37 /* Private types -------------------------------------------------------------*/
38 /* Private variables ---------------------------------------------------------*/
39 /* Private constants ---------------------------------------------------------*/
40 /* Private macros ------------------------------------------------------------*/
41 /** @addtogroup RCC_LL_Private_Macros
42 * @{
43 */
44 #if defined(USART6)
45 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
46 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
47 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE) \
48 || ((__VALUE__) == LL_RCC_USART6_CLKSOURCE) \
49 || ((__VALUE__) == LL_RCC_USART10_CLKSOURCE) \
50 || ((__VALUE__) == LL_RCC_USART11_CLKSOURCE))
51 #else
52 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
53 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
54 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
55 #endif /* USART6 */
56
57 #if defined(UART4)
58 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
59 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE) \
60 || ((__VALUE__) == LL_RCC_UART7_CLKSOURCE) \
61 || ((__VALUE__) == LL_RCC_UART8_CLKSOURCE) \
62 || ((__VALUE__) == LL_RCC_UART9_CLKSOURCE) \
63 || ((__VALUE__) == LL_RCC_UART12_CLKSOURCE))
64 #endif /* UART4 */
65
66 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
67
68 #if defined(I2C3)
69 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
70 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
71 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
72 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
73 #else
74 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
75 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE))
76 #endif /* I2C3*/
77
78 #if defined(I3C2)
79 #define IS_LL_RCC_I3C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I3C1_CLKSOURCE) \
80 || ((__VALUE__) == LL_RCC_I3C2_CLKSOURCE))
81 #else
82 #define IS_LL_RCC_I3C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I3C1_CLKSOURCE))
83 #endif /* I3C2 */
84
85 #if defined(SPI4)
86 #define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) \
87 || ((__VALUE__) == LL_RCC_SPI2_CLKSOURCE) \
88 || ((__VALUE__) == LL_RCC_SPI3_CLKSOURCE) \
89 || ((__VALUE__) == LL_RCC_SPI4_CLKSOURCE) \
90 || ((__VALUE__) == LL_RCC_SPI5_CLKSOURCE) \
91 || ((__VALUE__) == LL_RCC_SPI6_CLKSOURCE))
92 #else
93 #define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) \
94 || ((__VALUE__) == LL_RCC_SPI2_CLKSOURCE) \
95 || ((__VALUE__) == LL_RCC_SPI3_CLKSOURCE))
96 #endif /* SPI4 */
97
98 #if defined(LPTIM3)
99 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
100 || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \
101 || ((__VALUE__) == LL_RCC_LPTIM3_CLKSOURCE) \
102 || ((__VALUE__) == LL_RCC_LPTIM4_CLKSOURCE) \
103 || ((__VALUE__) == LL_RCC_LPTIM5_CLKSOURCE) \
104 || ((__VALUE__) == LL_RCC_LPTIM6_CLKSOURCE))
105 #else
106 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
107 || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE))
108 #endif /* LPTIM3 */
109
110 #if defined(SAI1)
111 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
112 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
113 #endif /* SAI1 */
114
115 #if defined (SDMMC2)
116 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE) \
117 || ((__VALUE__) == LL_RCC_SDMMC2_CLKSOURCE))
118 #elif defined (SDMMC1)
119 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
120 #endif /* SDMMC2*/
121
122 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
123
124 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
125
126 #define IS_LL_RCC_ADCDAC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADCDAC_CLKSOURCE))
127
128 #define IS_LL_RCC_DAC_LP_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DAC_LP_CLKSOURCE))
129
130 #define IS_LL_RCC_OCTOSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OCTOSPI_CLKSOURCE))
131
132 #define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE)
133
134 #if defined(CEC)
135 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
136 #endif /* CEC */
137
138 /**
139 * @}
140 */
141
142 /* Private function prototypes -----------------------------------------------*/
143 /** @defgroup RCC_LL_Private_Functions RCC Private functions
144 * @{
145 */
146 uint32_t RCC_GetSystemClockFreq(void);
147 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
148 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
149 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
150 uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency);
151 uint32_t RCC_PLL1_GetFreqSystem(void);
152 /**
153 * @}
154 */
155
156 /* Exported functions --------------------------------------------------------*/
157 /** @addtogroup RCC_LL_Exported_Functions
158 * @{
159 */
160
161 /** @addtogroup RCC_LL_EF_Init
162 * @{
163 */
164
165 /**
166 * @brief Reset the RCC clock configuration to the default reset state.
167 * @note The default reset state of the clock configuration is given below:
168 * - HSI ON and used as system clock source
169 * - HSE, CSI, PLL1, PLL2 and PLL3 OFF
170 * - AHB, APB1, APB2 and APB3 prescaler set to 1.
171 * - CSS OFF
172 * - All interrupts disabled
173 * @note This function doesn't modify the configuration of the
174 * - Peripheral clocks
175 * - LSI, LSE and RTC clocks
176 * @retval An ErrorStatus enumeration value:
177 * - SUCCESS: RCC registers are de-initialized
178 * - ERROR: not applicable
179 */
LL_RCC_DeInit(void)180 ErrorStatus LL_RCC_DeInit(void)
181 {
182
183 /* Set HSION bit */
184 LL_RCC_HSI_Enable();
185
186 /* Wait for HSI READY bit */
187 while (LL_RCC_HSI_IsReady() == 0U)
188 {
189 }
190
191 /* Set HSIDIV Default value */
192 CLEAR_BIT(RCC->CR, RCC_CR_HSIDIV);
193
194 /* Set HSITRIM bits to the reset value*/
195 LL_RCC_HSI_SetCalibTrimming(0x40U);
196
197 /* Reset CFGR register */
198 LL_RCC_WriteReg(CFGR1, 0x00000000U);
199 LL_RCC_WriteReg(CFGR2, 0x00000000U);
200
201 /* Wait till clock switch is ready */
202 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
203 {
204 }
205
206 #if defined(RCC_CR_PLL3ON)
207 /* Reset HSECSSON, HSEON, HSIKERON, CSION, CSIKERON, HSI48ON, PLL1ON, PLL2ON and PLL3ON bits */
208 CLEAR_BIT(RCC->CR, RCC_CR_CSION | RCC_CR_CSIKERON | RCC_CR_HSECSSON | RCC_CR_HSIKERON | RCC_CR_HSI48ON |
209 RCC_CR_HSEON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
210 #else
211 /* Reset HSECSSON, HSEON, HSIKERON, CSION, CSIKERON, HSI48ON, PLL1ON, PLL2ON and PLL3ON bits */
212 CLEAR_BIT(RCC->CR, RCC_CR_CSION | RCC_CR_CSIKERON | RCC_CR_HSECSSON | RCC_CR_HSIKERON | RCC_CR_HSI48ON |
213 RCC_CR_HSEON | RCC_CR_PLL1ON | RCC_CR_PLL2ON);
214 #endif /* PLL3 */
215
216 /* Wait for PLL1 READY bit to be reset */
217 while (LL_RCC_PLL1_IsReady() != 0U)
218 {}
219
220 /* Wait for PLL2 READY bit to be reset */
221 while (LL_RCC_PLL2_IsReady() != 0U)
222 {}
223
224 #if defined(RCC_CR_PLL3ON)
225 /* Wait for PLL3 READY bit to be reset */
226 while (LL_RCC_PLL3_IsReady() != 0U)
227 {}
228 #endif /* PLL3 */
229
230 /* Reset PLL1CFGR register */
231 CLEAR_REG(RCC->PLL1CFGR);
232
233 /* Reset PLL1DIVR register */
234 LL_RCC_WriteReg(PLL1DIVR, 0x01010280U);
235
236 /* Reset PLL1FRACR register */
237 CLEAR_REG(RCC->PLL1FRACR);
238
239 /* Reset PLL2CFGR register */
240 CLEAR_REG(RCC->PLL2CFGR);
241
242 /* Reset PLL2DIVR register */
243 LL_RCC_WriteReg(PLL2DIVR, 0x01010280U);
244
245 /* Reset PLL2FRACR register */
246 CLEAR_REG(RCC->PLL2FRACR);
247
248 #if defined(RCC_CR_PLL3ON)
249 /* Reset PLL3CFGR register */
250 CLEAR_REG(RCC->PLL3CFGR);
251
252 /* Reset PLL3DIVR register */
253 LL_RCC_WriteReg(PLL3DIVR, 0x01010280U);
254
255 /* Reset PLL3FRACR register */
256 CLEAR_REG(RCC->PLL3FRACR);
257 #endif /* PLL3 */
258
259 /* Reset HSEBYP bit */
260 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
261
262 /* Reset HSEEXT bit */
263 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);
264
265 #if defined(RCC_CR_PLL3ON)
266 /* Disable all interrupts */
267 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE | RCC_CIER_LSERDYIE | RCC_CIER_HSIRDYIE | RCC_CIER_HSERDYIE
268 | RCC_CIER_CSIRDYIE | RCC_CIER_HSI48RDYIE | RCC_CIER_PLL1RDYIE | RCC_CIER_PLL2RDYIE
269 | RCC_CIER_PLL3RDYIE);
270
271 /* Clear all interrupt flags */
272 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC
273 | RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLL1RDYC | RCC_CICR_PLL2RDYC
274 | RCC_CICR_PLL3RDYC | RCC_CICR_HSECSSC);
275 #else
276 /* Disable all interrupts */
277 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE | RCC_CIER_LSERDYIE | RCC_CIER_HSIRDYIE | RCC_CIER_HSERDYIE
278 | RCC_CIER_CSIRDYIE | RCC_CIER_HSI48RDYIE | RCC_CIER_PLL1RDYIE | RCC_CIER_PLL2RDYIE);
279
280 /* Clear all interrupt flags */
281 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC
282 | RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLL1RDYC | RCC_CICR_PLL2RDYC
283 | RCC_CICR_HSECSSC);
284 #endif /* PLL3 */
285
286
287 /* Clear all reset flags */
288 LL_RCC_ClearResetFlags();
289
290 /* Update the SystemCoreClock global variable */
291 SystemCoreClock = HSI_VALUE;
292
293 return SUCCESS;
294 }
295
296 /**
297 * @}
298 */
299
300 /** @addtogroup RCC_LL_EF_Get_Freq
301 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
302 * and different peripheral clocks available on the device.
303 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
304 * @note If SYSCLK source is CSI, function returns values based on CSI_VALUE(**)
305 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
306 * @note If SYSCLK source is PLL1, function returns values based on HSE_VALUE(***)
307 * or HSI_VALUE(**) or CSI_VALUE(*) multiplied/divided by the main PLL factors.
308 * @note (*) HSI_VALUE is a constant defined in this file (default value
309 * 64 MHz) but the real value may vary depending on the variations
310 * in voltage and temperature.
311 * @note (**) CSI_VALUE is a constant defined in this file (default value
312 * 4 MHz) but the real value may vary depending on the variations
313 * in voltage and temperature.
314 * @note (***) HSE_VALUE is a constant defined in this file (default value
315 * 32 MHz), user has to ensure that HSE_VALUE is same as the real
316 * frequency of the crystal used. Otherwise, this function may
317 * have wrong result.
318 * @note The result of this function could be incorrect when using fractional
319 * value for HSE crystal.
320 * @note This function can be used by the user application to compute the
321 * baud-rate for the communication peripherals or configure other parameters.
322 * @{
323 */
324
325 /**
326 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1, APB2 and APB3 buses clocks
327 * @note Each time SYSCLK, HCLK, PCLK1, PCLK2 and PCLK3 clock changes, this function
328 * must be called to update structure fields. Otherwise, any
329 * configuration based on this function will be incorrect.
330 * @param pRCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
331 * @retval None
332 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * pRCC_Clocks)333 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *pRCC_Clocks)
334 {
335 /* Get SYSCLK frequency */
336 pRCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
337
338 /* HCLK clock frequency */
339 pRCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(pRCC_Clocks->SYSCLK_Frequency);
340
341 /* PCLK1 clock frequency */
342 pRCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(pRCC_Clocks->HCLK_Frequency);
343
344 /* PCLK2 clock frequency */
345 pRCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(pRCC_Clocks->HCLK_Frequency);
346
347 /* PCLK3 clock frequency */
348 pRCC_Clocks->PCLK3_Frequency = RCC_GetPCLK3ClockFreq(pRCC_Clocks->HCLK_Frequency);
349 }
350
351 /**
352 * @brief Return PLL1 clocks frequencies
353 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
354 * @retval None
355 */
LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef * pPLL_Clocks)356 void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *pPLL_Clocks)
357 {
358 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
359 uint32_t pllsource;
360 uint32_t pllm;
361 uint32_t plln;
362 uint32_t fracn = 0U;
363
364 /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
365 SYSCLK = PLL_VCO / PLLP
366 */
367 pllsource = LL_RCC_PLL1_GetSource();
368
369 switch (pllsource)
370 {
371 case LL_RCC_PLL1SOURCE_HSI:
372 if (LL_RCC_HSI_IsReady() != 0U)
373 {
374 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
375 }
376 break;
377
378 case LL_RCC_PLL1SOURCE_CSI:
379 if (LL_RCC_CSI_IsReady() != 0U)
380 {
381 pllinputfreq = CSI_VALUE;
382 }
383 break;
384
385 case LL_RCC_PLL1SOURCE_HSE:
386 if (LL_RCC_HSE_IsReady() != 0U)
387 {
388 pllinputfreq = HSE_VALUE;
389 }
390 break;
391
392 case LL_RCC_PLL1SOURCE_NONE:
393 default:
394 /* PLL clock disabled */
395 break;
396 }
397
398 pPLL_Clocks->PLL_P_Frequency = 0U;
399 pPLL_Clocks->PLL_Q_Frequency = 0U;
400 pPLL_Clocks->PLL_R_Frequency = 0U;
401
402 pllm = LL_RCC_PLL1_GetM();
403 plln = LL_RCC_PLL1_GetN();
404 if (LL_RCC_PLL1FRACN_IsEnabled() != 0U)
405 {
406 fracn = LL_RCC_PLL1_GetFRACN();
407 }
408
409 if (pllm != 0U)
410 {
411 if (LL_RCC_PLL1P_IsEnabled() != 0U)
412 {
413 pPLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL1_GetP());
414 }
415
416 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
417 {
418 pPLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL1_GetQ());
419 }
420
421 if (LL_RCC_PLL1R_IsEnabled() != 0U)
422 {
423 pPLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL1_GetR());
424 }
425 }
426 }
427
428 /**
429 * @brief Return PLL2 clocks frequencies
430 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
431 * @retval None
432 */
LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef * pPLL_Clocks)433 void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *pPLL_Clocks)
434 {
435 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
436 uint32_t pllsource;
437 uint32_t pllm;
438 uint32_t plln;
439 uint32_t fracn = 0U;
440
441 /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
442 SYSCLK = PLL_VCO / PLLP
443 */
444 pllsource = LL_RCC_PLL2_GetSource();
445
446 switch (pllsource)
447 {
448 case LL_RCC_PLL2SOURCE_HSI:
449 if (LL_RCC_HSI_IsReady() != 0U)
450 {
451 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
452 }
453 break;
454
455 case LL_RCC_PLL2SOURCE_CSI:
456 if (LL_RCC_CSI_IsReady() != 0U)
457 {
458 pllinputfreq = CSI_VALUE;
459 }
460 break;
461
462 case LL_RCC_PLL2SOURCE_HSE:
463 if (LL_RCC_HSE_IsReady() != 0U)
464 {
465 pllinputfreq = HSE_VALUE;
466 }
467 break;
468
469 case LL_RCC_PLL2SOURCE_NONE:
470 default:
471 /* PLL clock disabled */
472 break;
473 }
474
475 pPLL_Clocks->PLL_P_Frequency = 0U;
476 pPLL_Clocks->PLL_Q_Frequency = 0U;
477 pPLL_Clocks->PLL_R_Frequency = 0U;
478
479 pllm = LL_RCC_PLL2_GetM();
480 plln = LL_RCC_PLL2_GetN();
481 if (LL_RCC_PLL2FRACN_IsEnabled() != 0U)
482 {
483 fracn = LL_RCC_PLL2_GetFRACN();
484 }
485
486 if (pllm != 0U)
487 {
488 if (LL_RCC_PLL2P_IsEnabled() != 0U)
489 {
490 pPLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL2_GetP());
491 }
492
493 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
494 {
495 pPLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL2_GetQ());
496 }
497
498 if (LL_RCC_PLL2R_IsEnabled() != 0U)
499 {
500 pPLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL2_GetR());
501 }
502 }
503 }
504
505 #if defined(RCC_CR_PLL3ON)
506 /**
507 * @brief Return PLL3 clocks frequencies
508 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
509 * @retval None
510 */
LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef * pPLL_Clocks)511 void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *pPLL_Clocks)
512 {
513 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
514 uint32_t pllsource;
515 uint32_t pllm;
516 uint32_t plln;
517 uint32_t fracn = 0U;
518
519 /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
520 SYSCLK = PLL_VCO / PLLP
521 */
522 pllsource = LL_RCC_PLL3_GetSource();
523
524 switch (pllsource)
525 {
526 case LL_RCC_PLL3SOURCE_HSI:
527 if (LL_RCC_HSI_IsReady() != 0U)
528 {
529 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
530 }
531 break;
532
533 case LL_RCC_PLL3SOURCE_CSI:
534 if (LL_RCC_CSI_IsReady() != 0U)
535 {
536 pllinputfreq = CSI_VALUE;
537 }
538 break;
539
540 case LL_RCC_PLL3SOURCE_HSE:
541 if (LL_RCC_HSE_IsReady() != 0U)
542 {
543 pllinputfreq = HSE_VALUE;
544 }
545 break;
546
547 case LL_RCC_PLL3SOURCE_NONE:
548 default:
549 /* PLL clock disabled */
550 break;
551 }
552
553 pPLL_Clocks->PLL_P_Frequency = 0U;
554 pPLL_Clocks->PLL_Q_Frequency = 0U;
555 pPLL_Clocks->PLL_R_Frequency = 0U;
556
557 pllm = LL_RCC_PLL3_GetM();
558 plln = LL_RCC_PLL3_GetN();
559 if (LL_RCC_PLL3FRACN_IsEnabled() != 0U)
560 {
561 fracn = LL_RCC_PLL3_GetFRACN();
562 }
563
564 if ((pllm != 0U) && (pllinputfreq != 0U))
565 {
566 if (LL_RCC_PLL3P_IsEnabled() != 0U)
567 {
568 pPLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL3_GetP());
569 }
570
571 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
572 {
573 pPLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL3_GetQ());
574 }
575
576 if (LL_RCC_PLL3R_IsEnabled() != 0U)
577 {
578 pPLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, pllm, plln, fracn, LL_RCC_PLL3_GetR());
579 }
580 }
581 }
582 #endif /* PLL3 */
583
584 /**
585 * @brief Helper function to calculate the PLL1 frequency output
586 * @note ex: @ref LL_RCC_CalcPLLClockFreq (HSE_VALUE, @ref LL_RCC_PLL1_GetM (),
587 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetFRACN (), @ref LL_RCC_PLL1_GetP ());
588 * @param PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/CSI)
589 * @param M Between 1 and 63
590 * @param N Between 4 and 512
591 * @param FRACN Between 0 and 0x1FFF
592 * @param PQR VCO output divider (P, Q or R)
593 * Between 1 and 128, except for PLL1P Odd value not allowed
594 * @retval PLL1 output clock frequency (in Hz)
595 */
LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq,uint32_t M,uint32_t N,uint32_t FRACN,uint32_t PQR)596 uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR)
597 {
598 float_t freq;
599
600 freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN / (float_t)0x2000));
601
602 freq = freq / (float_t)PQR;
603
604 return (uint32_t)freq;
605 }
606
607
608 /**
609 * @brief Return USARTx clock frequency
610 * @param USARTxSource This parameter can be one of the following values:
611 * @arg @ref LL_RCC_USART1_CLKSOURCE
612 * @arg @ref LL_RCC_USART2_CLKSOURCE
613 * @arg @ref LL_RCC_USART3_CLKSOURCE
614 * @arg @ref LL_RCC_USART6_CLKSOURCE (*)
615 * @arg @ref LL_RCC_USART10_CLKSOURCE (*)
616 * @arg @ref LL_RCC_USART11_CLKSOURCE (*)
617 *
618 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
619 * @retval USART clock frequency (in Hz)
620 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
621 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)622 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
623 {
624 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
625 LL_PLL_ClocksTypeDef PLL_Clocks;
626
627 /* Check parameter */
628 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
629
630 if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
631 {
632 /* USART1CLK clock frequency */
633 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
634 {
635 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
636 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
637 break;
638
639 case LL_RCC_USART1_CLKSOURCE_PLL2Q: /* USART1 Clock is PLL2 Q */
640 if (LL_RCC_PLL2_IsReady() != 0U)
641 {
642 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
643 {
644 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
645 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
646 }
647 }
648 break;
649
650 #if defined(LL_RCC_USART1_CLKSOURCE_PLL3Q)
651 case LL_RCC_USART1_CLKSOURCE_PLL3Q: /* USART1 Clock is PLL3 Q */
652 if (LL_RCC_PLL3_IsReady() != 0U)
653 {
654 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
655 {
656 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
657 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
658 }
659 }
660 break;
661 #endif /* LL_RCC_USART1_CLKSOURCE_PLL3 */
662
663 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
664 if (LL_RCC_HSI_IsReady() == 1U)
665 {
666 usart_frequency = HSI_VALUE;
667 }
668 break;
669
670 case LL_RCC_USART1_CLKSOURCE_CSI: /* USART1 Clock is CSI Osc. */
671 if (LL_RCC_CSI_IsReady() == 1U)
672 {
673 usart_frequency = CSI_VALUE;
674 }
675 break;
676
677 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
678 if (LL_RCC_LSE_IsReady() == 1U)
679 {
680 usart_frequency = LSE_VALUE;
681 }
682 break;
683
684 default:
685 /* unreachable code */
686 break;
687 }
688 }
689 else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
690 {
691 /* USART2CLK clock frequency */
692 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
693 {
694 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
695 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
696 break;
697
698 case LL_RCC_USART2_CLKSOURCE_PLL2Q: /* USART2 Clock is PLL2 Q */
699 if (LL_RCC_PLL2_IsReady() != 0U)
700 {
701 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
702 {
703 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
704 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
705 }
706 }
707 break;
708
709 #if defined(LL_RCC_USART2_CLKSOURCE_PLL3Q)
710 case LL_RCC_USART2_CLKSOURCE_PLL3Q: /* USART2 Clock is PLL3 Q */
711 if (LL_RCC_PLL3_IsReady() != 0U)
712 {
713 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
714 {
715 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
716 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
717 }
718 }
719 break;
720 #endif /* LL_RCC_USART2_CLKSOURCE_PLL3 */
721
722 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
723 if (LL_RCC_HSI_IsReady() == 1U)
724 {
725 usart_frequency = HSI_VALUE;
726 }
727 break;
728
729 case LL_RCC_USART2_CLKSOURCE_CSI: /* USART2 Clock is CSI Osc. */
730 if (LL_RCC_CSI_IsReady() == 1U)
731 {
732 usart_frequency = CSI_VALUE;
733 }
734 break;
735
736 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
737 if (LL_RCC_LSE_IsReady() == 1U)
738 {
739 usart_frequency = LSE_VALUE;
740 }
741 break;
742
743 default:
744 /* unreachable code */
745 break;
746 }
747 }
748 else if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
749 {
750 /* USART3CLK clock frequency */
751 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
752 {
753 case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
754 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
755 break;
756
757 case LL_RCC_USART3_CLKSOURCE_PLL2Q: /* USART3 Clock is PLL2 Q */
758 if (LL_RCC_PLL2_IsReady() != 0U)
759 {
760 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
761 {
762 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
763 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
764 }
765 }
766 break;
767
768 #if defined(LL_RCC_USART3_CLKSOURCE_PLL3Q)
769 case LL_RCC_USART3_CLKSOURCE_PLL3Q: /* USART3 Clock is PLL3 Q */
770 if (LL_RCC_PLL3_IsReady() != 0U)
771 {
772 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
773 {
774 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
775 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
776 }
777 }
778 break;
779 #endif /* LL_RCC_USART3_CLKSOURCE_PLL3 */
780
781 case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
782 if (LL_RCC_HSI_IsReady() == 1U)
783 {
784 usart_frequency = HSI_VALUE;
785 }
786 break;
787
788 case LL_RCC_USART3_CLKSOURCE_CSI: /* USART3 Clock is CSI Osc. */
789 if (LL_RCC_CSI_IsReady() == 1U)
790 {
791 usart_frequency = CSI_VALUE;
792 }
793 break;
794
795 case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
796 if (LL_RCC_LSE_IsReady() == 1U)
797 {
798 usart_frequency = LSE_VALUE;
799 }
800 break;
801
802 default:
803 /* unreachable code */
804 break;
805 }
806 }
807
808 #if defined(USART6)
809 else if (USARTxSource == LL_RCC_USART6_CLKSOURCE)
810 {
811 /* USART6CLK clock frequency */
812 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
813 {
814 case LL_RCC_USART6_CLKSOURCE_PCLK1: /* USART6 Clock is PCLK1 */
815 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
816 break;
817
818 case LL_RCC_USART6_CLKSOURCE_PLL2Q: /* USART6 Clock is PLL2 Q */
819 if (LL_RCC_PLL2_IsReady() != 0U)
820 {
821 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
822 {
823 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
824 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
825 }
826 }
827 break;
828
829 case LL_RCC_USART6_CLKSOURCE_PLL3Q: /* USART6 Clock is PLL3 Q */
830 if (LL_RCC_PLL3_IsReady() != 0U)
831 {
832 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
833 {
834 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
835 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
836 }
837 }
838 break;
839
840 case LL_RCC_USART6_CLKSOURCE_HSI: /* USART6 Clock is HSI Osc. */
841 if (LL_RCC_HSI_IsReady() == 1U)
842 {
843 usart_frequency = HSI_VALUE;
844 }
845 break;
846
847 case LL_RCC_USART6_CLKSOURCE_CSI: /* USART6 Clock is CSI Osc. */
848 if (LL_RCC_CSI_IsReady() == 1U)
849 {
850 usart_frequency = CSI_VALUE;
851 }
852 break;
853
854 case LL_RCC_USART6_CLKSOURCE_LSE: /* USART6 Clock is LSE Osc. */
855 if (LL_RCC_LSE_IsReady() == 1U)
856 {
857 usart_frequency = LSE_VALUE;
858 }
859 break;
860
861 default:
862 /* unreachable code */
863 break;
864 }
865 }
866 #endif /* USART6 */
867
868 #if defined(USART10)
869 else if (USARTxSource == LL_RCC_USART10_CLKSOURCE)
870 {
871 /* USART10CLK clock frequency */
872 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
873 {
874 case LL_RCC_USART10_CLKSOURCE_PCLK1: /* USART10 Clock is PCLK1 */
875 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
876 break;
877
878 case LL_RCC_USART10_CLKSOURCE_PLL2Q: /* USART10 Clock is PLL2 Q */
879 if (LL_RCC_PLL2_IsReady() != 0U)
880 {
881 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
882 {
883 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
884 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
885 }
886 }
887 break;
888
889 case LL_RCC_USART10_CLKSOURCE_PLL3Q: /* USART10 Clock is PLL3 Q */
890 if (LL_RCC_PLL3_IsReady() != 0U)
891 {
892 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
893 {
894 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
895 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
896 }
897 }
898 break;
899
900 case LL_RCC_USART10_CLKSOURCE_HSI: /* USART10 Clock is HSI Osc. */
901 if (LL_RCC_HSI_IsReady() == 1U)
902 {
903 usart_frequency = HSI_VALUE;
904 }
905 break;
906
907 case LL_RCC_USART10_CLKSOURCE_CSI: /* USART10 Clock is CSI Osc. */
908 if (LL_RCC_CSI_IsReady() == 1U)
909 {
910 usart_frequency = CSI_VALUE;
911 }
912 break;
913
914 case LL_RCC_USART10_CLKSOURCE_LSE: /* USART10 Clock is LSE Osc. */
915 if (LL_RCC_LSE_IsReady() == 1U)
916 {
917 usart_frequency = LSE_VALUE;
918 }
919 break;
920
921 default:
922 /* unreachable code */
923 break;
924 }
925 }
926 #endif /* USART10 */
927
928 #if defined(USART11)
929 else if (USARTxSource == LL_RCC_USART11_CLKSOURCE)
930 {
931 /* USART11CLK clock frequency */
932 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
933 {
934 case LL_RCC_USART11_CLKSOURCE_PCLK1: /* USART11 Clock is PCLK1 */
935 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
936 break;
937
938 case LL_RCC_USART11_CLKSOURCE_PLL2Q: /* USART11 Clock is PLL2 Q */
939 if (LL_RCC_PLL2_IsReady() != 0U)
940 {
941 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
942 {
943 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
944 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
945 }
946 }
947 break;
948
949 case LL_RCC_USART11_CLKSOURCE_PLL3Q: /* USART11 Clock is PLL3 Q */
950 if (LL_RCC_PLL3_IsReady() != 0U)
951 {
952 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
953 {
954 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
955 usart_frequency = PLL_Clocks.PLL_Q_Frequency;
956 }
957 }
958 break;
959
960 case LL_RCC_USART11_CLKSOURCE_HSI: /* USART11 Clock is HSI Osc. */
961 if (LL_RCC_HSI_IsReady() == 1U)
962 {
963 usart_frequency = HSI_VALUE;
964 }
965 break;
966
967 case LL_RCC_USART11_CLKSOURCE_CSI: /* USART11 Clock is CSI Osc. */
968 if (LL_RCC_CSI_IsReady() == 1U)
969 {
970 usart_frequency = CSI_VALUE;
971 }
972 break;
973
974 case LL_RCC_USART11_CLKSOURCE_LSE: /* USART11 Clock is LSE Osc. */
975 if (LL_RCC_LSE_IsReady() == 1U)
976 {
977 usart_frequency = LSE_VALUE;
978 }
979 break;
980
981 default:
982 /* unreachable code */
983 break;
984 }
985 }
986 #endif /* USART11 */
987 else
988 {
989 /* nothing to do */
990 }
991
992 return usart_frequency;
993 }
994
995 #if defined(UART4)
996 /**
997 * @brief Return UARTx clock frequency
998 * @param UARTxSource This parameter can be one of the following values:
999 * @arg @ref LL_RCC_UART4_CLKSOURCE
1000 * @arg @ref LL_RCC_UART5_CLKSOURCE
1001 * @arg @ref LL_RCC_UART7_CLKSOURCE
1002 * @arg @ref LL_RCC_UART8_CLKSOURCE
1003 * @arg @ref LL_RCC_UART9_CLKSOURCE
1004 * @arg @ref LL_RCC_UART12_CLKSOURCE
1005 * @retval UART clock frequency (in Hz)
1006 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
1007 */
LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)1008 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
1009 {
1010 uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1011 LL_PLL_ClocksTypeDef PLL_Clocks;
1012
1013 /* Check parameter */
1014 assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
1015
1016 if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
1017 {
1018 /* UART4CLK clock frequency */
1019 switch (LL_RCC_GetUARTClockSource(UARTxSource))
1020 {
1021 case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
1022 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1023 break;
1024
1025 case LL_RCC_UART4_CLKSOURCE_PLL2Q: /* UART4 Clock is PLL2 Q */
1026 if (LL_RCC_PLL2_IsReady() != 0U)
1027 {
1028 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
1029 {
1030 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1031 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1032 }
1033 }
1034 break;
1035
1036 case LL_RCC_UART4_CLKSOURCE_PLL3Q: /* UART4 Clock is PLL3 Q */
1037 if (LL_RCC_PLL3_IsReady() != 0U)
1038 {
1039 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
1040 {
1041 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1042 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1043 }
1044 }
1045 break;
1046
1047 case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
1048 if (LL_RCC_HSI_IsReady() == 1U)
1049 {
1050 uart_frequency = HSI_VALUE;
1051 }
1052 break;
1053
1054 case LL_RCC_UART4_CLKSOURCE_CSI: /* UART4 Clock is CSI Osc. */
1055 if (LL_RCC_CSI_IsReady() == 1U)
1056 {
1057 uart_frequency = CSI_VALUE;
1058 }
1059 break;
1060
1061 case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
1062 if (LL_RCC_LSE_IsReady() == 1U)
1063 {
1064 uart_frequency = LSE_VALUE;
1065 }
1066 break;
1067
1068 default:
1069 /* unreachable code */
1070 break;
1071 }
1072 }
1073 else if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
1074 {
1075 /* UART5CLK clock frequency */
1076 switch (LL_RCC_GetUARTClockSource(UARTxSource))
1077 {
1078 case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
1079 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1080 break;
1081
1082 case LL_RCC_UART5_CLKSOURCE_PLL2Q: /* UART5 Clock is PLL2 Q */
1083 if (LL_RCC_PLL2_IsReady() != 0U)
1084 {
1085 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
1086 {
1087 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1088 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1089 }
1090 }
1091 break;
1092
1093 case LL_RCC_UART5_CLKSOURCE_PLL3Q: /* UART5 Clock is PLL3 Q */
1094 if (LL_RCC_PLL3_IsReady() != 0U)
1095 {
1096 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
1097 {
1098 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1099 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1100 }
1101 }
1102 break;
1103
1104 case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
1105 if (LL_RCC_HSI_IsReady() == 1U)
1106 {
1107 uart_frequency = HSI_VALUE;
1108 }
1109 break;
1110
1111 case LL_RCC_UART5_CLKSOURCE_CSI: /* UART5 Clock is CSI Osc. */
1112 if (LL_RCC_CSI_IsReady() == 1U)
1113 {
1114 uart_frequency = CSI_VALUE;
1115 }
1116 break;
1117
1118 case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
1119 if (LL_RCC_LSE_IsReady() == 1U)
1120 {
1121 uart_frequency = LSE_VALUE;
1122 }
1123 break;
1124
1125 default:
1126 /* unreachable code */
1127 break;
1128 }
1129 }
1130 else if (UARTxSource == LL_RCC_UART7_CLKSOURCE)
1131 {
1132 /* UART7CLK clock frequency */
1133 switch (LL_RCC_GetUARTClockSource(UARTxSource))
1134 {
1135 case LL_RCC_UART7_CLKSOURCE_PCLK1: /* UART7 Clock is PCLK1 */
1136 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1137 break;
1138
1139 case LL_RCC_UART7_CLKSOURCE_PLL2Q: /* UART7 Clock is PLL2 Q */
1140 if (LL_RCC_PLL2_IsReady() != 0U)
1141 {
1142 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
1143 {
1144 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1145 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1146 }
1147 }
1148 break;
1149
1150 case LL_RCC_UART7_CLKSOURCE_PLL3Q: /* UART7 Clock is PLL3 Q */
1151 if (LL_RCC_PLL3_IsReady() != 0U)
1152 {
1153 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
1154 {
1155 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1156 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1157 }
1158 }
1159 break;
1160
1161 case LL_RCC_UART7_CLKSOURCE_HSI: /* UART7 Clock is HSI Osc. */
1162 if (LL_RCC_HSI_IsReady() == 1U)
1163 {
1164 uart_frequency = HSI_VALUE;
1165 }
1166 break;
1167
1168 case LL_RCC_UART7_CLKSOURCE_CSI: /* UART7 Clock is CSI Osc. */
1169 if (LL_RCC_CSI_IsReady() == 1U)
1170 {
1171 uart_frequency = CSI_VALUE;
1172 }
1173 break;
1174
1175 case LL_RCC_UART7_CLKSOURCE_LSE: /* UART7 Clock is LSE Osc. */
1176 if (LL_RCC_LSE_IsReady() == 1U)
1177 {
1178 uart_frequency = LSE_VALUE;
1179 }
1180 break;
1181
1182 default:
1183 /* unreachable code */
1184 break;
1185 }
1186 }
1187 else if (UARTxSource == LL_RCC_UART8_CLKSOURCE)
1188 {
1189 /* UART8CLK clock frequency */
1190 switch (LL_RCC_GetUARTClockSource(UARTxSource))
1191 {
1192 case LL_RCC_UART8_CLKSOURCE_PCLK1: /* UART8 Clock is PCLK1 */
1193 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1194 break;
1195
1196 case LL_RCC_UART8_CLKSOURCE_PLL2Q: /* UART8 Clock is PLL2 Q */
1197 if (LL_RCC_PLL2_IsReady() != 0U)
1198 {
1199 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
1200 {
1201 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1202 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1203 }
1204 }
1205 break;
1206
1207 case LL_RCC_UART8_CLKSOURCE_PLL3Q: /* UART8 Clock is PLL3 Q */
1208 if (LL_RCC_PLL3_IsReady() != 0U)
1209 {
1210 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
1211 {
1212 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1213 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1214 }
1215 }
1216 break;
1217
1218 case LL_RCC_UART8_CLKSOURCE_HSI: /* UART8 Clock is HSI Osc. */
1219 if (LL_RCC_HSI_IsReady() == 1U)
1220 {
1221 uart_frequency = HSI_VALUE;
1222 }
1223 break;
1224
1225 case LL_RCC_UART8_CLKSOURCE_CSI: /* UART8 Clock is CSI Osc. */
1226 if (LL_RCC_CSI_IsReady() == 1U)
1227 {
1228 uart_frequency = CSI_VALUE;
1229 }
1230 break;
1231
1232 case LL_RCC_UART8_CLKSOURCE_LSE: /* UART8 Clock is LSE Osc. */
1233 if (LL_RCC_LSE_IsReady() == 1U)
1234 {
1235 uart_frequency = LSE_VALUE;
1236 }
1237 break;
1238
1239 default:
1240 /* unreachable code */
1241 break;
1242 }
1243 }
1244 else if (UARTxSource == LL_RCC_UART9_CLKSOURCE)
1245 {
1246 /* UART9CLK clock frequency */
1247 switch (LL_RCC_GetUARTClockSource(UARTxSource))
1248 {
1249 case LL_RCC_UART9_CLKSOURCE_PCLK1: /* UART9 Clock is PCLK1 */
1250 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1251 break;
1252
1253 case LL_RCC_UART9_CLKSOURCE_PLL2Q: /* UART9 Clock is PLL2 Q */
1254 if (LL_RCC_PLL2_IsReady() != 0U)
1255 {
1256 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
1257 {
1258 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1259 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1260 }
1261 }
1262 break;
1263
1264 case LL_RCC_UART9_CLKSOURCE_PLL3Q: /* UART9 Clock is PLL3 Q */
1265 if (LL_RCC_PLL3_IsReady() != 0U)
1266 {
1267 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
1268 {
1269 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1270 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1271 }
1272 }
1273 break;
1274
1275 case LL_RCC_UART9_CLKSOURCE_HSI: /* UART9 Clock is HSI Osc. */
1276 if (LL_RCC_HSI_IsReady() == 1U)
1277 {
1278 uart_frequency = HSI_VALUE;
1279 }
1280 break;
1281
1282 case LL_RCC_UART9_CLKSOURCE_CSI: /* UART9 Clock is CSI Osc. */
1283 if (LL_RCC_CSI_IsReady() == 1U)
1284 {
1285 uart_frequency = CSI_VALUE;
1286 }
1287 break;
1288
1289 case LL_RCC_UART9_CLKSOURCE_LSE: /* UART9 Clock is LSE Osc. */
1290 if (LL_RCC_LSE_IsReady() == 1U)
1291 {
1292 uart_frequency = LSE_VALUE;
1293 }
1294 break;
1295
1296 default:
1297 /* unreachable code */
1298 break;
1299 }
1300 }
1301 else if (UARTxSource == LL_RCC_UART12_CLKSOURCE)
1302 {
1303 /* UART12CLK clock frequency */
1304 switch (LL_RCC_GetUARTClockSource(UARTxSource))
1305 {
1306 case LL_RCC_UART12_CLKSOURCE_PCLK1: /* UART12 Clock is PCLK1 */
1307 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1308 break;
1309
1310 case LL_RCC_UART12_CLKSOURCE_PLL2Q: /* UART12 Clock is PLL2 Q */
1311 if (LL_RCC_PLL2_IsReady() != 0U)
1312 {
1313 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
1314 {
1315 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1316 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1317 }
1318 }
1319 break;
1320
1321 case LL_RCC_UART12_CLKSOURCE_PLL3Q: /* UART12 Clock is PLL3 Q */
1322 if (LL_RCC_PLL3_IsReady() != 0U)
1323 {
1324 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
1325 {
1326 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1327 uart_frequency = PLL_Clocks.PLL_Q_Frequency;
1328 }
1329 }
1330 break;
1331
1332 case LL_RCC_UART12_CLKSOURCE_HSI: /* UART12 Clock is HSI Osc. */
1333 if (LL_RCC_HSI_IsReady() == 1U)
1334 {
1335 uart_frequency = HSI_VALUE;
1336 }
1337 break;
1338
1339 case LL_RCC_UART12_CLKSOURCE_CSI: /* UART12 Clock is CSI Osc. */
1340 if (LL_RCC_CSI_IsReady() == 1U)
1341 {
1342 uart_frequency = CSI_VALUE;
1343 }
1344 break;
1345
1346 case LL_RCC_UART12_CLKSOURCE_LSE: /* UART12 Clock is LSE Osc. */
1347 if (LL_RCC_LSE_IsReady() == 1U)
1348 {
1349 uart_frequency = LSE_VALUE;
1350 }
1351 break;
1352
1353 default:
1354 /* unreachable code */
1355 break;
1356 }
1357 }
1358 else
1359 {
1360 /* nothing to do */
1361 }
1362
1363 return uart_frequency;
1364 }
1365 #endif /* UART4 */
1366
1367 /**
1368 * @brief Return SPIx clock frequency
1369 * @param SPIxSource This parameter can be one of the following values:
1370 * @arg @ref LL_RCC_SPI1_CLKSOURCE
1371 * @arg @ref LL_RCC_SPI2_CLKSOURCE
1372 * @arg @ref LL_RCC_SPI3_CLKSOURCE
1373 * @arg @ref LL_RCC_SPI4_CLKSOURCE (*)
1374 * @arg @ref LL_RCC_SPI5_CLKSOURCE (*)
1375 * @arg @ref LL_RCC_SPI6_CLKSOURCE (*)
1376 *
1377 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
1378 * @retval SPI clock frequency (in Hz)
1379 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
1380 */
LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)1381 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
1382 {
1383 uint32_t spi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1384 LL_PLL_ClocksTypeDef PLL_Clocks;
1385
1386 /* Check parameter */
1387 assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource));
1388
1389 if (SPIxSource == LL_RCC_SPI1_CLKSOURCE)
1390 {
1391 /* SPI1 CLK clock frequency */
1392 switch (LL_RCC_GetSPIClockSource(SPIxSource))
1393 {
1394 case LL_RCC_SPI1_CLKSOURCE_PLL1Q: /* SPI1 Clock is PLL1 Q */
1395 if (LL_RCC_PLL1_IsReady() != 0U)
1396 {
1397 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
1398 {
1399 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1400 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1401 }
1402 }
1403 break;
1404
1405 case LL_RCC_SPI1_CLKSOURCE_PLL2P: /* SPI1 Clock is PLL2 P */
1406 if (LL_RCC_PLL2_IsReady() != 0U)
1407 {
1408 if (LL_RCC_PLL2P_IsEnabled() != 0U)
1409 {
1410 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1411 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1412 }
1413 }
1414 break;
1415
1416 #if defined(LL_RCC_SPI1_CLKSOURCE_PLL3P)
1417 case LL_RCC_SPI1_CLKSOURCE_PLL3P: /* SPI1 Clock is PLL3 P */
1418 if (LL_RCC_PLL3_IsReady() != 0U)
1419 {
1420 if (LL_RCC_PLL3P_IsEnabled() != 0U)
1421 {
1422 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1423 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1424 }
1425 }
1426 break;
1427 #endif /* PLL3 */
1428
1429 case LL_RCC_SPI1_CLKSOURCE_PIN: /* SPI1 Clock is External Clock */
1430 spi_frequency = EXTERNAL_CLOCK_VALUE;
1431 break;
1432
1433 case LL_RCC_SPI1_CLKSOURCE_CLKP: /* SPI1 Clock is CLKP */
1434 spi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
1435 break;
1436
1437 default:
1438 /* unreachable code */
1439 break;
1440 }
1441 }
1442 else if (SPIxSource == LL_RCC_SPI2_CLKSOURCE)
1443 {
1444 /* SPI2 CLK clock frequency */
1445 switch (LL_RCC_GetSPIClockSource(SPIxSource))
1446 {
1447 case LL_RCC_SPI2_CLKSOURCE_PLL1Q: /* SPI2 Clock is PLL1 Q */
1448 if (LL_RCC_PLL1_IsReady() != 0U)
1449 {
1450 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
1451 {
1452 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1453 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1454 }
1455 }
1456 break;
1457
1458 case LL_RCC_SPI2_CLKSOURCE_PLL2P: /* SPI2 Clock is PLL2 P */
1459 if (LL_RCC_PLL2_IsReady() != 0U)
1460 {
1461 if (LL_RCC_PLL2P_IsEnabled() != 0U)
1462 {
1463 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1464 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1465 }
1466 }
1467 break;
1468
1469 #if defined(LL_RCC_SPI2_CLKSOURCE_PLL3P)
1470 case LL_RCC_SPI2_CLKSOURCE_PLL3P: /* SPI2 Clock is PLL3 P */
1471 if (LL_RCC_PLL3_IsReady() != 0U)
1472 {
1473 if (LL_RCC_PLL3P_IsEnabled() != 0U)
1474 {
1475 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1476 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1477 }
1478 }
1479 break;
1480 #endif /* PLL3 */
1481
1482 case LL_RCC_SPI2_CLKSOURCE_PIN: /* SPI2 Clock is External Clock */
1483 spi_frequency = EXTERNAL_CLOCK_VALUE;
1484 break;
1485
1486 case LL_RCC_SPI2_CLKSOURCE_CLKP: /* SPI2 Clock is CLKP */
1487 spi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
1488 break;
1489
1490 default:
1491 /* unreachable code */
1492 break;
1493 }
1494 }
1495 else if (SPIxSource == LL_RCC_SPI3_CLKSOURCE)
1496 {
1497 /* SPI3 CLK clock frequency */
1498 switch (LL_RCC_GetSPIClockSource(SPIxSource))
1499 {
1500 case LL_RCC_SPI3_CLKSOURCE_PLL1Q: /* SPI3 Clock is PLL1 Q */
1501 if (LL_RCC_PLL1_IsReady() != 0U)
1502 {
1503 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
1504 {
1505 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
1506 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1507 }
1508 }
1509 break;
1510
1511 case LL_RCC_SPI3_CLKSOURCE_PLL2P: /* SPI3 Clock is PLL2 P*/
1512 if (LL_RCC_PLL2_IsReady() != 0U)
1513 {
1514 if (LL_RCC_PLL2P_IsEnabled() != 0U)
1515 {
1516 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1517 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1518 }
1519 }
1520 break;
1521
1522 #if defined(LL_RCC_SPI3_CLKSOURCE_PLL3P)
1523 case LL_RCC_SPI3_CLKSOURCE_PLL3P: /* SPI3 Clock is PLL3 P*/
1524 if (LL_RCC_PLL3_IsReady() != 0U)
1525 {
1526 if (LL_RCC_PLL3P_IsEnabled() != 0U)
1527 {
1528 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1529 spi_frequency = PLL_Clocks.PLL_P_Frequency;
1530 }
1531 }
1532 break;
1533 #endif /* PLL3 */
1534 case LL_RCC_SPI3_CLKSOURCE_PIN: /* SPI3 Clock is External Clock */
1535 spi_frequency = EXTERNAL_CLOCK_VALUE;
1536 break;
1537
1538 case LL_RCC_SPI3_CLKSOURCE_CLKP: /* SPI3 Clock is CLKP */
1539 spi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
1540 break;
1541
1542 default:
1543 /* unreachable code */
1544 break;
1545 }
1546 }
1547 #if defined(SPI4)
1548 else if (SPIxSource == LL_RCC_SPI4_CLKSOURCE)
1549 {
1550 /* SPI4 CLK clock frequency */
1551 switch (LL_RCC_GetSPIClockSource(SPIxSource))
1552 {
1553 case LL_RCC_SPI4_CLKSOURCE_PCLK2: /* SPI4 Clock is PCLK2 */
1554 spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1555 break;
1556
1557 case LL_RCC_SPI4_CLKSOURCE_PLL2Q: /* SPI4 Clock is PLL2 Q*/
1558 if (LL_RCC_PLL2_IsReady() != 0U)
1559 {
1560 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
1561 {
1562 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1563 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1564 }
1565 }
1566 break;
1567
1568 case LL_RCC_SPI4_CLKSOURCE_PLL3Q: /* SPI4 Clock is PLL3 Q*/
1569 if (LL_RCC_PLL3_IsReady() != 0U)
1570 {
1571 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
1572 {
1573 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1574 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1575 }
1576 }
1577 break;
1578
1579 case LL_RCC_SPI4_CLKSOURCE_HSI: /* SPI4 Clock is HSI Osc. */
1580 if (LL_RCC_HSI_IsReady() == 1U)
1581 {
1582 spi_frequency = HSI_VALUE;
1583 }
1584 break;
1585
1586 case LL_RCC_SPI4_CLKSOURCE_CSI: /* SPI4 Clock is CSI Osc. */
1587 if (LL_RCC_CSI_IsReady() == 1U)
1588 {
1589 spi_frequency = CSI_VALUE;
1590 }
1591 break;
1592
1593 case LL_RCC_SPI4_CLKSOURCE_HSE: /* SPI4 Clock is HSE Osc. */
1594 if (LL_RCC_HSE_IsReady() == 1U)
1595 {
1596 spi_frequency = HSE_VALUE;
1597 }
1598 break;
1599
1600 default:
1601 /* unreachable code */
1602 break;
1603 }
1604 }
1605 #endif /* SPI4 */
1606 #if defined(SPI5)
1607 else if (SPIxSource == LL_RCC_SPI5_CLKSOURCE)
1608 {
1609 /* SPI5 CLK clock frequency */
1610 switch (LL_RCC_GetSPIClockSource(SPIxSource))
1611 {
1612 case LL_RCC_SPI5_CLKSOURCE_PCLK3: /* SPI5 Clock is PCLK3 */
1613 spi_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1614 break;
1615
1616 case LL_RCC_SPI5_CLKSOURCE_PLL2Q: /* SPI5 Clock is PLL2 Q*/
1617 if (LL_RCC_PLL2_IsReady() != 0U)
1618 {
1619 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
1620 {
1621 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1622 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1623 }
1624 }
1625 break;
1626
1627 case LL_RCC_SPI5_CLKSOURCE_PLL3Q: /* SPI5 Clock is PLL3 Q*/
1628 if (LL_RCC_PLL3_IsReady() != 0U)
1629 {
1630 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
1631 {
1632 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1633 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1634 }
1635 }
1636 break;
1637
1638 case LL_RCC_SPI5_CLKSOURCE_HSI: /* SPI5 Clock is HSI Osc. */
1639 if (LL_RCC_HSI_IsReady() == 1U)
1640 {
1641 spi_frequency = HSI_VALUE;
1642 }
1643 break;
1644
1645 case LL_RCC_SPI5_CLKSOURCE_CSI: /* SPI5 Clock is CSI Osc. */
1646 if (LL_RCC_CSI_IsReady() == 1U)
1647 {
1648 spi_frequency = CSI_VALUE;
1649 }
1650 break;
1651
1652 case LL_RCC_SPI5_CLKSOURCE_HSE: /* SPI5 Clock is HSE Osc. */
1653 if (LL_RCC_HSE_IsReady() == 1U)
1654 {
1655 spi_frequency = HSE_VALUE;
1656 }
1657 break;
1658
1659 default:
1660 /* unreachable code */
1661 break;
1662 }
1663 }
1664 #endif /* SPI5 */
1665 #if defined(SPI6)
1666 else if (SPIxSource == LL_RCC_SPI6_CLKSOURCE)
1667 {
1668 /* SPI6 CLK clock frequency */
1669 switch (LL_RCC_GetSPIClockSource(SPIxSource))
1670 {
1671 case LL_RCC_SPI6_CLKSOURCE_PCLK2: /* SPI6 Clock is PCLK2 */
1672 spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1673 break;
1674
1675 case LL_RCC_SPI6_CLKSOURCE_PLL2Q: /* SPI6 Clock is PLL2 Q*/
1676 if (LL_RCC_PLL2_IsReady() != 0U)
1677 {
1678 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
1679 {
1680 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1681 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1682 }
1683 }
1684 break;
1685
1686 case LL_RCC_SPI6_CLKSOURCE_PLL3Q: /* SPI6 Clock is PLL3 Q*/
1687 if (LL_RCC_PLL3_IsReady() != 0U)
1688 {
1689 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
1690 {
1691 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1692 spi_frequency = PLL_Clocks.PLL_Q_Frequency;
1693 }
1694 }
1695 break;
1696
1697 case LL_RCC_SPI6_CLKSOURCE_HSI: /* SPI6 Clock is HSI Osc. */
1698 if (LL_RCC_HSI_IsReady() == 1U)
1699 {
1700 spi_frequency = HSI_VALUE;
1701 }
1702 break;
1703
1704 case LL_RCC_SPI6_CLKSOURCE_CSI: /* SPI6 Clock is CSI Osc. */
1705 if (LL_RCC_CSI_IsReady() == 1U)
1706 {
1707 spi_frequency = CSI_VALUE;
1708 }
1709 break;
1710
1711 case LL_RCC_SPI6_CLKSOURCE_HSE: /* SPI6 Clock is HSE Osc. */
1712 if (LL_RCC_HSE_IsReady() == 1U)
1713 {
1714 spi_frequency = HSE_VALUE;
1715 }
1716 break;
1717
1718 default:
1719 /* unreachable code */
1720 break;
1721 }
1722 }
1723 #endif /* SPI6 */
1724
1725 else
1726 {
1727 /* nothing to do */
1728 }
1729
1730 return spi_frequency;
1731 }
1732
1733 /**
1734 * @brief Return I2Cx clock frequency
1735 * @param I2CxSource This parameter can be one of the following values:
1736 * @arg @ref LL_RCC_I2C1_CLKSOURCE
1737 * @arg @ref LL_RCC_I2C2_CLKSOURCE
1738 * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
1739 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
1740 *
1741 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
1742 * @retval I2C clock frequency (in Hz)
1743 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
1744 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)1745 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
1746 {
1747 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1748 LL_PLL_ClocksTypeDef PLL_Clocks;
1749
1750 /* Check parameter */
1751 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
1752
1753 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
1754 {
1755 /* I2C1 CLK clock frequency */
1756 switch (LL_RCC_GetI2CClockSource(I2CxSource))
1757 {
1758 case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
1759 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1760 break;
1761
1762 #if defined(LL_RCC_I2C1_CLKSOURCE_PLL3R)
1763 case LL_RCC_I2C1_CLKSOURCE_PLL3R: /* I2C1 Clock is PLL3 R */
1764 if (LL_RCC_PLL3_IsReady() != 0U)
1765 {
1766 if (LL_RCC_PLL3R_IsEnabled() != 0U)
1767 {
1768 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1769 i2c_frequency = PLL_Clocks.PLL_R_Frequency;
1770 }
1771 }
1772 break;
1773 #else
1774 case LL_RCC_I2C1_CLKSOURCE_PLL2R: /* I2C1 Clock is PLL2 R */
1775 if (LL_RCC_PLL2_IsReady() != 0U)
1776 {
1777 if (LL_RCC_PLL2R_IsEnabled() != 0U)
1778 {
1779 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1780 i2c_frequency = PLL_Clocks.PLL_R_Frequency;
1781 }
1782 }
1783 break;
1784 #endif /* PLL3 */
1785
1786 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
1787 if (LL_RCC_HSI_IsReady() == 1U)
1788 {
1789 i2c_frequency = HSI_VALUE;
1790 }
1791 break;
1792
1793 case LL_RCC_I2C1_CLKSOURCE_CSI: /* I2C1 Clock is CSI Osc. */
1794 if (LL_RCC_CSI_IsReady() == 1U)
1795 {
1796 i2c_frequency = CSI_VALUE;
1797 }
1798 break;
1799
1800 default:
1801 /* unreachable code */
1802 break;
1803 }
1804 }
1805 else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
1806 {
1807 /* I2C2 CLK clock frequency */
1808 switch (LL_RCC_GetI2CClockSource(I2CxSource))
1809 {
1810 case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
1811 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1812 break;
1813
1814 #if defined(LL_RCC_I2C2_CLKSOURCE_PLL3R)
1815 case LL_RCC_I2C2_CLKSOURCE_PLL3R: /* I2C2 Clock is PLL3 R */
1816 if (LL_RCC_PLL3_IsReady() != 0U)
1817 {
1818 if (LL_RCC_PLL3R_IsEnabled() != 0U)
1819 {
1820 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1821 i2c_frequency = PLL_Clocks.PLL_R_Frequency;
1822 }
1823 }
1824 break;
1825 #else
1826 case LL_RCC_I2C2_CLKSOURCE_PLL2R: /* I2C2 Clock is PLL2 R */
1827 if (LL_RCC_PLL2_IsReady() != 0U)
1828 {
1829 if (LL_RCC_PLL2R_IsEnabled() != 0U)
1830 {
1831 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1832 i2c_frequency = PLL_Clocks.PLL_R_Frequency;
1833 }
1834 }
1835 break;
1836 #endif /* PLL3 */
1837
1838 case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
1839 if (LL_RCC_HSI_IsReady() == 1U)
1840 {
1841 i2c_frequency = HSI_VALUE;
1842 }
1843 break;
1844
1845 case LL_RCC_I2C2_CLKSOURCE_CSI: /* I2C2 Clock is CSI Osc. */
1846 if (LL_RCC_CSI_IsReady() == 1U)
1847 {
1848 i2c_frequency = CSI_VALUE;
1849 }
1850 break;
1851
1852 default:
1853 /* unreachable code */
1854 break;
1855 }
1856 }
1857 #if defined(I2C3)
1858 else if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
1859 {
1860 /* I2C3 CLK clock frequency */
1861 switch (LL_RCC_GetI2CClockSource(I2CxSource))
1862
1863 {
1864 case LL_RCC_I2C3_CLKSOURCE_PCLK3: /* I2C3 Clock is PCLK3 */
1865 i2c_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1866 break;
1867
1868 case LL_RCC_I2C3_CLKSOURCE_PLL3R: /* I2C3 Clock is PLL3 R */
1869 if (LL_RCC_PLL3_IsReady() != 0U)
1870 {
1871 if (LL_RCC_PLL3R_IsEnabled() != 0U)
1872 {
1873 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1874 i2c_frequency = PLL_Clocks.PLL_R_Frequency;
1875 }
1876 }
1877 break;
1878
1879 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
1880 if (LL_RCC_HSI_IsReady() == 1U)
1881 {
1882 i2c_frequency = HSI_VALUE;
1883 }
1884 break;
1885
1886 case LL_RCC_I2C3_CLKSOURCE_CSI: /* I2C3 Clock is CSI Osc. */
1887 if (LL_RCC_CSI_IsReady() == 1U)
1888 {
1889 i2c_frequency = CSI_VALUE;
1890 }
1891 break;
1892
1893 default:
1894 /* unreachable code */
1895 break;
1896 }
1897 }
1898 #endif /* I2C3 */
1899 #if defined(I2C4)
1900 else if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
1901 {
1902 /* I2C4 CLK clock frequency */
1903 switch (LL_RCC_GetI2CClockSource(I2CxSource))
1904 {
1905 case LL_RCC_I2C4_CLKSOURCE_PCLK3: /* I2C4 Clock is PCLK3 */
1906 i2c_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1907 break;
1908
1909 case LL_RCC_I2C4_CLKSOURCE_PLL3R: /* I2C4 Clock is PLL3 R */
1910 if (LL_RCC_PLL3_IsReady() != 0U)
1911 {
1912 if (LL_RCC_PLL3R_IsEnabled() != 0U)
1913 {
1914 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1915 i2c_frequency = PLL_Clocks.PLL_R_Frequency;
1916 }
1917 }
1918 break;
1919
1920 case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */
1921 if (LL_RCC_HSI_IsReady() == 1U)
1922 {
1923 i2c_frequency = HSI_VALUE;
1924 }
1925 break;
1926
1927 case LL_RCC_I2C4_CLKSOURCE_CSI: /* I2C4 Clock is CSI Osc. */
1928 if (LL_RCC_CSI_IsReady() == 1U)
1929 {
1930 i2c_frequency = CSI_VALUE;
1931 }
1932 break;
1933
1934 default:
1935 /* unreachable code */
1936 break;
1937 }
1938 }
1939 #endif /* I2C4 */
1940 else
1941 {
1942 /* nothing to do */
1943 }
1944
1945 return i2c_frequency;
1946 }
1947
1948 /**
1949 * @brief Return I3Cx clock frequency
1950 * @param I3CxSource This parameter can be one of the following values:
1951 * @arg @ref LL_RCC_I3C1_CLKSOURCE
1952 * @arg @ref LL_RCC_I3C2_CLKSOURCE (*)
1953 *
1954 * (*) : For stm32h503xx family line only.
1955 * @retval I3C clock frequency (in Hz)
1956 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready or no clock is selected
1957 */
LL_RCC_GetI3CClockFreq(uint32_t I3CxSource)1958 uint32_t LL_RCC_GetI3CClockFreq(uint32_t I3CxSource)
1959 {
1960 uint32_t I3C_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1961 LL_PLL_ClocksTypeDef PLL_Clocks;
1962
1963 /* Check parameter */
1964 assert_param(IS_LL_RCC_I3C_CLKSOURCE(I3CxSource));
1965
1966
1967 if (I3CxSource == LL_RCC_I3C1_CLKSOURCE)
1968 {
1969 /* I3C1 CLK clock frequency */
1970 switch (LL_RCC_GetI3CClockSource(I3CxSource))
1971 {
1972 case LL_RCC_I3C1_CLKSOURCE_PCLK1: /* I3C1 Clock is PCLK1 */
1973 I3C_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1974 break;
1975
1976 #if defined(LL_RCC_I3C1_CLKSOURCE_PLL3R)
1977 case LL_RCC_I3C1_CLKSOURCE_PLL3R: /* I3C1 Clock is PLL3 R */
1978 if (LL_RCC_PLL3_IsReady() != 0U)
1979 {
1980 if (LL_RCC_PLL3R_IsEnabled() != 0U)
1981 {
1982 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
1983 I3C_frequency = PLL_Clocks.PLL_R_Frequency;
1984 }
1985 }
1986 break;
1987 #else
1988 case LL_RCC_I3C1_CLKSOURCE_PLL2R: /* I3C1 Clock is PLL2 R */
1989 if (LL_RCC_PLL2_IsReady() != 0U)
1990 {
1991 if (LL_RCC_PLL2R_IsEnabled() != 0U)
1992 {
1993 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
1994 I3C_frequency = PLL_Clocks.PLL_R_Frequency;
1995 }
1996 }
1997 break;
1998 #endif /* LL_RCC_I3C1_CLKSOURCE_PLL3R */
1999
2000 case LL_RCC_I3C1_CLKSOURCE_HSI: /* I3C1 Clock is HSI Osc. */
2001 if (LL_RCC_HSI_IsReady() == 1U)
2002 {
2003 I3C_frequency = HSI_VALUE;
2004 }
2005 break;
2006
2007 case LL_RCC_I3C1_CLKSOURCE_NONE: /* No Clock used for I3C1 */
2008 break;
2009
2010 default:
2011 /* unreachable code */
2012 break;
2013 }
2014
2015 }
2016
2017 #if defined (I3C2)
2018 else if (I3CxSource == LL_RCC_I3C2_CLKSOURCE)
2019 {
2020 /* I3C2 CLK clock frequency */
2021 switch (LL_RCC_GetI3CClockSource(I3CxSource))
2022 {
2023 case LL_RCC_I3C2_CLKSOURCE_PCLK3: /* I3C2 Clock is PCLK3 */
2024 I3C_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
2025 break;
2026
2027 case LL_RCC_I3C2_CLKSOURCE_PLL2R: /* I3C2 Clock is PLL2 R */
2028 if (LL_RCC_PLL2_IsReady() != 0U)
2029 {
2030 if (LL_RCC_PLL2R_IsEnabled() != 0U)
2031 {
2032 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2033 I3C_frequency = PLL_Clocks.PLL_R_Frequency;
2034 }
2035 }
2036 break;
2037
2038 case LL_RCC_I3C2_CLKSOURCE_HSI: /* I3C2 Clock is HSI Osc. */
2039 if (LL_RCC_HSI_IsReady() == 1U)
2040 {
2041 I3C_frequency = HSI_VALUE;
2042 }
2043 break;
2044
2045 case LL_RCC_I3C2_CLKSOURCE_NONE: /* No Clock used for I3C2 */
2046 break;
2047
2048 default:
2049 /* unreachable code */
2050 break;
2051 }
2052 }
2053 #endif /* I3C2 */
2054 else
2055 {
2056 /* nothing to do */
2057 }
2058
2059 return I3C_frequency;
2060 }
2061
2062 /**
2063 * @brief Return LPUARTx clock frequency
2064 * @param LPUARTxSource This parameter can be one of the following values:
2065 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
2066 * @retval LPUART clock frequency (in Hz)
2067 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
2068 */
LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)2069 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
2070 {
2071 uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2072 LL_PLL_ClocksTypeDef PLL_Clocks;
2073
2074 /* Check parameter */
2075 assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
2076
2077 /* LPUART1CLK clock frequency */
2078 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
2079 {
2080 case LL_RCC_LPUART1_CLKSOURCE_PCLK3: /* LPUART1 Clock is is PCLK3 */
2081 lpuart_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
2082 break;
2083
2084 case LL_RCC_LPUART1_CLKSOURCE_PLL2Q: /* LPUART1 Clock is PLL2 Q */
2085 if (LL_RCC_PLL2_IsReady() != 0U)
2086 {
2087 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
2088 {
2089 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2090 lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
2091 }
2092 }
2093 break;
2094
2095 #if defined(LL_RCC_LPUART1_CLKSOURCE_PLL3Q)
2096 case LL_RCC_LPUART1_CLKSOURCE_PLL3Q: /* LPUART1 Clock is PLL3 Q */
2097 if (LL_RCC_PLL3_IsReady() != 0U)
2098 {
2099 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
2100 {
2101 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2102 lpuart_frequency = PLL_Clocks.PLL_Q_Frequency;
2103 }
2104 }
2105 break;
2106 #endif /* PLL3 */
2107
2108 case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
2109 if (LL_RCC_HSI_IsReady() == 1U)
2110 {
2111 lpuart_frequency = HSI_VALUE;
2112 }
2113 break;
2114
2115 case LL_RCC_LPUART1_CLKSOURCE_CSI: /* LPUART1 Clock is CSI Osc. */
2116 if (LL_RCC_CSI_IsReady() == 1U)
2117 {
2118 lpuart_frequency = CSI_VALUE;
2119 }
2120 break;
2121
2122 case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
2123 if (LL_RCC_LSE_IsReady() == 1U)
2124 {
2125 lpuart_frequency = LSE_VALUE;
2126 }
2127 break;
2128
2129 default:
2130 /* unreachable code */
2131 break;
2132 }
2133
2134 return lpuart_frequency;
2135 }
2136
2137 /**
2138 * @brief Return LPTIMx clock frequency
2139 * @param LPTIMxSource This parameter can be one of the following values:
2140 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
2141 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
2142 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE (*)
2143 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE (*)
2144 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE (*)
2145 * @arg @ref LL_RCC_LPTIM6_CLKSOURCE (*)
2146 *
2147 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
2148 * @retval LPTIM clock frequency (in Hz)
2149 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
2150 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)2151 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
2152 {
2153 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2154 LL_PLL_ClocksTypeDef PLL_Clocks;
2155
2156 /* Check parameter */
2157 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
2158
2159 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
2160 {
2161 /* LPTIM1CLK clock frequency */
2162 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
2163 {
2164 case LL_RCC_LPTIM1_CLKSOURCE_PCLK3: /* LPTIM1 Clock is is PCLK3 */
2165 lptim_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
2166 break;
2167
2168 case LL_RCC_LPTIM1_CLKSOURCE_PLL2P: /* LPTIM1 Clock is PLL2 P */
2169 if (LL_RCC_PLL2_IsReady() != 0U)
2170 {
2171 if (LL_RCC_PLL2P_IsEnabled() != 0U)
2172 {
2173 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2174 lptim_frequency = PLL_Clocks.PLL_P_Frequency;
2175 }
2176 }
2177 break;
2178
2179 #if defined(LL_RCC_LPTIM1_CLKSOURCE_PLL3R)
2180 case LL_RCC_LPTIM1_CLKSOURCE_PLL3R: /* LPTIM1 Clock is PLL3 R */
2181 if (LL_RCC_PLL3_IsReady() != 0U)
2182 {
2183 if (LL_RCC_PLL3R_IsEnabled() != 0U)
2184 {
2185 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2186 lptim_frequency = PLL_Clocks.PLL_R_Frequency;
2187 }
2188 }
2189 break;
2190 #endif /* PLL3 */
2191
2192 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
2193 if (LL_RCC_LSE_IsReady() == 1U)
2194 {
2195 lptim_frequency = LSE_VALUE;
2196 }
2197 break;
2198
2199 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
2200 if (LL_RCC_LSI_IsReady() == 1U)
2201 {
2202 lptim_frequency = LSI_VALUE;
2203 }
2204 break;
2205
2206 case LL_RCC_LPTIM1_CLKSOURCE_CLKP: /* LPTIM1 Clock is CLKP */
2207 lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
2208 break;
2209
2210 default:
2211 /* unreachable code */
2212 break;
2213 }
2214 }
2215 else if (LPTIMxSource == LL_RCC_LPTIM2_CLKSOURCE)
2216 {
2217 /* LPTIM2CLK clock frequency */
2218 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
2219 {
2220 case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is is PCLK1 */
2221 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
2222 break;
2223
2224 case LL_RCC_LPTIM2_CLKSOURCE_PLL2P: /* LPTIM2 Clock is PLL2 P */
2225 if (LL_RCC_PLL2_IsReady() != 0U)
2226 {
2227 if (LL_RCC_PLL2P_IsEnabled() != 0U)
2228 {
2229 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2230 lptim_frequency = PLL_Clocks.PLL_P_Frequency;
2231 }
2232 }
2233 break;
2234
2235 #if defined(LL_RCC_LPTIM2_CLKSOURCE_PLL3R)
2236 case LL_RCC_LPTIM2_CLKSOURCE_PLL3R: /* LPTIM2 Clock is PLL3 R */
2237 if (LL_RCC_PLL3_IsReady() != 0U)
2238 {
2239 if (LL_RCC_PLL3R_IsEnabled() != 0U)
2240 {
2241 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2242 lptim_frequency = PLL_Clocks.PLL_R_Frequency;
2243 }
2244 }
2245 break;
2246 #endif /* PLL3 */
2247
2248 case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */
2249 if (LL_RCC_LSE_IsReady() == 1U)
2250 {
2251 lptim_frequency = LSE_VALUE;
2252 }
2253 break;
2254
2255 case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */
2256 if (LL_RCC_LSI_IsReady() == 1U)
2257 {
2258 lptim_frequency = LSI_VALUE;
2259 }
2260 break;
2261
2262 case LL_RCC_LPTIM2_CLKSOURCE_CLKP: /* LPTIM2 Clock is CLKP */
2263 lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
2264 break;
2265
2266 default:
2267 /* unreachable code */
2268 break;
2269 }
2270 }
2271 #if defined(LPTIM3)
2272 else if (LPTIMxSource == LL_RCC_LPTIM3_CLKSOURCE)
2273 {
2274 /* LPTIM3CLK clock frequency */
2275 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
2276 {
2277 case LL_RCC_LPTIM3_CLKSOURCE_PCLK3: /* LPTIM3 Clock is is PCLK3 */
2278 lptim_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
2279 break;
2280
2281 case LL_RCC_LPTIM3_CLKSOURCE_PLL2P: /* LPTIM3 Clock is PLL2 P */
2282 if (LL_RCC_PLL2_IsReady() != 0U)
2283 {
2284 if (LL_RCC_PLL2P_IsEnabled() != 0U)
2285 {
2286 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2287 lptim_frequency = PLL_Clocks.PLL_P_Frequency;
2288 }
2289 }
2290 break;
2291
2292 case LL_RCC_LPTIM3_CLKSOURCE_PLL3R: /* LPTIM3 Clock is PLL3 R */
2293 if (LL_RCC_PLL3_IsReady() != 0U)
2294 {
2295 if (LL_RCC_PLL3R_IsEnabled() != 0U)
2296 {
2297 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2298 lptim_frequency = PLL_Clocks.PLL_R_Frequency;
2299 }
2300 }
2301 break;
2302
2303 case LL_RCC_LPTIM3_CLKSOURCE_LSE: /* LPTIM3 Clock is LSE Osc. */
2304 if (LL_RCC_LSE_IsReady() == 1U)
2305 {
2306 lptim_frequency = LSE_VALUE;
2307 }
2308 break;
2309
2310 case LL_RCC_LPTIM3_CLKSOURCE_LSI: /* LPTIM3 Clock is LSI Osc. */
2311 if (LL_RCC_LSI_IsReady() == 1U)
2312 {
2313 lptim_frequency = LSI_VALUE;
2314 }
2315 break;
2316
2317 case LL_RCC_LPTIM3_CLKSOURCE_CLKP: /* LPTIM3 Clock is CLKP */
2318 lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
2319 break;
2320
2321 default:
2322 /* unreachable code */
2323 break;
2324 }
2325 }
2326 #endif /* LPTIM3 */
2327 #if defined(LPTIM4)
2328 else if (LPTIMxSource == LL_RCC_LPTIM4_CLKSOURCE)
2329 {
2330 /* LPTIM4CLK clock frequency */
2331 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
2332 {
2333 case LL_RCC_LPTIM4_CLKSOURCE_PCLK3: /* LPTIM4 Clock is is PCLK3 */
2334 lptim_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
2335 break;
2336
2337 case LL_RCC_LPTIM4_CLKSOURCE_PLL2P: /* LPTIM4 Clock is PLL2 P */
2338 if (LL_RCC_PLL2_IsReady() != 0U)
2339 {
2340 if (LL_RCC_PLL2P_IsEnabled() != 0U)
2341 {
2342 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2343 lptim_frequency = PLL_Clocks.PLL_P_Frequency;
2344 }
2345 }
2346 break;
2347
2348 case LL_RCC_LPTIM4_CLKSOURCE_PLL3R: /* LPTIM4 Clock is PLL3 R */
2349 if (LL_RCC_PLL3_IsReady() != 0U)
2350 {
2351 if (LL_RCC_PLL3R_IsEnabled() != 0U)
2352 {
2353 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2354 lptim_frequency = PLL_Clocks.PLL_R_Frequency;
2355 }
2356 }
2357 break;
2358
2359 case LL_RCC_LPTIM4_CLKSOURCE_LSE: /* LPTIM4 Clock is LSE Osc. */
2360 if (LL_RCC_LSE_IsReady() == 1U)
2361 {
2362 lptim_frequency = LSE_VALUE;
2363 }
2364 break;
2365
2366 case LL_RCC_LPTIM4_CLKSOURCE_LSI: /* LPTIM4 Clock is LSI Osc. */
2367 if (LL_RCC_LSI_IsReady() == 1U)
2368 {
2369 lptim_frequency = LSI_VALUE;
2370 }
2371 break;
2372
2373 case LL_RCC_LPTIM4_CLKSOURCE_CLKP: /* LPTIM4 Clock is CLKP */
2374 lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
2375 break;
2376
2377 default:
2378 /* unreachable code */
2379 break;
2380 }
2381 }
2382 #endif /* LPTIM4 */
2383 #if defined(LPTIM5)
2384 else if (LPTIMxSource == LL_RCC_LPTIM5_CLKSOURCE)
2385 {
2386 /* LPTIM5CLK clock frequency */
2387 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
2388 {
2389 case LL_RCC_LPTIM5_CLKSOURCE_PCLK3: /* LPTIM5 Clock is is PCLK3 */
2390 lptim_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
2391 break;
2392
2393 case LL_RCC_LPTIM5_CLKSOURCE_PLL2P: /* LPTIM5 Clock is PLL2 P */
2394 if (LL_RCC_PLL2_IsReady() != 0U)
2395 {
2396 if (LL_RCC_PLL2P_IsEnabled() != 0U)
2397 {
2398 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2399 lptim_frequency = PLL_Clocks.PLL_P_Frequency;
2400 }
2401 }
2402 break;
2403
2404 case LL_RCC_LPTIM5_CLKSOURCE_PLL3R: /* LPTIM5 Clock is PLL3 R */
2405 if (LL_RCC_PLL3_IsReady() != 0U)
2406 {
2407 if (LL_RCC_PLL3R_IsEnabled() != 0U)
2408 {
2409 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2410 lptim_frequency = PLL_Clocks.PLL_R_Frequency;
2411 }
2412 }
2413 break;
2414
2415 case LL_RCC_LPTIM5_CLKSOURCE_LSE: /* LPTIM5 Clock is LSE Osc. */
2416 if (LL_RCC_LSE_IsReady() == 1U)
2417 {
2418 lptim_frequency = LSE_VALUE;
2419 }
2420 break;
2421
2422 case LL_RCC_LPTIM5_CLKSOURCE_LSI: /* LPTIM5 Clock is LSI Osc. */
2423 if (LL_RCC_LSI_IsReady() == 1U)
2424 {
2425 lptim_frequency = LSI_VALUE;
2426 }
2427 break;
2428
2429 case LL_RCC_LPTIM5_CLKSOURCE_CLKP: /* LPTIM5 Clock is CLKP */
2430 lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
2431 break;
2432
2433 default:
2434 /* unreachable code */
2435 break;
2436 }
2437 }
2438 #endif /* LPTIM5 */
2439 #if defined(LPTIM6)
2440 else if (LPTIMxSource == LL_RCC_LPTIM6_CLKSOURCE)
2441 {
2442 /* LPTIM6CLK clock frequency */
2443 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
2444 {
2445 case LL_RCC_LPTIM6_CLKSOURCE_PCLK3: /* LPTIM6 Clock is is PCLK3 */
2446 lptim_frequency = RCC_GetPCLK3ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
2447 break;
2448
2449 case LL_RCC_LPTIM6_CLKSOURCE_PLL2P: /* LPTIM6 Clock is PLL2 P */
2450 if (LL_RCC_PLL2_IsReady() != 0U)
2451 {
2452 if (LL_RCC_PLL2P_IsEnabled() != 0U)
2453 {
2454 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2455 lptim_frequency = PLL_Clocks.PLL_P_Frequency;
2456 }
2457 }
2458 break;
2459
2460 case LL_RCC_LPTIM6_CLKSOURCE_PLL3R: /* LPTIM6 Clock is PLL3 R */
2461 if (LL_RCC_PLL3_IsReady() != 0U)
2462 {
2463 if (LL_RCC_PLL3R_IsEnabled() != 0U)
2464 {
2465 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2466 lptim_frequency = PLL_Clocks.PLL_R_Frequency;
2467 }
2468 }
2469 break;
2470
2471 case LL_RCC_LPTIM6_CLKSOURCE_LSE: /* LPTIM6 Clock is LSE Osc. */
2472 if (LL_RCC_LSE_IsReady() == 1U)
2473 {
2474 lptim_frequency = LSE_VALUE;
2475 }
2476 break;
2477
2478 case LL_RCC_LPTIM6_CLKSOURCE_LSI: /* LPTIM6 Clock is LSI Osc. */
2479 if (LL_RCC_LSI_IsReady() == 1U)
2480 {
2481 lptim_frequency = LSI_VALUE;
2482 }
2483 break;
2484
2485 case LL_RCC_LPTIM6_CLKSOURCE_CLKP: /* LPTIM6 Clock is CLKP */
2486 lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
2487 break;
2488
2489 default:
2490 /* unreachable code */
2491 break;
2492 }
2493 }
2494 #endif /* LPTIM6 */
2495 else
2496 {
2497 /* nothing to do */
2498 }
2499
2500 return lptim_frequency;
2501 }
2502
2503 #if defined(SAI1)
2504 /**
2505 * @brief Return SAIx clock frequency
2506 * @param SAIxSource This parameter can be one of the following values:
2507 * @arg @ref LL_RCC_SAI1_CLKSOURCE
2508 * @arg @ref LL_RCC_SAI2_CLKSOURCE
2509 * @retval SAI clock frequency (in Hz)
2510 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
2511 */
LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)2512 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
2513 {
2514 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2515 LL_PLL_ClocksTypeDef PLL_Clocks;
2516
2517 /* Check parameter */
2518 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
2519
2520 if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
2521 {
2522 /* SAI1CLK clock frequency */
2523 switch (LL_RCC_GetSAIClockSource(SAIxSource))
2524 {
2525 case LL_RCC_SAI1_CLKSOURCE_PLL1Q: /* PLL1 Q clock used as SAI1 clock source */
2526 if (LL_RCC_PLL1_IsReady() != 0U)
2527 {
2528 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
2529 {
2530 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
2531 sai_frequency = PLL_Clocks.PLL_Q_Frequency;
2532 }
2533 }
2534 break;
2535
2536 case LL_RCC_SAI1_CLKSOURCE_PLL2P: /* PLL2 P clock used as SAI1 clock source */
2537 if (LL_RCC_PLL2_IsReady() != 0U)
2538 {
2539 if (LL_RCC_PLL2P_IsEnabled() != 0U)
2540 {
2541 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2542 sai_frequency = PLL_Clocks.PLL_P_Frequency;
2543 }
2544 }
2545 break;
2546
2547 case LL_RCC_SAI1_CLKSOURCE_PLL3P: /* PLL3 P clock used as SAI1 clock source */
2548 if (LL_RCC_PLL3_IsReady() != 0U)
2549 {
2550 if (LL_RCC_PLL3P_IsEnabled() != 0U)
2551 {
2552 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2553 sai_frequency = PLL_Clocks.PLL_P_Frequency;
2554 }
2555 }
2556 break;
2557
2558 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
2559 sai_frequency = EXTERNAL_CLOCK_VALUE;
2560 break;
2561
2562 case LL_RCC_SAI1_CLKSOURCE_CLKP: /* CLKP used as SAI1 clock source */
2563 sai_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
2564 break;
2565
2566 default:
2567 /* unreachable code */
2568 break;
2569 }
2570 }
2571 else if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
2572 {
2573 /* SAI2CLK clock frequency */
2574 switch (LL_RCC_GetSAIClockSource(SAIxSource))
2575 {
2576 case LL_RCC_SAI2_CLKSOURCE_PLL1Q: /* PLL1 Q clock used as SAI2 clock source */
2577 if (LL_RCC_PLL1_IsReady() != 0U)
2578 {
2579 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
2580 {
2581 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
2582 sai_frequency = PLL_Clocks.PLL_Q_Frequency;
2583 }
2584 }
2585 break;
2586
2587 case LL_RCC_SAI2_CLKSOURCE_PLL2P: /* PLL2 P clock used as SAI2 clock source */
2588 if (LL_RCC_PLL2_IsReady() != 0U)
2589 {
2590 if (LL_RCC_PLL2P_IsEnabled() != 0U)
2591 {
2592 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2593 sai_frequency = PLL_Clocks.PLL_P_Frequency;
2594 }
2595 }
2596 break;
2597
2598 case LL_RCC_SAI2_CLKSOURCE_PLL3P: /* PLL3 P clock used as SAI2 clock source */
2599 if (LL_RCC_PLL3_IsReady() != 0U)
2600 {
2601 if (LL_RCC_PLL3P_IsEnabled() != 0U)
2602 {
2603 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2604 sai_frequency = PLL_Clocks.PLL_P_Frequency;
2605 }
2606 }
2607 break;
2608
2609 case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */
2610 sai_frequency = EXTERNAL_CLOCK_VALUE;
2611 break;
2612
2613 case LL_RCC_SAI2_CLKSOURCE_CLKP: /* SAI2 Clock is CLKP */
2614 sai_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
2615 break;
2616
2617 default:
2618 /* unreachable code */
2619 break;
2620 }
2621 }
2622 else
2623 {
2624 /* nothing to do */
2625 }
2626
2627 return sai_frequency;
2628 }
2629 #endif /* SAI1 */
2630
2631 #if defined(SDMMC1)
2632 /**
2633 * @brief Return SDMMCx clock frequency
2634 * @param SDMMCxSource This parameter can be one of the following values:
2635 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
2636 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*)
2637 * @retval SDMMC clock frequency (in Hz)
2638 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
2639 *
2640 * (*) : Available on some STM32H5 lines only.
2641 */
LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)2642 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
2643 {
2644 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2645 LL_PLL_ClocksTypeDef PLL_Clocks;
2646
2647 /* Check parameter */
2648 assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
2649
2650 if (SDMMCxSource == LL_RCC_SDMMC1_CLKSOURCE)
2651 {
2652 /* SDMMC1CLK clock frequency */
2653 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
2654 {
2655 case LL_RCC_SDMMC1_CLKSOURCE_PLL1Q: /* PLL1 Q clock used as SDMMC1 clock source */
2656 if (LL_RCC_PLL1_IsReady() != 0U)
2657 {
2658 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
2659 {
2660 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
2661 sdmmc_frequency = PLL_Clocks.PLL_Q_Frequency;
2662 }
2663 }
2664 break;
2665
2666 case LL_RCC_SDMMC1_CLKSOURCE_PLL2R: /* PLL2 R clock used as SDMMC1 clock source */
2667 if (LL_RCC_PLL2_IsReady() != 0U)
2668 {
2669 if (LL_RCC_PLL2R_IsEnabled() != 0U)
2670 {
2671 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2672 sdmmc_frequency = PLL_Clocks.PLL_R_Frequency;
2673 }
2674 }
2675 break;
2676
2677 default:
2678 /* unreachable code */
2679 break;
2680 }
2681 }
2682
2683 #if defined(SDMMC2)
2684 else if (SDMMCxSource == LL_RCC_SDMMC2_CLKSOURCE)
2685 {
2686 /* SDMMC2CLK clock frequency */
2687 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
2688 {
2689 case LL_RCC_SDMMC2_CLKSOURCE_PLL1Q: /* PLL1 Q clock used as SDMMC2 clock source */
2690 if (LL_RCC_PLL1_IsReady() != 0U)
2691 {
2692 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
2693 {
2694 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
2695 sdmmc_frequency = PLL_Clocks.PLL_Q_Frequency;
2696 }
2697 }
2698 break;
2699
2700 case LL_RCC_SDMMC2_CLKSOURCE_PLL2R: /* PLL2 R clock used as SDMMC2 clock source */
2701 if (LL_RCC_PLL2_IsReady() != 0U)
2702 {
2703 if (LL_RCC_PLL2R_IsEnabled() != 0U)
2704 {
2705 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2706 sdmmc_frequency = PLL_Clocks.PLL_R_Frequency;
2707 }
2708 }
2709 break;
2710
2711 default:
2712 /* unreachable code */
2713 break;
2714 }
2715 }
2716 #endif /* SDMMC2 */
2717
2718 else
2719 {
2720 /* nothing to do */
2721 }
2722
2723 return sdmmc_frequency;
2724 }
2725 #endif /* SDMMC1 */
2726
2727 /**
2728 * @brief Return RNGx clock frequency
2729 * @param RNGxSource This parameter can be one of the following values:
2730 * @arg @ref LL_RCC_RNG_CLKSOURCE
2731 * @retval RNG clock frequency (in Hz)
2732 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
2733 */
LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)2734 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
2735 {
2736 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2737 LL_PLL_ClocksTypeDef PLL_Clocks;
2738
2739 /* Check parameter */
2740 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
2741
2742 /* RNGCLK clock frequency */
2743 switch (LL_RCC_GetRNGClockSource(RNGxSource))
2744 {
2745 case LL_RCC_RNG_CLKSOURCE_HSI48: /* HSI48 clock used as RNG clock source */
2746 if (LL_RCC_HSI48_IsReady() == 1U)
2747 {
2748 rng_frequency = HSI48_VALUE;
2749 }
2750 break;
2751
2752 case LL_RCC_RNG_CLKSOURCE_PLL1Q: /* PLL1 Q clock used as RNG clock source */
2753 if (LL_RCC_PLL1_IsReady() != 0U)
2754 {
2755 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
2756 {
2757 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
2758 rng_frequency = PLL_Clocks.PLL_Q_Frequency;
2759 }
2760 }
2761 break;
2762
2763 case LL_RCC_RNG_CLKSOURCE_LSE: /* LSE clock used as RNG clock source */
2764 if (LL_RCC_LSE_IsReady() == 1U)
2765 {
2766 rng_frequency = LSE_VALUE;
2767 }
2768 break;
2769
2770 case LL_RCC_RNG_CLKSOURCE_LSI: /* LSI clock used as RNG clock source */
2771 if (LL_RCC_LSI_IsReady() == 1U)
2772 {
2773 rng_frequency = LSI_VALUE;
2774 }
2775 break;
2776
2777 default:
2778 /* unreachable code */
2779 break;
2780
2781 }
2782
2783 return rng_frequency;
2784 }
2785
2786 /**
2787 * @brief Return USBx clock frequency
2788 * @param USBxSource This parameter can be one of the following values:
2789 * @arg @ref LL_RCC_USB_CLKSOURCE
2790 * @retval USB clock frequency (in Hz)
2791 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready or no clock is selected
2792 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)2793 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
2794 {
2795 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2796 LL_PLL_ClocksTypeDef PLL_Clocks;
2797
2798 /* Check parameter */
2799 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
2800
2801 /* USBCLK clock frequency */
2802 switch (LL_RCC_GetUSBClockSource(USBxSource))
2803 {
2804
2805 case LL_RCC_USB_CLKSOURCE_NONE: /* NO clock used as USB clock source */
2806 break;
2807
2808 case LL_RCC_USB_CLKSOURCE_PLL1Q: /* PLL1 Q clock used as USB clock source */
2809 if (LL_RCC_PLL1_IsReady() != 0U)
2810 {
2811 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
2812 {
2813 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
2814 usb_frequency = PLL_Clocks.PLL_Q_Frequency;
2815 }
2816 }
2817 break;
2818
2819 #if defined(LL_RCC_USB_CLKSOURCE_PLL3Q)
2820 case LL_RCC_USB_CLKSOURCE_PLL3Q: /* PLL3 Q clock used as USB clock source */
2821 if (LL_RCC_PLL3_IsReady() != 0U)
2822 {
2823 if (LL_RCC_PLL3Q_IsEnabled() != 0U)
2824 {
2825 LL_RCC_GetPLL3ClockFreq(&PLL_Clocks);
2826 usb_frequency = PLL_Clocks.PLL_Q_Frequency;
2827 }
2828 }
2829 break;
2830 #endif /* LL_RCC_USB_CLKSOURCE_PLL3 */
2831
2832 case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */
2833 if (LL_RCC_HSI48_IsReady() == 1U)
2834 {
2835 usb_frequency = HSI48_VALUE;
2836 }
2837 break;
2838
2839 default:
2840 /* unreachable code */
2841 break;
2842 }
2843
2844 return usb_frequency;
2845 }
2846
2847 /**
2848 * @brief Return ADCxDAC clock frequency
2849 * @param ADCDACxSource This parameter can be one of the following values:
2850 * @arg @ref LL_RCC_ADCDAC_CLKSOURCE
2851 * @retval ADCDAC clock frequency (in Hz)
2852 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
2853 */
LL_RCC_GetADCDACClockFreq(uint32_t ADCDACxSource)2854 uint32_t LL_RCC_GetADCDACClockFreq(uint32_t ADCDACxSource)
2855 {
2856 uint32_t adcdac_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2857 LL_PLL_ClocksTypeDef PLL_Clocks;
2858
2859 /* Check parameter */
2860 assert_param(IS_LL_RCC_ADCDAC_CLKSOURCE(ADCDACxSource));
2861
2862 /* ADCCLK clock frequency */
2863 switch (LL_RCC_GetADCDACClockSource(ADCDACxSource))
2864 {
2865 case LL_RCC_ADCDAC_CLKSOURCE_HCLK: /* ADCDAC Clock is AHB clock */
2866 adcdac_frequency = RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq());
2867 break;
2868
2869 case LL_RCC_ADCDAC_CLKSOURCE_SYSCLK: /* ADCDAC Clock is SYSCLK clock */
2870 adcdac_frequency = RCC_GetSystemClockFreq();
2871 break;
2872
2873 case LL_RCC_ADCDAC_CLKSOURCE_PLL2R: /* ADCDAC Clock is PLL2 R */
2874 if (LL_RCC_PLL2_IsReady() != 0U)
2875 {
2876 if (LL_RCC_PLL2R_IsEnabled() != 0U)
2877 {
2878 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2879 adcdac_frequency = PLL_Clocks.PLL_R_Frequency;
2880 }
2881 }
2882 break;
2883
2884 case LL_RCC_ADCDAC_CLKSOURCE_HSE: /* ADCDAC Clock is HSE Osc. */
2885 if (LL_RCC_HSE_IsReady() == 1U)
2886 {
2887 adcdac_frequency = HSE_VALUE;
2888 }
2889 break;
2890
2891 case LL_RCC_ADCDAC_CLKSOURCE_HSI: /* ADCDAC Clock is HSI Osc. */
2892 if (LL_RCC_HSI_IsReady() == 1U)
2893 {
2894 adcdac_frequency = HSI_VALUE;
2895 }
2896 break;
2897
2898 case LL_RCC_ADCDAC_CLKSOURCE_CSI: /* ADCDAC Clock is CSI Osc. */
2899 if (LL_RCC_CSI_IsReady() == 1U)
2900 {
2901 adcdac_frequency = CSI_VALUE;
2902 }
2903 break;
2904
2905 default:
2906 /* unreachable code */
2907 break;
2908 }
2909
2910 return adcdac_frequency;
2911 }
2912
2913 /**
2914 * @brief Return DAC low-power clock frequency
2915 * @param DACLPxSource This parameter can be one of the following values:
2916 * @arg @ref LL_RCC_DAC_LP_CLKSOURCE
2917 * @retval DAC low-power clock frequency (in Hz)
2918 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that LSI or LSE oscillator is not ready
2919 */
LL_RCC_GetDACLPClockFreq(uint32_t DACLPxSource)2920 uint32_t LL_RCC_GetDACLPClockFreq(uint32_t DACLPxSource)
2921 {
2922 uint32_t daclp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2923
2924 /* Check parameter */
2925 assert_param(IS_LL_RCC_DAC_LP_CLKSOURCE(DACLPxSource));
2926
2927 /* DAC clock frequency */
2928 switch (LL_RCC_GetDACLPClockSource(DACLPxSource))
2929 {
2930 case LL_RCC_DAC_LP_CLKSOURCE_LSE: /* DAC low-power Clock is LSE Osc. */
2931 if (LL_RCC_LSE_IsReady() == 1U)
2932 {
2933 daclp_frequency = LSE_VALUE;
2934 }
2935 break;
2936
2937 case LL_RCC_DAC_LP_CLKSOURCE_LSI: /* DAC low-power Clock is LSI Osc. */
2938 if (LL_RCC_LSI_IsReady() == 1U)
2939 {
2940 daclp_frequency = LSI_VALUE;
2941 }
2942 break;
2943
2944 default:
2945 /* unreachable code */
2946 break;
2947 }
2948
2949 return daclp_frequency;
2950 }
2951
2952 #if defined( OCTOSPI1)
2953 /**
2954 * @brief Return OCTOSPI clock frequency
2955 * @param OCTOSPIxSource This parameter can be one of the following values:
2956 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
2957 * @retval OCTOSPI clock frequency (in Hz)
2958 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
2959 */
LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)2960 uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)
2961 {
2962 uint32_t octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2963 LL_PLL_ClocksTypeDef PLL_Clocks;
2964
2965 /* Check parameter */
2966 assert_param(IS_LL_RCC_OCTOSPI_CLKSOURCE(OCTOSPIxSource));
2967
2968 /* OCTOSPI clock frequency */
2969 switch (LL_RCC_GetOCTOSPIClockSource(OCTOSPIxSource))
2970 {
2971 case LL_RCC_OSPI_CLKSOURCE_HCLK: /* OCTOSPI clock is SYSCLK */
2972 octospi_frequency = RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq());
2973 break;
2974
2975 case LL_RCC_OSPI_CLKSOURCE_PLL1Q: /* OSPI Clock is PLL1 Q */
2976 if (LL_RCC_PLL1_IsReady() != 0U)
2977 {
2978 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
2979 {
2980 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
2981 octospi_frequency = PLL_Clocks.PLL_Q_Frequency;
2982 }
2983 }
2984 break;
2985
2986 case LL_RCC_OSPI_CLKSOURCE_PLL2R: /* OSPI Clock is PLL2 R */
2987 if (LL_RCC_PLL2_IsReady() != 0U)
2988 {
2989 if (LL_RCC_PLL2R_IsEnabled() != 0U)
2990 {
2991 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
2992 octospi_frequency = PLL_Clocks.PLL_R_Frequency;
2993 }
2994 }
2995 break;
2996
2997 case LL_RCC_OSPI_CLKSOURCE_CLKP: /* OSPI Clock is CLKP */
2998 octospi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_GetCLKPClockSource(LL_RCC_CLKP_CLKSOURCE));
2999 break;
3000
3001 default:
3002 /* unreachable code */
3003 break;
3004 }
3005
3006 return octospi_frequency;
3007 }
3008 #endif /* OCTOSPI1 */
3009
3010 /**
3011 * @brief Return FDCAN kernel clock frequency
3012 * @param FDCANxSource This parameter can be one of the following values:
3013 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
3014 * @retval FDCAN kernel clock frequency (in Hz)
3015 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready or no clock is selected
3016 *
3017 */
LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)3018 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
3019 {
3020 uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
3021 LL_PLL_ClocksTypeDef PLL_Clocks;
3022
3023 /* Check parameter */
3024 assert_param(IS_LL_RCC_FDCAN_CLKSOURCE(FDCANxSource));
3025
3026 /* FDCANCLK clock frequency */
3027 switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
3028 {
3029 case LL_RCC_FDCAN_CLKSOURCE_HSE: /* HSE clock used as FDCAN clock source */
3030 if (LL_RCC_HSE_IsReady() == 1U)
3031 {
3032 fdcan_frequency = HSE_VALUE;
3033 }
3034 break;
3035
3036 case LL_RCC_FDCAN_CLKSOURCE_PLL1Q: /* PLL1 Q clock used as FDCAN clock source */
3037 if (LL_RCC_PLL1_IsReady() != 0U)
3038 {
3039 if (LL_RCC_PLL1Q_IsEnabled() != 0U)
3040 {
3041 LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
3042 fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
3043 }
3044 }
3045 break;
3046
3047 case LL_RCC_FDCAN_CLKSOURCE_PLL2Q: /* PLL2 Q clock used as FDCAN clock source */
3048 if (LL_RCC_PLL2_IsReady() != 0U)
3049 {
3050 if (LL_RCC_PLL2Q_IsEnabled() != 0U)
3051 {
3052 LL_RCC_GetPLL2ClockFreq(&PLL_Clocks);
3053 fdcan_frequency = PLL_Clocks.PLL_Q_Frequency;
3054 }
3055 }
3056 break;
3057
3058 case LL_RCC_FDCAN_CLKSOURCE_NONE: /* No clock used as FDCAN clock source */
3059 break;
3060
3061 default:
3062 /* unreachable code */
3063 break;
3064 }
3065
3066 return fdcan_frequency;
3067 }
3068
3069 #if defined(CEC)
3070 /**
3071 * @brief Return CEC clock frequency
3072 * @param CECxSource This parameter can be one of the following values:
3073 * @arg @ref LL_RCC_CEC_CLKSOURCE
3074 * @retval CEC clock frequency (in Hz)
3075 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or no clock is selected
3076 */
LL_RCC_GetCECClockFreq(uint32_t CECxSource)3077 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
3078 {
3079 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
3080
3081 switch (LL_RCC_GetCECClockSource(CECxSource))
3082 {
3083 case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE */
3084 if (LL_RCC_LSE_IsReady() != 0U)
3085 {
3086 cec_frequency = LSE_VALUE;
3087 }
3088 break;
3089
3090 case LL_RCC_CEC_CLKSOURCE_LSI: /* CEC Clock is LSI */
3091 if (LL_RCC_LSI_IsReady() != 0U)
3092 {
3093 cec_frequency = LSI_VALUE;
3094 }
3095 break;
3096
3097 case LL_RCC_CEC_CLKSOURCE_CSI_DIV122: /* CEC Clock is CSI divided by 122 */
3098 if (LL_RCC_CSI_IsReady() != 0U)
3099 {
3100 cec_frequency = CSI_VALUE / 122U;
3101 }
3102 break;
3103
3104 case LL_RCC_CEC_CLKSOURCE_NONE: /* No Clock selected for CEC */
3105 break;
3106
3107 default:
3108 /* Kernel clock disabled */
3109 break;
3110 }
3111
3112 return cec_frequency;
3113 }
3114 #endif /* CEC */
3115
3116 /**
3117 * @brief Return CLKP clock frequency
3118 * @param CLKPxSource This parameter can be one of the following values:
3119 * @arg @ref LL_RCC_CLKP_CLKSOURCE
3120 * @retval CLKP clock frequency (in Hz)
3121 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or no clock is selected
3122 */
LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)3123 uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)
3124 {
3125 uint32_t clkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
3126
3127 switch (LL_RCC_GetCLKPClockSource(CLKPxSource))
3128 {
3129 case LL_RCC_CLKP_CLKSOURCE_HSI: /* HSI used as CLKP clock source */
3130 if (LL_RCC_HSI_IsReady() != 0U)
3131 {
3132 clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
3133 }
3134 break;
3135
3136 case LL_RCC_CLKP_CLKSOURCE_CSI: /* CSI used as CLKP clock source */
3137 if (LL_RCC_CSI_IsReady() != 0U)
3138 {
3139 clkp_frequency = CSI_VALUE;
3140 }
3141 break;
3142
3143 case LL_RCC_CLKP_CLKSOURCE_HSE: /* HSE used as CLKP clock source */
3144 if (LL_RCC_HSE_IsReady() != 0U)
3145 {
3146 clkp_frequency = HSE_VALUE;
3147 }
3148 break;
3149
3150 case LL_RCC_CLKP_CLKSOURCE_NONE: /* NO clock used as CLKP clock source */
3151 break;
3152
3153 default:
3154 /* CLKP clock disabled */
3155 break;
3156 }
3157
3158 return clkp_frequency;
3159 }
3160
3161 /**
3162 * @}
3163 */
3164
3165 /**
3166 * @}
3167 */
3168
3169 /** @addtogroup RCC_LL_Private_Functions
3170 * @{
3171 */
3172
3173 /**
3174 * @brief Return SYSTEM clock frequency
3175 * @retval SYSTEM clock frequency (in Hz)
3176 */
RCC_GetSystemClockFreq(void)3177 uint32_t RCC_GetSystemClockFreq(void)
3178 {
3179 uint32_t frequency;
3180
3181 /* Get SYSCLK source -------------------------------------------------------*/
3182 switch (LL_RCC_GetSysClkSource())
3183 {
3184 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
3185 frequency = HSI_VALUE;
3186 break;
3187
3188 case LL_RCC_SYS_CLKSOURCE_STATUS_CSI: /* CSI used as system clock source */
3189 frequency = CSI_VALUE;
3190 break;
3191
3192 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
3193 frequency = HSE_VALUE;
3194 break;
3195
3196 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1: /* PLL1 used as system clock source */
3197 frequency = RCC_PLL1_GetFreqSystem();
3198 break;
3199
3200 default:
3201 frequency = HSI_VALUE;
3202 break;
3203 }
3204
3205 return frequency;
3206 }
3207
3208 /**
3209 * @brief Return HCLK clock frequency
3210 * @param SYSCLK_Frequency SYSCLK clock frequency
3211 * @retval HCLK clock frequency (in Hz)
3212 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)3213 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
3214 {
3215 /* HCLK clock frequency */
3216 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
3217 }
3218
3219 /**
3220 * @brief Return PCLK1 clock frequency
3221 * @param HCLK_Frequency HCLK clock frequency
3222 * @retval PCLK1 clock frequency (in Hz)
3223 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)3224 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
3225 {
3226 /* PCLK1 clock frequency */
3227 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
3228 }
3229
3230 /**
3231 * @brief Return PCLK2 clock frequency
3232 * @param HCLK_Frequency HCLK clock frequency
3233 * @retval PCLK2 clock frequency (in Hz)
3234 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)3235 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
3236 {
3237 /* PCLK2 clock frequency */
3238 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
3239 }
3240
3241
3242 /**
3243 * @brief Return PCLK3 clock frequency
3244 * @param HCLK_Frequency HCLK clock frequency
3245 * @retval PCLK3 clock frequency (in Hz)
3246 */
RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)3247 uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency)
3248 {
3249 /* PCLK3 clock frequency */
3250 return __LL_RCC_CALC_PCLK3_FREQ(HCLK_Frequency, LL_RCC_GetAPB3Prescaler());
3251 }
3252
3253 /**
3254 * @brief Return PLL1 clock frequency used for system clock
3255 * @retval PLL1 clock frequency (in Hz)
3256 */
RCC_PLL1_GetFreqSystem(void)3257 uint32_t RCC_PLL1_GetFreqSystem(void)
3258 {
3259 uint32_t pllinputfreq;
3260 uint32_t pllsource;
3261
3262 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
3263 SYSCLK = PLL_VCO / PLLP
3264 */
3265 pllsource = LL_RCC_PLL1_GetSource();
3266
3267 switch (pllsource)
3268 {
3269 case LL_RCC_PLL1SOURCE_HSI: /* HSI used as PLL1 clock source */
3270 pllinputfreq = HSI_VALUE;
3271 break;
3272
3273 case LL_RCC_PLL1SOURCE_CSI: /* CSI used as PLL1 clock source */
3274 pllinputfreq = CSI_VALUE;
3275 break;
3276
3277 case LL_RCC_PLL1SOURCE_HSE: /* HSE used as PLL1 clock source */
3278 pllinputfreq = HSE_VALUE;
3279 break;
3280
3281 default:
3282 pllinputfreq = 0;
3283 break;
3284 }
3285 return __LL_RCC_CALC_PLL1CLK_P_FREQ(pllinputfreq, LL_RCC_PLL1_GetM(),
3286 LL_RCC_PLL1_GetN(), LL_RCC_PLL1_GetP());
3287 }
3288
3289
3290
3291
3292
3293
3294
3295
3296 /**
3297 * @}
3298 */
3299
3300
3301
3302 /**
3303 * @}
3304 */
3305
3306 #endif /* defined(RCC) */
3307
3308 /**
3309 * @}
3310 */
3311
3312 #endif /* USE_FULL_LL_DRIVER */
3313
