1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### LL DMA driver acronyms #####
20 ==============================================================================
21 [..] Acronyms table :
22 =========================================
23 || Acronym || ||
24 =========================================
25 || SRC || Source ||
26 || DEST || Destination ||
27 || ADDR || Address ||
28 || ADDRS || Addresses ||
29 || INC || Increment / Incremented ||
30 || DEC || Decrement / Decremented ||
31 || BLK || Block ||
32 || RPT || Repeat / Repeated ||
33 || TRIG || Trigger ||
34 =========================================
35 @endverbatim
36 ******************************************************************************
37 */
38
39 #if defined (USE_FULL_LL_DRIVER)
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32h5xx_ll_dma.h"
43 #include "stm32h5xx_ll_bus.h"
44 #ifdef USE_FULL_ASSERT
45 #include "stm32_assert.h"
46 #else
47 #define assert_param(expr) ((void)0U)
48 #endif /* USE_FULL_ASSERT */
49
50 /** @addtogroup STM32H5xx_LL_Driver
51 * @{
52 */
53
54 #if defined (GPDMA1)
55
56 /** @addtogroup DMA_LL
57 * @{
58 */
59
60 /* Private types -------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62 /* Private constants ---------------------------------------------------------*/
63 /* Private macros ------------------------------------------------------------*/
64
65 /** @addtogroup DMA_LL_Private_Macros
66 * @{
67 */
68 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, Channel) ((((INSTANCE) == GPDMA1) && \
69 (((Channel) == LL_DMA_CHANNEL_0) || \
70 ((Channel) == LL_DMA_CHANNEL_1) || \
71 ((Channel) == LL_DMA_CHANNEL_2) || \
72 ((Channel) == LL_DMA_CHANNEL_3) || \
73 ((Channel) == LL_DMA_CHANNEL_4) || \
74 ((Channel) == LL_DMA_CHANNEL_5) || \
75 ((Channel) == LL_DMA_CHANNEL_6) || \
76 ((Channel) == LL_DMA_CHANNEL_7) || \
77 ((Channel) == LL_DMA_CHANNEL_ALL))) || \
78 (((INSTANCE) == GPDMA2) && \
79 (((Channel) == LL_DMA_CHANNEL_0) || \
80 ((Channel) == LL_DMA_CHANNEL_1) || \
81 ((Channel) == LL_DMA_CHANNEL_2) || \
82 ((Channel) == LL_DMA_CHANNEL_3) || \
83 ((Channel) == LL_DMA_CHANNEL_4) || \
84 ((Channel) == LL_DMA_CHANNEL_5) || \
85 ((Channel) == LL_DMA_CHANNEL_6) || \
86 ((Channel) == LL_DMA_CHANNEL_7) || \
87 ((Channel) == LL_DMA_CHANNEL_ALL))))
88
89
90 #define IS_LL_GPDMA_CHANNEL_INSTANCE(INSTANCE, Channel) ((((INSTANCE) == GPDMA1) && \
91 (((Channel) == LL_DMA_CHANNEL_0) || \
92 ((Channel) == LL_DMA_CHANNEL_1) || \
93 ((Channel) == LL_DMA_CHANNEL_2) || \
94 ((Channel) == LL_DMA_CHANNEL_3) || \
95 ((Channel) == LL_DMA_CHANNEL_4) || \
96 ((Channel) == LL_DMA_CHANNEL_5) || \
97 ((Channel) == LL_DMA_CHANNEL_6) || \
98 ((Channel) == LL_DMA_CHANNEL_7))) || \
99 (((INSTANCE) == GPDMA2) && \
100 (((Channel) == LL_DMA_CHANNEL_0) || \
101 ((Channel) == LL_DMA_CHANNEL_1) || \
102 ((Channel) == LL_DMA_CHANNEL_2) || \
103 ((Channel) == LL_DMA_CHANNEL_3) || \
104 ((Channel) == LL_DMA_CHANNEL_4) || \
105 ((Channel) == LL_DMA_CHANNEL_5) || \
106 ((Channel) == LL_DMA_CHANNEL_6) || \
107 ((Channel) == LL_DMA_CHANNEL_7))))
108
109 #define IS_LL_DMA_2D_CHANNEL_INSTANCE(INSTANCE, Channel) ((((INSTANCE) == GPDMA1) && \
110 (((Channel) == LL_DMA_CHANNEL_6) || \
111 ((Channel) == LL_DMA_CHANNEL_7))) || \
112 (((INSTANCE) == GPDMA2) && \
113 (((Channel) == LL_DMA_CHANNEL_6) || \
114 ((Channel) == LL_DMA_CHANNEL_7))))
115
116 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY) || \
117 ((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
118 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH))
119
120 #define IS_LL_DMA_DATA_ALIGNMENT(__VALUE__) (((__VALUE__) == LL_DMA_DATA_ALIGN_ZEROPADD) || \
121 ((__VALUE__) == LL_DMA_DATA_ALIGN_SIGNEXTPADD) || \
122 ((__VALUE__) == LL_DMA_DATA_PACK_UNPACK))
123
124 #define IS_LL_DMA_BURST_LENGTH(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= 64U))
125
126 #define IS_LL_DMA_SRC_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_SRC_DATAWIDTH_BYTE) || \
127 ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_HALFWORD) || \
128 ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_WORD))
129
130 #define IS_LL_DMA_DEST_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_DEST_DATAWIDTH_BYTE) || \
131 ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_HALFWORD) || \
132 ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_WORD))
133
134 #define IS_LL_DMA_SRC_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_FIXED) || \
135 ((__VALUE__) == LL_DMA_SRC_INCREMENT))
136
137 #define IS_LL_DMA_DEST_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_FIXED) || \
138 ((__VALUE__) == LL_DMA_DEST_INCREMENT))
139
140 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_LOW_PRIORITY_LOW_WEIGHT) || \
141 ((__VALUE__) == LL_DMA_LOW_PRIORITY_MID_WEIGHT) || \
142 ((__VALUE__) == LL_DMA_LOW_PRIORITY_HIGH_WEIGHT) || \
143 ((__VALUE__) == LL_DMA_HIGH_PRIORITY))
144
145 #define IS_LL_DMA_BLK_DATALENGTH(__VALUE__) ((__VALUE__) <= 0xFFFFU)
146
147 #define IS_LL_DMA_BLK_REPEATCOUNT(__VALUE__) ((__VALUE__) <= 0x0EFFU)
148
149 #define IS_LL_DMA_TRIGGER_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TRIGM_BLK_TRANSFER) || \
150 ((__VALUE__) == LL_DMA_TRIGM_RPT_BLK_TRANSFER) || \
151 ((__VALUE__) == LL_DMA_TRIGM_LLI_LINK_TRANSFER) || \
152 ((__VALUE__) == LL_DMA_TRIGM_SINGLBURST_TRANSFER ))
153
154 #define IS_LL_DMA_TRIGGER_POLARITY(__VALUE__) (((__VALUE__) == LL_DMA_TRIG_POLARITY_MASKED) || \
155 ((__VALUE__) == LL_DMA_TRIG_POLARITY_RISING) || \
156 ((__VALUE__) == LL_DMA_TRIG_POLARITY_FALLING))
157
158 #define IS_LL_DMA_BLKHW_REQUEST(__VALUE__) (((__VALUE__) == LL_DMA_HWREQUEST_SINGLEBURST) || \
159 ((__VALUE__) == LL_DMA_HWREQUEST_BLK))
160
161 #if defined (I3C2)
162 #define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_EVENTOUT)
163 #else
164 #define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_LPTIM6_CH2)
165 #endif /* I3C2 */
166
167 #if defined (I3C2)
168 #define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_I3C2_RS)
169 #else
170 #define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_LPTIM6_UE)
171 #endif /* I3C2 */
172
173 #define IS_LL_DMA_TRANSFER_EVENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TCEM_BLK_TRANSFER) || \
174 ((__VALUE__) == LL_DMA_TCEM_RPT_BLK_TRANSFER) || \
175 ((__VALUE__) == LL_DMA_TCEM_EACH_LLITEM_TRANSFER) || \
176 ((__VALUE__) == LL_DMA_TCEM_LAST_LLITEM_TRANSFER))
177
178 #define IS_LL_DMA_DEST_HALFWORD_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_HALFWORD_PRESERVE) || \
179 ((__VALUE__) == LL_DMA_DEST_HALFWORD_EXCHANGE))
180
181 #define IS_LL_DMA_DEST_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_BYTE_PRESERVE) || \
182 ((__VALUE__) == LL_DMA_DEST_BYTE_EXCHANGE))
183
184 #define IS_LL_DMA_SRC_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_BYTE_PRESERVE) || \
185 ((__VALUE__) == LL_DMA_SRC_BYTE_EXCHANGE))
186
187 #define IS_LL_DMA_LINK_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT0) || \
188 ((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT1))
189
190 #define IS_LL_DMA_SRC_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT0) || \
191 ((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT1))
192
193 #define IS_LL_DMA_DEST_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT0) || \
194 ((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT1))
195
196 #define IS_LL_DMA_LINK_STEP_MODE(__VALUE__) (((__VALUE__) == LL_DMA_LSM_FULL_EXECUTION) || \
197 ((__VALUE__) == LL_DMA_LSM_1LINK_EXECUTION))
198
199 #define IS_LL_DMA_BURST_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_SRC_ADDR_INCREMENT) || \
200 ((__VALUE__) == LL_DMA_BURST_SRC_ADDR_DECREMENT))
201
202 #define IS_LL_DMA_BURST_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_DEST_ADDR_INCREMENT) || \
203 ((__VALUE__) == LL_DMA_BURST_DEST_ADDR_DECREMENT))
204
205 #define IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU)
206
207 #define IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_INCREMENT) || \
208 ((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_DECREMENT))
209
210 #define IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_INCREMENT) || \
211 ((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_DECREMENT))
212
213 #define IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0xFFFFU)
214
215 #define IS_LL_DMA_LINK_BASEADDR(__VALUE__) (((__VALUE__) & 0xFFFFU) == 0U)
216
217 #define IS_LL_DMA_LINK_ADDR_OFFSET(__VALUE__) (((__VALUE__) & 0x03U) == 0U)
218
219 #define IS_LL_DMA_LINK_UPDATE_REGISTERS(__VALUE__) ((((__VALUE__) & 0x01FE0000U) == 0U) && ((__VALUE__) != 0U))
220
221 #define IS_LL_DMA_LINK_NODETYPE(__VALUE__) (((__VALUE__) == LL_DMA_GPDMA_2D_NODE) || \
222 ((__VALUE__) == LL_DMA_GPDMA_LINEAR_NODE))
223
224 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
225 #define IS_LL_DMA_CHANNEL_SRC_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_SRC_NSEC) || \
226 ((__VALUE__) == LL_DMA_CHANNEL_SRC_SEC))
227
228 #define IS_LL_DMA_CHANNEL_DEST_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_DEST_NSEC) || \
229 ((__VALUE__) == LL_DMA_CHANNEL_DEST_SEC))
230 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
231 /**
232 * @}
233 */
234
235 /* Private function prototypes -----------------------------------------------*/
236 /* Exported functions --------------------------------------------------------*/
237
238 /** @addtogroup DMA_LL_Exported_Functions
239 * @{
240 */
241
242 /** @addtogroup DMA_LL_EF_Init
243 * @{
244 */
245
246 /**
247 * @brief De-initialize the DMA registers to their default reset values.
248 * @note This API is used for all available DMA channels.
249 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
250 * helper macros :
251 * @arg @ref LL_DMA_GET_INSTANCE
252 * @arg @ref LL_DMA_GET_CHANNEL
253 * @param DMAx DMAx Instance
254 * @param Channel This parameter can be one of the following values:
255 * @arg @ref LL_DMA_CHANNEL_0
256 * @arg @ref LL_DMA_CHANNEL_1
257 * @arg @ref LL_DMA_CHANNEL_2
258 * @arg @ref LL_DMA_CHANNEL_3
259 * @arg @ref LL_DMA_CHANNEL_4
260 * @arg @ref LL_DMA_CHANNEL_5
261 * @arg @ref LL_DMA_CHANNEL_6
262 * @arg @ref LL_DMA_CHANNEL_7
263 * @arg @ref LL_DMA_CHANNEL_8
264 * @arg @ref LL_DMA_CHANNEL_9
265 * @arg @ref LL_DMA_CHANNEL_10
266 * @arg @ref LL_DMA_CHANNEL_11
267 * @arg @ref LL_DMA_CHANNEL_12
268 * @arg @ref LL_DMA_CHANNEL_13
269 * @arg @ref LL_DMA_CHANNEL_14
270 * @arg @ref LL_DMA_CHANNEL_15
271 * @retval An ErrorStatus enumeration value:
272 * - SUCCESS : DMA registers are de-initialized.
273 * - ERROR : DMA registers are not de-initialized.
274 */
LL_DMA_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)275 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
276 {
277 DMA_Channel_TypeDef *tmp;
278 ErrorStatus status = SUCCESS;
279
280 /* Check the DMA Instance DMAx and Channel parameters */
281 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
282
283 if (Channel == LL_DMA_CHANNEL_ALL)
284 {
285 if (DMAx == GPDMA1)
286 {
287 /* Force reset of DMA clock */
288 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPDMA1);
289
290 /* Release reset of DMA clock */
291 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPDMA1);
292 }
293 else
294 {
295 /* Force reset of DMA clock */
296 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPDMA2);
297
298 /* Release reset of DMA clock */
299 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPDMA2);
300 }
301 }
302 else
303 {
304 /* Get the DMA Channel Instance */
305 tmp = (DMA_Channel_TypeDef *)(LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
306
307 /* Suspend DMA channel */
308 LL_DMA_SuspendChannel(DMAx, Channel);
309
310 /* Disable the selected Channel */
311 LL_DMA_ResetChannel(DMAx, Channel);
312
313 /* Reset DMAx_Channely control register */
314 LL_DMA_WriteReg(tmp, CLBAR, 0U);
315
316 /* Reset DMAx_Channely control register */
317 LL_DMA_WriteReg(tmp, CCR, 0U);
318
319 /* Reset DMAx_Channely Configuration register */
320 LL_DMA_WriteReg(tmp, CTR1, 0U);
321
322 /* Reset DMAx_Channely transfer register 2 */
323 LL_DMA_WriteReg(tmp, CTR2, 0U);
324
325 /* Reset DMAx_Channely block number of data register */
326 LL_DMA_WriteReg(tmp, CBR1, 0U);
327
328 /* Reset DMAx_Channely source address register */
329 LL_DMA_WriteReg(tmp, CSAR, 0U);
330
331 /* Reset DMAx_Channely destination address register */
332 LL_DMA_WriteReg(tmp, CDAR, 0U);
333
334 /* Check DMA channel */
335 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
336 {
337 /* Reset DMAx_Channely transfer register 3 */
338 LL_DMA_WriteReg(tmp, CTR3, 0U);
339
340 /* Reset DMAx_Channely Block register 2 */
341 LL_DMA_WriteReg(tmp, CBR2, 0U);
342 }
343
344 /* Reset DMAx_Channely Linked list address register */
345 LL_DMA_WriteReg(tmp, CLLR, 0U);
346
347 /* Reset DMAx_Channely pending flags */
348 LL_DMA_WriteReg(tmp, CFCR, 0x00003F00U);
349
350 /* Reset DMAx_Channely attribute */
351 LL_DMA_DisableChannelPrivilege(DMAx, Channel);
352 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
353 LL_DMA_DisableChannelSecure(DMAx, Channel);
354 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
355 }
356
357 return (uint32_t)status;
358 }
359
360 /**
361 * @brief Initialize the DMA registers according to the specified parameters
362 * in DMA_InitStruct.
363 * @note This API is used for all available DMA channels.
364 * @note A software request transfer can be done once programming the direction
365 * field in memory to memory value.
366 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
367 * helper macros :
368 * @arg @ref LL_DMA_GET_INSTANCE
369 * @arg @ref LL_DMA_GET_CHANNEL
370 * @param DMAx DMAx Instance
371 * @param Channel This parameter can be one of the following values:
372 * @arg @ref LL_DMA_CHANNEL_0
373 * @arg @ref LL_DMA_CHANNEL_1
374 * @arg @ref LL_DMA_CHANNEL_2
375 * @arg @ref LL_DMA_CHANNEL_3
376 * @arg @ref LL_DMA_CHANNEL_4
377 * @arg @ref LL_DMA_CHANNEL_5
378 * @arg @ref LL_DMA_CHANNEL_6
379 * @arg @ref LL_DMA_CHANNEL_7
380 * @arg @ref LL_DMA_CHANNEL_8
381 * @arg @ref LL_DMA_CHANNEL_9
382 * @arg @ref LL_DMA_CHANNEL_10
383 * @arg @ref LL_DMA_CHANNEL_11
384 * @arg @ref LL_DMA_CHANNEL_12
385 * @arg @ref LL_DMA_CHANNEL_13
386 * @arg @ref LL_DMA_CHANNEL_14
387 * @arg @ref LL_DMA_CHANNEL_15
388 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
389 * @retval An ErrorStatus enumeration value:
390 * - SUCCESS : DMA registers are initialized.
391 * - ERROR : Not applicable.
392 */
LL_DMA_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitTypeDef * DMA_InitStruct)393 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
394 {
395 /* Check the DMA Instance DMAx and Channel parameters*/
396 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
397
398 /* Check the DMA parameters from DMA_InitStruct */
399 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
400
401 /* Check direction */
402 if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
403 {
404 assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitStruct->Request));
405 }
406
407 assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitStruct->DataAlignment));
408 assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitStruct->SrcDataWidth));
409 assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitStruct->DestDataWidth));
410 assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitStruct->SrcIncMode));
411 assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitStruct->DestIncMode));
412 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
413 assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitStruct->BlkDataLength));
414 assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitStruct->TriggerPolarity));
415 assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitStruct->BlkHWRequest));
416 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitStruct->TransferEventMode));
417 assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitStruct->LinkStepMode));
418 assert_param(IS_LL_DMA_LINK_BASEADDR(DMA_InitStruct->LinkedListBaseAddr));
419 assert_param(IS_LL_DMA_LINK_ADDR_OFFSET(DMA_InitStruct->LinkedListAddrOffset));
420
421 /* Check DMA instance */
422 if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
423 {
424 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->SrcBurstLength));
425 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->DestBurstLength));
426 assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitStruct->DestHWordExchange));
427 assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitStruct->DestByteExchange));
428 assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitStruct->SrcByteExchange));
429 assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitStruct->LinkAllocatedPort));
430 assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitStruct->SrcAllocatedPort));
431 assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitStruct->DestAllocatedPort));
432 }
433
434 /* Check trigger polarity */
435 if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
436 {
437 assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitStruct->TriggerMode));
438 assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitStruct->TriggerSelection));
439 }
440
441 /* Check DMA channel */
442 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
443 {
444 assert_param(IS_LL_DMA_BLK_REPEATCOUNT(DMA_InitStruct->BlkRptCount));
445 assert_param(IS_LL_DMA_BURST_SRC_ADDR_UPDATE(DMA_InitStruct->SrcAddrUpdateMode));
446 assert_param(IS_LL_DMA_BURST_DEST_ADDR_UPDATE(DMA_InitStruct->DestAddrUpdateMode));
447 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitStruct->SrcAddrOffset));
448 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitStruct->DestAddrOffset));
449 assert_param(IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(DMA_InitStruct->BlkRptSrcAddrUpdateMode));
450 assert_param(IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(DMA_InitStruct->BlkRptDestAddrUpdateMode));
451 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitStruct->BlkRptSrcAddrOffset));
452 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitStruct->BlkRptDestAddrOffset));
453 }
454
455 /*-------------------------- DMAx CLBAR Configuration ------------------------
456 * Configure the Transfer linked list address with parameter :
457 * - LinkedListBaseAdd: DMA_CLBAR_LBA[31:16] bits
458 */
459 LL_DMA_SetLinkedListBaseAddr(DMAx, Channel, DMA_InitStruct->LinkedListBaseAddr);
460
461 /*-------------------------- DMAx CCR Configuration --------------------------
462 * Configure the control parameter :
463 * - LinkAllocatedPort: DMA_CCR_LAP bit
464 * LinkAllocatedPort field is not supported by LPDMA channels.
465 * - LinkStepMode: DMA_CCR_LSM bit
466 * - Priority: DMA_CCR_PRIO [23:22] bits
467 */
468 LL_DMA_ConfigControl(DMAx, Channel, DMA_InitStruct->Priority | \
469 DMA_InitStruct->LinkAllocatedPort | \
470 DMA_InitStruct->LinkStepMode);
471
472 /*-------------------------- DMAx CTR1 Configuration -------------------------
473 * Configure the Data transfer parameter :
474 * - DestAllocatedPort: DMA_CTR1_DAP bit
475 * DestAllocatedPort field is not supported by LPDMA channels.
476 * - DestHWordExchange: DMA_CTR1_DHX bit
477 * DestHWordExchange field is not supported by LPDMA channels.
478 * - DestByteExchange: DMA_CTR1_DBX bit
479 * DestByteExchange field is not supported by LPDMA channels.
480 * - DestIncMode: DMA_CTR1_DINC bit
481 * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits
482 * - SrcAllocatedPort: DMA_CTR1_SAP bit
483 * SrcAllocatedPort field is not supported by LPDMA channels.
484 * - SrcByteExchange: DMA_CTR1_SBX bit
485 * SrcByteExchange field is not supported by LPDMA channels.
486 * - DataAlignment: DMA_CTR1_PAM [12:11] bits
487 * DataAlignment field is reduced to one bit by LPDMA channels.
488 * - SrcIncMode: DMA_CTR1_SINC bit
489 * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits
490 * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits
491 * SrcBurstLength field is not supported by LPDMA channels.
492 * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits
493 * DestBurstLength field is not supported by LPDMA channels.
494 */
495 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->DestAllocatedPort | \
496 DMA_InitStruct->DestHWordExchange | \
497 DMA_InitStruct->DestByteExchange | \
498 DMA_InitStruct->DestIncMode | \
499 DMA_InitStruct->DestDataWidth | \
500 DMA_InitStruct->SrcAllocatedPort | \
501 DMA_InitStruct->SrcByteExchange | \
502 DMA_InitStruct->DataAlignment | \
503 DMA_InitStruct->SrcIncMode | \
504 DMA_InitStruct->SrcDataWidth);
505 /* Check DMA instance */
506 if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
507 {
508 LL_DMA_ConfigBurstLength(DMAx, Channel, DMA_InitStruct->SrcBurstLength,
509 DMA_InitStruct->DestBurstLength);
510 }
511
512 /*-------------------------- DMAx CTR2 Configuration -------------------------
513 * Configure the channel transfer parameter :
514 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
515 * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits
516 * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits
517 * - BlkHWRequest: DMA_CTR2_BREQ bit
518 * - Direction: DMA_CTR2_DREQ bit
519 * - Direction: DMA_CTR2_SWREQ bit
520 * Direction field is reduced to one bit for LPDMA channels (SWREQ).
521 * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits
522 * TriggerSelection field is reduced to 5 bits for LPDMA channels.
523 * - Request: DMA_CTR2_REQSEL [6:0] bits
524 * Request field is reduced to 5 bits for LPDMA channels.
525 */
526 LL_DMA_ConfigChannelTransfer(DMAx, Channel, DMA_InitStruct->TransferEventMode | \
527 DMA_InitStruct->TriggerPolarity | \
528 DMA_InitStruct->BlkHWRequest | \
529 DMA_InitStruct->Direction);
530
531 /* Check direction */
532 if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
533 {
534 LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->Request);
535 }
536
537 /* Check trigger polarity */
538 if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
539 {
540 LL_DMA_SetHWTrigger(DMAx, Channel, DMA_InitStruct->TriggerSelection);
541 LL_DMA_SetTriggerMode(DMAx, Channel, DMA_InitStruct->TriggerMode);
542 }
543
544 /*-------------------------- DMAx CBR1 Configuration -------------------------
545 * Configure the Transfer Block counters and update mode with parameter :
546 * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits
547 * - BlkRptCount: DMA_CBR1_BRC[26:16] bits
548 * BlkRptCount field is supported only by 2D addressing channels.
549 * - BlkRptSrcAddrUpdateMode: DMA_CBR1_BRSDEC bit
550 * BlkRptSrcAddrUpdateMode field is supported only by 2D addressing channels.
551 * - BlkRptDestAddrUpdateMode: DMA_CBR1_BRDDEC bit
552 * BlkRptDestAddrUpdateMode field is supported only by 2D addressing channels.
553 * - SrcAddrUpdateMode: DMA_CBR1_SDEC bit
554 * SrcAddrUpdateMode field is supported only by 2D addressing channels.
555 * - DestAddrUpdateMode: DMA_CBR1_DDEC bit
556 * DestAddrUpdateMode field is supported only by 2D addressing channels.
557 */
558 LL_DMA_SetBlkDataLength(DMAx, Channel, DMA_InitStruct->BlkDataLength);
559
560 /* Check DMA channel */
561 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
562 {
563 LL_DMA_SetBlkRptCount(DMAx, Channel, DMA_InitStruct->BlkRptCount);
564 LL_DMA_ConfigBlkRptAddrUpdate(DMAx, Channel, DMA_InitStruct->BlkRptSrcAddrUpdateMode | \
565 DMA_InitStruct->BlkRptDestAddrUpdateMode | \
566 DMA_InitStruct->SrcAddrUpdateMode | \
567 DMA_InitStruct->DestAddrUpdateMode);
568 }
569
570 /*-------------------------- DMAx CSAR and CDAR Configuration ----------------
571 * Configure the Transfer source address with parameter :
572 * - SrcAddress: DMA_CSAR_SA[31:0] bits
573 * - DestAddress: DMA_CDAR_DA[31:0] bits
574 */
575 LL_DMA_ConfigAddresses(DMAx, Channel, DMA_InitStruct->SrcAddress, DMA_InitStruct->DestAddress);
576
577 /* Check DMA channel */
578 if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
579 {
580 /*------------------------ DMAx CTR3 Configuration -------------------------
581 * Configure the Transfer Block counters and update mode with parameter :
582 * - SrcAddrOffset: DMA_CTR3_SAO[28:16] bits
583 * SrcAddrOffset field is supported only by 2D addressing channels.
584 * - DestAddrOffset: DMA_CTR3_DAO[12:0] bits
585 * DestAddrOffset field is supported only by 2D addressing channels.
586 */
587 LL_DMA_ConfigAddrUpdateValue(DMAx, Channel, DMA_InitStruct->SrcAddrOffset, DMA_InitStruct->DestAddrOffset);
588
589 /*------------------------ DMAx CBR2 Configuration -----------------------
590 * Configure the Transfer Block counters and update mode with parameter :
591 * - BlkRptSrcAddrOffset: DMA_CBR2_BRSAO[15:0] bits
592 * BlkRptSrcAddrOffset field is supported only by 2D addressing channels.
593 * - BlkRptDestAddrOffset: DMA_CBR2_BRDAO[31:16] bits
594 * BlkRptDestAddrOffset field is supported only by 2D addressing channels.
595 */
596 LL_DMA_ConfigBlkRptAddrUpdateValue(DMAx, Channel, DMA_InitStruct->BlkRptSrcAddrOffset,
597 DMA_InitStruct->BlkRptDestAddrOffset);
598 }
599
600 /*-------------------------- DMAx CLLR Configuration -------------------------
601 * Configure the Transfer linked list address with parameter :
602 * - DestAddrOffset: DMA_CLLR_LA[15:2] bits
603 */
604 LL_DMA_SetLinkedListAddrOffset(DMAx, Channel, DMA_InitStruct->LinkedListAddrOffset);
605
606 return (uint32_t)SUCCESS;
607 }
608
609 /**
610 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
611 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
612 * @retval None.
613 */
LL_DMA_StructInit(LL_DMA_InitTypeDef * DMA_InitStruct)614 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
615 {
616 /* Set DMA_InitStruct fields to default values */
617 DMA_InitStruct->SrcAddress = 0x00000000U;
618 DMA_InitStruct->DestAddress = 0x00000000U;
619 DMA_InitStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
620 DMA_InitStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
621 DMA_InitStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
622 DMA_InitStruct->SrcBurstLength = 1U;
623 DMA_InitStruct->DestBurstLength = 1U;
624 DMA_InitStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE;
625 DMA_InitStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE;
626 DMA_InitStruct->SrcIncMode = LL_DMA_SRC_FIXED;
627 DMA_InitStruct->DestIncMode = LL_DMA_DEST_FIXED;
628 DMA_InitStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
629 DMA_InitStruct->BlkDataLength = 0x00000000U;
630 DMA_InitStruct->BlkRptCount = 0x00000000U;
631 DMA_InitStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER;
632 DMA_InitStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED;
633 DMA_InitStruct->TriggerSelection = 0x00000000U;
634 DMA_InitStruct->Request = 0x00000000U;
635 DMA_InitStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER;
636 DMA_InitStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE;
637 DMA_InitStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE;
638 DMA_InitStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE;
639 DMA_InitStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0;
640 DMA_InitStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0;
641 DMA_InitStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0;
642 DMA_InitStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION;
643 DMA_InitStruct->SrcAddrUpdateMode = LL_DMA_BURST_SRC_ADDR_INCREMENT;
644 DMA_InitStruct->DestAddrUpdateMode = LL_DMA_BURST_DEST_ADDR_INCREMENT;
645 DMA_InitStruct->SrcAddrOffset = 0x00000000U;
646 DMA_InitStruct->DestAddrOffset = 0x00000000U;
647 DMA_InitStruct->BlkRptSrcAddrUpdateMode = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT;
648 DMA_InitStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT;
649 DMA_InitStruct->BlkRptSrcAddrOffset = 0x00000000U;
650 DMA_InitStruct->BlkRptDestAddrOffset = 0x00000000U;
651 DMA_InitStruct->LinkedListBaseAddr = 0x00000000U;
652 DMA_InitStruct->LinkedListAddrOffset = 0x00000000U;
653 }
654
655 /**
656 * @brief Set each @ref LL_DMA_InitLinkedListTypeDef field to default value.
657 * @param DMA_InitLinkedListStruct Pointer to
658 * a @ref LL_DMA_InitLinkedListTypeDef structure.
659 * @retval None.
660 */
LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef * DMA_InitLinkedListStruct)661 void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct)
662 {
663 /* Set LL_DMA_InitLinkedListTypeDef fields to default values */
664 DMA_InitLinkedListStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT;
665 DMA_InitLinkedListStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION;
666 DMA_InitLinkedListStruct->TransferEventMode = LL_DMA_TCEM_LAST_LLITEM_TRANSFER;
667 DMA_InitLinkedListStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0;
668 }
669
670 /**
671 * @brief De-initialize the DMA linked list.
672 * @note This API is used for all available DMA channels.
673 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
674 * helper macros :
675 * @arg @ref LL_DMA_GET_INSTANCE
676 * @arg @ref LL_DMA_GET_CHANNEL
677 * @param DMAx DMAx Instance
678 * @param Channel This parameter can be one of the following values:
679 * @arg @ref LL_DMA_CHANNEL_0
680 * @arg @ref LL_DMA_CHANNEL_1
681 * @arg @ref LL_DMA_CHANNEL_2
682 * @arg @ref LL_DMA_CHANNEL_3
683 * @arg @ref LL_DMA_CHANNEL_4
684 * @arg @ref LL_DMA_CHANNEL_5
685 * @arg @ref LL_DMA_CHANNEL_6
686 * @arg @ref LL_DMA_CHANNEL_7
687 * @arg @ref LL_DMA_CHANNEL_8
688 * @arg @ref LL_DMA_CHANNEL_9
689 * @arg @ref LL_DMA_CHANNEL_10
690 * @arg @ref LL_DMA_CHANNEL_11
691 * @arg @ref LL_DMA_CHANNEL_12
692 * @arg @ref LL_DMA_CHANNEL_13
693 * @arg @ref LL_DMA_CHANNEL_14
694 * @arg @ref LL_DMA_CHANNEL_15
695 * @retval An ErrorStatus enumeration value:
696 * - SUCCESS : DMA registers are de-initialized.
697 * - ERROR : DMA registers are not de-initialized.
698 */
LL_DMA_List_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)699 uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
700 {
701 return LL_DMA_DeInit(DMAx, Channel);
702 }
703
704 /**
705 * @brief Initialize the DMA linked list according to the specified parameters
706 * in LL_DMA_InitLinkedListTypeDef.
707 * @note This API is used for all available DMA channels.
708 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use
709 * helper macros :
710 * @arg @ref LL_DMA_GET_INSTANCE
711 * @arg @ref LL_DMA_GET_CHANNEL
712 * @param DMAx DMAx Instance
713 * @param Channel This parameter can be one of the following values:
714 * @arg @ref LL_DMA_CHANNEL_0
715 * @arg @ref LL_DMA_CHANNEL_1
716 * @arg @ref LL_DMA_CHANNEL_2
717 * @arg @ref LL_DMA_CHANNEL_3
718 * @arg @ref LL_DMA_CHANNEL_4
719 * @arg @ref LL_DMA_CHANNEL_5
720 * @arg @ref LL_DMA_CHANNEL_6
721 * @arg @ref LL_DMA_CHANNEL_7
722 * @arg @ref LL_DMA_CHANNEL_8
723 * @arg @ref LL_DMA_CHANNEL_9
724 * @arg @ref LL_DMA_CHANNEL_10
725 * @arg @ref LL_DMA_CHANNEL_11
726 * @arg @ref LL_DMA_CHANNEL_12
727 * @arg @ref LL_DMA_CHANNEL_13
728 * @arg @ref LL_DMA_CHANNEL_14
729 * @arg @ref LL_DMA_CHANNEL_15
730 * @param DMA_InitLinkedListStruct pointer to
731 * a @ref LL_DMA_InitLinkedListTypeDef structure.
732 * @retval An ErrorStatus enumeration value:
733 * - SUCCESS : DMA registers are initialized.
734 * - ERROR : Not applicable.
735 */
LL_DMA_List_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitLinkedListTypeDef * DMA_InitLinkedListStruct)736 uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct)
737 {
738 /* Check the DMA Instance DMAx and Channel parameters*/
739 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
740
741 /* Check the DMA parameters from DMA_InitLinkedListStruct */
742 assert_param(IS_LL_DMA_PRIORITY(DMA_InitLinkedListStruct->Priority));
743 assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitLinkedListStruct->LinkStepMode));
744 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitLinkedListStruct->TransferEventMode));
745 /* Check DMA instance */
746 if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U)
747 {
748 assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitLinkedListStruct->LinkAllocatedPort));
749 }
750
751 /*-------------------------- DMAx CCR Configuration --------------------------
752 * Configure the control parameter :
753 * - LinkAllocatedPort: DMA_CCR_LAP bit
754 * LinkAllocatedPort field is supported only by GPDMA channels.
755 * - LinkStepMode: DMA_CCR_LSM bit
756 * - Priority: DMA_CCR_PRIO [23:22] bits
757 */
758 LL_DMA_ConfigControl(DMAx, Channel, DMA_InitLinkedListStruct->Priority | \
759 DMA_InitLinkedListStruct->LinkAllocatedPort | \
760 DMA_InitLinkedListStruct->LinkStepMode);
761
762 /*-------------------------- DMAx CTR2 Configuration -------------------------
763 * Configure the channel transfer parameter :
764 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
765 */
766 LL_DMA_SetTransferEventMode(DMAx, Channel, DMA_InitLinkedListStruct->TransferEventMode);
767
768 return (uint32_t)SUCCESS;
769 }
770
771 /**
772 * @brief Set each @ref LL_DMA_InitNodeTypeDef field to default value.
773 * @param DMA_InitNodeStruct Pointer to a @ref LL_DMA_InitNodeTypeDef
774 * structure.
775 * @retval None.
776 */
LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef * DMA_InitNodeStruct)777 void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct)
778 {
779 /* Set DMA_InitNodeStruct fields to default values */
780 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
781 DMA_InitNodeStruct->DestSecure = LL_DMA_CHANNEL_DEST_NSEC;
782 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
783 DMA_InitNodeStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0;
784 DMA_InitNodeStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE;
785 DMA_InitNodeStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE;
786 DMA_InitNodeStruct->DestBurstLength = 1U;
787 DMA_InitNodeStruct->DestIncMode = LL_DMA_DEST_FIXED;
788 DMA_InitNodeStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE;
789 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
790 DMA_InitNodeStruct->SrcSecure = LL_DMA_CHANNEL_SRC_NSEC;
791 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
792 DMA_InitNodeStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0;
793 DMA_InitNodeStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE;
794 DMA_InitNodeStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
795 DMA_InitNodeStruct->SrcBurstLength = 1U;
796 DMA_InitNodeStruct->SrcIncMode = LL_DMA_SRC_FIXED;
797 DMA_InitNodeStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE;
798 DMA_InitNodeStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER;
799 DMA_InitNodeStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED;
800 DMA_InitNodeStruct->TriggerSelection = 0x00000000U;
801 DMA_InitNodeStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER;
802 DMA_InitNodeStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
803 DMA_InitNodeStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
804 DMA_InitNodeStruct->Request = 0x00000000U;
805 DMA_InitNodeStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT;
806 DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT;
807 DMA_InitNodeStruct->DestAddrUpdateMode = LL_DMA_BURST_DEST_ADDR_INCREMENT;
808 DMA_InitNodeStruct->SrcAddrUpdateMode = LL_DMA_BURST_SRC_ADDR_INCREMENT;
809 DMA_InitNodeStruct->BlkRptCount = 0x00000000U;
810 DMA_InitNodeStruct->BlkDataLength = 0x00000000U;
811 DMA_InitNodeStruct->SrcAddress = 0x00000000U;
812 DMA_InitNodeStruct->DestAddress = 0x00000000U;
813 DMA_InitNodeStruct->DestAddrOffset = 0x00000000U;
814 DMA_InitNodeStruct->SrcAddrOffset = 0x00000000U;
815 DMA_InitNodeStruct->BlkRptDestAddrOffset = 0x00000000U;
816 DMA_InitNodeStruct->BlkRptSrcAddrOffset = 0x00000000U;
817 DMA_InitNodeStruct->UpdateRegisters = (LL_DMA_UPDATE_CTR1 | LL_DMA_UPDATE_CTR2 | \
818 LL_DMA_UPDATE_CBR1 | LL_DMA_UPDATE_CSAR | \
819 LL_DMA_UPDATE_CDAR | LL_DMA_UPDATE_CTR3 | \
820 LL_DMA_UPDATE_CBR2 | LL_DMA_UPDATE_CLLR);
821 DMA_InitNodeStruct->NodeType = LL_DMA_GPDMA_LINEAR_NODE;
822 }
823
824 /**
825 * @brief Initializes DMA linked list node according to the specified
826 * parameters in the DMA_InitNodeStruct.
827 * @param DMA_InitNodeStruct Pointer to a LL_DMA_InitNodeTypeDef structure
828 * that contains linked list node
829 * registers configurations.
830 * @param pNode Pointer to linked list node to fill according to
831 * LL_DMA_LinkNodeTypeDef parameters.
832 * @retval None
833 */
LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef * DMA_InitNodeStruct,LL_DMA_LinkNodeTypeDef * pNode)834 uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode)
835 {
836 uint32_t reg_counter = 0U;
837
838 /* Check the DMA Node type */
839 assert_param(IS_LL_DMA_LINK_NODETYPE(DMA_InitNodeStruct->NodeType));
840
841 /* Check the DMA parameters from DMA_InitNodeStruct */
842 assert_param(IS_LL_DMA_DIRECTION(DMA_InitNodeStruct->Direction));
843
844 /* Check direction */
845 if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
846 {
847 assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitNodeStruct->Request));
848 }
849
850 assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitNodeStruct->DataAlignment));
851 assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitNodeStruct->SrcDataWidth));
852 assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitNodeStruct->DestDataWidth));
853 assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitNodeStruct->SrcIncMode));
854 assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitNodeStruct->DestIncMode));
855 assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitNodeStruct->BlkDataLength));
856 assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitNodeStruct->TriggerPolarity));
857 assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitNodeStruct->BlkHWRequest));
858 assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitNodeStruct->TransferEventMode));
859 assert_param(IS_LL_DMA_LINK_UPDATE_REGISTERS(DMA_InitNodeStruct->UpdateRegisters));
860
861 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
862 assert_param(IS_LL_DMA_CHANNEL_SRC_SEC(DMA_InitNodeStruct->SrcSecure));
863 assert_param(IS_LL_DMA_CHANNEL_DEST_SEC(DMA_InitNodeStruct->DestSecure));
864 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
865
866 /* Check trigger polarity */
867 if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
868 {
869 assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitNodeStruct->TriggerMode));
870 assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection));
871 }
872
873 /* Check node type */
874 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_LINEAR_NODE)
875 {
876 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->SrcBurstLength));
877 assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->DestBurstLength));
878 assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitNodeStruct->DestHWordExchange));
879 assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitNodeStruct->DestByteExchange));
880 assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitNodeStruct->SrcByteExchange));
881 assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitNodeStruct->SrcAllocatedPort));
882 assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitNodeStruct->DestAllocatedPort));
883 }
884
885 /* Check DMA channel */
886 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
887 {
888 assert_param(IS_LL_DMA_BLK_REPEATCOUNT(DMA_InitNodeStruct->BlkRptCount));
889 assert_param(IS_LL_DMA_BURST_SRC_ADDR_UPDATE(DMA_InitNodeStruct->SrcAddrUpdateMode));
890 assert_param(IS_LL_DMA_BURST_DEST_ADDR_UPDATE(DMA_InitNodeStruct->DestAddrUpdateMode));
891 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->SrcAddrOffset));
892 assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->DestAddrOffset));
893 assert_param(IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode));
894 assert_param(IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(DMA_InitNodeStruct->BlkRptDestAddrUpdateMode));
895 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->BlkRptSrcAddrOffset));
896 assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->BlkRptDestAddrOffset));
897 }
898
899 /* Check if CTR1 register update is enabled */
900 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR1) == LL_DMA_UPDATE_CTR1)
901 {
902 /*-------------------------- DMAx CTR1 Configuration -----------------------
903 * Configure the Data transfer parameter :
904 * - DestAllocatedPort: DMA_CTR1_DAP bit
905 * DestAllocatedPort field is not supported by LPDMA channels.
906 * - DestHWordExchange: DMA_CTR1_DHX bit
907 * DestHWordExchange field is not supported by LPDMA channels.
908 * - DestByteExchange: DMA_CTR1_DBX bit
909 * DestByteExchange field is not supported by LPDMA channels.
910 * - DestIncMode: DMA_CTR1_DINC bit
911 * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits
912 * - SrcAllocatedPort: DMA_CTR1_SAP bit
913 * SrcAllocatedPort field is not supported by LPDMA channels.
914 * - SrcByteExchange: DMA_CTR1_SBX bit
915 * SrcByteExchange field is not supported by LPDMA channels.
916 * - DataAlignment: DMA_CTR1_PAM [12:11] bits
917 * DataAlignment field is reduced to one bit for LPDMA channels.
918 * - SrcIncMode: DMA_CTR1_SINC bit
919 * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits
920 * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits
921 * SrcBurstLength field is not supported by LPDMA channels.
922 * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits
923 * DestBurstLength field is not supported by LPDMA channels.
924 */
925
926 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->DestIncMode | \
927 DMA_InitNodeStruct->DestDataWidth | \
928 DMA_InitNodeStruct->DataAlignment | \
929 DMA_InitNodeStruct->SrcIncMode | \
930 DMA_InitNodeStruct->SrcDataWidth);
931
932 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
933 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestSecure | \
934 DMA_InitNodeStruct->SrcSecure);
935 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
936
937 /* Update CTR1 register fields for not LPDMA channels */
938 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestAllocatedPort | \
939 DMA_InitNodeStruct->DestHWordExchange | \
940 DMA_InitNodeStruct->DestByteExchange | \
941 ((DMA_InitNodeStruct->DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) | \
942 DMA_InitNodeStruct->SrcAllocatedPort | \
943 DMA_InitNodeStruct->SrcByteExchange | \
944 ((DMA_InitNodeStruct->SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos));
945
946 /* Increment counter for the next register */
947 reg_counter++;
948 }
949
950
951 /* Check if CTR2 register update is enabled */
952 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR2) == LL_DMA_UPDATE_CTR2)
953 {
954 /*-------------------------- DMAx CTR2 Configuration -----------------------
955 * Configure the channel transfer parameter :
956 * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits
957 * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits
958 * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits
959 * - BlkHWRequest: DMA_CTR2_BREQ bit
960 * - Direction: DMA_CTR2_DREQ bit
961 * - Direction: DMA_CTR2_SWREQ bit
962 * Direction field is reduced to one bit for LPDMA channels (SWREQ).
963 * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits
964 * DataAlignment field is reduced to 5 bits for LPDMA channels.
965 * - Request: DMA_CTR2_REQSEL [6:0] bits
966 * DataAlignment field is reduced to 5 bits for LPDMA channels.
967 */
968 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->TransferEventMode | \
969 DMA_InitNodeStruct->TriggerPolarity | \
970 DMA_InitNodeStruct->BlkHWRequest | \
971 DMA_InitNodeStruct->Direction);
972
973 /* Check direction */
974 if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY)
975 {
976 pNode->LinkRegisters[reg_counter] |= DMA_InitNodeStruct->Request & DMA_CTR2_REQSEL;
977 }
978
979 /* Check trigger polarity */
980 if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED)
981 {
982 pNode->LinkRegisters[reg_counter] |= (((DMA_InitNodeStruct->TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & \
983 DMA_CTR2_TRIGSEL) | DMA_InitNodeStruct->TriggerMode);
984 }
985
986
987 /* Increment counter for the next register */
988 reg_counter++;
989 }
990
991
992 /* Check if CBR1 register update is enabled */
993 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR1) == LL_DMA_UPDATE_CBR1)
994 {
995 /*-------------------------- DMAx CBR1 Configuration -----------------------
996 * Configure the Transfer Block counters and update mode with parameter :
997 * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits
998 * - BlkRptCount: DMA_CBR1_BRC[26:16] bits
999 * BlkRptCount field is supported only by 2D addressing channels.
1000 * - BlkRptSrcAddrUpdateMode: DMA_CBR1_BRSDEC bit
1001 * BlkRptSrcAddrUpdateMode field is supported only by 2D addressing channels.
1002 * - BlkRptDestAddrUpdateMode: DMA_CBR1_BRDDEC bit
1003 * BlkRptDestAddrUpdateMode field is supported only by 2D addressing channels.
1004 * - SrcAddrUpdateMode: DMA_CBR1_SDEC bit
1005 * SrcAddrUpdateMode field is supported only by 2D addressing channels.
1006 * - DestAddrUpdateMode: DMA_CBR1_DDEC bit
1007 * DestAddrUpdateMode field is supported only by 2D addressing channels.
1008 */
1009 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->BlkDataLength;
1010
1011 /* Update CBR1 register fields for 2D addressing channels */
1012 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
1013 {
1014 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->BlkRptDestAddrUpdateMode | \
1015 DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode | \
1016 DMA_InitNodeStruct->DestAddrUpdateMode | \
1017 DMA_InitNodeStruct->SrcAddrUpdateMode | \
1018 ((DMA_InitNodeStruct->BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC));
1019 }
1020
1021 /* Increment counter for the next register */
1022 reg_counter++;
1023 }
1024
1025
1026 /* Check if CSAR register update is enabled */
1027 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CSAR) == LL_DMA_UPDATE_CSAR)
1028 {
1029 /*-------------------------- DMAx CSAR Configuration -----------------------
1030 * Configure the Transfer Block counters and update mode with parameter :
1031 * - SrcAddress: DMA_CSAR_SA[31:0] bits
1032 */
1033 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->SrcAddress;
1034
1035 /* Increment counter for the next register */
1036 reg_counter++;
1037 }
1038
1039
1040 /* Check if CDAR register update is enabled */
1041 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CDAR) == LL_DMA_UPDATE_CDAR)
1042 {
1043 /*-------------------------- DMAx CDAR Configuration -----------------------
1044 * Configure the Transfer Block counters and update mode with parameter :
1045 * - DestAddress: DMA_CDAR_DA[31:0] bits
1046 */
1047 pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->DestAddress;
1048
1049 /* Increment counter for the next register */
1050 reg_counter++;
1051 }
1052
1053
1054 /* Update CTR3 register fields for 2D addressing channels */
1055 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
1056 {
1057 /* Check if CTR3 register update is enabled */
1058 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR3) == LL_DMA_UPDATE_CTR3)
1059 {
1060 /*-------------------------- DMAx CTR3 Configuration ---------------------
1061 * Configure the Block counters and update mode with parameter :
1062 * - DestAddressOffset: DMA_CTR3_DAO[12:0] bits
1063 * DestAddressOffset field is supported only by 2D addressing channels.
1064 * - SrcAddressOffset: DMA_CTR3_SAO[12:0] bits
1065 * SrcAddressOffset field is supported only by 2D addressing channels.
1066 */
1067 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->SrcAddrOffset | \
1068 ((DMA_InitNodeStruct->DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
1069
1070 /* Increment counter for the next register */
1071 reg_counter++;
1072 }
1073 }
1074
1075
1076 /* Update CBR2 register fields for 2D addressing channels */
1077 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
1078 {
1079 /* Check if CBR2 register update is enabled */
1080 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR2) == LL_DMA_UPDATE_CBR2)
1081 {
1082 /*-------------------------- DMAx CBR2 Configuration ---------------------
1083 * Configure the Block counters and update mode with parameter :
1084 * - BlkRptDestAddrOffset: DMA_CBR2_BRDAO[31:16] bits
1085 * BlkRptDestAddrOffset field is supported only by 2D addressing channels.
1086 * - BlkRptSrcAddrOffset: DMA_CBR2_BRSAO[15:0] bits
1087 * BlkRptSrcAddrOffset field is supported only by 2D addressing channels.
1088 */
1089 pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->BlkRptSrcAddrOffset | \
1090 ((DMA_InitNodeStruct->BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & \
1091 DMA_CBR2_BRDAO));
1092
1093 /* Increment counter for the next register */
1094 reg_counter++;
1095 }
1096 }
1097
1098 /* Check if CLLR register update is enabled */
1099 if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CLLR) == LL_DMA_UPDATE_CLLR)
1100 {
1101 /*-------------------------- DMAx CLLR Configuration -----------------------
1102 * Configure the Transfer Block counters and update mode with parameter :
1103 * - UpdateRegisters DMA_CLLR_UT1 bit
1104 * - UpdateRegisters DMA_CLLR_UT2 bit
1105 * - UpdateRegisters DMA_CLLR_UB1 bit
1106 * - UpdateRegisters DMA_CLLR_USA bit
1107 * - UpdateRegisters DMA_CLLR_UDA bit
1108 * - UpdateRegisters DMA_CLLR_UT3 bit
1109 * DMA_CLLR_UT3 bit is discarded for linear addressing channels.
1110 * - UpdateRegisters DMA_CLLR_UB2 bit
1111 * DMA_CLLR_UB2 bit is discarded for linear addressing channels.
1112 * - UpdateRegisters DMA_CLLR_ULL bit
1113 */
1114 pNode->LinkRegisters[reg_counter] = ((DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT1 | DMA_CLLR_UT2 | \
1115 DMA_CLLR_UB1 | DMA_CLLR_USA | \
1116 DMA_CLLR_UDA | DMA_CLLR_ULL)));
1117
1118 /* Update CLLR register fields for 2D addressing channels */
1119 if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE)
1120 {
1121 pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT3 | DMA_CLLR_UB2));
1122 }
1123 }
1124
1125 return (uint32_t)SUCCESS;
1126 }
1127
1128 /**
1129 * @brief Connect Linked list Nodes.
1130 * @param pPrevLinkNode Pointer to previous linked list node to be connected to new Linked list node.
1131 * @param PrevNodeCLLRIdx Offset of Previous Node CLLR register.
1132 * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET.
1133 * @param pNewLinkNode Pointer to new Linked list.
1134 * @param NewNodeCLLRIdx Offset of New Node CLLR register.
1135 * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET.
1136 * @retval None
1137 */
LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef * pPrevLinkNode,uint32_t PrevNodeCLLRIdx,LL_DMA_LinkNodeTypeDef * pNewLinkNode,uint32_t NewNodeCLLRIdx)1138 void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
1139 LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx)
1140 {
1141 pPrevLinkNode->LinkRegisters[PrevNodeCLLRIdx] = (((uint32_t)pNewLinkNode & DMA_CLLR_LA) | \
1142 (pNewLinkNode->LinkRegisters[NewNodeCLLRIdx] & (DMA_CLLR_UT1 | \
1143 DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \
1144 DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL)));
1145 }
1146
1147 /**
1148 * @brief Disconnect the next linked list node.
1149 * @param pLinkNode Pointer to linked list node to be disconnected from the next one.
1150 * @param LinkNodeCLLRIdx Offset of Link Node CLLR register.
1151 * @retval None.
1152 */
LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef * pLinkNode,uint32_t LinkNodeCLLRIdx)1153 void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx)
1154 {
1155 pLinkNode->LinkRegisters[LinkNodeCLLRIdx] = 0;
1156 }
1157
1158 /**
1159 * @}
1160 */
1161
1162 /**
1163 * @}
1164 */
1165
1166 /**
1167 * @}
1168 */
1169
1170 #endif /* defined (GPDMA1) */
1171
1172 /**
1173 * @}
1174 */
1175
1176 #endif /* defined (USE_FULL_LL_DRIVER) */
1177
