1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32h5xx_ll_adc.h"
22 #include "stm32h5xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 /* Definitions of ADC hardware constraints delays */
48 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49 /* not timeout values: */
50 /* Timeout values for ADC operations are dependent to device clock */
51 /* configuration (system clock versus ADC clock), */
52 /* and therefore must be defined in user application. */
53 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54 /* values definition. */
55 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
56 /* of device clock setting. */
57 /* In user application, ADC timeout values should be defined with */
58 /* temporal values, in function of device clock settings. */
59 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
60 /* - ADC clock from synchronous clock with AHB prescaler 512, */
61 /* ADC prescaler 4. */
62 /* Ratio max = 512 *4 = 2048 */
63 /* - ADC clock from asynchronous clock (PLLP) with prescaler 256. */
64 /* Highest CPU clock PLL (PLLR). */
65 /* Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256 */
66 /* = 3968 */
67 /* Unit: CPU cycles. */
68 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (3968UL)
69 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
70 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
71
72 /**
73 * @}
74 */
75
76 /* Private macros ------------------------------------------------------------*/
77
78 /** @addtogroup ADC_LL_Private_Macros
79 * @{
80 */
81
82 /* Check of parameters for configuration of ADC hierarchical scope: */
83 /* common to several ADC instances. */
84 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
85 (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
86 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
87 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
93 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
94 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
97 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
98 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
99 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
100 )
101
102 /* Check of parameters for configuration of ADC hierarchical scope: */
103 /* ADC instance. */
104 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
105 (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
106 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
107 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
108 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
109 )
110
111 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
112 (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
113 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
114 )
115
116 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
117 (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
118 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
119 )
120
121 /* Check of parameters for configuration of ADC hierarchical scope: */
122 /* ADC group regular */
123 #if defined(TIM8)
124 /* Devices STM32H563/H573xx */
125 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
126 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
127 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
128 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
129 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
130 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
131 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
132 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
133 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
134 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
135 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
136 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
137 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE15) \
144 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) \
145 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) \
146 )
147 #else
148 /* Devices STM32H503xx */
149 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
150 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
151 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
152 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
153 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
154 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
155 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
156 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
157 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
158 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
159 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
160 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
161 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
162 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE15) \
163 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \
164 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) \
165 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) \
166 )
167 #endif /* Devices STM32H563/H573xx or STM32H503xx */
168
169 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
170 (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
171 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
172 )
173
174 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
175 (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
176 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
177 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
178 )
179
180 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
181 (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
182 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
183 )
184
185 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
186 (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
187 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
188 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
189 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
190 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
191 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
192 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
193 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
194 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
195 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
196 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
197 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
198 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
199 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
200 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
201 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
202 )
203
204 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
205 (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
206 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
207 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
208 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
209 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
210 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
211 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
212 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
213 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
214 )
215
216 /* Check of parameters for configuration of ADC hierarchical scope: */
217 /* ADC group injected */
218 #if defined(TIM8)
219 /* Devices STM32H563/H573xx */
220 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
221 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
222 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
223 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
224 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
225 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
226 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
227 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
228 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
229 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
230 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
231 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
232 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
233 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
234 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
235 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
236 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
237 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
238 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_CH1) \
239 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_CH1) \
240 )
241 #else
242 /* Devices STM32H503xx */
243 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
244 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
245 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
246 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
247 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
248 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
249 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
250 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
251 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
252 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
253 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
254 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
255 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
256 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \
257 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_CH1) \
258 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_CH1) \
259 )
260 #endif /* Devices STM32H563/H573xx or STM32H503xx */
261
262 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
263 (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
264 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
265 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
266 )
267
268 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
269 (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
270 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
271 )
272
273 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
274 (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
275 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
276 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
277 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
278 )
279
280 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
281 (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
282 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
283 )
284
285 #if defined(ADC_MULTIMODE_SUPPORT)
286 /* Check of parameters for configuration of ADC hierarchical scope: */
287 /* multimode. */
288 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
289 (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
290 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
291 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
292 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
293 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
294 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
295 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
296 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
297 )
298
299 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
300 (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
301 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \
302 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \
303 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \
304 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \
305 )
306
307 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
308 (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
309 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \
310 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \
311 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \
312 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
313 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
314 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
315 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
316 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
317 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
318 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
319 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
320 )
321
322 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
323 (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
324 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
325 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
326 )
327
328 #endif /* ADC_MULTIMODE_SUPPORT */
329 /**
330 * @}
331 */
332
333
334 /* Private function prototypes -----------------------------------------------*/
335
336 /* Exported functions --------------------------------------------------------*/
337 /** @addtogroup ADC_LL_Exported_Functions
338 * @{
339 */
340
341 /** @addtogroup ADC_LL_EF_Init
342 * @{
343 */
344
345 /**
346 * @brief De-initialize registers of all ADC instances belonging to
347 * the same ADC common instance to their default reset values.
348 * @note This function is performing a hard reset, using high level
349 * clock source RCC ADC reset.
350 * Caution: On this STM32 series, if several ADC instances are available
351 * on the selected device, RCC ADC reset will reset
352 * all ADC instances belonging to the common ADC instance.
353 * To de-initialize only 1 ADC instance, use
354 * function @ref LL_ADC_DeInit().
355 * @param ADCxy_COMMON ADC common instance
356 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
357 * @retval An ErrorStatus enumeration value:
358 * - SUCCESS: ADC common registers are de-initialized
359 * - ERROR: not applicable
360 */
LL_ADC_CommonDeInit(ADC_Common_TypeDef * ADCxy_COMMON)361 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
362 {
363 /* Check the parameters */
364 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
365
366 /* Prevent unused argument compilation warning */
367 (void)(ADCxy_COMMON);
368
369 /* Force reset of ADC clock (core clock) */
370 LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC);
371
372 /* Release reset of ADC clock (core clock) */
373 LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC);
374
375 return SUCCESS;
376 }
377
378 /**
379 * @brief Initialize some features of ADC common parameters
380 * (all ADC instances belonging to the same ADC common instance)
381 * and multimode (for devices with several ADC instances available).
382 * @note The setting of ADC common parameters is conditioned to
383 * ADC instances state:
384 * All ADC instances belonging to the same ADC common instance
385 * must be disabled.
386 * @param ADCxy_COMMON ADC common instance
387 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
388 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
389 * @retval An ErrorStatus enumeration value:
390 * - SUCCESS: ADC common registers are initialized
391 * - ERROR: ADC common registers are not initialized
392 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,const LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)393 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
394 {
395 ErrorStatus status = SUCCESS;
396
397 /* Check the parameters */
398 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
399 assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock));
400
401 #if defined(ADC_MULTIMODE_SUPPORT)
402 assert_param(IS_LL_ADC_MULTI_MODE(pADC_CommonInitStruct->Multimode));
403 if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
404 {
405 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(pADC_CommonInitStruct->MultiDMATransfer));
406 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(pADC_CommonInitStruct->MultiTwoSamplingDelay));
407 }
408 #endif /* ADC_MULTIMODE_SUPPORT */
409
410 /* Note: Hardware constraint (refer to description of functions */
411 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
412 /* On this STM32 series, setting of these features is conditioned to */
413 /* ADC state: */
414 /* All ADC instances of the ADC common group must be disabled. */
415 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
416 {
417 /* Configuration of ADC hierarchical scope: */
418 /* - common to several ADC */
419 /* (all ADC instances belonging to the same ADC common instance) */
420 /* - Set ADC clock (conversion clock) */
421 /* - multimode (if several ADC instances available on the */
422 /* selected device) */
423 /* - Set ADC multimode configuration */
424 /* - Set ADC multimode DMA transfer */
425 /* - Set ADC multimode: delay between 2 sampling phases */
426 #if defined(ADC_MULTIMODE_SUPPORT)
427 if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
428 {
429 MODIFY_REG(ADCxy_COMMON->CCR,
430 ADC_CCR_CKMODE
431 | ADC_CCR_PRESC
432 | ADC_CCR_DUAL
433 | ADC_CCR_MDMA
434 | ADC_CCR_DELAY
435 ,
436 pADC_CommonInitStruct->CommonClock
437 | pADC_CommonInitStruct->Multimode
438 | pADC_CommonInitStruct->MultiDMATransfer
439 | pADC_CommonInitStruct->MultiTwoSamplingDelay
440 );
441 }
442 else
443 {
444 MODIFY_REG(ADCxy_COMMON->CCR,
445 ADC_CCR_CKMODE
446 | ADC_CCR_PRESC
447 | ADC_CCR_DUAL
448 | ADC_CCR_MDMA
449 | ADC_CCR_DELAY
450 ,
451 pADC_CommonInitStruct->CommonClock
452 | LL_ADC_MULTI_INDEPENDENT
453 );
454 }
455 #else
456 LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock);
457 #endif /* ADC_MULTIMODE_SUPPORT */
458 }
459 else
460 {
461 /* Initialization error: One or several ADC instances belonging to */
462 /* the same ADC common instance are not disabled. */
463 status = ERROR;
464 }
465
466 return status;
467 }
468
469 /**
470 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
471 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
472 * whose fields will be set to default values.
473 * @retval None
474 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)475 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
476 {
477 /* Set pADC_CommonInitStruct fields to default values */
478 /* Set fields of ADC common */
479 /* (all ADC instances belonging to the same ADC common instance) */
480 pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
481
482 #if defined(ADC_MULTIMODE_SUPPORT)
483 /* Set fields of ADC multimode */
484 pADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
485 pADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
486 pADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
487 #endif /* ADC_MULTIMODE_SUPPORT */
488 }
489
490 /**
491 * @brief De-initialize registers of the selected ADC instance
492 * to their default reset values.
493 * @note To reset all ADC instances quickly (perform a hard reset),
494 * use function @ref LL_ADC_CommonDeInit().
495 * @note If this functions returns error status, it means that ADC instance
496 * is in an unknown state.
497 * In this case, perform a hard reset using high level
498 * clock source RCC ADC reset.
499 * Caution: On this STM32 series, if several ADC instances are available
500 * on the selected device, RCC ADC reset will reset
501 * all ADC instances belonging to the common ADC instance.
502 * Refer to function @ref LL_ADC_CommonDeInit().
503 * @param ADCx ADC instance
504 * @retval An ErrorStatus enumeration value:
505 * - SUCCESS: ADC registers are de-initialized
506 * - ERROR: ADC registers are not de-initialized
507 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)508 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
509 {
510 ErrorStatus status = SUCCESS;
511
512 __IO uint32_t timeout_cpu_cycles = 0UL;
513
514 /* Check the parameters */
515 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
516
517 /* Disable ADC instance if not already disabled. */
518 if (LL_ADC_IsEnabled(ADCx) == 1UL)
519 {
520 /* Set ADC group regular trigger source to SW start to ensure to not */
521 /* have an external trigger event occurring during the conversion stop */
522 /* ADC disable process. */
523 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
524
525 /* Stop potential ADC conversion on going on ADC group regular. */
526 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
527 {
528 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
529 {
530 LL_ADC_REG_StopConversion(ADCx);
531 }
532 }
533
534 /* Set ADC group injected trigger source to SW start to ensure to not */
535 /* have an external trigger event occurring during the conversion stop */
536 /* ADC disable process. */
537 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
538
539 /* Stop potential ADC conversion on going on ADC group injected. */
540 if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
541 {
542 if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
543 {
544 LL_ADC_INJ_StopConversion(ADCx);
545 }
546 }
547
548 /* Wait for ADC conversions are effectively stopped */
549 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
550 while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
551 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
552 {
553 timeout_cpu_cycles--;
554 if (timeout_cpu_cycles == 0UL)
555 {
556 /* Time-out error */
557 status = ERROR;
558 break;
559 }
560 }
561
562 /* Flush group injected contexts queue (register JSQR): */
563 /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
564 /* contexts queue is maintained with the last active context). */
565 LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
566
567 /* Disable the ADC instance */
568 LL_ADC_Disable(ADCx);
569
570 /* Wait for ADC instance is effectively disabled */
571 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
572 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
573 {
574 timeout_cpu_cycles--;
575 if (timeout_cpu_cycles == 0UL)
576 {
577 /* Time-out error */
578 status = ERROR;
579 break;
580 }
581 }
582 }
583
584 /* Check whether ADC state is compliant with expected state */
585 if (READ_BIT(ADCx->CR,
586 (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
587 | ADC_CR_ADDIS | ADC_CR_ADEN)
588 )
589 == 0UL)
590 {
591 /* ========== Reset ADC registers ========== */
592 /* Reset register IER */
593 CLEAR_BIT(ADCx->IER,
594 (LL_ADC_IT_ADRDY
595 | LL_ADC_IT_EOC
596 | LL_ADC_IT_EOS
597 | LL_ADC_IT_OVR
598 | LL_ADC_IT_EOSMP
599 | LL_ADC_IT_JEOC
600 | LL_ADC_IT_JEOS
601 | LL_ADC_IT_JQOVF
602 | LL_ADC_IT_AWD1
603 | LL_ADC_IT_AWD2
604 | LL_ADC_IT_AWD3
605 )
606 );
607
608 /* Reset register ISR */
609 SET_BIT(ADCx->ISR,
610 (LL_ADC_FLAG_ADRDY
611 | LL_ADC_FLAG_EOC
612 | LL_ADC_FLAG_EOS
613 | LL_ADC_FLAG_OVR
614 | LL_ADC_FLAG_EOSMP
615 | LL_ADC_FLAG_JEOC
616 | LL_ADC_FLAG_JEOS
617 | LL_ADC_FLAG_JQOVF
618 | LL_ADC_FLAG_AWD1
619 | LL_ADC_FLAG_AWD2
620 | LL_ADC_FLAG_AWD3
621 )
622 );
623
624 /* Reset register CR */
625 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
626 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
627 /* access mode "read-set": no direct reset applicable. */
628 /* - Reset Calibration mode to default setting (single ended). */
629 /* - Disable ADC internal voltage regulator. */
630 /* - Enable ADC deep power down. */
631 /* Note: ADC internal voltage regulator disable and ADC deep power */
632 /* down enable are conditioned to ADC state disabled: */
633 /* already done above. */
634 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
635 SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
636
637 /* Reset register CFGR */
638 MODIFY_REG(ADCx->CFGR,
639 (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
640 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
641 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
642 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
643 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN
644 | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN),
645 ADC_CFGR_JQDIS
646 );
647
648 /* Reset register CFGR2 */
649 CLEAR_BIT(ADCx->CFGR2,
650 (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
651 | ADC_CFGR2_SWTRIG | ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG
652 | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
653 );
654
655 /* Reset register SMPR1 */
656 CLEAR_BIT(ADCx->SMPR1,
657 (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
658 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
659 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
660 );
661
662 /* Reset register SMPR2 */
663 CLEAR_BIT(ADCx->SMPR2,
664 (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
665 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
666 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
667 );
668
669 /* Reset register TR1 */
670 MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT | ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
671
672 /* Reset register TR2 */
673 MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
674
675 /* Reset register TR3 */
676 MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
677
678 /* Reset register SQR1 */
679 CLEAR_BIT(ADCx->SQR1,
680 (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
681 | ADC_SQR1_SQ1 | ADC_SQR1_L)
682 );
683
684 /* Reset register SQR2 */
685 CLEAR_BIT(ADCx->SQR2,
686 (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
687 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
688 );
689
690 /* Reset register SQR3 */
691 CLEAR_BIT(ADCx->SQR3,
692 (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
693 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
694 );
695
696 /* Reset register SQR4 */
697 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
698
699 /* Reset register JSQR */
700 CLEAR_BIT(ADCx->JSQR,
701 (ADC_JSQR_JL
702 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
703 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
704 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1)
705 );
706
707 /* Reset register DR */
708 /* Note: bits in access mode read only, no direct reset applicable */
709
710 /* Reset register OFR1 */
711 CLEAR_BIT(ADCx->OFR1,
712 ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 | ADC_OFR1_SATEN | ADC_OFR1_OFFSETPOS);
713 /* Reset register OFR2 */
714 CLEAR_BIT(ADCx->OFR2,
715 ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 | ADC_OFR2_SATEN | ADC_OFR2_OFFSETPOS);
716 /* Reset register OFR3 */
717 CLEAR_BIT(ADCx->OFR3,
718 ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN | ADC_OFR3_OFFSETPOS);
719 /* Reset register OFR4 */
720 CLEAR_BIT(ADCx->OFR4,
721 ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN | ADC_OFR4_OFFSETPOS);
722
723 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
724 /* Note: bits in access mode read only, no direct reset applicable */
725
726 /* Reset register AWD2CR */
727 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
728
729 /* Reset register AWD3CR */
730 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
731
732 /* Reset register DIFSEL */
733 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
734
735 /* Reset register CALFACT */
736 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
737 }
738 else
739 {
740 /* ADC instance is in an unknown state */
741 /* Need to performing a hard reset of ADC instance, using high level */
742 /* clock source RCC ADC reset. */
743 /* Caution: On this STM32 series, if several ADC instances are available */
744 /* on the selected device, RCC ADC reset will reset */
745 /* all ADC instances belonging to the common ADC instance. */
746 /* Caution: On this STM32 series, if several ADC instances are available */
747 /* on the selected device, RCC ADC reset will reset */
748 /* all ADC instances belonging to the common ADC instance. */
749 status = ERROR;
750 }
751
752 return status;
753 }
754
755 /**
756 * @brief Initialize some features of ADC instance.
757 * @note These parameters have an impact on ADC scope: ADC instance.
758 * Affects both group regular and group injected (availability
759 * of ADC group injected depends on STM32 series).
760 * Refer to corresponding unitary functions into
761 * @ref ADC_LL_EF_Configuration_ADC_Instance .
762 * @note The setting of these parameters by function @ref LL_ADC_Init()
763 * is conditioned to ADC state:
764 * ADC instance must be disabled.
765 * This condition is applied to all ADC features, for efficiency
766 * and compatibility over all STM32 series. However, the different
767 * features can be set under different ADC state conditions
768 * (setting possible with ADC enabled without conversion on going,
769 * ADC enabled with conversion on going, ...)
770 * Each feature can be updated afterwards with a unitary function
771 * and potentially with ADC in a different state than disabled,
772 * refer to description of each function for setting
773 * conditioned to ADC state.
774 * @note After using this function, some other features must be configured
775 * using LL unitary functions.
776 * The minimum configuration remaining to be done is:
777 * - Set ADC group regular or group injected sequencer:
778 * map channel on the selected sequencer rank.
779 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
780 * - Set ADC channel sampling time
781 * Refer to function LL_ADC_SetChannelSamplingTime();
782 * @param ADCx ADC instance
783 * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
784 * @retval An ErrorStatus enumeration value:
785 * - SUCCESS: ADC registers are initialized
786 * - ERROR: ADC registers are not initialized
787 */
LL_ADC_Init(ADC_TypeDef * ADCx,const LL_ADC_InitTypeDef * pADC_InitStruct)788 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct)
789 {
790 ErrorStatus status = SUCCESS;
791
792 /* Check the parameters */
793 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
794
795 assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
796 assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment));
797 assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
798
799 /* Note: Hardware constraint (refer to description of this function): */
800 /* ADC instance must be disabled. */
801 if (LL_ADC_IsEnabled(ADCx) == 0UL)
802 {
803 /* Configuration of ADC hierarchical scope: */
804 /* - ADC instance */
805 /* - Set ADC data resolution */
806 /* - Set ADC conversion data alignment */
807 /* - Set ADC low power mode */
808 MODIFY_REG(ADCx->CFGR,
809 ADC_CFGR_RES
810 | ADC_CFGR_ALIGN
811 | ADC_CFGR_AUTDLY
812 ,
813 pADC_InitStruct->Resolution
814 | pADC_InitStruct->DataAlignment
815 | pADC_InitStruct->LowPowerMode
816 );
817
818 }
819 else
820 {
821 /* Initialization error: ADC instance is not disabled. */
822 status = ERROR;
823 }
824
825 return status;
826 }
827
828 /**
829 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
830 * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
831 * whose fields will be set to default values.
832 * @retval None
833 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * pADC_InitStruct)834 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct)
835 {
836 /* Set pADC_InitStruct fields to default values */
837 /* Set fields of ADC instance */
838 pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
839 pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
840 pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
841
842 }
843
844 /**
845 * @brief Initialize some features of ADC group regular.
846 * @note These parameters have an impact on ADC scope: ADC group regular.
847 * Refer to corresponding unitary functions into
848 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
849 * (functions with prefix "REG").
850 * @note The setting of these parameters by function @ref LL_ADC_Init()
851 * is conditioned to ADC state:
852 * ADC instance must be disabled.
853 * This condition is applied to all ADC features, for efficiency
854 * and compatibility over all STM32 series. However, the different
855 * features can be set under different ADC state conditions
856 * (setting possible with ADC enabled without conversion on going,
857 * ADC enabled with conversion on going, ...)
858 * Each feature can be updated afterwards with a unitary function
859 * and potentially with ADC in a different state than disabled,
860 * refer to description of each function for setting
861 * conditioned to ADC state.
862 * @note After using this function, other features must be configured
863 * using LL unitary functions.
864 * The minimum configuration remaining to be done is:
865 * - Set ADC group regular or group injected sequencer:
866 * map channel on the selected sequencer rank.
867 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
868 * - Set ADC channel sampling time
869 * Refer to function LL_ADC_SetChannelSamplingTime();
870 * @param ADCx ADC instance
871 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
872 * @retval An ErrorStatus enumeration value:
873 * - SUCCESS: ADC registers are initialized
874 * - ERROR: ADC registers are not initialized
875 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,const LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)876 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
877 {
878 ErrorStatus status = SUCCESS;
879
880 /* Check the parameters */
881 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
882 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource));
883 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
884 if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
885 {
886 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont));
887
888 /* ADC group regular continuous mode and discontinuous mode */
889 /* can not be enabled simultenaeously */
890 assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
891 || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
892 }
893 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode));
894 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer));
895 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun));
896
897 /* Note: Hardware constraint (refer to description of this function): */
898 /* ADC instance must be disabled. */
899 if (LL_ADC_IsEnabled(ADCx) == 0UL)
900 {
901 /* Configuration of ADC hierarchical scope: */
902 /* - ADC group regular */
903 /* - Set ADC group regular trigger source */
904 /* - Set ADC group regular sequencer length */
905 /* - Set ADC group regular sequencer discontinuous mode */
906 /* - Set ADC group regular continuous mode */
907 /* - Set ADC group regular conversion data transfer: no transfer or */
908 /* transfer by DMA, and DMA requests mode */
909 /* - Set ADC group regular overrun behavior */
910 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
911 /* setting of trigger source to SW start. */
912 if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
913 {
914 MODIFY_REG(ADCx->CFGR,
915 ADC_CFGR_EXTSEL
916 | ADC_CFGR_EXTEN
917 | ADC_CFGR_DISCEN
918 | ADC_CFGR_DISCNUM
919 | ADC_CFGR_CONT
920 | ADC_CFGR_DMAEN
921 | ADC_CFGR_DMACFG
922 | ADC_CFGR_OVRMOD
923 ,
924 pADC_RegInitStruct->TriggerSource
925 | pADC_RegInitStruct->SequencerDiscont
926 | pADC_RegInitStruct->ContinuousMode
927 | pADC_RegInitStruct->DMATransfer
928 | pADC_RegInitStruct->Overrun
929 );
930 }
931 else
932 {
933 MODIFY_REG(ADCx->CFGR,
934 ADC_CFGR_EXTSEL
935 | ADC_CFGR_EXTEN
936 | ADC_CFGR_DISCEN
937 | ADC_CFGR_DISCNUM
938 | ADC_CFGR_CONT
939 | ADC_CFGR_DMAEN
940 | ADC_CFGR_DMACFG
941 | ADC_CFGR_OVRMOD
942 ,
943 pADC_RegInitStruct->TriggerSource
944 | LL_ADC_REG_SEQ_DISCONT_DISABLE
945 | pADC_RegInitStruct->ContinuousMode
946 | pADC_RegInitStruct->DMATransfer
947 | pADC_RegInitStruct->Overrun
948 );
949 }
950
951 /* Set ADC group regular sequencer length and scan direction */
952 LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength);
953 }
954 else
955 {
956 /* Initialization error: ADC instance is not disabled. */
957 status = ERROR;
958 }
959 return status;
960 }
961
962 /**
963 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
964 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
965 * whose fields will be set to default values.
966 * @retval None
967 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)968 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
969 {
970 /* Set pADC_RegInitStruct fields to default values */
971 /* Set fields of ADC group regular */
972 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
973 /* setting of trigger source to SW start. */
974 pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
975 pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
976 pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
977 pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
978 pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
979 pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
980 }
981
982 /**
983 * @brief Initialize some features of ADC group injected.
984 * @note These parameters have an impact on ADC scope: ADC group injected.
985 * Refer to corresponding unitary functions into
986 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
987 * (functions with prefix "INJ").
988 * @note The setting of these parameters by function @ref LL_ADC_Init()
989 * is conditioned to ADC state:
990 * ADC instance must be disabled.
991 * This condition is applied to all ADC features, for efficiency
992 * and compatibility over all STM32 series. However, the different
993 * features can be set under different ADC state conditions
994 * (setting possible with ADC enabled without conversion on going,
995 * ADC enabled with conversion on going, ...)
996 * Each feature can be updated afterwards with a unitary function
997 * and potentially with ADC in a different state than disabled,
998 * refer to description of each function for setting
999 * conditioned to ADC state.
1000 * @note After using this function, other features must be configured
1001 * using LL unitary functions.
1002 * The minimum configuration remaining to be done is:
1003 * - Set ADC group injected sequencer:
1004 * map channel on the selected sequencer rank.
1005 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
1006 * - Set ADC channel sampling time
1007 * Refer to function LL_ADC_SetChannelSamplingTime();
1008 * @note Caution if feature ADC group injected contexts queue is enabled
1009 * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
1010 * using successively several times this function will appear as
1011 * having no effect.
1012 * To set several features of ADC group injected, use
1013 * function @ref LL_ADC_INJ_ConfigQueueContext().
1014 * @param ADCx ADC instance
1015 * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1016 * @retval An ErrorStatus enumeration value:
1017 * - SUCCESS: ADC registers are initialized
1018 * - ERROR: ADC registers are not initialized
1019 */
LL_ADC_INJ_Init(ADC_TypeDef * ADCx,const LL_ADC_INJ_InitTypeDef * pADC_InjInitStruct)1020 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
1021 {
1022 ErrorStatus status = SUCCESS;
1023
1024 /* Check the parameters */
1025 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1026 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(pADC_InjInitStruct->TriggerSource));
1027 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(pADC_InjInitStruct->SequencerLength));
1028 if (pADC_InjInitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
1029 {
1030 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(pADC_InjInitStruct->SequencerDiscont));
1031 }
1032 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(pADC_InjInitStruct->TrigAuto));
1033
1034 /* Note: Hardware constraint (refer to description of this function): */
1035 /* ADC instance must be disabled. */
1036 if (LL_ADC_IsEnabled(ADCx) == 0UL)
1037 {
1038 /* Configuration of ADC hierarchical scope: */
1039 /* - ADC group injected */
1040 /* - Set ADC group injected trigger source */
1041 /* - Set ADC group injected sequencer length */
1042 /* - Set ADC group injected sequencer discontinuous mode */
1043 /* - Set ADC group injected conversion trigger: independent or */
1044 /* from ADC group regular */
1045 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
1046 /* setting of trigger source to SW start. */
1047 if (pADC_InjInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1048 {
1049 MODIFY_REG(ADCx->CFGR,
1050 ADC_CFGR_JDISCEN
1051 | ADC_CFGR_JAUTO
1052 ,
1053 pADC_InjInitStruct->SequencerDiscont
1054 | pADC_InjInitStruct->TrigAuto
1055 );
1056 }
1057 else
1058 {
1059 MODIFY_REG(ADCx->CFGR,
1060 ADC_CFGR_JDISCEN
1061 | ADC_CFGR_JAUTO
1062 ,
1063 LL_ADC_REG_SEQ_DISCONT_DISABLE
1064 | pADC_InjInitStruct->TrigAuto
1065 );
1066 }
1067
1068 MODIFY_REG(ADCx->JSQR,
1069 ADC_JSQR_JEXTSEL
1070 | ADC_JSQR_JEXTEN
1071 | ADC_JSQR_JL
1072 ,
1073 pADC_InjInitStruct->TriggerSource
1074 | pADC_InjInitStruct->SequencerLength
1075 );
1076 }
1077 else
1078 {
1079 /* Initialization error: ADC instance is not disabled. */
1080 status = ERROR;
1081 }
1082 return status;
1083 }
1084
1085 /**
1086 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1087 * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1088 * whose fields will be set to default values.
1089 * @retval None
1090 */
LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef * pADC_InjInitStruct)1091 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
1092 {
1093 /* Set pADC_InjInitStruct fields to default values */
1094 /* Set fields of ADC group injected */
1095 pADC_InjInitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1096 pADC_InjInitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1097 pADC_InjInitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1098 pADC_InjInitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1099 }
1100
1101 /**
1102 * @}
1103 */
1104
1105 /**
1106 * @}
1107 */
1108
1109 /**
1110 * @}
1111 */
1112
1113 #endif /* ADC1 || ADC2 */
1114
1115 /**
1116 * @}
1117 */
1118
1119 #endif /* USE_FULL_LL_DRIVER */
1120
