1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_sdram.c
4 * @author MCD Application Team
5 * @brief SDRAM HAL module driver.
6 * This file provides a generic firmware to drive SDRAM memories mounted
7 * as external device.
8 *
9 ******************************************************************************
10 * @attention
11 *
12 * Copyright (c) 2022 STMicroelectronics.
13 * All rights reserved.
14 *
15 * This software is licensed under terms that can be found in the LICENSE file
16 * in the root directory of this software component.
17 * If no LICENSE file comes with this software, it is provided AS-IS.
18 *
19 ******************************************************************************
20 @verbatim
21 ==============================================================================
22 ##### How to use this driver #####
23 ==============================================================================
24 [..]
25 This driver is a generic layered driver which contains a set of APIs used to
26 control SDRAM memories. It uses the FMC layer functions to interface
27 with SDRAM devices.
28 The following sequence should be followed to configure the FMC to interface
29 with SDRAM memories:
30
31 (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
32 SDRAM_HandleTypeDef hsdram
33
34 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
35 values of the structure member.
36
37 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
38 base register instance for NOR or SDRAM device
39
40 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
41 FMC_SDRAM_TimingTypeDef Timing;
42 and fill its fields with the allowed values of the structure member.
43
44 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
45 performs the following sequence:
46
47 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
48 (##) Control register configuration using the FMC SDRAM interface function
49 FMC_SDRAM_Init()
50 (##) Timing register configuration using the FMC SDRAM interface function
51 FMC_SDRAM_Timing_Init()
52 (##) Program the SDRAM external device by applying its initialization sequence
53 according to the device plugged in your hardware. This step is mandatory
54 for accessing the SDRAM device.
55
56 (#) At this stage you can perform read/write accesses from/to the memory connected
57 to the SDRAM Bank. You can perform either polling or DMA transfer using the
58 following APIs:
59 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
60 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
61
62 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
63 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
64 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
65 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
66 structure.
67
68 (#) You can continuously monitor the SDRAM device HAL state by calling the function
69 HAL_SDRAM_GetState()
70
71 *** Callback registration ***
72 =============================================
73 [..]
74 The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1
75 allows the user to configure dynamically the driver callbacks.
76
77 Use Functions HAL_SDRAM_RegisterCallback() to register a user callback,
78 it allows to register following callbacks:
79 (+) MspInitCallback : SDRAM MspInit.
80 (+) MspDeInitCallback : SDRAM MspDeInit.
81 This function takes as parameters the HAL peripheral handle, the Callback ID
82 and a pointer to the user callback function.
83
84 Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
85 weak (overridden) function. It allows to reset following callbacks:
86 (+) MspInitCallback : SDRAM MspInit.
87 (+) MspDeInitCallback : SDRAM MspDeInit.
88 This function) takes as parameters the HAL peripheral handle and the Callback ID.
89
90 By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
91 all callbacks are reset to the corresponding legacy weak (overridden) functions.
92 Exception done for MspInit and MspDeInit callbacks that are respectively
93 reset to the legacy weak (overridden) functions in the HAL_SDRAM_Init
94 and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
95 If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit
96 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
97
98 Callbacks can be registered/unregistered in READY state only.
99 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
100 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
101 during the Init/DeInit.
102 In that case first register the MspInit/MspDeInit user callbacks
103 using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit
104 or HAL_SDRAM_Init function.
105
106 When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
107 not defined, the callback registering feature is not available
108 and weak (overridden) callbacks are used.
109
110 @endverbatim
111 ******************************************************************************
112 */
113
114 /* Includes ------------------------------------------------------------------*/
115 #include "stm32h5xx_hal.h"
116
117
118 /** @addtogroup STM32H5xx_HAL_Driver
119 * @{
120 */
121
122 #ifdef HAL_SDRAM_MODULE_ENABLED
123
124 /** @defgroup SDRAM SDRAM
125 * @brief SDRAM driver modules
126 * @{
127 */
128
129 /* Private typedef -----------------------------------------------------------*/
130 /* Private define ------------------------------------------------------------*/
131 /* Private macro -------------------------------------------------------------*/
132 /* Private variables ---------------------------------------------------------*/
133 /* Private function prototypes -----------------------------------------------*/
134 /** @addtogroup SDRAM_Private_Functions SDRAM Private Functions
135 * @{
136 */
137 static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma);
138 static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
139 static void SDRAM_DMAError(DMA_HandleTypeDef *hdma);
140 /**
141 * @}
142 */
143
144 /* Exported functions --------------------------------------------------------*/
145 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
146 * @{
147 */
148
149 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
150 * @brief Initialization and Configuration functions
151 *
152 @verbatim
153 ==============================================================================
154 ##### SDRAM Initialization and de_initialization functions #####
155 ==============================================================================
156 [..]
157 This section provides functions allowing to initialize/de-initialize
158 the SDRAM memory
159
160 @endverbatim
161 * @{
162 */
163
164 /**
165 * @brief Performs the SDRAM device initialization sequence.
166 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
167 * the configuration information for SDRAM module.
168 * @param Timing Pointer to SDRAM control timing structure
169 * @retval HAL status
170 */
HAL_SDRAM_Init(SDRAM_HandleTypeDef * hsdram,FMC_SDRAM_TimingTypeDef * Timing)171 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
172 {
173 /* Check the SDRAM handle parameter */
174 if (hsdram == NULL)
175 {
176 return HAL_ERROR;
177 }
178
179 if (hsdram->State == HAL_SDRAM_STATE_RESET)
180 {
181 /* Allocate lock resource and initialize it */
182 hsdram->Lock = HAL_UNLOCKED;
183 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
184 if (hsdram->MspInitCallback == NULL)
185 {
186 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
187 }
188 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
189 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
190 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
191
192 /* Init the low level hardware */
193 hsdram->MspInitCallback(hsdram);
194 #else
195 /* Initialize the low level hardware (MSP) */
196 HAL_SDRAM_MspInit(hsdram);
197 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
198 }
199
200 /* Initialize the SDRAM controller state */
201 hsdram->State = HAL_SDRAM_STATE_BUSY;
202
203 /* Initialize SDRAM control Interface */
204 (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
205
206 /* Initialize SDRAM timing Interface */
207 (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
208
209 /* Enable FMC Peripheral */
210 __FMC_ENABLE();
211 /* Update the SDRAM controller state */
212 hsdram->State = HAL_SDRAM_STATE_READY;
213
214 return HAL_OK;
215 }
216
217 /**
218 * @brief Perform the SDRAM device initialization sequence.
219 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
220 * the configuration information for SDRAM module.
221 * @retval HAL status
222 */
HAL_SDRAM_DeInit(SDRAM_HandleTypeDef * hsdram)223 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
224 {
225 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
226 if (hsdram->MspDeInitCallback == NULL)
227 {
228 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
229 }
230
231 /* DeInit the low level hardware */
232 hsdram->MspDeInitCallback(hsdram);
233 #else
234 /* Initialize the low level hardware (MSP) */
235 HAL_SDRAM_MspDeInit(hsdram);
236 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
237
238 /* Configure the SDRAM registers with their reset values */
239 (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
240
241 /* Reset the SDRAM controller state */
242 hsdram->State = HAL_SDRAM_STATE_RESET;
243
244 /* Release Lock */
245 __HAL_UNLOCK(hsdram);
246
247 return HAL_OK;
248 }
249
250 /**
251 * @brief SDRAM MSP Init.
252 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
253 * the configuration information for SDRAM module.
254 * @retval None
255 */
HAL_SDRAM_MspInit(SDRAM_HandleTypeDef * hsdram)256 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
257 {
258 /* Prevent unused argument(s) compilation warning */
259 UNUSED(hsdram);
260
261 /* NOTE: This function Should not be modified, when the callback is needed,
262 the HAL_SDRAM_MspInit could be implemented in the user file
263 */
264 }
265
266 /**
267 * @brief SDRAM MSP DeInit.
268 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
269 * the configuration information for SDRAM module.
270 * @retval None
271 */
HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef * hsdram)272 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
273 {
274 /* Prevent unused argument(s) compilation warning */
275 UNUSED(hsdram);
276
277 /* NOTE: This function Should not be modified, when the callback is needed,
278 the HAL_SDRAM_MspDeInit could be implemented in the user file
279 */
280 }
281
282 /**
283 * @brief This function handles SDRAM refresh error interrupt request.
284 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
285 * the configuration information for SDRAM module.
286 * @retval HAL status
287 */
HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef * hsdram)288 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
289 {
290 /* Check SDRAM interrupt Rising edge flag */
291 if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
292 {
293 /* SDRAM refresh error interrupt callback */
294 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
295 hsdram->RefreshErrorCallback(hsdram);
296 #else
297 HAL_SDRAM_RefreshErrorCallback(hsdram);
298 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
299
300 /* Clear SDRAM refresh error interrupt pending bit */
301 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
302 }
303 }
304
305 /**
306 * @brief SDRAM Refresh error callback.
307 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
308 * the configuration information for SDRAM module.
309 * @retval None
310 */
HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef * hsdram)311 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
312 {
313 /* Prevent unused argument(s) compilation warning */
314 UNUSED(hsdram);
315
316 /* NOTE: This function Should not be modified, when the callback is needed,
317 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
318 */
319 }
320
321 /**
322 * @brief DMA transfer complete callback.
323 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
324 * the configuration information for the specified DMA module.
325 * @retval None
326 */
HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef * hdma)327 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
328 {
329 /* Prevent unused argument(s) compilation warning */
330 UNUSED(hdma);
331
332 /* NOTE: This function Should not be modified, when the callback is needed,
333 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
334 */
335 }
336
337 /**
338 * @brief DMA transfer complete error callback.
339 * @param hdma DMA handle
340 * @retval None
341 */
HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef * hdma)342 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
343 {
344 /* Prevent unused argument(s) compilation warning */
345 UNUSED(hdma);
346
347 /* NOTE: This function Should not be modified, when the callback is needed,
348 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
349 */
350 }
351
352 /**
353 * @}
354 */
355
356 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
357 * @brief Input Output and memory control functions
358 *
359 @verbatim
360 ==============================================================================
361 ##### SDRAM Input and Output functions #####
362 ==============================================================================
363 [..]
364 This section provides functions allowing to use and control the SDRAM memory
365
366 @endverbatim
367 * @{
368 */
369
370 /**
371 * @brief Reads 8-bit data buffer from the SDRAM memory.
372 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
373 * the configuration information for SDRAM module.
374 * @param pAddress Pointer to read start address
375 * @param pDstBuffer Pointer to destination buffer
376 * @param BufferSize Size of the buffer to read from memory
377 * @retval HAL status
378 */
HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint8_t * pDstBuffer,uint32_t BufferSize)379 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
380 uint32_t BufferSize)
381 {
382 uint32_t size;
383 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
384 uint8_t *pdestbuff = pDstBuffer;
385 HAL_SDRAM_StateTypeDef state = hsdram->State;
386
387 /* Check the SDRAM controller state */
388 if (state == HAL_SDRAM_STATE_BUSY)
389 {
390 return HAL_BUSY;
391 }
392 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
393 {
394 /* Process Locked */
395 __HAL_LOCK(hsdram);
396
397 /* Update the SDRAM controller state */
398 hsdram->State = HAL_SDRAM_STATE_BUSY;
399
400 /* Read data from source */
401 for (size = BufferSize; size != 0U; size--)
402 {
403 *pdestbuff = *(__IO uint8_t *)pSdramAddress;
404 pdestbuff++;
405 pSdramAddress++;
406 }
407
408 /* Update the SDRAM controller state */
409 hsdram->State = state;
410
411 /* Process Unlocked */
412 __HAL_UNLOCK(hsdram);
413 }
414 else
415 {
416 return HAL_ERROR;
417 }
418
419 return HAL_OK;
420 }
421
422 /**
423 * @brief Writes 8-bit data buffer to SDRAM memory.
424 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
425 * the configuration information for SDRAM module.
426 * @param pAddress Pointer to write start address
427 * @param pSrcBuffer Pointer to source buffer to write
428 * @param BufferSize Size of the buffer to write to memory
429 * @retval HAL status
430 */
HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint8_t * pSrcBuffer,uint32_t BufferSize)431 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
432 uint32_t BufferSize)
433 {
434 uint32_t size;
435 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
436 uint8_t *psrcbuff = pSrcBuffer;
437
438 /* Check the SDRAM controller state */
439 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
440 {
441 return HAL_BUSY;
442 }
443 else if (hsdram->State == HAL_SDRAM_STATE_READY)
444 {
445 /* Process Locked */
446 __HAL_LOCK(hsdram);
447
448 /* Update the SDRAM controller state */
449 hsdram->State = HAL_SDRAM_STATE_BUSY;
450
451 /* Write data to memory */
452 for (size = BufferSize; size != 0U; size--)
453 {
454 *(__IO uint8_t *)pSdramAddress = *psrcbuff;
455 psrcbuff++;
456 pSdramAddress++;
457 }
458
459 /* Update the SDRAM controller state */
460 hsdram->State = HAL_SDRAM_STATE_READY;
461
462 /* Process Unlocked */
463 __HAL_UNLOCK(hsdram);
464 }
465 else
466 {
467 return HAL_ERROR;
468 }
469
470 return HAL_OK;
471 }
472
473 /**
474 * @brief Reads 16-bit data buffer from the SDRAM memory.
475 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
476 * the configuration information for SDRAM module.
477 * @param pAddress Pointer to read start address
478 * @param pDstBuffer Pointer to destination buffer
479 * @param BufferSize Size of the buffer to read from memory
480 * @retval HAL status
481 */
HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint16_t * pDstBuffer,uint32_t BufferSize)482 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
483 uint32_t BufferSize)
484 {
485 uint32_t size;
486 __IO uint32_t *pSdramAddress = pAddress;
487 uint16_t *pdestbuff = pDstBuffer;
488 HAL_SDRAM_StateTypeDef state = hsdram->State;
489
490 /* Check the SDRAM controller state */
491 if (state == HAL_SDRAM_STATE_BUSY)
492 {
493 return HAL_BUSY;
494 }
495 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
496 {
497 /* Process Locked */
498 __HAL_LOCK(hsdram);
499
500 /* Update the SDRAM controller state */
501 hsdram->State = HAL_SDRAM_STATE_BUSY;
502
503 /* Read data from memory */
504 for (size = BufferSize; size >= 2U ; size -= 2U)
505 {
506 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
507 pdestbuff++;
508 *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U);
509 pdestbuff++;
510 pSdramAddress++;
511 }
512
513 /* Read last 16-bits if size is not 32-bits multiple */
514 if ((BufferSize % 2U) != 0U)
515 {
516 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
517 }
518
519 /* Update the SDRAM controller state */
520 hsdram->State = state;
521
522 /* Process Unlocked */
523 __HAL_UNLOCK(hsdram);
524 }
525 else
526 {
527 return HAL_ERROR;
528 }
529
530 return HAL_OK;
531 }
532
533 /**
534 * @brief Writes 16-bit data buffer to SDRAM memory.
535 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
536 * the configuration information for SDRAM module.
537 * @param pAddress Pointer to write start address
538 * @param pSrcBuffer Pointer to source buffer to write
539 * @param BufferSize Size of the buffer to write to memory
540 * @retval HAL status
541 */
HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint16_t * pSrcBuffer,uint32_t BufferSize)542 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
543 uint32_t BufferSize)
544 {
545 uint32_t size;
546 __IO uint32_t *psdramaddress = pAddress;
547 uint16_t *psrcbuff = pSrcBuffer;
548
549 /* Check the SDRAM controller state */
550 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
551 {
552 return HAL_BUSY;
553 }
554 else if (hsdram->State == HAL_SDRAM_STATE_READY)
555 {
556 /* Process Locked */
557 __HAL_LOCK(hsdram);
558
559 /* Update the SDRAM controller state */
560 hsdram->State = HAL_SDRAM_STATE_BUSY;
561
562 /* Write data to memory */
563 for (size = BufferSize; size >= 2U ; size -= 2U)
564 {
565 *psdramaddress = (uint32_t)(*psrcbuff);
566 psrcbuff++;
567 *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U);
568 psrcbuff++;
569 psdramaddress++;
570 }
571
572 /* Write last 16-bits if size is not 32-bits multiple */
573 if ((BufferSize % 2U) != 0U)
574 {
575 *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U);
576 }
577
578 /* Update the SDRAM controller state */
579 hsdram->State = HAL_SDRAM_STATE_READY;
580
581 /* Process Unlocked */
582 __HAL_UNLOCK(hsdram);
583 }
584 else
585 {
586 return HAL_ERROR;
587 }
588
589 return HAL_OK;
590 }
591
592 /**
593 * @brief Reads 32-bit data buffer from the SDRAM memory.
594 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
595 * the configuration information for SDRAM module.
596 * @param pAddress Pointer to read start address
597 * @param pDstBuffer Pointer to destination buffer
598 * @param BufferSize Size of the buffer to read from memory
599 * @retval HAL status
600 */
HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)601 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
602 uint32_t BufferSize)
603 {
604 uint32_t size;
605 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
606 uint32_t *pdestbuff = pDstBuffer;
607 HAL_SDRAM_StateTypeDef state = hsdram->State;
608
609 /* Check the SDRAM controller state */
610 if (state == HAL_SDRAM_STATE_BUSY)
611 {
612 return HAL_BUSY;
613 }
614 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
615 {
616 /* Process Locked */
617 __HAL_LOCK(hsdram);
618
619 /* Update the SDRAM controller state */
620 hsdram->State = HAL_SDRAM_STATE_BUSY;
621
622 /* Read data from source */
623 for (size = BufferSize; size != 0U; size--)
624 {
625 *pdestbuff = *(__IO uint32_t *)pSdramAddress;
626 pdestbuff++;
627 pSdramAddress++;
628 }
629
630 /* Update the SDRAM controller state */
631 hsdram->State = state;
632
633 /* Process Unlocked */
634 __HAL_UNLOCK(hsdram);
635 }
636 else
637 {
638 return HAL_ERROR;
639 }
640
641 return HAL_OK;
642 }
643
644 /**
645 * @brief Writes 32-bit data buffer to SDRAM memory.
646 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
647 * the configuration information for SDRAM module.
648 * @param pAddress Pointer to write start address
649 * @param pSrcBuffer Pointer to source buffer to write
650 * @param BufferSize Size of the buffer to write to memory
651 * @retval HAL status
652 */
HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)653 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
654 uint32_t BufferSize)
655 {
656 uint32_t size;
657 __IO uint32_t *pSdramAddress = pAddress;
658 uint32_t *psrcbuff = pSrcBuffer;
659
660 /* Check the SDRAM controller state */
661 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
662 {
663 return HAL_BUSY;
664 }
665 else if (hsdram->State == HAL_SDRAM_STATE_READY)
666 {
667 /* Process Locked */
668 __HAL_LOCK(hsdram);
669
670 /* Update the SDRAM controller state */
671 hsdram->State = HAL_SDRAM_STATE_BUSY;
672
673 /* Write data to memory */
674 for (size = BufferSize; size != 0U; size--)
675 {
676 *pSdramAddress = *psrcbuff;
677 psrcbuff++;
678 pSdramAddress++;
679 }
680
681 /* Update the SDRAM controller state */
682 hsdram->State = HAL_SDRAM_STATE_READY;
683
684 /* Process Unlocked */
685 __HAL_UNLOCK(hsdram);
686 }
687 else
688 {
689 return HAL_ERROR;
690 }
691
692 return HAL_OK;
693 }
694
695 /**
696 * @brief Reads a Words data from the SDRAM memory using DMA transfer.
697 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
698 * the configuration information for SDRAM module.
699 * @param pAddress Pointer to read start address
700 * @param pDstBuffer Pointer to destination buffer
701 * @param BufferSize Size of the buffer to read from memory
702 * @retval HAL status
703 */
HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)704 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
705 uint32_t BufferSize)
706 {
707 HAL_StatusTypeDef status;
708 HAL_SDRAM_StateTypeDef state = hsdram->State;
709 uint32_t size;
710 uint32_t data_width;
711
712 /* Check the SDRAM controller state */
713 if (state == HAL_SDRAM_STATE_BUSY)
714 {
715 status = HAL_BUSY;
716 }
717 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
718 {
719 /* Process Locked */
720 __HAL_LOCK(hsdram);
721
722 /* Update the SDRAM controller state */
723 hsdram->State = HAL_SDRAM_STATE_BUSY;
724
725 /* Configure DMA user callbacks */
726 if (state == HAL_SDRAM_STATE_READY)
727 {
728 hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
729 }
730 else
731 {
732 hsdram->hdma->XferCpltCallback = SDRAM_DMACpltProt;
733 }
734 hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
735
736 if ((hsdram->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
737 {
738 if ((hsdram->hdma->LinkedListQueue != 0U) && (hsdram->hdma->LinkedListQueue->Head != 0U))
739 {
740 /* Check destination data width and set the size to be transferred */
741 data_width = hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
742
743 if (data_width == DMA_DEST_DATAWIDTH_WORD)
744 {
745 size = (BufferSize * 4U);
746 }
747 else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
748 {
749 size = (BufferSize * 2U);
750 }
751 else
752 {
753 size = (BufferSize);
754 }
755 /* Set Source , destination , buffer size */
756 /* Set DMA data size */
757 hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = size;
758 /* Set DMA source address */
759 hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pAddress;
760 /* Set DMA destination address */
761 hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pDstBuffer;
762
763 /* Enable the DMA Stream */
764 status = HAL_DMAEx_List_Start_IT(hsdram->hdma);
765 }
766 else
767 {
768 /* Process Unlocked */
769 __HAL_UNLOCK(hsdram);
770
771 status = HAL_ERROR;
772 }
773 }
774 else
775 {
776 /* Check destination data width and set the size to be transferred */
777 data_width = hsdram->hdma->Init.DestDataWidth;
778
779 if (data_width == DMA_DEST_DATAWIDTH_WORD)
780 {
781 size = (BufferSize * 4U);
782 }
783 else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
784 {
785 size = (BufferSize * 2U);
786 }
787 else
788 {
789 size = (BufferSize);
790 }
791
792 /* Enable the DMA Stream */
793 status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, size);
794 }
795
796 /* Process Unlocked */
797 __HAL_UNLOCK(hsdram);
798 }
799 else
800 {
801 status = HAL_ERROR;
802 }
803
804 return status;
805 }
806
807 /**
808 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
809 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
810 * the configuration information for SDRAM module.
811 * @param pAddress Pointer to write start address
812 * @param pSrcBuffer Pointer to source buffer to write
813 * @param BufferSize Size of the buffer to write to memory
814 * @retval HAL status
815 */
HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)816 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
817 uint32_t BufferSize)
818 {
819 HAL_StatusTypeDef status;
820 uint32_t size;
821 uint32_t data_width;
822
823 /* Check the SDRAM controller state */
824 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
825 {
826 status = HAL_BUSY;
827 }
828 else if (hsdram->State == HAL_SDRAM_STATE_READY)
829 {
830 /* Process Locked */
831 __HAL_LOCK(hsdram);
832
833 /* Update the SDRAM controller state */
834 hsdram->State = HAL_SDRAM_STATE_BUSY;
835
836 /* Configure DMA user callbacks */
837 hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
838 hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
839
840 if ((hsdram->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
841 {
842 if ((hsdram->hdma->LinkedListQueue != 0U) && (hsdram->hdma->LinkedListQueue->Head != 0U))
843 {
844 /* Check destination data width and set the size to be transferred */
845 data_width = hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
846
847 if (data_width == DMA_DEST_DATAWIDTH_WORD)
848 {
849 size = (BufferSize * 4U);
850 }
851 else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
852 {
853 size = (BufferSize * 2U);
854 }
855 else
856 {
857 size = (BufferSize);
858 }
859 /* Set Source , destination , buffer size */
860 /* Set DMA data size */
861 hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = size;
862 /* Set DMA source address */
863 hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pSrcBuffer;
864 /* Set DMA destination address */
865 hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pAddress;
866
867 /* Enable the DMA Stream */
868 status = HAL_DMAEx_List_Start_IT(hsdram->hdma);
869 }
870 else
871 {
872 /* Process Unlocked */
873 __HAL_UNLOCK(hsdram);
874
875 status = HAL_ERROR;
876 }
877 }
878 else
879 {
880 /* Check destination data width and set the size to be transferred */
881 data_width = hsdram->hdma->Init.DestDataWidth;
882
883 if (data_width == DMA_DEST_DATAWIDTH_WORD)
884 {
885 size = (BufferSize * 4U);
886 }
887 else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
888 {
889 size = (BufferSize * 2U);
890 }
891 else
892 {
893 size = (BufferSize);
894 }
895
896 /* Enable the DMA Stream */
897 status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, size);
898 }
899
900 /* Process Unlocked */
901 __HAL_UNLOCK(hsdram);
902 }
903 else
904 {
905 status = HAL_ERROR;
906 }
907
908 return status;
909 }
910
911 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
912 /**
913 * @brief Register a User SDRAM Callback
914 * To be used to override the weak predefined callback
915 * @param hsdram : SDRAM handle
916 * @param CallbackId : ID of the callback to be registered
917 * This parameter can be one of the following values:
918 * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
919 * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
920 * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
921 * @param pCallback : pointer to the Callback function
922 * @retval status
923 */
HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId,pSDRAM_CallbackTypeDef pCallback)924 HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
925 pSDRAM_CallbackTypeDef pCallback)
926 {
927 HAL_StatusTypeDef status = HAL_OK;
928 HAL_SDRAM_StateTypeDef state;
929
930 if (pCallback == NULL)
931 {
932 return HAL_ERROR;
933 }
934
935 state = hsdram->State;
936 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
937 {
938 switch (CallbackId)
939 {
940 case HAL_SDRAM_MSP_INIT_CB_ID :
941 hsdram->MspInitCallback = pCallback;
942 break;
943 case HAL_SDRAM_MSP_DEINIT_CB_ID :
944 hsdram->MspDeInitCallback = pCallback;
945 break;
946 case HAL_SDRAM_REFRESH_ERR_CB_ID :
947 hsdram->RefreshErrorCallback = pCallback;
948 break;
949 default :
950 /* update return status */
951 status = HAL_ERROR;
952 break;
953 }
954 }
955 else if (hsdram->State == HAL_SDRAM_STATE_RESET)
956 {
957 switch (CallbackId)
958 {
959 case HAL_SDRAM_MSP_INIT_CB_ID :
960 hsdram->MspInitCallback = pCallback;
961 break;
962 case HAL_SDRAM_MSP_DEINIT_CB_ID :
963 hsdram->MspDeInitCallback = pCallback;
964 break;
965 default :
966 /* update return status */
967 status = HAL_ERROR;
968 break;
969 }
970 }
971 else
972 {
973 /* update return status */
974 status = HAL_ERROR;
975 }
976
977 return status;
978 }
979
980 /**
981 * @brief Unregister a User SDRAM Callback
982 * SDRAM Callback is redirected to the weak predefined callback
983 * @param hsdram : SDRAM handle
984 * @param CallbackId : ID of the callback to be unregistered
985 * This parameter can be one of the following values:
986 * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
987 * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
988 * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
989 * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
990 * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
991 * @retval status
992 */
HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId)993 HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
994 {
995 HAL_StatusTypeDef status = HAL_OK;
996 HAL_SDRAM_StateTypeDef state;
997
998 state = hsdram->State;
999 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
1000 {
1001 switch (CallbackId)
1002 {
1003 case HAL_SDRAM_MSP_INIT_CB_ID :
1004 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
1005 break;
1006 case HAL_SDRAM_MSP_DEINIT_CB_ID :
1007 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
1008 break;
1009 case HAL_SDRAM_REFRESH_ERR_CB_ID :
1010 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
1011 break;
1012 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
1013 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
1014 break;
1015 case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
1016 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
1017 break;
1018 default :
1019 /* update return status */
1020 status = HAL_ERROR;
1021 break;
1022 }
1023 }
1024 else if (hsdram->State == HAL_SDRAM_STATE_RESET)
1025 {
1026 switch (CallbackId)
1027 {
1028 case HAL_SDRAM_MSP_INIT_CB_ID :
1029 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
1030 break;
1031 case HAL_SDRAM_MSP_DEINIT_CB_ID :
1032 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
1033 break;
1034 default :
1035 /* update return status */
1036 status = HAL_ERROR;
1037 break;
1038 }
1039 }
1040 else
1041 {
1042 /* update return status */
1043 status = HAL_ERROR;
1044 }
1045
1046 return status;
1047 }
1048
1049 /**
1050 * @brief Register a User SDRAM Callback for DMA transfers
1051 * To be used to override the weak predefined callback
1052 * @param hsdram : SDRAM handle
1053 * @param CallbackId : ID of the callback to be registered
1054 * This parameter can be one of the following values:
1055 * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
1056 * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
1057 * @param pCallback : pointer to the Callback function
1058 * @retval status
1059 */
HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId,pSDRAM_DmaCallbackTypeDef pCallback)1060 HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
1061 pSDRAM_DmaCallbackTypeDef pCallback)
1062 {
1063 HAL_StatusTypeDef status = HAL_OK;
1064 HAL_SDRAM_StateTypeDef state;
1065
1066 if (pCallback == NULL)
1067 {
1068 return HAL_ERROR;
1069 }
1070
1071 /* Process locked */
1072 __HAL_LOCK(hsdram);
1073
1074 state = hsdram->State;
1075 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
1076 {
1077 switch (CallbackId)
1078 {
1079 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
1080 hsdram->DmaXferCpltCallback = pCallback;
1081 break;
1082 case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
1083 hsdram->DmaXferErrorCallback = pCallback;
1084 break;
1085 default :
1086 /* update return status */
1087 status = HAL_ERROR;
1088 break;
1089 }
1090 }
1091 else
1092 {
1093 /* update return status */
1094 status = HAL_ERROR;
1095 }
1096
1097 /* Release Lock */
1098 __HAL_UNLOCK(hsdram);
1099 return status;
1100 }
1101 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1102
1103 /**
1104 * @}
1105 */
1106
1107 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
1108 * @brief management functions
1109 *
1110 @verbatim
1111 ==============================================================================
1112 ##### SDRAM Control functions #####
1113 ==============================================================================
1114 [..]
1115 This subsection provides a set of functions allowing to control dynamically
1116 the SDRAM interface.
1117
1118 @endverbatim
1119 * @{
1120 */
1121
1122 /**
1123 * @brief Enables dynamically SDRAM write protection.
1124 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1125 * the configuration information for SDRAM module.
1126 * @retval HAL status
1127 */
HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef * hsdram)1128 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
1129 {
1130 /* Check the SDRAM controller state */
1131 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1132 {
1133 return HAL_BUSY;
1134 }
1135 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1136 {
1137 /* Update the SDRAM state */
1138 hsdram->State = HAL_SDRAM_STATE_BUSY;
1139
1140 /* Enable write protection */
1141 (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
1142
1143 /* Update the SDRAM state */
1144 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
1145 }
1146 else
1147 {
1148 return HAL_ERROR;
1149 }
1150
1151 return HAL_OK;
1152 }
1153
1154 /**
1155 * @brief Disables dynamically SDRAM write protection.
1156 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1157 * the configuration information for SDRAM module.
1158 * @retval HAL status
1159 */
HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef * hsdram)1160 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
1161 {
1162 HAL_SDRAM_StateTypeDef state = hsdram->State;
1163
1164 /* Check the SDRAM controller state */
1165 if (state == HAL_SDRAM_STATE_BUSY)
1166 {
1167 return HAL_BUSY;
1168 }
1169 else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED)
1170 {
1171 /* Update the SDRAM state */
1172 hsdram->State = HAL_SDRAM_STATE_BUSY;
1173
1174 /* Disable write protection */
1175 (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
1176
1177 /* Update the SDRAM state */
1178 hsdram->State = HAL_SDRAM_STATE_READY;
1179 }
1180 else
1181 {
1182 return HAL_ERROR;
1183 }
1184
1185 return HAL_OK;
1186 }
1187
1188 /**
1189 * @brief Sends Command to the SDRAM bank.
1190 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1191 * the configuration information for SDRAM module.
1192 * @param Command SDRAM command structure
1193 * @param Timeout Timeout duration
1194 * @retval HAL status
1195 */
HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef * hsdram,FMC_SDRAM_CommandTypeDef * Command,uint32_t Timeout)1196 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command,
1197 uint32_t Timeout)
1198 {
1199 HAL_SDRAM_StateTypeDef state = hsdram->State;
1200
1201 /* Check the SDRAM controller state */
1202 if (state == HAL_SDRAM_STATE_BUSY)
1203 {
1204 return HAL_BUSY;
1205 }
1206 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED))
1207 {
1208 /* Update the SDRAM state */
1209 hsdram->State = HAL_SDRAM_STATE_BUSY;
1210
1211 /* Send SDRAM command */
1212 (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
1213
1214 /* Update the SDRAM controller state state */
1215 if (Command->CommandMode == FMC_SDRAM_CMD_PALL)
1216 {
1217 hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
1218 }
1219 else
1220 {
1221 hsdram->State = HAL_SDRAM_STATE_READY;
1222 }
1223 }
1224 else
1225 {
1226 return HAL_ERROR;
1227 }
1228
1229 return HAL_OK;
1230 }
1231
1232 /**
1233 * @brief Programs the SDRAM Memory Refresh rate.
1234 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1235 * the configuration information for SDRAM module.
1236 * @param RefreshRate The SDRAM refresh rate value
1237 * @retval HAL status
1238 */
HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef * hsdram,uint32_t RefreshRate)1239 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
1240 {
1241 /* Check the SDRAM controller state */
1242 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1243 {
1244 return HAL_BUSY;
1245 }
1246 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1247 {
1248 /* Update the SDRAM state */
1249 hsdram->State = HAL_SDRAM_STATE_BUSY;
1250
1251 /* Program the refresh rate */
1252 (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate);
1253
1254 /* Update the SDRAM state */
1255 hsdram->State = HAL_SDRAM_STATE_READY;
1256 }
1257 else
1258 {
1259 return HAL_ERROR;
1260 }
1261
1262 return HAL_OK;
1263 }
1264
1265 /**
1266 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
1267 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1268 * the configuration information for SDRAM module.
1269 * @param AutoRefreshNumber The SDRAM auto Refresh number
1270 * @retval HAL status
1271 */
HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef * hsdram,uint32_t AutoRefreshNumber)1272 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
1273 {
1274 /* Check the SDRAM controller state */
1275 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1276 {
1277 return HAL_BUSY;
1278 }
1279 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1280 {
1281 /* Update the SDRAM state */
1282 hsdram->State = HAL_SDRAM_STATE_BUSY;
1283
1284 /* Set the Auto-Refresh number */
1285 (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber);
1286
1287 /* Update the SDRAM state */
1288 hsdram->State = HAL_SDRAM_STATE_READY;
1289 }
1290 else
1291 {
1292 return HAL_ERROR;
1293 }
1294
1295 return HAL_OK;
1296 }
1297
1298 /**
1299 * @brief Returns the SDRAM memory current mode.
1300 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1301 * the configuration information for SDRAM module.
1302 * @retval The SDRAM memory mode.
1303 */
HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef * hsdram)1304 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
1305 {
1306 /* Return the SDRAM memory current mode */
1307 return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
1308 }
1309
1310 /**
1311 * @}
1312 */
1313
1314 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
1315 * @brief Peripheral State functions
1316 *
1317 @verbatim
1318 ==============================================================================
1319 ##### SDRAM State functions #####
1320 ==============================================================================
1321 [..]
1322 This subsection permits to get in run-time the status of the SDRAM controller
1323 and the data flow.
1324
1325 @endverbatim
1326 * @{
1327 */
1328
1329 /**
1330 * @brief Returns the SDRAM state.
1331 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1332 * the configuration information for SDRAM module.
1333 * @retval HAL state
1334 */
HAL_SDRAM_GetState(SDRAM_HandleTypeDef * hsdram)1335 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
1336 {
1337 return hsdram->State;
1338 }
1339
1340 /**
1341 * @}
1342 */
1343
1344 /**
1345 * @}
1346 */
1347
1348 /** @addtogroup SDRAM_Private_Functions SDRAM Private Functions
1349 * @{
1350 */
1351 /**
1352 * @brief DMA SDRAM process complete callback.
1353 * @param hdma : DMA handle
1354 * @retval None
1355 */
SDRAM_DMACplt(DMA_HandleTypeDef * hdma)1356 static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma)
1357 {
1358 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
1359
1360 /* Disable the DMA channel */
1361 __HAL_DMA_DISABLE(hdma);
1362
1363 /* Update the SDRAM controller state */
1364 hsdram->State = HAL_SDRAM_STATE_READY;
1365
1366 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1367 hsdram->DmaXferCpltCallback(hdma);
1368 #else
1369 HAL_SDRAM_DMA_XferCpltCallback(hdma);
1370 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1371 }
1372
1373 /**
1374 * @brief DMA SRAM process complete callback.
1375 * @param hdma : DMA handle
1376 * @retval None
1377 */
SDRAM_DMACpltProt(DMA_HandleTypeDef * hdma)1378 static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
1379 {
1380 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
1381
1382 /* Disable the DMA channel */
1383 __HAL_DMA_DISABLE(hdma);
1384
1385 /* Update the SDRAM controller state */
1386 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
1387
1388 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1389 hsdram->DmaXferCpltCallback(hdma);
1390 #else
1391 HAL_SDRAM_DMA_XferCpltCallback(hdma);
1392 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1393 }
1394
1395 /**
1396 * @brief DMA SDRAM error callback.
1397 * @param hdma : DMA handle
1398 * @retval None
1399 */
SDRAM_DMAError(DMA_HandleTypeDef * hdma)1400 static void SDRAM_DMAError(DMA_HandleTypeDef *hdma)
1401 {
1402 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
1403
1404 /* Disable the DMA channel */
1405 __HAL_DMA_DISABLE(hdma);
1406
1407 /* Update the SDRAM controller state */
1408 hsdram->State = HAL_SDRAM_STATE_ERROR;
1409
1410 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1411 hsdram->DmaXferErrorCallback(hdma);
1412 #else
1413 HAL_SDRAM_DMA_XferErrorCallback(hdma);
1414 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1415 }
1416
1417 /**
1418 * @}
1419 */
1420 /**
1421 * @}
1422 */
1423
1424 #endif /* HAL_SDRAM_MODULE_ENABLED */
1425
1426 /**
1427 * @}
1428 */
1429
