1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_rcc_ex.c
4 * @author MCD Application Team
5 * @brief Extended RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities RCC extended peripheral:
8 * + Extended Peripheral Control functions
9 * + Extended Clock management functions
10 * + Extended Clock Recovery System Control functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2022 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 */
24
25 /* Includes ------------------------------------------------------------------*/
26 #include "stm32h5xx_hal.h"
27
28 /** @addtogroup STM32H5xx_HAL_Driver
29 * @{
30 */
31
32 /** @defgroup RCCEx RCCEx
33 * @brief RCC Extended HAL module driver
34 * @{
35 */
36
37 #ifdef HAL_RCC_MODULE_ENABLED
38
39 /* Private typedef -----------------------------------------------------------*/
40 /* Private defines -----------------------------------------------------------*/
41 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
42 * @{
43 */
44 #define PLL1_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
45 #define PLL2_TIMEOUT_VALUE ((uint32_t)/*8U*/2U) /* 2 ms (minimum Tick + 1) */
46 #if defined(RCC_CR_PLL3ON)
47 #define PLL3_TIMEOUT_VALUE ((uint32_t)/*8U*/2U) /* 2 ms (minimum Tick + 1) */
48 #endif /* RCC_CR_PLL3ON */
49
50 #define __LSCO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
51
52 #define LSCO_GPIO_PORT GPIOB
53
54 #define LSCO_PIN GPIO_PIN_2
55
56 /**
57 * @}
58 */
59
60 /* Private macros ------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62 /* Private function prototypes -----------------------------------------------*/
63 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
64 * @{
65 */
66 static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource);
67 static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *Pll2);
68 #if defined(RCC_CR_PLL3ON)
69 static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *Pll3);
70 #endif /* RCC_CR_PLL3ON */
71 /**
72 * @}
73 */
74
75 /* Exported functions --------------------------------------------------------*/
76
77 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
78 * @{
79 */
80
81 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
82 * @brief Extended Peripheral Control functions
83 *
84 @verbatim
85 ===============================================================================
86 ##### Extended Peripheral Control functions #####
87 ===============================================================================
88 [..]
89 This subsection provides a set of functions allowing to control the RCC Clocks
90 frequencies.
91 [..]
92 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
93 select the RTC clock source; in this case the Backup domain will be reset in
94 order to modify the RTC Clock source, as consequence RTC registers (including
95 the backup registers) are set to their reset values.
96
97 @endverbatim
98 * @{
99 */
100 /**
101 * @brief Initialize the RCC extended peripherals clocks according to the specified
102 * parameters in the RCC_PeriphCLKInitTypeDef.
103 * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
104 * contains a field PeriphClockSelection which can be a combination of the following values:
105 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
106 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
107 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
108 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (*)
109 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (*)
110 * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock (*)
111 * @arg @ref RCC_PERIPHCLK_UART7 UART7 peripheral clock (*)
112 * @arg @ref RCC_PERIPHCLK_UART8 UART8 peripheral clock (*)
113 * @arg @ref RCC_PERIPHCLK_UART9 UART9 peripheral clock (*)
114 * @arg @ref RCC_PERIPHCLK_USART10 USART10 peripheral clock (*)
115 * @arg @ref RCC_PERIPHCLK_USART11 USART11 peripheral clock (*)
116 * @arg @ref RCC_PERIPHCLK_UART12 UART12 peripheral clock (*)
117 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
118 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
119 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
120 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock (*)
121 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (*)
122 * @arg @ref RCC_PERIPHCLK_I3C1 I3C1 peripheral clock
123 * @arg @ref RCC_PERIPHCLK_I3C2 I3C2 peripheral clock (***)
124 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
125 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
126 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (*)
127 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (*)
128 * @arg @ref RCC_PERIPHCLK_ADCDAC ADCDAC peripheral clock
129 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
130 * @arg @ref RCC_PERIPHCLK_ADC2 ADC2 peripheral clock
131 * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock (*)
132 * @arg @ref RCC_PERIPHCLK_SDMMC2 SDMMC2 peripheral clock (**)
133 * @arg @ref RCC_PERIPHCLK_CKPER CKPER peripheral clock
134 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
135 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
136 * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock
137 * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock
138 * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
139 * @arg @ref RCC_PERIPHCLK_SPI4 SPI4 peripheral clock (*)
140 * @arg @ref RCC_PERIPHCLK_SPI5 SPI5 peripheral clock (*)
141 * @arg @ref RCC_PERIPHCLK_SPI6 SPI6 peripheral clock (*)
142 * @arg @ref RCC_PERIPHCLK_OSPI OCTOSPI peripheral clock (*)
143 * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock
144 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock (*)
145 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
146 * @arg @ref RCC_PERIPHCLK_LPTIM3 LPTIM3 peripheral clock (*)
147 * @arg @ref RCC_PERIPHCLK_LPTIM4 LPTIM4 peripheral clock (*)
148 * @arg @ref RCC_PERIPHCLK_LPTIM5 LPTIM5 peripheral clock (*)
149 * @arg @ref RCC_PERIPHCLK_LPTIM6 LPTIM6 peripheral clock (*)
150 * @arg @ref RCC_PERIPHCLK_DAC_LP DAC peripheral low-power clock
151 * @arg @ref RCC_PERIPHCLK_TIM TIM peripheral clock
152 *
153 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
154 * the RTC clock source: in this case the access to Backup domain is enabled.
155 *
156 * @retval HAL status
157 *
158 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
159 * (**) : For stm32h563xx and stm32h57xxx family lines only.
160 * (***) : For stm32h503xx family line only.
161 */
HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef * pPeriphClkInit)162 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
163 {
164 uint32_t tmpregister;
165 uint32_t tickstart;
166 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
167 HAL_StatusTypeDef status = HAL_OK; /* Final status */
168
169 /* Check the parameters */
170 assert_param(IS_RCC_PERIPHCLOCK(pPeriphClkInit->PeriphClockSelection));
171
172 /*------------------------------------ CKPER configuration --------------------------------------*/
173 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
174 {
175 /* Check the parameters */
176 assert_param(IS_RCC_CLKPSOURCE(pPeriphClkInit->CkperClockSelection));
177
178 /* Configure the CKPER clock source */
179 __HAL_RCC_CLKP_CONFIG(pPeriphClkInit->CkperClockSelection);
180 }
181
182 /*-------------------------- USART1 clock source configuration -------------------*/
183 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
184 {
185 /* Check the parameters */
186 assert_param(IS_RCC_USART1CLKSOURCE(pPeriphClkInit->Usart1ClockSelection));
187
188 switch (pPeriphClkInit->Usart1ClockSelection)
189 {
190 case RCC_USART1CLKSOURCE_PCLK2: /* PCLK2 is used as clock source for USART1*/
191
192 /* USART1 clock source config set later after clock selection check */
193 break;
194
195 case RCC_USART1CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART1*/
196 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
197 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
198 /* USART1 clock source config set later after clock selection check */
199 break;
200 #if defined(RCC_USART1CLKSOURCE_PLL3Q)
201 case RCC_USART1CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART1*/
202 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
203 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
204 /* USART1 clock source config set later after clock selection check */
205 break;
206 #endif /* RCC_CR_PLL3ON */
207
208 case RCC_USART1CLKSOURCE_HSI: /* HSI clock is used as source of USART1 clock*/
209 /* USART1 clock source config set later after clock selection check */
210 break;
211
212 case RCC_USART1CLKSOURCE_CSI: /* CSI clock is used as source of USART1 clock*/
213 /* USART1 clock source config set later after clock selection check */
214 break;
215
216 case RCC_USART1CLKSOURCE_LSE: /* LSE clock is used as source of USART1 clock*/
217 /* USART1 clock source config set later after clock selection check */
218 break;
219
220 default:
221 ret = HAL_ERROR;
222 break;
223 }
224
225 if (ret == HAL_OK)
226 {
227 /* Set the source of USART1 clock*/
228 __HAL_RCC_USART1_CONFIG(pPeriphClkInit->Usart1ClockSelection);
229 }
230 else
231 {
232 /* set overall return value */
233 status = ret;
234 }
235 }
236
237 /*-------------------------- USART2 clock source configuration -------------------*/
238 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
239 {
240 /* Check the parameters */
241 assert_param(IS_RCC_USART2CLKSOURCE(pPeriphClkInit->Usart2ClockSelection));
242
243 switch (pPeriphClkInit->Usart2ClockSelection)
244 {
245 case RCC_USART2CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART2*/
246
247 /* USART2 clock source config set later after clock selection check */
248 break;
249
250 case RCC_USART2CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART2*/
251 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
252 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
253 /* USART2 clock source config set later after clock selection check */
254 break;
255
256 #if defined(RCC_USART2CLKSOURCE_PLL3Q)
257 case RCC_USART2CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART2*/
258 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
259 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
260 /* USART2 clock source config set later after clock selection check */
261 break;
262 #endif /* RCC_USART2CLKSOURCE_PLL3 */
263
264 case RCC_USART2CLKSOURCE_HSI: /* HSI clock is used as source of USART2 clock*/
265 /* USART2 clock source config set later after clock selection check */
266 break;
267
268 case RCC_USART2CLKSOURCE_CSI: /* CSI clock is used as source of USART2 clock*/
269 /* USART2 clock source config set later after clock selection check */
270 break;
271
272 case RCC_USART2CLKSOURCE_LSE: /* LSE clock is used as source of USART2 clock*/
273 /* USART2 clock source config set later after clock selection check */
274 break;
275
276 default:
277 ret = HAL_ERROR;
278 break;
279 }
280
281 if (ret == HAL_OK)
282 {
283 /* Set the source of USART2 clock*/
284 __HAL_RCC_USART2_CONFIG(pPeriphClkInit->Usart2ClockSelection);
285 }
286 else
287 {
288 /* set overall return value */
289 status = ret;
290 }
291 }
292
293 /*-------------------------- USART3 clock source configuration -------------------*/
294 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
295 {
296 /* Check the parameters */
297 assert_param(IS_RCC_USART3CLKSOURCE(pPeriphClkInit->Usart3ClockSelection));
298
299 switch (pPeriphClkInit->Usart3ClockSelection)
300 {
301 case RCC_USART3CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART3*/
302
303 /* USART3 clock source config set later after clock selection check */
304 break;
305
306 case RCC_USART3CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART3*/
307 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
308 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
309 /* USART3 clock source config set later after clock selection check */
310 break;
311
312 #if defined(RCC_USART3CLKSOURCE_PLL3Q)
313 case RCC_USART3CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART3*/
314 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
315 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
316 /* USART3 clock source config set later after clock selection check */
317 break;
318 #endif /* RCC_USART3CLKSOURCE_PLL3 */
319
320 case RCC_USART3CLKSOURCE_HSI: /* HSI clock is used as source of USART3 clock*/
321 /* USART3 clock source config set later after clock selection check */
322 break;
323
324 case RCC_USART3CLKSOURCE_CSI: /* CSI clock is used as source of USART3 clock*/
325 /* USART3 clock source config set later after clock selection check */
326 break;
327
328 case RCC_USART3CLKSOURCE_LSE: /* LSE clock is used as source of USART3 clock*/
329 /* USART3 clock source config set later after clock selection check */
330 break;
331
332 default:
333 ret = HAL_ERROR;
334 break;
335 }
336
337 if (ret == HAL_OK)
338 {
339 /* Set the source of USART3 clock*/
340 __HAL_RCC_USART3_CONFIG(pPeriphClkInit->Usart3ClockSelection);
341 }
342 else
343 {
344 /* set overall return value */
345 status = ret;
346 }
347 }
348
349 #if defined(UART4)
350 /*-------------------------- UART4 clock source configuration --------------------*/
351 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
352 {
353 /* Check the parameters */
354 assert_param(IS_RCC_UART4CLKSOURCE(pPeriphClkInit->Uart4ClockSelection));
355
356 switch (pPeriphClkInit->Uart4ClockSelection)
357 {
358 case RCC_UART4CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART4*/
359
360 /* UART4 clock source config set later after clock selection check */
361 break;
362
363 case RCC_UART4CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART4*/
364 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
365 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
366 /* UART4 clock source config set later after clock selection check */
367 break;
368
369 case RCC_UART4CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART4*/
370 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
371 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
372 /* UART4 clock source config set later after clock selection check */
373 break;
374
375 case RCC_UART4CLKSOURCE_HSI: /* HSI clock is used as source of UART4 clock*/
376 /* UART4 clock source config set later after clock selection check */
377 break;
378
379 case RCC_UART4CLKSOURCE_CSI: /* CSI clock is used as source of UART4 clock*/
380 /* UART4 clock source config set later after clock selection check */
381 break;
382
383 case RCC_UART4CLKSOURCE_LSE: /* LSE clock is used as source of UART4 clock*/
384 /* UART4 clock source config set later after clock selection check */
385 break;
386
387 default:
388 ret = HAL_ERROR;
389 break;
390 }
391
392 if (ret == HAL_OK)
393 {
394 /* Set the source of UART4 clock*/
395 __HAL_RCC_UART4_CONFIG(pPeriphClkInit->Uart4ClockSelection);
396 }
397 else
398 {
399 /* set overall return value */
400 status = ret;
401 }
402 }
403 #endif /* UART4 */
404
405 #if defined(UART5)
406 /*-------------------------- UART5 clock source configuration --------------------*/
407 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
408 {
409 /* Check the parameters */
410 assert_param(IS_RCC_UART5CLKSOURCE(pPeriphClkInit->Uart5ClockSelection));
411
412 switch (pPeriphClkInit->Uart5ClockSelection)
413 {
414 case RCC_UART5CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART5*/
415
416 /* UART5 clock source config set later after clock selection check */
417 break;
418
419 case RCC_UART5CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART5*/
420 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
421 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
422 /* UART5 clock source config set later after clock selection check */
423 break;
424
425 case RCC_UART5CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART5*/
426 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
427 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
428 /* UART5 clock source config set later after clock selection check */
429 break;
430
431 case RCC_UART5CLKSOURCE_HSI: /* HSI clock is used as source of UART5 clock*/
432 /* UART5 clock source config set later after clock selection check */
433 break;
434
435 case RCC_UART5CLKSOURCE_CSI: /* CSI clock is used as source of UART5 clock*/
436 /* UART5 clock source config set later after clock selection check */
437 break;
438
439 case RCC_UART5CLKSOURCE_LSE: /* LSE clock is used as source of UART5 clock*/
440 /* UART5 clock source config set later after clock selection check */
441 break;
442
443 default:
444 ret = HAL_ERROR;
445 break;
446 }
447
448 if (ret == HAL_OK)
449 {
450 /* Set the source of UART5 clock*/
451 __HAL_RCC_UART5_CONFIG(pPeriphClkInit->Uart5ClockSelection);
452 }
453 else
454 {
455 /* set overall return value */
456 status = ret;
457 }
458 }
459 #endif /* UART5 */
460
461 #if defined(USART6)
462 /*-------------------------- USART6 clock source configuration -------------------*/
463 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
464 {
465 /* Check the parameters */
466 assert_param(IS_RCC_USART6CLKSOURCE(pPeriphClkInit->Usart6ClockSelection));
467
468 switch (pPeriphClkInit->Usart6ClockSelection)
469 {
470 case RCC_USART6CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART6*/
471
472 /* USART6 clock source config set later after clock selection check */
473 break;
474
475 case RCC_USART6CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART6*/
476 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
477 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
478 /* USART6 clock source config set later after clock selection check */
479 break;
480
481 case RCC_USART6CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART6*/
482 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
483 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
484 /* USART6 clock source config set later after clock selection check */
485 break;
486
487 case RCC_USART6CLKSOURCE_HSI: /* HSI clock is used as source of USART6 clock*/
488 /* USART6 clock source config set later after clock selection check */
489 break;
490
491 case RCC_USART6CLKSOURCE_CSI: /* CSI clock is used as source of USART6 clock*/
492 /* USART6 clock source config set later after clock selection check */
493 break;
494
495 case RCC_USART6CLKSOURCE_LSE: /* LSE clock is used as source of USART6 clock*/
496 /* USART6 clock source config set later after clock selection check */
497 break;
498
499 default:
500 ret = HAL_ERROR;
501 break;
502 }
503
504 if (ret == HAL_OK)
505 {
506 /* Set the source of USART6 clock*/
507 __HAL_RCC_USART6_CONFIG(pPeriphClkInit->Usart6ClockSelection);
508 }
509 else
510 {
511 /* set overall return value */
512 status = ret;
513 }
514 }
515 #endif /* USART6 */
516
517 #if defined(UART7)
518 /*-------------------------- UART7 clock source configuration -------------------*/
519 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
520 {
521 /* Check the parameters */
522 assert_param(IS_RCC_UART7CLKSOURCE(pPeriphClkInit->Uart7ClockSelection));
523
524 switch (pPeriphClkInit->Uart7ClockSelection)
525 {
526 case RCC_UART7CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART7*/
527
528 /* UART7 clock source config set later after clock selection check */
529 break;
530
531 case RCC_UART7CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART7*/
532 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
533 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
534 /* UART7 clock source config set later after clock selection check */
535 break;
536
537 case RCC_UART7CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART7*/
538 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
539 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
540 /* UART7 clock source config set later after clock selection check */
541 break;
542
543 case RCC_UART7CLKSOURCE_HSI: /* HSI clock is used as source of UART7 clock*/
544 /* UART7 clock source config set later after clock selection check */
545 break;
546
547 case RCC_UART7CLKSOURCE_CSI: /* CSI clock is used as source of UART7 clock*/
548 /* UART7 clock source config set later after clock selection check */
549 break;
550
551 case RCC_UART7CLKSOURCE_LSE: /* LSE clock is used as source of UART7 clock*/
552 /* UART7 clock source config set later after clock selection check */
553 break;
554
555 default:
556 ret = HAL_ERROR;
557 break;
558 }
559
560 if (ret == HAL_OK)
561 {
562 /* Set the source of UART7 clock*/
563 __HAL_RCC_UART7_CONFIG(pPeriphClkInit->Uart7ClockSelection);
564 }
565 else
566 {
567 /* set overall return value */
568 status = ret;
569 }
570 }
571 #endif /* UART7 */
572
573 #if defined(UART8)
574 /*-------------------------- UART8 clock source configuration -------------------*/
575 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
576 {
577 /* Check the parameters */
578 assert_param(IS_RCC_UART8CLKSOURCE(pPeriphClkInit->Uart8ClockSelection));
579
580 switch (pPeriphClkInit->Uart8ClockSelection)
581 {
582 case RCC_UART8CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART8*/
583
584 /* UART8 clock source config set later after clock selection check */
585 break;
586
587 case RCC_UART8CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART8*/
588 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
589 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
590 /* UART8 clock source config set later after clock selection check */
591 break;
592
593 case RCC_UART8CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART8*/
594 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
595 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
596 /* UART8 clock source config set later after clock selection check */
597 break;
598
599 case RCC_UART8CLKSOURCE_HSI: /* HSI clock is used as source of UART8 clock*/
600 /* UART8 clock source config set later after clock selection check */
601 break;
602
603 case RCC_UART8CLKSOURCE_CSI: /* CSI clock is used as source of UART8 clock*/
604 /* UART8 clock source config set later after clock selection check */
605 break;
606
607 case RCC_UART8CLKSOURCE_LSE: /* LSE clock is used as source of UART8 clock*/
608 /* UART8 clock source config set later after clock selection check */
609 break;
610
611 default:
612 ret = HAL_ERROR;
613 break;
614 }
615
616 if (ret == HAL_OK)
617 {
618 /* Set the source of UART8 clock*/
619 __HAL_RCC_UART8_CONFIG(pPeriphClkInit->Uart8ClockSelection);
620 }
621 else
622 {
623 /* set overall return value */
624 status = ret;
625 }
626 }
627 #endif /* UART9 */
628
629 #if defined(UART9)
630 /*-------------------------- UART9 clock source configuration -------------------*/
631 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART9) == RCC_PERIPHCLK_UART9)
632 {
633 /* Check the parameters */
634 assert_param(IS_RCC_UART9CLKSOURCE(pPeriphClkInit->Uart9ClockSelection));
635
636 switch (pPeriphClkInit->Uart9ClockSelection)
637 {
638 case RCC_UART9CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART9*/
639
640 /* UART9 clock source config set later after clock selection check */
641 break;
642
643 case RCC_UART9CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART9*/
644 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
645 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
646 /* UART9 clock source config set later after clock selection check */
647 break;
648
649 case RCC_UART9CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART9*/
650 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
651 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
652 /* UART9 clock source config set later after clock selection check */
653 break;
654
655 case RCC_UART9CLKSOURCE_HSI: /* HSI clock is used as source of UART9 clock*/
656 /* UART9 clock source config set later after clock selection check */
657 break;
658
659 case RCC_UART9CLKSOURCE_CSI: /* CSI clock is used as source of UART9 clock*/
660 /* UART9 clock source config set later after clock selection check */
661 break;
662
663 case RCC_UART9CLKSOURCE_LSE: /* LSE clock is used as source of UART9 clock*/
664 /* UART9 clock source config set later after clock selection check */
665 break;
666
667 default:
668 ret = HAL_ERROR;
669 break;
670 }
671
672 if (ret == HAL_OK)
673 {
674 /* Set the source of UART9 clock*/
675 __HAL_RCC_UART9_CONFIG(pPeriphClkInit->Uart9ClockSelection);
676 }
677 else
678 {
679 /* set overall return value */
680 status = ret;
681 }
682 }
683 #endif /* UART9 */
684
685 #if defined(USART10)
686 /*-------------------------- USART10 clock source configuration -------------------*/
687 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART10) == RCC_PERIPHCLK_USART10)
688 {
689 /* Check the parameters */
690 assert_param(IS_RCC_USART10CLKSOURCE(pPeriphClkInit->Usart10ClockSelection));
691
692 switch (pPeriphClkInit->Usart10ClockSelection)
693 {
694 case RCC_USART10CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART10*/
695
696 /* USART10 clock source config set later after clock selection check */
697 break;
698
699 case RCC_USART10CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART10*/
700 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
701 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
702 /* USART10 clock source config set later after clock selection check */
703 break;
704
705 case RCC_USART10CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART10*/
706 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
707 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
708 /* USART10 clock source config set later after clock selection check */
709 break;
710
711 case RCC_USART10CLKSOURCE_HSI: /* HSI clock is used as source of USART10 clock*/
712 /* USART10 clock source config set later after clock selection check */
713 break;
714
715 case RCC_USART10CLKSOURCE_CSI: /* CSI clock is used as source of USART10 clock*/
716 /* USART10 clock source config set later after clock selection check */
717 break;
718
719 case RCC_USART10CLKSOURCE_LSE: /* LSE clock is used as source of USART10 clock*/
720 /* USART10 clock source config set later after clock selection check */
721 break;
722
723 default:
724 ret = HAL_ERROR;
725 break;
726 }
727
728 if (ret == HAL_OK)
729 {
730 /* Set the source of USART10 clock*/
731 __HAL_RCC_USART10_CONFIG(pPeriphClkInit->Usart10ClockSelection);
732 }
733 else
734 {
735 /* set overall return value */
736 status = ret;
737 }
738 }
739 #endif /* USART10 */
740
741 #if defined(USART11)
742 /*-------------------------- USART11 clock source configuration -------------------*/
743 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART11) == RCC_PERIPHCLK_USART11)
744 {
745 /* Check the parameters */
746 assert_param(IS_RCC_USART11CLKSOURCE(pPeriphClkInit->Usart11ClockSelection));
747
748 switch (pPeriphClkInit->Usart11ClockSelection)
749 {
750 case RCC_USART11CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for USART11*/
751
752 /* USART11 clock source config set later after clock selection check */
753 break;
754
755 case RCC_USART11CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USART11*/
756 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
757 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
758 /* USART11 clock source config set later after clock selection check */
759 break;
760
761 case RCC_USART11CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USART11*/
762 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
763 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
764 /* USART11 clock source config set later after clock selection check */
765 break;
766
767 case RCC_USART11CLKSOURCE_HSI: /* HSI clock is used as source of USART11 clock*/
768 /* USART11 clock source config set later after clock selection check */
769 break;
770
771 case RCC_USART11CLKSOURCE_CSI: /* CSI clock is used as source of USART11 clock*/
772 /* USART11 clock source config set later after clock selection check */
773 break;
774
775 case RCC_USART11CLKSOURCE_LSE: /* LSE clock is used as source of USART11 clock*/
776 /* USART11 clock source config set later after clock selection check */
777 break;
778
779 default:
780 ret = HAL_ERROR;
781 break;
782 }
783
784 if (ret == HAL_OK)
785 {
786 /* Set the source of USART11 clock*/
787 __HAL_RCC_USART11_CONFIG(pPeriphClkInit->Usart11ClockSelection);
788 }
789 else
790 {
791 /* set overall return value */
792 status = ret;
793 }
794 }
795 #endif /*USART11*/
796
797 #if defined(UART12)
798 /*-------------------------- UART12 clock source configuration -------------------*/
799 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART12) == RCC_PERIPHCLK_UART12)
800 {
801 /* Check the parameters */
802 assert_param(IS_RCC_UART12CLKSOURCE(pPeriphClkInit->Uart12ClockSelection));
803
804 switch (pPeriphClkInit->Uart12ClockSelection)
805 {
806 case RCC_UART12CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for UART12*/
807
808 /* UART12 clock source config set later after clock selection check */
809 break;
810
811 case RCC_UART12CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for UART12*/
812 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
813 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
814 /* UART12 clock source config set later after clock selection check */
815 break;
816
817 case RCC_UART12CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for UART12*/
818 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
819 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
820 /* UART12 clock source config set later after clock selection check */
821 break;
822
823 case RCC_UART12CLKSOURCE_HSI: /* HSI clock is used as source of UART12 clock*/
824 /* UART12 clock source config set later after clock selection check */
825 break;
826
827 case RCC_UART12CLKSOURCE_CSI: /* CSI clock is used as source of UART12 clock*/
828 /* UART12 clock source config set later after clock selection check */
829 break;
830
831 case RCC_UART12CLKSOURCE_LSE: /* LSE clock is used as source of UART12 clock*/
832 /* UART12 clock source config set later after clock selection check */
833 break;
834
835 default:
836 ret = HAL_ERROR;
837 break;
838 }
839
840 if (ret == HAL_OK)
841 {
842 /* Set the source of UART12 clock*/
843 __HAL_RCC_UART12_CONFIG(pPeriphClkInit->Uart12ClockSelection);
844 }
845 else
846 {
847 /* set overall return value */
848 status = ret;
849 }
850 }
851 #endif /* UART12 */
852
853 /*-------------------------- LPUART1 clock source configuration ------------------*/
854 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
855 {
856 /* Check the parameters */
857 assert_param(IS_RCC_LPUART1CLKSOURCE(pPeriphClkInit->Lpuart1ClockSelection));
858
859 switch (pPeriphClkInit->Lpuart1ClockSelection)
860 {
861 case RCC_LPUART1CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPUART1*/
862
863 /* LPUART1 clock source config set later after clock selection check */
864 break;
865
866 case RCC_LPUART1CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for LPUART1*/
867 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
868 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
869 /* LPUART1 clock source config set later after clock selection check */
870 break;
871
872 #if defined(RCC_LPUART1CLKSOURCE_PLL3Q)
873 case RCC_LPUART1CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for LPUART1*/
874 /* PLL3 input clock, parameters M, N & Q configuration clock output (PLL3ClockOut) */
875 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
876 /* LPUART1 clock source config set later after clock selection check */
877 break;
878 #endif /* RCC_LPUART1CLKSOURCE_PLL3Q */
879
880 case RCC_LPUART1CLKSOURCE_HSI: /* HSI clock is used as source of LPUART1 clock*/
881 /* LPUART1 clock source config set later after clock selection check */
882 break;
883
884 case RCC_LPUART1CLKSOURCE_CSI: /* CSI clock is used as source of LPUART1 clock*/
885 /* LPUART1 clock source config set later after clock selection check */
886 break;
887
888 case RCC_LPUART1CLKSOURCE_LSE: /* LSE clock is used as source of LPUART1 clock*/
889 /* LPUART1 clock source config set later after clock selection check */
890 break;
891
892 default:
893 ret = HAL_ERROR;
894 break;
895 }
896
897 if (ret == HAL_OK)
898 {
899 /* Set the source of LPUART1 clock*/
900 __HAL_RCC_LPUART1_CONFIG(pPeriphClkInit->Lpuart1ClockSelection);
901 }
902 else
903 {
904 /* set overall return value */
905 status = ret;
906 }
907 }
908
909 /*-------------------------- I2C1 clock source configuration ---------------------*/
910 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
911 {
912 /* Check the parameters */
913 assert_param(IS_RCC_I2C1CLKSOURCE(pPeriphClkInit->I2c1ClockSelection));
914
915 switch (pPeriphClkInit->I2c1ClockSelection)
916 {
917 case RCC_I2C1CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for I2C1*/
918
919 /* I2C1 clock source config set later after clock selection check */
920 break;
921
922 #if defined(RCC_I2C1CLKSOURCE_PLL3R)
923 case RCC_I2C1CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I2C1*/
924 /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
925 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
926 #else
927 case RCC_I2C1CLKSOURCE_PLL2R: /* PLL2 is used as clock source for I2C1*/
928 /* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */
929 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
930 #endif /* RCC_I2C1CLKSOURCE_PLL3R */
931 /* I2C1 clock source config set later after clock selection check */
932 break;
933
934
935 case RCC_I2C1CLKSOURCE_HSI: /* HSI clock is used as source of I2C1 clock*/
936 /* I2C1 clock source config set later after clock selection check */
937 break;
938
939 case RCC_I2C1CLKSOURCE_CSI: /* CSI clock is used as source of I2C1 clock*/
940 /* I2C1 clock source config set later after clock selection check */
941 break;
942
943 default:
944 ret = HAL_ERROR;
945 break;
946 }
947
948 if (ret == HAL_OK)
949 {
950 /* Set the source of I2C1 clock*/
951 __HAL_RCC_I2C1_CONFIG(pPeriphClkInit->I2c1ClockSelection);
952 }
953 else
954 {
955 /* set overall return value */
956 status = ret;
957 }
958 }
959
960 /*-------------------------- I2C2 clock source configuration ---------------------*/
961 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
962 {
963 /* Check the parameters */
964 assert_param(IS_RCC_I2C2CLKSOURCE(pPeriphClkInit->I2c2ClockSelection));
965
966 switch (pPeriphClkInit->I2c2ClockSelection)
967 {
968 case RCC_I2C2CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for I2C2*/
969
970 /* I2C2 clock source config set later after clock selection check */
971 break;
972
973 #if defined(RCC_I2C2CLKSOURCE_PLL3R)
974 case RCC_I2C2CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I2C2*/
975 /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
976 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
977 #else
978 case RCC_I2C2CLKSOURCE_PLL2R: /* PLL32 is used as clock source for I2C2*/
979 /* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */
980 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
981 #endif /* RCC_I2C2CLKSOURCE_PLL3R */
982 /* I2C2 clock source config set later after clock selection check */
983 break;
984
985 case RCC_I2C2CLKSOURCE_HSI: /* HSI clock is used as source of I2C2 clock*/
986 /* I2C2 clock source config set later after clock selection check */
987 break;
988
989 case RCC_I2C2CLKSOURCE_CSI: /* CSI clock is used as source of I2C2 clock*/
990 /* I2C2 clock source config set later after clock selection check */
991 break;
992
993 default:
994 ret = HAL_ERROR;
995 break;
996 }
997
998 if (ret == HAL_OK)
999 {
1000 /* Set the source of I2C2 clock*/
1001 __HAL_RCC_I2C2_CONFIG(pPeriphClkInit->I2c2ClockSelection);
1002 }
1003 else
1004 {
1005 /* set overall return value */
1006 status = ret;
1007 }
1008 }
1009
1010 #if defined(I2C3)
1011 /*-------------------------- I2C3 clock source configuration ---------------------*/
1012 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
1013 {
1014 /* Check the parameters */
1015 assert_param(IS_RCC_I2C3CLKSOURCE(pPeriphClkInit->I2c3ClockSelection));
1016
1017 switch (pPeriphClkInit->I2c3ClockSelection)
1018 {
1019 case RCC_I2C3CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for I2C3*/
1020
1021 /* I2C3 clock source config set later after clock selection check */
1022 break;
1023
1024 case RCC_I2C3CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I2C3*/
1025 /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1026 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1027 /* I2C3 clock source config set later after clock selection check */
1028 break;
1029
1030 case RCC_I2C3CLKSOURCE_HSI: /* HSI clock is used as source of I2C3 clock*/
1031 /* I2C3 clock source config set later after clock selection check */
1032 break;
1033
1034 case RCC_I2C3CLKSOURCE_CSI: /* CSI clock is used as source of I2C3 clock*/
1035 /* I2C3 clock source config set later after clock selection check */
1036 break;
1037
1038 default:
1039 ret = HAL_ERROR;
1040 break;
1041 }
1042
1043 if (ret == HAL_OK)
1044 {
1045 /* Set the source of I2C3 clock*/
1046 __HAL_RCC_I2C3_CONFIG(pPeriphClkInit->I2c3ClockSelection);
1047 }
1048 else
1049 {
1050 /* set overall return value */
1051 status = ret;
1052 }
1053 }
1054 #endif /* I2C3 */
1055
1056 #if defined(I2C4)
1057 /*-------------------------- I2C4 clock source configuration ---------------------*/
1058 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
1059 {
1060 /* Check the parameters */
1061 assert_param(IS_RCC_I2C4CLKSOURCE(pPeriphClkInit->I2c4ClockSelection));
1062
1063 switch (pPeriphClkInit->I2c4ClockSelection)
1064 {
1065 case RCC_I2C4CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for I2C4*/
1066
1067 /* I2C4 clock source config set later after clock selection check */
1068 break;
1069
1070 case RCC_I2C4CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I2C4*/
1071 /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1072 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1073 /* I2C4 clock source config set later after clock selection check */
1074 break;
1075
1076 case RCC_I2C4CLKSOURCE_HSI: /* HSI clock is used as source of I2C4 clock*/
1077 /* I2C4 clock source config set later after clock selection check */
1078 break;
1079
1080 case RCC_I2C4CLKSOURCE_CSI: /* CSI clock is used as source of I2C4 clock*/
1081 /* I2C4 clock source config set later after clock selection check */
1082 break;
1083
1084 default:
1085 ret = HAL_ERROR;
1086 break;
1087 }
1088
1089 if (ret == HAL_OK)
1090 {
1091 /* Set the source of I2C4 clock*/
1092 __HAL_RCC_I2C4_CONFIG(pPeriphClkInit->I2c4ClockSelection);
1093 }
1094 else
1095 {
1096 /* set overall return value */
1097 status = ret;
1098 }
1099 }
1100 #endif /* I2C4 */
1101
1102 /*-------------------------- I3C1 clock source configuration ---------------------*/
1103 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I3C1) == RCC_PERIPHCLK_I3C1)
1104 {
1105 /* Check the parameters */
1106 assert_param(IS_RCC_I3C1CLKSOURCE(pPeriphClkInit->I3c1ClockSelection));
1107
1108 switch (pPeriphClkInit->I3c1ClockSelection)
1109 {
1110 case RCC_I3C1CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for I3C1*/
1111
1112 /* I3C1 clock source config set later after clock selection check */
1113 break;
1114
1115 #if defined(RCC_I3C1CLKSOURCE_PLL3R)
1116 case RCC_I3C1CLKSOURCE_PLL3R: /* PLL3 is used as clock source for I3C1*/
1117 /* PLL3 input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1118 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1119 #else
1120 case RCC_I3C1CLKSOURCE_PLL2R: /* PLL2 is used as clock source for I3C1*/
1121 /* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */
1122 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1123 #endif /* RCC_I3C1CLKSOURCE_PLL3R */
1124 /* I3C1 clock source config set later after clock selection check */
1125 break;
1126
1127 case RCC_I3C1CLKSOURCE_HSI: /* HSI clock is used as source of I3C1 clock*/
1128 /* I3C1 clock source config set later after clock selection check */
1129 break;
1130
1131 default:
1132 ret = HAL_ERROR;
1133 break;
1134 }
1135
1136 if (ret == HAL_OK)
1137 {
1138 /* Set the source of I3C1 clock*/
1139 __HAL_RCC_I3C1_CONFIG(pPeriphClkInit->I3c1ClockSelection);
1140 }
1141 else
1142 {
1143 /* set overall return value */
1144 status = ret;
1145 }
1146 }
1147
1148 #if defined (I3C2)
1149 /*-------------------------- I3C2 clock source configuration ---------------------*/
1150 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I3C2) == RCC_PERIPHCLK_I3C2)
1151 {
1152 /* Check the parameters */
1153 assert_param(IS_RCC_I3C2CLKSOURCE(pPeriphClkInit->I3c2ClockSelection));
1154
1155 switch (pPeriphClkInit->I3c2ClockSelection)
1156 {
1157 case RCC_I3C2CLKSOURCE_PCLK3: /* PCLK1 is used as clock source for I3C2*/
1158
1159 /* I3C2 clock source config set later after clock selection check */
1160 break;
1161
1162 case RCC_I3C2CLKSOURCE_PLL2R: /* PLL2 is used as clock source for I3C2*/
1163 /* PLL2 input clock, parameters M, N & R configuration clock output (PLL2ClockOut) */
1164 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1165 /* I3C2 clock source config set later after clock selection check */
1166 break;
1167
1168 case RCC_I3C2CLKSOURCE_HSI: /* HSI clock is used as source of I3C2 clock*/
1169 /* I3C2 clock source config set later after clock selection check */
1170 break;
1171
1172 default:
1173 ret = HAL_ERROR;
1174 break;
1175 }
1176
1177 if (ret == HAL_OK)
1178 {
1179 /* Set the source of I3C2 clock*/
1180 __HAL_RCC_I3C2_CONFIG(pPeriphClkInit->I3c2ClockSelection);
1181 }
1182 else
1183 {
1184 /* set overall return value */
1185 status = ret;
1186 }
1187 }
1188 #endif /* I3C2 */
1189
1190 /*------------------------------------ TIM configuration --------------------------------------*/
1191 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
1192 {
1193 /* Check the parameters */
1194 assert_param(IS_RCC_TIMPRES(pPeriphClkInit->TimPresSelection));
1195
1196 /* Configure Timer Prescaler */
1197 __HAL_RCC_TIMCLKPRESCALER(pPeriphClkInit->TimPresSelection);
1198 }
1199
1200 /*-------------------------- LPTIM1 clock source configuration ---------------------*/
1201 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
1202 {
1203 /* Check the parameters */
1204 assert_param(IS_RCC_LPTIM1CLK(pPeriphClkInit->Lptim1ClockSelection));
1205
1206 switch (pPeriphClkInit->Lptim1ClockSelection)
1207 {
1208 case RCC_LPTIM1CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM1*/
1209
1210 /* LPTIM1 clock source config set later after clock selection check */
1211 break;
1212
1213 case RCC_LPTIM1CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM1*/
1214 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1215 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1216 /* LPTIM1 clock source config set later after clock selection check */
1217 break;
1218
1219 #if defined(RCC_LPTIM1CLKSOURCE_PLL3R)
1220 case RCC_LPTIM1CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM1*/
1221 /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1222 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1223 /* LPTIM1 clock source config set later after clock selection check */
1224 break;
1225 #endif /* RCC_LPTIM1CLKSOURCE_PLL3R */
1226
1227 case RCC_LPTIM1CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM1 clock*/
1228 /* LPTIM1 clock source config set later after clock selection check */
1229 break;
1230
1231 case RCC_LPTIM1CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM1 clock*/
1232 /* LPTIM1 clock source config set later after clock selection check */
1233 break;
1234
1235 case RCC_LPTIM1CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM1 clock*/
1236 /* LPTIM1 clock source config set later after clock selection check */
1237 break;
1238
1239 default:
1240 ret = HAL_ERROR;
1241 break;
1242 }
1243
1244 if (ret == HAL_OK)
1245 {
1246 /* Set the source of LPTIM1 clock*/
1247 __HAL_RCC_LPTIM1_CONFIG(pPeriphClkInit->Lptim1ClockSelection);
1248 }
1249 else
1250 {
1251 /* set overall return value */
1252 status = ret;
1253 }
1254 }
1255
1256 /*-------------------------- LPTIM2 clock source configuration ---------------------*/
1257 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
1258 {
1259 /* Check the parameters */
1260 assert_param(IS_RCC_LPTIM2CLK(pPeriphClkInit->Lptim2ClockSelection));
1261
1262 switch (pPeriphClkInit->Lptim2ClockSelection)
1263 {
1264 case RCC_LPTIM2CLKSOURCE_PCLK1: /* PCLK1 is used as clock source for LPTIM2*/
1265
1266 /* LPTIM2 clock source config set later after clock selection check */
1267 break;
1268
1269 case RCC_LPTIM2CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM2*/
1270 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1271 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1272 /* LPTIM2 clock source config set later after clock selection check */
1273 break;
1274
1275 #if defined(RCC_LPTIM2CLKSOURCE_PLL3R)
1276 case RCC_LPTIM2CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM2*/
1277 /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1278 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1279 /* LPTIM2 clock source config set later after clock selection check */
1280 break;
1281 #endif /* RCC_LPTIM2CLKSOURCE_PLL3R */
1282
1283 case RCC_LPTIM2CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM2 clock*/
1284 /* LPTIM2 clock source config set later after clock selection check */
1285 break;
1286
1287 case RCC_LPTIM2CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM2 clock*/
1288 /* LPTIM2 clock source config set later after clock selection check */
1289 break;
1290
1291 case RCC_LPTIM2CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM2 clock*/
1292 /* LPTIM2 clock source config set later after clock selection check */
1293 break;
1294
1295 default:
1296 ret = HAL_ERROR;
1297 break;
1298 }
1299
1300 if (ret == HAL_OK)
1301 {
1302 /* Set the source of LPTIM2 clock*/
1303 __HAL_RCC_LPTIM2_CONFIG(pPeriphClkInit->Lptim2ClockSelection);
1304 }
1305 else
1306 {
1307 /* set overall return value */
1308 status = ret;
1309 }
1310 }
1311
1312 #if defined(LPTIM3)
1313 /*-------------------------- LPTIM3 clock source configuration ---------------------*/
1314 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM3) == RCC_PERIPHCLK_LPTIM3)
1315 {
1316 /* Check the parameters */
1317 assert_param(IS_RCC_LPTIM3CLK(pPeriphClkInit->Lptim3ClockSelection));
1318
1319 switch (pPeriphClkInit->Lptim3ClockSelection)
1320 {
1321 case RCC_LPTIM3CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM3*/
1322
1323 /* LPTIM3 clock source config set later after clock selection check */
1324 break;
1325
1326 case RCC_LPTIM3CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM3*/
1327 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1328 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1329 /* LPTIM3 clock source config set later after clock selection check */
1330 break;
1331
1332 case RCC_LPTIM3CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM3*/
1333 /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1334 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1335 /* LPTIM3 clock source config set later after clock selection check */
1336 break;
1337
1338 case RCC_LPTIM3CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM3 clock*/
1339 /* LPTIM3 clock source config set later after clock selection check */
1340 break;
1341
1342 case RCC_LPTIM3CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM3 clock*/
1343 /* LPTIM3 clock source config set later after clock selection check */
1344 break;
1345
1346 case RCC_LPTIM3CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM3 clock*/
1347 /* LPTIM3 clock source config set later after clock selection check */
1348 break;
1349
1350 default:
1351 ret = HAL_ERROR;
1352 break;
1353 }
1354
1355 if (ret == HAL_OK)
1356 {
1357 /* Set the source of LPTIM3 clock*/
1358 __HAL_RCC_LPTIM3_CONFIG(pPeriphClkInit->Lptim3ClockSelection);
1359 }
1360 else
1361 {
1362 /* set overall return value */
1363 status = ret;
1364 }
1365 }
1366 #endif /* LPTIM3 */
1367
1368 #if defined(LPTIM4)
1369 /*-------------------------- LPTIM4 clock source configuration ---------------------*/
1370 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM4) == RCC_PERIPHCLK_LPTIM4)
1371 {
1372 /* Check the parameters */
1373 assert_param(IS_RCC_LPTIM4CLK(pPeriphClkInit->Lptim4ClockSelection));
1374
1375 switch (pPeriphClkInit->Lptim4ClockSelection)
1376 {
1377 case RCC_LPTIM4CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM4*/
1378
1379 /* LPTIM4 clock source config set later after clock selection check */
1380 break;
1381
1382 case RCC_LPTIM4CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM4*/
1383 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1384 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1385 /* LPTIM4 clock source config set later after clock selection check */
1386 break;
1387
1388 case RCC_LPTIM4CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM4*/
1389 /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1390 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1391 /* LPTIM4 clock source config set later after clock selection check */
1392 break;
1393
1394 case RCC_LPTIM4CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM4 clock*/
1395 /* LPTIM4 clock source config set later after clock selection check */
1396 break;
1397
1398 case RCC_LPTIM4CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM4 clock*/
1399 /* LPTIM4 clock source config set later after clock selection check */
1400 break;
1401
1402 case RCC_LPTIM4CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM4 clock*/
1403 /* LPTIM4 clock source config set later after clock selection check */
1404 break;
1405
1406 default:
1407 ret = HAL_ERROR;
1408 break;
1409 }
1410
1411 if (ret == HAL_OK)
1412 {
1413 /* Set the source of LPTIM4 clock*/
1414 __HAL_RCC_LPTIM4_CONFIG(pPeriphClkInit->Lptim4ClockSelection);
1415 }
1416 else
1417 {
1418 /* set overall return value */
1419 status = ret;
1420 }
1421 }
1422 #endif /* LPTIM4 */
1423
1424 #if defined(LPTIM5)
1425 /*-------------------------- LPTIM5 clock source configuration ---------------------*/
1426 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM5) == RCC_PERIPHCLK_LPTIM5)
1427 {
1428 /* Check the parameters */
1429 assert_param(IS_RCC_LPTIM5CLK(pPeriphClkInit->Lptim5ClockSelection));
1430
1431 switch (pPeriphClkInit->Lptim5ClockSelection)
1432 {
1433 case RCC_LPTIM5CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM5*/
1434
1435 /* LPTIM5 clock source config set later after clock selection check */
1436 break;
1437
1438 case RCC_LPTIM5CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM5*/
1439 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1440 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1441 /* LPTIM5 clock source config set later after clock selection check */
1442 break;
1443
1444 case RCC_LPTIM5CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM5*/
1445 /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1446 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1447 /* LPTIM5 clock source config set later after clock selection check */
1448 break;
1449
1450 case RCC_LPTIM5CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM5 clock*/
1451 /* LPTIM5 clock source config set later after clock selection check */
1452 break;
1453
1454 case RCC_LPTIM5CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM5 clock*/
1455 /* LPTIM5 clock source config set later after clock selection check */
1456 break;
1457
1458 case RCC_LPTIM5CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM5 clock*/
1459 /* LPTIM5 clock source config set later after clock selection check */
1460 break;
1461
1462 default:
1463 ret = HAL_ERROR;
1464 break;
1465 }
1466
1467 if (ret == HAL_OK)
1468 {
1469 /* Set the source of LPTIM5 clock*/
1470 __HAL_RCC_LPTIM5_CONFIG(pPeriphClkInit->Lptim5ClockSelection);
1471 }
1472 else
1473 {
1474 /* set overall return value */
1475 status = ret;
1476 }
1477 }
1478 #endif /* LPTIM5 */
1479
1480 #if defined(LPTIM6)
1481 /*-------------------------- LPTIM6 clock source configuration ---------------------*/
1482 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM6) == RCC_PERIPHCLK_LPTIM6)
1483 {
1484 /* Check the parameters */
1485 assert_param(IS_RCC_LPTIM6CLK(pPeriphClkInit->Lptim6ClockSelection));
1486
1487 switch (pPeriphClkInit->Lptim6ClockSelection)
1488 {
1489 case RCC_LPTIM6CLKSOURCE_PCLK3: /* PCLK3 is used as clock source for LPTIM6*/
1490
1491 /* LPTIM6 clock source config set later after clock selection check */
1492 break;
1493
1494 case RCC_LPTIM6CLKSOURCE_PLL2P: /* PLL2 is used as clock source for LPTIM6*/
1495 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1496 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1497 /* LPTIM6 clock source config set later after clock selection check */
1498 break;
1499
1500 case RCC_LPTIM6CLKSOURCE_PLL3R: /* PLL3 is used as clock source for LPTIM6*/
1501 /* PLL3 R input clock, parameters M, N & R configuration clock output (PLL3ClockOut) */
1502 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1503 /* LPTIM6 clock source config set later after clock selection check */
1504 break;
1505
1506 case RCC_LPTIM6CLKSOURCE_LSE: /* LSE clock is used as source of LPTIM6 clock*/
1507 /* LPTIM6 clock source config set later after clock selection check */
1508 break;
1509
1510 case RCC_LPTIM6CLKSOURCE_LSI: /* LSI clock is used as source of LPTIM6 clock*/
1511 /* LPTIM6 clock source config set later after clock selection check */
1512 break;
1513
1514 case RCC_LPTIM6CLKSOURCE_CLKP: /* CLKP is used as source of LPTIM6 clock*/
1515 /* LPTIM6 clock source config set later after clock selection check */
1516 break;
1517
1518 default:
1519 ret = HAL_ERROR;
1520 break;
1521 }
1522
1523 if (ret == HAL_OK)
1524 {
1525 /* Set the source of LPTIM6 clock*/
1526 __HAL_RCC_LPTIM6_CONFIG(pPeriphClkInit->Lptim6ClockSelection);
1527 }
1528 else
1529 {
1530 /* set overall return value */
1531 status = ret;
1532 }
1533 }
1534 #endif /* LPTIM6 */
1535
1536 #if defined(SAI1)
1537 /*-------------------------- SAI1 clock source configuration ---------------------*/
1538 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
1539 {
1540 /* Check the parameters */
1541 assert_param(IS_RCC_SAI1CLK(pPeriphClkInit->Sai1ClockSelection));
1542
1543 switch (pPeriphClkInit->Sai1ClockSelection)
1544 {
1545 case RCC_SAI1CLKSOURCE_PLL1Q: /* PLL is used as clock source for SAI1*/
1546 /* Enable SAI Clock output generated from System PLL . */
1547 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1548 /* SAI1 clock source config set later after clock selection check */
1549 break;
1550
1551 case RCC_SAI1CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SAI1*/
1552 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1553 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1554 /* SAI1 clock source config set later after clock selection check */
1555 break;
1556
1557 case RCC_SAI1CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SAI1*/
1558 /* PLL3 P input clock, parameters M, N & P configuration clock output (PLL3ClockOut) */
1559 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1560 /* SAI1 clock source config set later after clock selection check */
1561 break;
1562
1563 case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/
1564 break;
1565
1566 case RCC_SAI1CLKSOURCE_CLKP: /* CLKP is used as source of SAI1 clock*/
1567 /* SAI1 clock source config set later after clock selection check */
1568 break;
1569
1570 default:
1571 ret = HAL_ERROR;
1572 break;
1573 }
1574
1575 if (ret == HAL_OK)
1576 {
1577 /* Set the source of SAI1 clock*/
1578 __HAL_RCC_SAI1_CONFIG(pPeriphClkInit->Sai1ClockSelection);
1579 }
1580 else
1581 {
1582 /* set overall return value */
1583 status = ret;
1584 }
1585 }
1586 #endif /* SAI1*/
1587
1588 #if defined(SAI2)
1589 /*-------------------------- SAI2 clock source configuration ---------------------*/
1590 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2)
1591 {
1592 /* Check the parameters */
1593 assert_param(IS_RCC_SAI2CLK(pPeriphClkInit->Sai2ClockSelection));
1594
1595 switch (pPeriphClkInit->Sai2ClockSelection)
1596 {
1597 case RCC_SAI2CLKSOURCE_PLL1Q: /* PLL is used as clock source for SAI2*/
1598 /* Enable SAI Clock output generated from System PLL . */
1599 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1600 /* SAI2 clock source config set later after clock selection check */
1601 break;
1602
1603 case RCC_SAI2CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SAI2*/
1604 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1605 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1606 /* SAI2 clock source config set later after clock selection check */
1607 break;
1608
1609 case RCC_SAI2CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SAI2*/
1610 /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
1611 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1612 /* SAI2 clock source config set later after clock selection check */
1613 break;
1614
1615 case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/
1616 case RCC_SAI2CLKSOURCE_CLKP: /* CLKP is used as source of SAI2 clock*/
1617 /* SAI2 clock source config set later after clock selection check */
1618 break;
1619
1620 default:
1621 ret = HAL_ERROR;
1622 break;
1623 }
1624
1625 if (ret == HAL_OK)
1626 {
1627 /* Set the source of SAI2 clock*/
1628 __HAL_RCC_SAI2_CONFIG(pPeriphClkInit->Sai2ClockSelection);
1629 }
1630 else
1631 {
1632 /* set overall return value */
1633 status = ret;
1634 }
1635 }
1636 #endif /* SAI2*/
1637
1638 /*-------------------------- ADCDAC clock source configuration ----------------------*/
1639 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADCDAC) == RCC_PERIPHCLK_ADCDAC)
1640 {
1641 /* Check the parameters */
1642 assert_param(IS_RCC_ADCDACCLKSOURCE(pPeriphClkInit->AdcDacClockSelection));
1643
1644 switch (pPeriphClkInit->AdcDacClockSelection)
1645 {
1646
1647 case RCC_ADCDACCLKSOURCE_HCLK: /* Bus clock is used as source of ADCDAC clock*/
1648 case RCC_ADCDACCLKSOURCE_SYSCLK: /* System clock is used as source of ADCDAC clock*/
1649 /* ADCDAC clock source config set later after clock selection check */
1650 break;
1651
1652 case RCC_ADCDACCLKSOURCE_PLL2R:
1653 /* PLL2 input clock, parameters M, N & R configuration and clock output (PLL2ClockOut) */
1654 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1655 break;
1656
1657 case RCC_ADCDACCLKSOURCE_HSE:/* HSE clock is used as source of ADCDAC clock*/
1658 case RCC_ADCDACCLKSOURCE_HSI:/* HSI clock is used as source of ADCDAC clock*/
1659 case RCC_ADCDACCLKSOURCE_CSI:/* CSI clock is used as source of ADCDAC clock*/
1660 /* ADCDAC clock source configuration done later after clock selection check */
1661 break;
1662
1663
1664 default:
1665 ret = HAL_ERROR;
1666 break;
1667 }
1668
1669 if (ret == HAL_OK)
1670 {
1671 /* Configure the ADCDAC interface clock source */
1672 __HAL_RCC_ADCDAC_CONFIG(pPeriphClkInit->AdcDacClockSelection);
1673 }
1674 else
1675 {
1676 /* set overall return value */
1677 status = ret;
1678 }
1679
1680 }
1681
1682 /*-------------------------- DAC low-power clock source configuration ----------------------*/
1683 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DAC_LP) == RCC_PERIPHCLK_DAC_LP)
1684 {
1685 /* Check the parameters */
1686 assert_param(IS_RCC_DACLPCLKSOURCE(pPeriphClkInit->DacLowPowerClockSelection));
1687
1688 switch (pPeriphClkInit->DacLowPowerClockSelection)
1689 {
1690
1691 case RCC_DACLPCLKSOURCE_LSE:
1692 /* LSE oscillator is used as source of DAC low-power clock */
1693 /* DAC clock source configuration done later after clock selection check */
1694 break;
1695
1696 case RCC_DACLPCLKSOURCE_LSI:
1697 /* LSI is used as clock source for DAC low-power clock */
1698 /* DAC clock source configuration done later after clock selection check */
1699 break;
1700
1701 default:
1702 ret = HAL_ERROR;
1703 break;
1704 }
1705
1706 if (ret == HAL_OK)
1707 {
1708 /* Configure the DAC low-power interface clock source */
1709 __HAL_RCC_DAC_LP_CONFIG(pPeriphClkInit->DacLowPowerClockSelection);
1710 }
1711 else
1712 {
1713 /* set overall return value */
1714 status = ret;
1715 }
1716
1717 }
1718
1719 /*-------------------------- RTC clock source configuration ----------------------*/
1720 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
1721 {
1722
1723 /* Check for RTC Parameters used to output RTCCLK */
1724 assert_param(IS_RCC_RTCCLKSOURCE(pPeriphClkInit->RTCClockSelection));
1725
1726 /* Enable write access to Backup domain */
1727 SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP);
1728
1729 /* Wait for Backup domain Write protection disable */
1730 tickstart = HAL_GetTick();
1731
1732 while (HAL_IS_BIT_CLR(PWR->DBPCR, PWR_DBPCR_DBP))
1733 {
1734 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
1735 {
1736 ret = HAL_TIMEOUT;
1737 break;
1738 }
1739 }
1740
1741 if (ret == HAL_OK)
1742 {
1743 /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
1744 tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
1745
1746 if ((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != pPeriphClkInit->RTCClockSelection))
1747 {
1748 /* Store the content of BDCR register before the reset of Backup Domain */
1749 tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
1750 /* RTC Clock selection can be changed only if the Backup Domain is reset */
1751 __HAL_RCC_BACKUPRESET_FORCE();
1752 __HAL_RCC_BACKUPRESET_RELEASE();
1753 /* Restore the Content of BDCR register */
1754 RCC->BDCR = tmpregister;
1755 }
1756
1757 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
1758 if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
1759 {
1760 /* Get Start Tick*/
1761 tickstart = HAL_GetTick();
1762
1763 /* Wait till LSE is ready */
1764 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
1765 {
1766 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
1767 {
1768 ret = HAL_TIMEOUT;
1769 break;
1770 }
1771 }
1772 }
1773
1774 if (ret == HAL_OK)
1775 {
1776 /* Apply new RTC clock source selection */
1777 __HAL_RCC_RTC_CONFIG(pPeriphClkInit->RTCClockSelection);
1778 }
1779 else
1780 {
1781 /* set overall return value */
1782 status = ret;
1783 }
1784 }
1785 else
1786 {
1787 /* set overall return value */
1788 status = ret;
1789 }
1790
1791 }
1792
1793 /*------------------------------ RNG Configuration -------------------------*/
1794 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
1795 {
1796
1797 /* Check the parameters */
1798 assert_param(IS_RCC_RNGCLKSOURCE(pPeriphClkInit->RngClockSelection));
1799
1800 switch (pPeriphClkInit->RngClockSelection)
1801 {
1802
1803 case RCC_RNGCLKSOURCE_HSI48: /* HSI48 is used as clock source for RNG*/
1804
1805 /* RNG clock source configuration done later after clock selection check */
1806 break;
1807
1808 case RCC_RNGCLKSOURCE_PLL1Q: /* PLL1 is used as clock source for RNG*/
1809 /* Enable PLL1Q Clock output generated from System PLL . */
1810 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1811 /* RNG clock source configuration done later after clock selection check */
1812 break;
1813 case RCC_RNGCLKSOURCE_LSE:
1814 /* LSE oscillator is used as source of RNG clock */
1815 /* RNG clock source configuration done later after clock selection check */
1816 break;
1817
1818 case RCC_RNGCLKSOURCE_LSI: /* HSI48 is used as clock source for RNG*/
1819
1820 /* RNG clock source configuration done later after clock selection check */
1821 break;
1822
1823 default:
1824 ret = HAL_ERROR;
1825 break;
1826 }
1827
1828 if (ret == HAL_OK)
1829 {
1830 /* Set the source of RNG clock*/
1831 __HAL_RCC_RNG_CONFIG(pPeriphClkInit->RngClockSelection);
1832 }
1833 else
1834 {
1835 /* set overall return value */
1836 status = ret;
1837 }
1838
1839 }
1840
1841 #if defined(SDMMC1)
1842 /*-------------------------- SDMMC1 clock source configuration -------------------*/
1843 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
1844 {
1845
1846 /* Check the parameters */
1847 assert_param(IS_RCC_SDMMC1CLKSOURCE(pPeriphClkInit->Sdmmc1ClockSelection));
1848
1849 switch (pPeriphClkInit->Sdmmc1ClockSelection)
1850 {
1851 case RCC_SDMMC1CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SDMMC1 kernel clock*/
1852 /* Enable PLL1Q Clock output generated from System PLL . */
1853 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1854 /* SDMMC1 kernel clock source config set later after clock selection check */
1855 break;
1856
1857 case RCC_SDMMC1CLKSOURCE_PLL2R: /* PLL2 is used as clock source for SDMMC1 kernel clock*/
1858 /* PLL2R input clock, parameters M, N & R configuration and clock output (PLL2ClockOut) */
1859 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1860 /* SDMMC1 kernel clock source config set later after clock selection check */
1861 break;
1862
1863 default:
1864 ret = HAL_ERROR;
1865 break;
1866 }
1867
1868 if (ret == HAL_OK)
1869 {
1870 /* Configure the SDMMC1 clock source */
1871 __HAL_RCC_SDMMC1_CONFIG(pPeriphClkInit->Sdmmc1ClockSelection);
1872 }
1873 else
1874 {
1875 /* set overall return value */
1876 status = ret;
1877 }
1878
1879 }
1880 #endif /* SDMMC1 */
1881
1882 #if defined(SDMMC2)
1883 /*-------------------------- SDMMC2 clock source configuration -------------------*/
1884 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
1885 {
1886
1887 /* Check the parameters */
1888 assert_param(IS_RCC_SDMMC2CLKSOURCE(pPeriphClkInit->Sdmmc2ClockSelection));
1889
1890 switch (pPeriphClkInit->Sdmmc2ClockSelection)
1891 {
1892 case RCC_SDMMC2CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SDMMC2 kernel clock*/
1893 /* Enable PLL1Q Clock output generated from System PLL . */
1894 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1895 /* SDMMC2 kernel clock source config set later after clock selection check */
1896 break;
1897
1898 case RCC_SDMMC2CLKSOURCE_PLL2R: /* PLL2 is used as clock source for SDMMC2 kernel clock*/
1899 /* PLL2R input clock, parameters M, N & R configuration and clock output (PLL2ClockOut) */
1900 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1901 /* SDMMC2 kernel clock source config set later after clock selection check */
1902 break;
1903
1904 default:
1905 ret = HAL_ERROR;
1906 break;
1907 }
1908
1909 if (ret == HAL_OK)
1910 {
1911 /* Configure the SDMMC2 clock source */
1912 __HAL_RCC_SDMMC2_CONFIG(pPeriphClkInit->Sdmmc2ClockSelection);
1913 }
1914 else
1915 {
1916 /* set overall return value */
1917 status = ret;
1918 }
1919
1920 }
1921 #endif /* SDMMC2 */
1922
1923 /*-------------------------- SPI1 clock source configuration ----------------*/
1924 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1)
1925 {
1926
1927 /* Check the parameters */
1928 assert_param(IS_RCC_SPI1CLKSOURCE(pPeriphClkInit->Spi1ClockSelection));
1929
1930 switch (pPeriphClkInit->Spi1ClockSelection)
1931 {
1932 case RCC_SPI1CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SPI1 */
1933 /* Enable SPI Clock output generated from System PLL . */
1934 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1935
1936 /* SPI1 clock source configuration done later after clock selection check */
1937 break;
1938
1939 case RCC_SPI1CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SPI1*/
1940 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1941 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1942
1943 /* SPI1 clock source configuration done later after clock selection check */
1944 break;
1945
1946 #if defined(RCC_SPI1CLKSOURCE_PLL3P)
1947 case RCC_SPI1CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SPI1 */
1948 /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
1949 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1950
1951 /* SPI1 clock source configuration done later after clock selection check */
1952 break;
1953 #endif /* RCC_SPI1CLKSOURCE_PLL3P */
1954
1955 case RCC_SPI1CLKSOURCE_PIN:
1956 /* External clock is used as source of SPI1 clock*/
1957 /* SPI1 clock source configuration done later after clock selection check */
1958 break;
1959
1960 case RCC_SPI1CLKSOURCE_CLKP:
1961 /* HSI, HSE, or CSI oscillator is used as source of SPI1 clock */
1962 /* SPI1 clock source configuration done later after clock selection check */
1963 break;
1964
1965 default:
1966 ret = HAL_ERROR;
1967 break;
1968 }
1969
1970 if (ret == HAL_OK)
1971 {
1972 /* Configure the SPI1 clock source */
1973 __HAL_RCC_SPI1_CONFIG(pPeriphClkInit->Spi1ClockSelection);
1974 }
1975 else
1976 {
1977 /* set overall return value */
1978 status = ret;
1979 }
1980
1981 }
1982
1983 /*-------------------------- SPI2 clock source configuration ----------------*/
1984 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI2) == RCC_PERIPHCLK_SPI2)
1985 {
1986
1987 /* Check the parameters */
1988 assert_param(IS_RCC_SPI2CLKSOURCE(pPeriphClkInit->Spi2ClockSelection));
1989
1990 switch (pPeriphClkInit->Spi2ClockSelection)
1991 {
1992 case RCC_SPI2CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SPI2 */
1993 /* Enable SPI Clock output generated from System PLL . */
1994 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
1995
1996 /* SPI2 clock source configuration done later after clock selection check */
1997 break;
1998
1999 case RCC_SPI2CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SPI2*/
2000 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
2001 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2002
2003 /* SPI2 clock source configuration done later after clock selection check */
2004 break;
2005
2006 #if defined(RCC_SPI2CLKSOURCE_PLL3P)
2007 case RCC_SPI2CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SPI2 */
2008 /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
2009 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
2010
2011 /* SPI2 clock source configuration done later after clock selection check */
2012 break;
2013 #endif /* RCC_SPI2CLKSOURCE_PLL3P */
2014
2015 case RCC_SPI2CLKSOURCE_PIN:
2016 /* External clock is used as source of SPI2 clock*/
2017 /* SPI2 clock source configuration done later after clock selection check */
2018 break;
2019
2020 case RCC_SPI2CLKSOURCE_CLKP:
2021 /* HSI, HSE, or CSI oscillator is used as source of SPI2 clock */
2022 /* SPI2 clock source configuration done later after clock selection check */
2023 break;
2024
2025 default:
2026 ret = HAL_ERROR;
2027 break;
2028 }
2029
2030 if (ret == HAL_OK)
2031 {
2032 /* Configure the SPI2 clock source */
2033 __HAL_RCC_SPI2_CONFIG(pPeriphClkInit->Spi2ClockSelection);
2034 }
2035 else
2036 {
2037 /* set overall return value */
2038 status = ret;
2039 }
2040
2041 }
2042
2043 /*-------------------------- SPI3 clock source configuration ----------------*/
2044 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3)
2045 {
2046
2047 /* Check the parameters */
2048 assert_param(IS_RCC_SPI3CLKSOURCE(pPeriphClkInit->Spi3ClockSelection));
2049
2050 switch (pPeriphClkInit->Spi3ClockSelection)
2051 {
2052 case RCC_SPI3CLKSOURCE_PLL1Q: /* PLL1 is used as clock source for SPI3 */
2053 /* Enable SPI Clock output generated from System PLL . */
2054 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
2055
2056 /* SPI3 clock source configuration done later after clock selection check */
2057 break;
2058
2059 case RCC_SPI3CLKSOURCE_PLL2P: /* PLL2 is used as clock source for SPI3*/
2060 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
2061 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2062
2063 /* SPI3 clock source configuration done later after clock selection check */
2064 break;
2065
2066 #if defined(RCC_SPI3CLKSOURCE_PLL3P)
2067 case RCC_SPI3CLKSOURCE_PLL3P: /* PLL3 is used as clock source for SPI3 */
2068 /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
2069 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
2070
2071 /* SPI3 clock source configuration done later after clock selection check */
2072 break;
2073 #endif /* RCC_SPI3CLKSOURCE_PLL3P */
2074
2075 case RCC_SPI3CLKSOURCE_PIN:
2076 /* External clock is used as source of SPI3 clock*/
2077 /* SPI3 clock source configuration done later after clock selection check */
2078 break;
2079
2080 case RCC_SPI3CLKSOURCE_CLKP:
2081 /* HSI, HSE, or CSI oscillator is used as source of SPI3 clock */
2082 /* SPI3 clock source configuration done later after clock selection check */
2083 break;
2084
2085 default:
2086 ret = HAL_ERROR;
2087 break;
2088 }
2089
2090 if (ret == HAL_OK)
2091 {
2092 /* Configure the SPI3 clock source */
2093 __HAL_RCC_SPI3_CONFIG(pPeriphClkInit->Spi3ClockSelection);
2094 }
2095 else
2096 {
2097 /* set overall return value */
2098 status = ret;
2099 }
2100
2101 }
2102
2103 #if defined(SPI4)
2104 /*-------------------------- SPI4 clock source configuration ----------------*/
2105 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI4) == RCC_PERIPHCLK_SPI4)
2106 {
2107
2108 /* Check the parameters */
2109 assert_param(IS_RCC_SPI4CLKSOURCE(pPeriphClkInit->Spi4ClockSelection));
2110
2111 switch (pPeriphClkInit->Spi4ClockSelection)
2112 {
2113 case RCC_SPI4CLKSOURCE_PCLK2: /* PCLK2 (APB2 Clock) is used as clock source for SPI4 */
2114 /* SPI4 clock source configuration done later after clock selection check */
2115 break;
2116
2117 case RCC_SPI4CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for SPI4*/
2118 /* PLL2 Q input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
2119 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2120
2121 /* SPI4 clock source configuration done later after clock selection check */
2122 break;
2123
2124 case RCC_SPI4CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for SPI4 */
2125 /* PLL3 Q input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
2126 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
2127
2128 /* SPI4 clock source configuration done later after clock selection check */
2129 break;
2130
2131 case RCC_SPI4CLKSOURCE_HSI:
2132 /* HSI oscillator is used as source of SPI4 clock*/
2133 /* SPI4 clock source configuration done later after clock selection check */
2134 break;
2135
2136 case RCC_SPI4CLKSOURCE_CSI:
2137 /* CSI oscillator is used as source of SPI4 clock */
2138 /* SPI4 clock source configuration done later after clock selection check */
2139 break;
2140
2141 case RCC_SPI4CLKSOURCE_HSE:
2142 /* HSE oscillator is used as source of SPI4 clock */
2143 /* SPI4 clock source configuration done later after clock selection check */
2144 break;
2145
2146 default:
2147 ret = HAL_ERROR;
2148 break;
2149 }
2150
2151 if (ret == HAL_OK)
2152 {
2153 /* Configure the SPI4 clock source */
2154 __HAL_RCC_SPI4_CONFIG(pPeriphClkInit->Spi4ClockSelection);
2155 }
2156 else
2157 {
2158 /* set overall return value */
2159 status = ret;
2160 }
2161
2162 }
2163 #endif /* SPI4 */
2164
2165 #if defined(SPI5)
2166 /*-------------------------- SPI5 clock source configuration ----------------*/
2167 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI5) == RCC_PERIPHCLK_SPI5)
2168 {
2169
2170 /* Check the parameters */
2171 assert_param(IS_RCC_SPI5CLKSOURCE(pPeriphClkInit->Spi5ClockSelection));
2172
2173 switch (pPeriphClkInit->Spi5ClockSelection)
2174 {
2175 case RCC_SPI5CLKSOURCE_PCLK3: /* PCLK3 (APB3 Clock) is used as clock source for SPI5 */
2176 /* SPI5 clock source configuration done later after clock selection check */
2177 break;
2178
2179 case RCC_SPI5CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for SPI5*/
2180 /* PLL2 Q input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
2181 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2182
2183 /* SPI5 clock source configuration done later after clock selection check */
2184 break;
2185
2186 case RCC_SPI5CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for SPI5 */
2187 /* PLL3 Q input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
2188 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
2189
2190 /* SPI5 clock source configuration done later after clock selection check */
2191 break;
2192
2193 case RCC_SPI5CLKSOURCE_HSI:
2194 /* HSI oscillator is used as source of SPI5 clock*/
2195 /* SPI5 clock source configuration done later after clock selection check */
2196 break;
2197
2198 case RCC_SPI5CLKSOURCE_CSI:
2199 /* CSI oscillator is used as source of SPI5 clock */
2200 /* SPI5 clock source configuration done later after clock selection check */
2201 break;
2202
2203 case RCC_SPI5CLKSOURCE_HSE:
2204 /* HSE oscillator is used as source of SPI5 clock */
2205 /* SPI5 clock source configuration done later after clock selection check */
2206 break;
2207
2208 default:
2209 ret = HAL_ERROR;
2210 break;
2211 }
2212
2213 if (ret == HAL_OK)
2214 {
2215 /* Configure the SPI5 clock source */
2216 __HAL_RCC_SPI5_CONFIG(pPeriphClkInit->Spi5ClockSelection);
2217 }
2218 else
2219 {
2220 /* set overall return value */
2221 status = ret;
2222 }
2223
2224 }
2225 #endif /* SPI5 */
2226
2227 #if defined(SPI6)
2228 /*-------------------------- SPI6 clock source configuration ----------------*/
2229 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
2230 {
2231
2232 /* Check the parameters */
2233 assert_param(IS_RCC_SPI6CLKSOURCE(pPeriphClkInit->Spi6ClockSelection));
2234
2235 switch (pPeriphClkInit->Spi6ClockSelection)
2236 {
2237 case RCC_SPI6CLKSOURCE_PCLK2: /* PCLK2 (APB2 Clock) is used as clock source for SPI6 */
2238 /* SPI6 clock source configuration done later after clock selection check */
2239 break;
2240
2241 case RCC_SPI6CLKSOURCE_PLL2Q: /* PLL2 is used as clock source for SPI6*/
2242 /* PLL2 Q input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
2243 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2244
2245 /* SPI6 clock source configuration done later after clock selection check */
2246 break;
2247
2248 case RCC_SPI6CLKSOURCE_PLL3Q: /* PLL3 is used as clock source for SPI6 */
2249 /* PLL3 Q input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
2250 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
2251
2252 /* SPI6 clock source configuration done later after clock selection check */
2253 break;
2254
2255 case RCC_SPI6CLKSOURCE_HSI:
2256 /* HSI oscillator is used as source of SPI6 clock*/
2257 /* SPI6 clock source configuration done later after clock selection check */
2258 break;
2259
2260 case RCC_SPI6CLKSOURCE_CSI:
2261 /* CSI oscillator is used as source of SPI6 clock */
2262 /* SPI6 clock source configuration done later after clock selection check */
2263 break;
2264
2265 case RCC_SPI6CLKSOURCE_HSE:
2266 /* HSE oscillator is used as source of SPI6 clock */
2267 /* SPI6 clock source configuration done later after clock selection check */
2268 break;
2269
2270 default:
2271 ret = HAL_ERROR;
2272 break;
2273 }
2274
2275 if (ret == HAL_OK)
2276 {
2277 /* Configure the SPI6 clock source */
2278 __HAL_RCC_SPI6_CONFIG(pPeriphClkInit->Spi6ClockSelection);
2279 }
2280 else
2281 {
2282 /* set overall return value */
2283 status = ret;
2284 }
2285
2286 }
2287 #endif /* SPI6 */
2288
2289 #if defined(OCTOSPI1)
2290 /*-------------------------- OctoSPIx clock source configuration ----------------*/
2291 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
2292 {
2293 /* Check the parameters */
2294 assert_param(IS_RCC_OSPICLKSOURCE(pPeriphClkInit->OspiClockSelection));
2295
2296 switch (pPeriphClkInit->OspiClockSelection)
2297 {
2298 case RCC_OSPICLKSOURCE_HCLK: /* HCLK is used as clock source for OCTOSPI */
2299
2300 /* OCTOSPI clock source config set later after clock selection check */
2301 break;
2302
2303 case RCC_OSPICLKSOURCE_PLL1Q: /* PLL1 Q is used as clock source for OCTOSPI*/
2304
2305 /* Enable PLL1 Q CLK output */
2306 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
2307 break;
2308
2309 case RCC_OSPICLKSOURCE_PLL2R: /* PLL2 is used as clock source for OCTOSPI*/
2310 /* PLL2 R input clock, parameters M, N & R configuration and clock output (PLL2ClockOut) */
2311 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2312 /* OCTOSPI clock source config set later after clock selection check */
2313 break;
2314
2315 case RCC_OSPICLKSOURCE_CLKP: /* CLKP is used as source of OCTOSPI clock*/
2316 /* OCTOSPI clock source config set later after clock selection check */
2317 break;
2318
2319 default:
2320 ret = HAL_ERROR;
2321 break;
2322 }
2323
2324 if (ret == HAL_OK)
2325 {
2326 /* Configure the OctoSPI clock source */
2327 __HAL_RCC_OSPI_CONFIG(pPeriphClkInit->OspiClockSelection);
2328 }
2329 else
2330 {
2331 /* set overall return value */
2332 status = ret;
2333 }
2334 }
2335 #endif /* OCTOSPI1*/
2336
2337 /*-------------------------- FDCAN kernel clock source configuration -------------*/
2338 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
2339 {
2340 assert_param(IS_RCC_FDCANCLK(pPeriphClkInit->FdcanClockSelection));
2341
2342 switch (pPeriphClkInit->FdcanClockSelection)
2343 {
2344 case RCC_FDCANCLKSOURCE_HSE: /* HSE is used as source of FDCAN kernel clock*/
2345 /* FDCAN kernel clock source config set later after clock selection check */
2346 break;
2347
2348 case RCC_FDCANCLKSOURCE_PLL1Q: /* PLL1 is used as clock source for FDCAN kernel clock*/
2349 /* Enable PLL1Q Clock output generated from System PLL . */
2350 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
2351 /* FDCAN kernel clock source config set later after clock selection check */
2352 break;
2353
2354 case RCC_FDCANCLKSOURCE_PLL2Q: /* PLL2 is used as clock source for FDCAN kernel clock*/
2355 /* PLL2Q input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
2356 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2357 /* FDCAN kernel clock source config set later after clock selection check */
2358 break;
2359
2360 default:
2361 ret = HAL_ERROR;
2362 break;
2363 }
2364
2365 if (ret == HAL_OK)
2366 {
2367 /* Set the source of FDCAN kernel clock*/
2368 __HAL_RCC_FDCAN_CONFIG(pPeriphClkInit->FdcanClockSelection);
2369 }
2370 else
2371 {
2372 /* set overall return value */
2373 status = ret;
2374 }
2375 }
2376
2377 /*------------------------------ USB Configuration -------------------------*/
2378 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
2379 {
2380
2381 /* Check the parameters */
2382 assert_param(IS_RCC_USBCLKSOURCE(pPeriphClkInit->UsbClockSelection));
2383
2384 switch (pPeriphClkInit->UsbClockSelection)
2385 {
2386 case RCC_USBCLKSOURCE_PLL1Q: /* PLL is used as clock source for USB*/
2387 /* Enable USB Clock output generated form System USB . */
2388 __HAL_RCC_PLL1_CLKOUT_ENABLE(RCC_PLL1_DIVQ);
2389
2390 /* USB clock source configuration done later after clock selection check */
2391 break;
2392
2393 #if defined(RCC_USBCLKSOURCE_PLL3Q)
2394 case RCC_USBCLKSOURCE_PLL3Q: /* PLL3 is used as clock source for USB*/
2395 /* PLL3Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */
2396 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
2397 #else
2398 case RCC_USBCLKSOURCE_PLL2Q: /* PLL2 is used as clock source for USB*/
2399 /* PLL2Q input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
2400 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
2401 #endif /* RCC_USBCLKSOURCE_PLL3Q */
2402 /* USB clock source configuration done later after clock selection check */
2403 break;
2404
2405 case RCC_USBCLKSOURCE_HSI48:
2406 /* HSI48 oscillator is used as source of USB clock */
2407 /* USB clock source configuration done later after clock selection check */
2408 break;
2409
2410 default:
2411 ret = HAL_ERROR;
2412 break;
2413 }
2414
2415 if (ret == HAL_OK)
2416 {
2417 /* Set the source of USB clock*/
2418 __HAL_RCC_USB_CONFIG(pPeriphClkInit->UsbClockSelection);
2419 }
2420 else
2421 {
2422 /* set overall return value */
2423 status = ret;
2424 }
2425
2426 }
2427
2428 #if defined(CEC)
2429 /*-------------------------- CEC clock source configuration ----------------*/
2430 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
2431 {
2432
2433 /* Check the parameters */
2434 assert_param(IS_RCC_CECCLKSOURCE(pPeriphClkInit->CecClockSelection));
2435
2436 /* Configure the CEC clock source */
2437 __HAL_RCC_CEC_CONFIG(pPeriphClkInit->CecClockSelection);
2438
2439 }
2440 #endif /* CEC */
2441
2442 return status;
2443 }
2444
2445
2446
2447 /**
2448 * @brief Get the pPeriphClkInit according to the internal RCC configuration registers.
2449 * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
2450 * returns the configuration information for the Extended Peripherals
2451 * clocks (ADC12, DAC, SDMMC1, SDMMC2, OCTOSPI1, TIM, LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPTIM6,
2452 * SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, USART1, USART2, USART3, UART4, UART5, USART6, UART7, UART8,
2453 * UART9, USART10, USART11, UART12, LPUART1, I2C1, I2C2, I2C3, I2C4, I3C1, I3C2, CEC, FDCAN, SAI1,
2454 * SAI2, USB,), PLL2 and PLL3.
2455 * @retval None
2456 */
HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef * pPeriphClkInit)2457 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
2458 {
2459 /* Set all possible values for the extended clock type parameter------------*/
2460 pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
2461 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
2462 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_ADCDAC | \
2463 RCC_PERIPHCLK_DAC_LP | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | \
2464 RCC_PERIPHCLK_I3C1 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \
2465 RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_CKPER | RCC_PERIPHCLK_USB;
2466
2467 #if defined(UART4)
2468 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART4;
2469 #endif /* UART4 */
2470 #if defined(UART5)
2471 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART5;
2472 #endif /* UART5 */
2473 #if defined(USART6)
2474 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART6;
2475 #endif /* UART6 */
2476 #if defined(UART7)
2477 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART7;
2478 #endif /* UART7 */
2479 #if defined(UART8)
2480 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART8;
2481 #endif /* UART8 */
2482 #if defined(UART9)
2483 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART9;
2484 #endif /* UART9 */
2485 #if defined(USART10)
2486 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART10;
2487 #endif /* UART10 */
2488 #if defined(USART11)
2489 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART11;
2490 #endif /* UART11 */
2491 #if defined(UART12)
2492 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_UART12;
2493 #endif /* UART12 */
2494 #if defined(I2C3)
2495 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3;
2496 #endif /* I2C3 */
2497 #if defined(I2C4)
2498 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C4;
2499 #endif /* I2C4 */
2500 #if defined(I3C2)
2501 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I3C2;
2502 #endif /* I3C2 */
2503 #if defined(LPTIM3)
2504 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM3;
2505 #endif /* LPTIM3 */
2506 #if defined(LPTIM4)
2507 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM4;
2508 #endif /* LPTIM4 */
2509 #if defined(LPTIM5)
2510 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM5;
2511 #endif /* LPTIM5 */
2512 #if defined(LPTIM6)
2513 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM6;
2514 #endif /* LPTIM6 */
2515 #if defined(SPI4)
2516 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SPI4;
2517 #endif /* SPI4 */
2518 #if defined(SPI5)
2519 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SPI5;
2520 #endif /* SPI5 */
2521 #if defined(SPI6)
2522 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SPI6;
2523 #endif /* SPI6 */
2524 #if defined(SAI1)
2525 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI1;
2526 #endif /* SAI1 */
2527 #if defined(SAI2)
2528 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2;
2529 #endif /* SAI2 */
2530 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_FDCAN;
2531 #if defined(SDMMC1)
2532 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDMMC1;
2533 #endif /* SDMMC1*/
2534 #if defined(SDMMC2)
2535 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDMMC2;
2536 #endif /* SDMMC2*/
2537 #if defined(OCTOSPI1)
2538 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI;
2539 #endif /* OCTOSPI1 */
2540 #if defined(CEC)
2541 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
2542 #endif /* CEC */
2543
2544 /* Get the PLL2 Clock configuration -----------------------------------------------*/
2545 pPeriphClkInit->PLL2.PLL2Source = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC) >> RCC_PLL2CFGR_PLL2SRC_Pos);
2546 pPeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos);
2547 pPeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N_Pos) + 1U;
2548 pPeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + 1U;
2549 pPeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1U;
2550 pPeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + 1U;
2551 pPeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2RGE) >> RCC_PLL2CFGR_PLL2RGE_Pos);
2552 pPeriphClkInit->PLL2.PLL2FRACN = (uint32_t)((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \
2553 RCC_PLL2FRACR_PLL2FRACN_Pos);
2554
2555 #if defined(RCC_CR_PLL3ON)
2556 /* Get the PLL3 Clock configuration -----------------------------------------------*/
2557 pPeriphClkInit->PLL3.PLL3Source = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC) >> RCC_PLL3CFGR_PLL3SRC_Pos);
2558 pPeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos);
2559 pPeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) >> RCC_PLL3DIVR_PLL3N_Pos) + 1U;
2560 pPeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + 1U;
2561 pPeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + 1U;
2562 pPeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + 1U;
2563 pPeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3RGE) >> RCC_PLL3CFGR_PLL3RGE_Pos);
2564 pPeriphClkInit->PLL3.PLL3FRACN = (uint32_t)((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \
2565 RCC_PLL3FRACR_PLL3FRACN_Pos);
2566 #endif /* RCC_CR_PLL3ON */
2567
2568 /* Get the USART1 clock source ---------------------------------------------*/
2569 pPeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
2570
2571 /* Get the USART2 clock source ---------------------------------------------*/
2572 pPeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
2573
2574 /* Get the USART3 clock source ---------------------------------------------*/
2575 pPeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
2576
2577 #if defined(UART4)
2578 /* Get the UART4 clock source ----------------------------------------------*/
2579 pPeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
2580 #endif /* UART4 */
2581
2582 #if defined(UART5)
2583 /* Get the UART5 clock source ----------------------------------------------*/
2584 pPeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
2585 #endif /* UART5 */
2586
2587 #if defined(USART6)
2588 /* Get the USART6 clock source ---------------------------------------------*/
2589 pPeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
2590 #endif /* USART6 */
2591
2592 #if defined(UART7)
2593 /* Get the UART7 clock source ---------------------------------------------*/
2594 pPeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();
2595 #endif /* UART7 */
2596
2597 #if defined(UART8)
2598 /* Get the UART8 clock source ---------------------------------------------*/
2599 pPeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();
2600 #endif /* UART8 */
2601
2602 #if defined(UART9)
2603 /* Get the UART9 clock source ---------------------------------------------*/
2604 pPeriphClkInit->Uart9ClockSelection = __HAL_RCC_GET_UART9_SOURCE();
2605 #endif /* UART9 */
2606
2607 #if defined(USART10)
2608 /* Get the USART10 clock source ---------------------------------------------*/
2609 pPeriphClkInit->Usart10ClockSelection = __HAL_RCC_GET_USART10_SOURCE();
2610 #endif /* USART10 */
2611
2612 #if defined(USART11)
2613 /* Get the USART11 clock source ---------------------------------------------*/
2614 pPeriphClkInit->Usart11ClockSelection = __HAL_RCC_GET_USART11_SOURCE();
2615 #endif /* USART11 */
2616
2617 #if defined(UART12)
2618 /* Get the UART12 clock source ---------------------------------------------*/
2619 pPeriphClkInit->Uart12ClockSelection = __HAL_RCC_GET_UART12_SOURCE();
2620 #endif /* UART12 */
2621
2622 /* Get the LPUART1 clock source --------------------------------------------*/
2623 pPeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
2624
2625 /* Get the I2C1 clock source -----------------------------------------------*/
2626 pPeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
2627
2628 /* Get the I2C2 clock source -----------------------------------------------*/
2629 pPeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
2630
2631 #if defined(I2C3)
2632 /* Get the I2C3 clock source -----------------------------------------------*/
2633 pPeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
2634 #endif /* I2C3 */
2635
2636 #if defined(I2C4)
2637 /* Get the I2C4 clock source -----------------------------------------------*/
2638 pPeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
2639 #endif /* I2C4 */
2640
2641 /* Get the I3C1 clock source -----------------------------------------------*/
2642 pPeriphClkInit->I3c1ClockSelection = __HAL_RCC_GET_I3C1_SOURCE();
2643
2644 #if defined(I3C2)
2645 /* Get the I3C2 clock source -----------------------------------------------*/
2646 pPeriphClkInit->I3c2ClockSelection = __HAL_RCC_GET_I3C2_SOURCE();
2647 #endif /* I3C2 */
2648
2649 /* Get the LPTIM1 clock source ---------------------------------------------*/
2650 pPeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
2651
2652 /* Get the LPTIM2 clock source ---------------------------------------------*/
2653 pPeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
2654
2655 #if defined(LPTIM3)
2656 /* Get the LPTIM3 clock source ---------------------------------------------*/
2657 pPeriphClkInit->Lptim3ClockSelection = __HAL_RCC_GET_LPTIM3_SOURCE();
2658 #endif /* LPTIM3 */
2659
2660 #if defined(LPTIM4)
2661 /* Get the LPTIM4 clock source ---------------------------------------------*/
2662 pPeriphClkInit->Lptim4ClockSelection = __HAL_RCC_GET_LPTIM4_SOURCE();
2663 #endif /* LPTIM4 */
2664
2665 #if defined(LPTIM5)
2666 /* Get the LPTIM5 clock source ---------------------------------------------*/
2667 pPeriphClkInit->Lptim5ClockSelection = __HAL_RCC_GET_LPTIM5_SOURCE();
2668 #endif /* LPTIM5 */
2669
2670 #if defined(LPTIM6)
2671 /* Get the LPTIM6 clock source ---------------------------------------------*/
2672 pPeriphClkInit->Lptim6ClockSelection = __HAL_RCC_GET_LPTIM6_SOURCE();
2673 #endif /* LPTIM6 */
2674
2675 /* Get the FDCAN clock source ---------------------------------------------*/
2676 pPeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE();
2677
2678 #if defined(SAI1)
2679 /* Get the SAI1 clock source -----------------------------------------------*/
2680 pPeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
2681 #endif /* SAI1 */
2682
2683 #if defined(SAI2)
2684 /* Get the SAI2 clock source -----------------------------------------------*/
2685 pPeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
2686 #endif /* SAI2 */
2687
2688 #if defined(SDMMC1)
2689 /* Get the SDMMC1 clock source ----------------------------------------------*/
2690 pPeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
2691 #endif /* SDMMC1 */
2692
2693 #if defined(SDMMC2)
2694 /* Get the SDMMC2 clock source ----------------------------------------------*/
2695 pPeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();
2696 #endif /* SDMMC2 */
2697
2698 /* Get the ADCDAC clock source ---------------------------------------------*/
2699 pPeriphClkInit->AdcDacClockSelection = __HAL_RCC_GET_ADCDAC_SOURCE();
2700
2701 /* Get the DAC low-power clock source ---------------------------------------------*/
2702 pPeriphClkInit->DacLowPowerClockSelection = __HAL_RCC_GET_DAC_LP_SOURCE();
2703
2704 #if defined(OCTOSPI1)
2705 /* Get the OSPI clock source -----------------------------------------------*/
2706 pPeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE();
2707 #endif /* OCTOSPI1 */
2708
2709 /* Get the SPI1 clock source -----------------------------------------------*/
2710 pPeriphClkInit->Spi1ClockSelection = __HAL_RCC_GET_SPI1_SOURCE();
2711
2712 /* Get the SPI2 clock source -----------------------------------------------*/
2713 pPeriphClkInit->Spi2ClockSelection = __HAL_RCC_GET_SPI2_SOURCE();
2714
2715 /* Get the SPI3 clock source -----------------------------------------------*/
2716 pPeriphClkInit->Spi3ClockSelection = __HAL_RCC_GET_SPI3_SOURCE();
2717
2718 #if defined(SPI4)
2719 /* Get the SPI4 clock source -----------------------------------------------*/
2720 pPeriphClkInit->Spi4ClockSelection = __HAL_RCC_GET_SPI4_SOURCE();
2721 #endif /* SPI4 */
2722
2723 #if defined(SPI5)
2724 /* Get the SPI5 clock source -----------------------------------------------*/
2725 pPeriphClkInit->Spi5ClockSelection = __HAL_RCC_GET_SPI5_SOURCE();
2726 #endif /* SPI5 */
2727
2728 #if defined(SPI6)
2729 /* Get the SPI6 clock source -----------------------------------------------*/
2730 pPeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE();
2731 #endif /* SPI6 */
2732
2733 /* Get the RTC clock source ------------------------------------------------*/
2734 pPeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
2735
2736 /* Get the RNG clock source ------------------------------------------------*/
2737 pPeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
2738
2739 /* Get the CKPER clock source ------------------------------------------------*/
2740 pPeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE();
2741
2742 #if defined(CEC)
2743 /* Get the CEC clock source ------------------------------------------------*/
2744 pPeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
2745 #endif /* CEC */
2746
2747 /* Get the USB clock source ------------------------------------------------*/
2748 pPeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
2749
2750 /* Get the TIM Prescaler configuration -------------------------------------*/
2751 if ((RCC->CFGR1 & RCC_CFGR1_TIMPRE) == 0U)
2752 {
2753 pPeriphClkInit->TimPresSelection = RCC_TIMPRES_DEACTIVATED;
2754 }
2755 else
2756 {
2757 pPeriphClkInit->TimPresSelection = RCC_TIMPRES_ACTIVATED;
2758 }
2759 }
2760
2761 /**
2762 * @brief Returns the PLL1 clock frequencies : PLL1_P_Frequency, PLL1_R_Frequency and PLL1_Q_Frequency
2763 * @note The PLL1 clock frequencies computed by this function may not be the real
2764 * frequency in the chip. It is calculated based on the predefined
2765 * constant and the selected clock source:
2766 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by
2767 the PLL factors.
2768 * @note This function can be used by the user application to compute the
2769 * baud-rate for the communication peripherals or configure other parameters.
2770 *
2771 * @note Each time PLL1CLK changes, this function must be called to update the
2772 * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
2773 * @param pPLL1_Clocks pointer to PLL1_ClocksTypeDef structure.
2774 * @retval None
2775 */
HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef * pPLL1_Clocks)2776 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *pPLL1_Clocks)
2777 {
2778 uint32_t pll1source;
2779 uint32_t pll1m;
2780 uint32_t pll1n;
2781 uint32_t pll1fracen;
2782 uint32_t hsivalue;
2783 float_t fracn1;
2784 float_t pll1vco;
2785
2786 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL1M) * PLL1N
2787 PLL1xCLK = PLL1_VCO / PLL1x
2788 */
2789
2790 pll1n = (RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N);
2791 pll1source = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
2792 pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos);
2793 pll1fracen = RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN;
2794 fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \
2795 RCC_PLL1FRACR_PLL1FRACN_Pos));
2796
2797 if (pll1m != 0U)
2798 {
2799 switch (pll1source)
2800 {
2801
2802 case RCC_PLL1_SOURCE_HSI: /* HSI used as PLL1 clock source */
2803 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
2804 pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)pll1n + (fracn1 / (float_t)0x2000) + \
2805 (float_t)1);
2806 break;
2807
2808 case RCC_PLL1_SOURCE_CSI: /* CSI used as PLL1 clock source */
2809 pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)pll1n + (fracn1 / (float_t)0x2000) + \
2810 (float_t)1);
2811 break;
2812
2813 case RCC_PLL1_SOURCE_HSE: /* HSE used as PLL1 clock source */
2814 pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)pll1n + (fracn1 / (float_t)0x2000) + \
2815 (float_t)1);
2816 break;
2817
2818 default:
2819 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
2820 pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)pll1n + (fracn1 / (float_t)0x2000) + \
2821 (float_t)1);
2822 break;
2823 }
2824
2825 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2826 {
2827 if (__HAL_RCC_GET_PLL1_CLKOUT_CONFIG(RCC_PLL1_DIVP) != 0U)
2828 {
2829 pPLL1_Clocks->PLL1_P_Frequency = \
2830 (uint32_t)(float_t)(pll1vco / \
2831 ((float_t)(uint32_t)((RCC->PLL1DIVR & \
2832 RCC_PLL1DIVR_PLL1P) >> \
2833 RCC_PLL1DIVR_PLL1P_Pos) + \
2834 (float_t)1));
2835 }
2836 else
2837 {
2838 pPLL1_Clocks->PLL1_P_Frequency = 0U;
2839 }
2840 }
2841 else
2842 {
2843 pPLL1_Clocks->PLL1_P_Frequency = 0U;
2844 }
2845
2846 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2847 {
2848 if (__HAL_RCC_GET_PLL1_CLKOUT_CONFIG(RCC_PLL1_DIVQ) != 0U)
2849 {
2850 pPLL1_Clocks->PLL1_Q_Frequency = \
2851 (uint32_t)(float_t)(pll1vco / \
2852 ((float_t)(uint32_t)((RCC->PLL1DIVR & \
2853 RCC_PLL1DIVR_PLL1Q) >> \
2854 RCC_PLL1DIVR_PLL1Q_Pos) + \
2855 (float_t)1));
2856 }
2857 else
2858 {
2859 pPLL1_Clocks->PLL1_Q_Frequency = 0U;
2860 }
2861 }
2862 else
2863 {
2864 pPLL1_Clocks->PLL1_Q_Frequency = 0U;
2865 }
2866
2867 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
2868 {
2869 if (__HAL_RCC_GET_PLL1_CLKOUT_CONFIG(RCC_PLL1_DIVR) != 0U)
2870 {
2871 pPLL1_Clocks->PLL1_R_Frequency = \
2872 (uint32_t)(float_t)(pll1vco / \
2873 ((float_t)(uint32_t)((RCC->PLL1DIVR & \
2874 RCC_PLL1DIVR_PLL1R) >> \
2875 RCC_PLL1DIVR_PLL1R_Pos) + \
2876 (float_t)1)) ;
2877 }
2878 else
2879 {
2880 pPLL1_Clocks->PLL1_R_Frequency = 0U;
2881 }
2882 }
2883 else
2884 {
2885 pPLL1_Clocks->PLL1_R_Frequency = 0U;
2886 }
2887
2888 }
2889 else
2890 {
2891 pPLL1_Clocks->PLL1_P_Frequency = 0U;
2892 pPLL1_Clocks->PLL1_Q_Frequency = 0U;
2893 pPLL1_Clocks->PLL1_R_Frequency = 0U;
2894 }
2895
2896 }
2897
2898 /**
2899 * @brief Returns the PLL2 clock frequencies: PLL2_P_Frequency, PLL2_R_Frequency and PLL2_Q_Frequency
2900 * @note The PLL2 clock frequencies computed by this function may not be the real
2901 * frequency in the chip. It is calculated based on the predefined
2902 * constant and the selected clock source:
2903 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by
2904 the PLL factors.
2905 * @note This function can be used by the user application to compute the
2906 * baud-rate for the communication peripherals or configure other parameters.
2907 *
2908 * @note Each time PLL2CLK changes, this function must be called to update the
2909 * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
2910 * @param pPLL2_Clocks pointer to PLL2_ClocksTypeDef structure.
2911 * @retval None
2912 */
HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef * pPLL2_Clocks)2913 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *pPLL2_Clocks)
2914 {
2915 uint32_t pll2source;
2916 uint32_t pll2m;
2917 uint32_t pll2n;
2918 uint32_t pll2fracen;
2919 uint32_t hsivalue;
2920 float_t fracn2;
2921 float_t pll2vco;
2922
2923 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
2924 PLL2xCLK = PLL2_VCO / PLL2x
2925 */
2926 pll2n = (RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N);
2927 pll2source = (RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC);
2928 pll2m = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos);
2929 pll2fracen = RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN;
2930 fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \
2931 RCC_PLL2FRACR_PLL2FRACN_Pos));
2932
2933 if (pll2m != 0U)
2934 {
2935 switch (pll2source)
2936 {
2937 case RCC_PLL2_SOURCE_HSI: /* HSI used as PLL clock source */
2938 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
2939 pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)pll2n + (fracn2 / (float_t)0x2000) + \
2940 (float_t)1);
2941 break;
2942
2943 case RCC_PLL2_SOURCE_CSI: /* CSI used as PLL clock source */
2944 pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)pll2n + (fracn2 / (float_t)0x2000) + \
2945 (float_t)1);
2946 break;
2947
2948 case RCC_PLL2_SOURCE_HSE: /* HSE used as PLL clock source */
2949 pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)pll2n + (fracn2 / (float_t)0x2000) + \
2950 (float_t)1);
2951 break;
2952
2953 default:
2954 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
2955 pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)pll2n + (fracn2 / (float_t)0x2000) + \
2956 (float_t)1);
2957 break;
2958 }
2959
2960 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2961 {
2962 if (__HAL_RCC_GET_PLL2_CLKOUT_CONFIG(RCC_PLL2_DIVP) != 0U)
2963 {
2964 pPLL2_Clocks->PLL2_P_Frequency = \
2965 (uint32_t)(float_t)(pll2vco / \
2966 ((float_t)(uint32_t)((RCC->PLL2DIVR & \
2967 RCC_PLL2DIVR_PLL2P) >> \
2968 RCC_PLL2DIVR_PLL2P_Pos) + \
2969 (float_t)1));
2970 }
2971 else
2972 {
2973 pPLL2_Clocks->PLL2_P_Frequency = 0U;
2974 }
2975 }
2976 else
2977 {
2978 pPLL2_Clocks->PLL2_P_Frequency = 0U;
2979 }
2980
2981 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
2982 {
2983 if (__HAL_RCC_GET_PLL2_CLKOUT_CONFIG(RCC_PLL2_DIVQ) != 0U)
2984 {
2985 pPLL2_Clocks->PLL2_Q_Frequency = \
2986 (uint32_t)(float_t)(pll2vco / \
2987 ((float_t)(uint32_t)((RCC->PLL2DIVR & \
2988 RCC_PLL2DIVR_PLL2Q) >> \
2989 RCC_PLL2DIVR_PLL2Q_Pos) + \
2990 (float_t)1));
2991 }
2992 else
2993 {
2994 pPLL2_Clocks->PLL2_Q_Frequency = 0U;
2995 }
2996 }
2997 else
2998 {
2999 pPLL2_Clocks->PLL2_Q_Frequency = 0U;
3000 }
3001
3002 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
3003 {
3004 if (__HAL_RCC_GET_PLL2_CLKOUT_CONFIG(RCC_PLL2_DIVR) != 0U)
3005 {
3006 pPLL2_Clocks->PLL2_R_Frequency = \
3007 (uint32_t)(float_t)(pll2vco / \
3008 ((float_t)(uint32_t)((RCC->PLL2DIVR & \
3009 RCC_PLL2DIVR_PLL2R) >> \
3010 RCC_PLL2DIVR_PLL2R_Pos) + \
3011 (float_t)1));
3012 }
3013 else
3014 {
3015 pPLL2_Clocks->PLL2_R_Frequency = 0U;
3016 }
3017 }
3018 else
3019 {
3020 pPLL2_Clocks->PLL2_R_Frequency = 0U;
3021 }
3022 }
3023 else
3024 {
3025 pPLL2_Clocks->PLL2_P_Frequency = 0U;
3026 pPLL2_Clocks->PLL2_Q_Frequency = 0U;
3027 pPLL2_Clocks->PLL2_R_Frequency = 0U;
3028 }
3029 }
3030
3031 #if defined(RCC_CR_PLL3ON)
3032 /**
3033 * @brief Returns the PLL3 clock frequencies: PLL3_P_Frequency, PLL3_R_Frequency and PLL3_Q_Frequency
3034 * @note The PLL3 clock frequencies computed by this function may not be the real
3035 * frequency in the chip. It is calculated based on the predefined
3036 * constant and the selected clock source:
3037 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by
3038 the PLL factors.
3039 * @note This function can be used by the user application to compute the
3040 * baud-rate for the communication peripherals or configure other parameters.
3041 *
3042 * @note Each time PLL3CLK changes, this function must be called to update the
3043 * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
3044 * @param pPLL3_Clocks pointer to PLL3_ClocksTypeDef structure.
3045 * @retval None
3046 */
HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef * pPLL3_Clocks)3047 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *pPLL3_Clocks)
3048 {
3049 uint32_t pll3source;
3050 uint32_t pll3m;
3051 uint32_t pll3n;
3052 uint32_t pll3fracen;
3053 uint32_t hsivalue;
3054 float_t fracn3;
3055 float_t pll3vco;
3056
3057 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
3058 PLL3xCLK = PLL3_VCO / PLL3x
3059 */
3060 pll3n = (RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N);
3061 pll3source = (RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC);
3062 pll3m = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos);
3063 pll3fracen = RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN;
3064 fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \
3065 RCC_PLL3FRACR_PLL3FRACN_Pos));
3066
3067 if (pll3m != 0U)
3068 {
3069 switch (pll3source)
3070 {
3071 case RCC_PLL3_SOURCE_HSI: /* HSI used as PLL clock source */
3072 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3073 pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)pll3n + (fracn3 / (float_t)0x2000) + \
3074 (float_t)1);
3075 break;
3076
3077 case RCC_PLL3_SOURCE_CSI: /* CSI used as PLL clock source */
3078 pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)pll3n + (fracn3 / (float_t)0x2000) + \
3079 (float_t)1);
3080 break;
3081
3082 case RCC_PLL3_SOURCE_HSE: /* HSE used as PLL clock source */
3083 pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)pll3n + (fracn3 / (float_t)0x2000) + \
3084 (float_t)1);
3085 break;
3086
3087 default:
3088 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3089 pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)pll3n + (fracn3 / (float_t)0x2000) + \
3090 (float_t)1);
3091 break;
3092 }
3093
3094 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
3095 {
3096 if (__HAL_RCC_GET_PLL3_CLKOUT_CONFIG(RCC_PLL3_DIVP) != 0U)
3097 {
3098 pPLL3_Clocks->PLL3_P_Frequency = \
3099 (uint32_t)(float_t)(pll3vco / \
3100 ((float_t)(uint32_t)((RCC->PLL3DIVR & \
3101 RCC_PLL3DIVR_PLL3P) >> \
3102 RCC_PLL3DIVR_PLL3P_Pos) + \
3103 (float_t)1));
3104 }
3105 else
3106 {
3107 pPLL3_Clocks->PLL3_P_Frequency = 0U;
3108 }
3109 }
3110 else
3111 {
3112 pPLL3_Clocks->PLL3_P_Frequency = 0U;
3113 }
3114
3115 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
3116 {
3117 if (__HAL_RCC_GET_PLL3_CLKOUT_CONFIG(RCC_PLL3_DIVQ) != 0U)
3118 {
3119 pPLL3_Clocks->PLL3_Q_Frequency = \
3120 (uint32_t)(float_t)(pll3vco / \
3121 ((float_t)(uint32_t)((RCC->PLL3DIVR & \
3122 RCC_PLL3DIVR_PLL3Q) >> \
3123 RCC_PLL3DIVR_PLL3Q_Pos) + \
3124 (float_t)1));
3125 }
3126 else
3127 {
3128 pPLL3_Clocks->PLL3_Q_Frequency = 0U;
3129 }
3130 }
3131 else
3132 {
3133 pPLL3_Clocks->PLL3_Q_Frequency = 0U;
3134 }
3135
3136 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
3137 {
3138 if (__HAL_RCC_GET_PLL3_CLKOUT_CONFIG(RCC_PLL3_DIVR) != 0U)
3139 {
3140 pPLL3_Clocks->PLL3_R_Frequency = \
3141 (uint32_t)(float_t)(pll3vco / \
3142 ((float_t)(uint32_t)((RCC->PLL3DIVR & \
3143 RCC_PLL3DIVR_PLL3R) >> \
3144 RCC_PLL3DIVR_PLL3R_Pos) + \
3145 (float_t)1));
3146 }
3147 else
3148 {
3149 pPLL3_Clocks->PLL3_R_Frequency = 0U;
3150 }
3151 }
3152 else
3153 {
3154 pPLL3_Clocks->PLL3_R_Frequency = 0U;
3155 }
3156 }
3157 else
3158 {
3159 pPLL3_Clocks->PLL3_P_Frequency = 0U;
3160 pPLL3_Clocks->PLL3_Q_Frequency = 0U;
3161 pPLL3_Clocks->PLL3_R_Frequency = 0U;
3162 }
3163 }
3164 #endif /* RCC_CR_PLL3ON */
3165
3166 /**
3167 * @brief Return the peripheral clock frequency for peripherals
3168 * @note Return 0 if peripheral clock identifier not managed by this API
3169 * @param PeriphClk Peripheral clock identifier
3170 * This parameter can be one of the following values:
3171 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
3172 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
3173 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
3174 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (*)
3175 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (*)
3176 * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock (*)
3177 * @arg @ref RCC_PERIPHCLK_UART7 UART7 peripheral clock (*)
3178 * @arg @ref RCC_PERIPHCLK_UART8 UART8 peripheral clock (*)
3179 * @arg @ref RCC_PERIPHCLK_UART9 UART9 peripheral clock (*)
3180 * @arg @ref RCC_PERIPHCLK_USART10 USART10 peripheral clock (*)
3181 * @arg @ref RCC_PERIPHCLK_USART11 USART11 peripheral clock (*)
3182 * @arg @ref RCC_PERIPHCLK_UART12 UART12 peripheral clock (*)
3183 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
3184 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
3185 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
3186 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock (*)
3187 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (*)
3188 * @arg @ref RCC_PERIPHCLK_I3C1 I3C1 peripheral clock
3189 * @arg @ref RCC_PERIPHCLK_I3C2 I3C2 peripheral clock (***)
3190 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
3191 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
3192 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (*)
3193 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (*)
3194 * @arg @ref RCC_PERIPHCLK_ADCDAC ADCDAC peripheral clock
3195 * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock
3196 * @arg @ref RCC_PERIPHCLK_ADC2 ADC2 peripheral clock
3197 * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock (*)
3198 * @arg @ref RCC_PERIPHCLK_SDMMC2 SDMMC2 peripheral clock (**)
3199 * @arg @ref RCC_PERIPHCLK_CKPER CKPER peripheral clock
3200 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
3201 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
3202 * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock
3203 * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock
3204 * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
3205 * @arg @ref RCC_PERIPHCLK_SPI4 SPI4 peripheral clock (*)
3206 * @arg @ref RCC_PERIPHCLK_SPI5 SPI5 peripheral clock (*)
3207 * @arg @ref RCC_PERIPHCLK_SPI6 SPI6 peripheral clock (*)
3208 * @arg @ref RCC_PERIPHCLK_OSPI OCTOSPI peripheral clock (*)
3209 * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock
3210 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock (*)
3211 * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
3212 * @arg @ref RCC_PERIPHCLK_LPTIM3 LPTIM3 peripheral clock (*)
3213 * @arg @ref RCC_PERIPHCLK_LPTIM4 LPTIM4 peripheral clock (*)
3214 * @arg @ref RCC_PERIPHCLK_LPTIM5 LPTIM5 peripheral clock (*)
3215 * @arg @ref RCC_PERIPHCLK_LPTIM6 LPTIM6 peripheral clock (*)
3216 * @arg @ref RCC_PERIPHCLK_DAC_LP DAC low-power peripheral clock
3217 * @arg @ref RCC_PERIPHCLK_TIM TIM peripheral clock
3218 *
3219 * @retval Frequency in Hz
3220 *
3221 * (*) : For stm32h56xxx and stm32h57xxx family lines only.
3222 * (**) : For stm32h563xx and stm32h57xxx family lines only.
3223 * (***) : For stm32h503xx family line only.
3224 */
HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)3225 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
3226 {
3227 PLL1_ClocksTypeDef pll1_clocks;
3228 PLL2_ClocksTypeDef pll2_clocks;
3229 #if defined(RCC_CR_PLL3ON)
3230 PLL3_ClocksTypeDef pll3_clocks;
3231 #endif /* RCC_CR_PLL3ON */
3232
3233 uint32_t frequency;
3234 uint32_t ckpclocksource;
3235 uint32_t srcclk;
3236
3237 /* Check the parameters */
3238 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
3239
3240 if (PeriphClk == RCC_PERIPHCLK_RTC)
3241 {
3242 /* Get the current RTC source */
3243 srcclk = __HAL_RCC_GET_RTC_SOURCE();
3244
3245 /* Check if LSE is ready and if RTC clock selection is LSE */
3246 if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE))
3247 {
3248 frequency = LSE_VALUE;
3249 }
3250 /* Check if LSI is ready and if RTC clock selection is LSI */
3251 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI))
3252 {
3253 frequency = LSI_VALUE;
3254 }
3255 /* Check if HSE is ready and if RTC clock selection is HSE_DIVx*/
3256 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIVx))
3257 {
3258 if (__HAL_RCC_GET_RTC_HSE_PRESCALER() >= RCC_RTC_HSE_DIV2)
3259 {
3260 frequency = (HSE_VALUE / ((uint32_t)(__HAL_RCC_GET_RTC_HSE_PRESCALER() >> RCC_CFGR1_RTCPRE_Pos)));
3261 }
3262 else
3263 {
3264 frequency = 0U;
3265 }
3266
3267 }
3268 /* Clock not enabled for RTC*/
3269 else
3270 {
3271 frequency = 0U;
3272 }
3273 }
3274 else
3275 {
3276 /* Other external peripheral clock source than RTC */
3277 switch (PeriphClk)
3278 {
3279 #if defined (SAI1)
3280 case RCC_PERIPHCLK_SAI1:
3281
3282 srcclk = __HAL_RCC_GET_SAI1_SOURCE();
3283
3284 switch (srcclk)
3285 {
3286 case RCC_SAI1CLKSOURCE_PLL1Q: /* PLL1Q is the clock source for SAI1 */
3287 {
3288 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
3289 frequency = pll1_clocks.PLL1_Q_Frequency;
3290 break;
3291 }
3292 case RCC_SAI1CLKSOURCE_PLL2P: /* PLL2P is the clock source for SAI1 */
3293 {
3294 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3295 frequency = pll2_clocks.PLL2_P_Frequency;
3296 break;
3297 }
3298 case RCC_SAI1CLKSOURCE_PLL3P: /* PLLI3P is the clock source for SAI1 */
3299 {
3300 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3301 frequency = pll3_clocks.PLL3_P_Frequency;
3302 break;
3303 }
3304 case RCC_SAI1CLKSOURCE_PIN:
3305 {
3306 frequency = EXTERNAL_CLOCK_VALUE;
3307 break;
3308 }
3309 case RCC_SAI1CLKSOURCE_CLKP: /* CLKP is the clock source for SAI1 */
3310 {
3311
3312 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
3313
3314 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
3315 {
3316 /* In Case the CKPER Source is HSI */
3317 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3318 }
3319
3320 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
3321 {
3322 /* In Case the CKPER Source is CSI */
3323 frequency = CSI_VALUE;
3324 }
3325
3326 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
3327 {
3328 /* In Case the CKPER Source is HSE */
3329 frequency = HSE_VALUE;
3330 }
3331
3332 else
3333 {
3334 /* In Case the CKPER is disabled*/
3335 frequency = 0U;
3336 }
3337
3338 break;
3339 }
3340 default :
3341 {
3342 frequency = 0U;
3343 break;
3344 }
3345 }
3346 break;
3347 #endif /*SAI1*/
3348
3349 #if defined(SAI2)
3350 case RCC_PERIPHCLK_SAI2:
3351
3352 srcclk = __HAL_RCC_GET_SAI2_SOURCE();
3353
3354 switch (srcclk)
3355 {
3356 case RCC_SAI2CLKSOURCE_PLL1Q: /* PLL1Q is the clock source for SAI2 */
3357 {
3358 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
3359 frequency = pll1_clocks.PLL1_Q_Frequency;
3360 break;
3361 }
3362 case RCC_SAI2CLKSOURCE_PLL2P: /* PLL2P is the clock source for SAI2 */
3363 {
3364 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3365 frequency = pll2_clocks.PLL2_P_Frequency;
3366 break;
3367 }
3368 case RCC_SAI2CLKSOURCE_PLL3P: /* PLLI3P is the clock source for SAI2 */
3369 {
3370 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3371 frequency = pll3_clocks.PLL3_P_Frequency;
3372 break;
3373 }
3374 case RCC_SAI2CLKSOURCE_PIN:
3375 {
3376 frequency = EXTERNAL_CLOCK_VALUE;
3377 break;
3378 }
3379 case RCC_SAI2CLKSOURCE_CLKP: /* CLKP is the clock source for SAI2 */
3380 {
3381
3382 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
3383
3384 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
3385 {
3386 /* In Case the CKPER Source is HSI */
3387 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3388 }
3389
3390 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
3391 {
3392 /* In Case the CKPER Source is CSI */
3393 frequency = CSI_VALUE;
3394 }
3395
3396 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
3397 {
3398 /* In Case the CKPER Source is HSE */
3399 frequency = HSE_VALUE;
3400 }
3401
3402 else
3403 {
3404 /* In Case the CKPER is disabled*/
3405 frequency = 0U;
3406 }
3407
3408 break;
3409 }
3410 default :
3411 {
3412 frequency = 0U;
3413 break;
3414 }
3415 }
3416 break;
3417 #endif /* SAI2 */
3418
3419 #if defined(SDMMC1)
3420 case RCC_PERIPHCLK_SDMMC1:
3421 srcclk = __HAL_RCC_GET_SDMMC1_SOURCE();
3422 if (srcclk == RCC_SDMMC1CLKSOURCE_PLL1Q)
3423 {
3424 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
3425 frequency = pll1_clocks.PLL1_Q_Frequency;
3426 }
3427 else if (srcclk == RCC_SDMMC1CLKSOURCE_PLL2R)
3428 {
3429 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3430 frequency = pll2_clocks.PLL2_R_Frequency;
3431 }
3432 else
3433 {
3434 frequency = 0U;
3435 }
3436 break;
3437 #endif /* SDMMC1 */
3438
3439 #if defined(SDMMC2)
3440 case RCC_PERIPHCLK_SDMMC2:
3441 srcclk = __HAL_RCC_GET_SDMMC2_SOURCE();
3442 if (srcclk == RCC_SDMMC2CLKSOURCE_PLL1Q)
3443 {
3444 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
3445 frequency = pll1_clocks.PLL1_Q_Frequency;
3446 }
3447 else if (srcclk == RCC_SDMMC2CLKSOURCE_PLL2R)
3448 {
3449 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3450 frequency = pll2_clocks.PLL2_R_Frequency;
3451 }
3452 else
3453 {
3454 frequency = 0U;
3455 }
3456 break;
3457 #endif /* SDMMC2 */
3458
3459 case RCC_PERIPHCLK_USART1:
3460 /* Get the current USART1 source */
3461 srcclk = __HAL_RCC_GET_USART1_SOURCE();
3462
3463 if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
3464 {
3465 frequency = HAL_RCC_GetPCLK2Freq();
3466 }
3467 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART1CLKSOURCE_PLL2Q))
3468 {
3469 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3470 frequency = pll2_clocks.PLL2_Q_Frequency;
3471 }
3472 #if defined(RCC_USART1CLKSOURCE_PLL3Q)
3473 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART1CLKSOURCE_PLL3Q))
3474 {
3475 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3476 frequency = pll3_clocks.PLL3_Q_Frequency;
3477 }
3478 #endif /* RCC_USART1CLKSOURCE_PLL3Q */
3479 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI))
3480 {
3481 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3482 }
3483 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_CSI))
3484 {
3485 frequency = CSI_VALUE;
3486 }
3487 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE))
3488 {
3489 frequency = LSE_VALUE;
3490 }
3491 /* Clock not enabled for USART1 */
3492 else
3493 {
3494 frequency = 0U;
3495 }
3496 break;
3497
3498 case RCC_PERIPHCLK_USART2:
3499 /* Get the current USART2 source */
3500 srcclk = __HAL_RCC_GET_USART2_SOURCE();
3501
3502 if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
3503 {
3504 frequency = HAL_RCC_GetPCLK1Freq();
3505 }
3506 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART2CLKSOURCE_PLL2Q))
3507 {
3508 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3509 frequency = pll2_clocks.PLL2_Q_Frequency;
3510 }
3511 #if defined(RCC_USART2CLKSOURCE_PLL3Q)
3512 else if ((srcclk == RCC_USART2CLKSOURCE_PLL3Q))
3513 {
3514 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3515 frequency = pll3_clocks.PLL3_Q_Frequency;
3516 }
3517 #endif /* RCC_USART2CLKSOURCE_PLL3Q */
3518 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI))
3519 {
3520 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3521 }
3522 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_CSI))
3523 {
3524 frequency = CSI_VALUE;
3525 }
3526 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE))
3527 {
3528 frequency = LSE_VALUE;
3529 }
3530 /* Clock not enabled for USART2 */
3531 else
3532 {
3533 frequency = 0U;
3534 }
3535 break;
3536
3537 case RCC_PERIPHCLK_USART3:
3538 /* Get the current USART3 source */
3539 srcclk = __HAL_RCC_GET_USART3_SOURCE();
3540
3541 if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
3542 {
3543 frequency = HAL_RCC_GetPCLK1Freq();
3544 }
3545 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART3CLKSOURCE_PLL2Q))
3546 {
3547 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3548 frequency = pll2_clocks.PLL2_Q_Frequency;
3549 }
3550 #if defined(RCC_USART3CLKSOURCE_PLL3Q)
3551 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART3CLKSOURCE_PLL3Q))
3552 {
3553 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3554 frequency = pll3_clocks.PLL3_Q_Frequency;
3555 }
3556 #endif /* RCC_USART3CLKSOURCE_PLL3S */
3557 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI))
3558 {
3559 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3560 }
3561 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_CSI))
3562 {
3563 frequency = CSI_VALUE;
3564 }
3565 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE))
3566 {
3567 frequency = LSE_VALUE;
3568 }
3569 /* Clock not enabled for USART3 */
3570 else
3571 {
3572 frequency = 0U;
3573 }
3574 break;
3575
3576 #if defined(UART4)
3577 case RCC_PERIPHCLK_UART4:
3578 /* Get the current UART4 source */
3579 srcclk = __HAL_RCC_GET_UART4_SOURCE();
3580
3581 if (srcclk == RCC_UART4CLKSOURCE_PCLK1)
3582 {
3583 frequency = HAL_RCC_GetPCLK1Freq();
3584 }
3585 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART4CLKSOURCE_PLL2Q))
3586 {
3587 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3588 frequency = pll2_clocks.PLL2_Q_Frequency;
3589 }
3590 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART4CLKSOURCE_PLL3Q))
3591 {
3592 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3593 frequency = pll3_clocks.PLL3_Q_Frequency;
3594 }
3595 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI))
3596 {
3597 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3598 }
3599 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_CSI))
3600 {
3601 frequency = CSI_VALUE;
3602 }
3603 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE))
3604 {
3605 frequency = LSE_VALUE;
3606 }
3607 /* Clock not enabled for UART4 */
3608 else
3609 {
3610 frequency = 0U;
3611 }
3612 break;
3613 #endif /* UART4 */
3614
3615 #if defined(UART5)
3616 case RCC_PERIPHCLK_UART5:
3617 /* Get the current UART5 source */
3618 srcclk = __HAL_RCC_GET_UART5_SOURCE();
3619
3620 if (srcclk == RCC_UART5CLKSOURCE_PCLK1)
3621 {
3622 frequency = HAL_RCC_GetPCLK1Freq();
3623 }
3624 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART5CLKSOURCE_PLL2Q))
3625 {
3626 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3627 frequency = pll2_clocks.PLL2_Q_Frequency;
3628 }
3629 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART5CLKSOURCE_PLL3Q))
3630 {
3631 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3632 frequency = pll3_clocks.PLL3_Q_Frequency;
3633 }
3634 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI))
3635 {
3636 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3637 }
3638 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_CSI))
3639 {
3640 frequency = CSI_VALUE;
3641 }
3642 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE))
3643 {
3644 frequency = LSE_VALUE;
3645 }
3646 /* Clock not enabled for UART5 */
3647 else
3648 {
3649 frequency = 0U;
3650 }
3651 break;
3652 #endif /* UART5 */
3653
3654 #if defined(USART6)
3655 case RCC_PERIPHCLK_USART6:
3656 /* Get the current USART6 source */
3657 srcclk = __HAL_RCC_GET_USART6_SOURCE();
3658
3659 if (srcclk == RCC_USART6CLKSOURCE_PCLK1)
3660 {
3661 frequency = HAL_RCC_GetPCLK1Freq();
3662 }
3663 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART6CLKSOURCE_PLL2Q))
3664 {
3665 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3666 frequency = pll2_clocks.PLL2_Q_Frequency;
3667 }
3668 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART6CLKSOURCE_PLL3Q))
3669 {
3670 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3671 frequency = pll3_clocks.PLL3_Q_Frequency;
3672 }
3673 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART6CLKSOURCE_HSI))
3674 {
3675 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3676 }
3677 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART6CLKSOURCE_CSI))
3678 {
3679 frequency = CSI_VALUE;
3680 }
3681 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART6CLKSOURCE_LSE))
3682 {
3683 frequency = LSE_VALUE;
3684 }
3685 /* Clock not enabled for USART6 */
3686 else
3687 {
3688 frequency = 0U;
3689 }
3690 break;
3691 #endif /* USART6 */
3692
3693 #if defined(UART7)
3694 case RCC_PERIPHCLK_UART7:
3695 /* Get the current UART7 source */
3696 srcclk = __HAL_RCC_GET_UART7_SOURCE();
3697
3698 if (srcclk == RCC_UART7CLKSOURCE_PCLK1)
3699 {
3700 frequency = HAL_RCC_GetPCLK1Freq();
3701 }
3702 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART7CLKSOURCE_PLL2Q))
3703 {
3704 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3705 frequency = pll2_clocks.PLL2_Q_Frequency;
3706 }
3707 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART7CLKSOURCE_PLL3Q))
3708 {
3709 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3710 frequency = pll3_clocks.PLL3_Q_Frequency;
3711 }
3712 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART7CLKSOURCE_HSI))
3713 {
3714 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3715 }
3716 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART7CLKSOURCE_CSI))
3717 {
3718 frequency = CSI_VALUE;
3719 }
3720 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART7CLKSOURCE_LSE))
3721 {
3722 frequency = LSE_VALUE;
3723 }
3724 /* Clock not enabled for UART7 */
3725 else
3726 {
3727 frequency = 0U;
3728 }
3729 break;
3730 #endif /* UART7 */
3731
3732 #if defined(UART8)
3733 case RCC_PERIPHCLK_UART8:
3734 /* Get the current UART8 source */
3735 srcclk = __HAL_RCC_GET_UART8_SOURCE();
3736
3737 if (srcclk == RCC_UART8CLKSOURCE_PCLK1)
3738 {
3739 frequency = HAL_RCC_GetPCLK1Freq();
3740 }
3741 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART8CLKSOURCE_PLL2Q))
3742 {
3743 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3744 frequency = pll2_clocks.PLL2_Q_Frequency;
3745 }
3746 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART8CLKSOURCE_PLL3Q))
3747 {
3748 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3749 frequency = pll3_clocks.PLL3_Q_Frequency;
3750 }
3751 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART8CLKSOURCE_HSI))
3752 {
3753 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3754 }
3755 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART8CLKSOURCE_CSI))
3756 {
3757 frequency = CSI_VALUE;
3758 }
3759 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART8CLKSOURCE_LSE))
3760 {
3761 frequency = LSE_VALUE;
3762 }
3763 /* Clock not enabled for UART8 */
3764 else
3765 {
3766 frequency = 0U;
3767 }
3768 break;
3769 #endif /* UART8 */
3770
3771 #if defined(UART9)
3772 case RCC_PERIPHCLK_UART9:
3773 /* Get the current UART9 source */
3774 srcclk = __HAL_RCC_GET_UART9_SOURCE();
3775
3776 if (srcclk == RCC_UART9CLKSOURCE_PCLK1)
3777 {
3778 frequency = HAL_RCC_GetPCLK1Freq();
3779 }
3780 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART9CLKSOURCE_PLL2Q))
3781 {
3782 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3783 frequency = pll2_clocks.PLL2_Q_Frequency;
3784 }
3785 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART9CLKSOURCE_PLL3Q))
3786 {
3787 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3788 frequency = pll3_clocks.PLL3_Q_Frequency;
3789 }
3790 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART9CLKSOURCE_HSI))
3791 {
3792 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3793 }
3794 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART9CLKSOURCE_CSI))
3795 {
3796 frequency = CSI_VALUE;
3797 }
3798 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART9CLKSOURCE_LSE))
3799 {
3800 frequency = LSE_VALUE;
3801 }
3802 /* Clock not enabled for UART9 */
3803 else
3804 {
3805 frequency = 0U;
3806 }
3807 break;
3808 #endif /* UART9 */
3809
3810 #if defined(USART10)
3811 case RCC_PERIPHCLK_USART10:
3812 /* Get the current USART10 source */
3813 srcclk = __HAL_RCC_GET_USART10_SOURCE();
3814
3815 if (srcclk == RCC_USART10CLKSOURCE_PCLK1)
3816 {
3817 frequency = HAL_RCC_GetPCLK1Freq();
3818 }
3819 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART10CLKSOURCE_PLL2Q))
3820 {
3821 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3822 frequency = pll2_clocks.PLL2_Q_Frequency;
3823 }
3824 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART10CLKSOURCE_PLL3Q))
3825 {
3826 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3827 frequency = pll3_clocks.PLL3_Q_Frequency;
3828 }
3829 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART10CLKSOURCE_HSI))
3830 {
3831 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3832 }
3833 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART10CLKSOURCE_CSI))
3834 {
3835 frequency = CSI_VALUE;
3836 }
3837 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART10CLKSOURCE_LSE))
3838 {
3839 frequency = LSE_VALUE;
3840 }
3841 /* Clock not enabled for USART10 */
3842 else
3843 {
3844 frequency = 0U;
3845 }
3846 break;
3847 #endif /* USART10 */
3848
3849 #if defined(USART11)
3850 case RCC_PERIPHCLK_USART11:
3851 /* Get the current USART11 source */
3852 srcclk = __HAL_RCC_GET_USART11_SOURCE();
3853
3854 if (srcclk == RCC_USART11CLKSOURCE_PCLK1)
3855 {
3856 frequency = HAL_RCC_GetPCLK1Freq();
3857 }
3858 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USART11CLKSOURCE_PLL2Q))
3859 {
3860 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3861 frequency = pll2_clocks.PLL2_Q_Frequency;
3862 }
3863 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USART11CLKSOURCE_PLL3Q))
3864 {
3865 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3866 frequency = pll3_clocks.PLL3_Q_Frequency;
3867 }
3868 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART11CLKSOURCE_HSI))
3869 {
3870 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3871 }
3872 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_USART11CLKSOURCE_CSI))
3873 {
3874 frequency = CSI_VALUE;
3875 }
3876 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART11CLKSOURCE_LSE))
3877 {
3878 frequency = LSE_VALUE;
3879 }
3880 /* Clock not enabled for USART11 */
3881 else
3882 {
3883 frequency = 0U;
3884 }
3885 break;
3886 #endif /* USART11 */
3887
3888 #if defined(UART12)
3889 case RCC_PERIPHCLK_UART12:
3890 /* Get the current UART12 source */
3891 srcclk = __HAL_RCC_GET_UART12_SOURCE();
3892
3893 if (srcclk == RCC_UART12CLKSOURCE_PCLK1)
3894 {
3895 frequency = HAL_RCC_GetPCLK1Freq();
3896 }
3897 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_UART12CLKSOURCE_PLL2Q))
3898 {
3899 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3900 frequency = pll2_clocks.PLL2_Q_Frequency;
3901 }
3902 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_UART12CLKSOURCE_PLL3Q))
3903 {
3904 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3905 frequency = pll3_clocks.PLL3_Q_Frequency;
3906 }
3907 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART12CLKSOURCE_HSI))
3908 {
3909 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3910 }
3911 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_UART12CLKSOURCE_CSI))
3912 {
3913 frequency = CSI_VALUE;
3914 }
3915 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART12CLKSOURCE_LSE))
3916 {
3917 frequency = LSE_VALUE;
3918 }
3919 /* Clock not enabled for UART12 */
3920 else
3921 {
3922 frequency = 0U;
3923 }
3924 break;
3925 #endif /* UART12 */
3926
3927 case RCC_PERIPHCLK_LPUART1:
3928 /* Get the current LPUART1 source */
3929 srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
3930
3931 if (srcclk == RCC_LPUART1CLKSOURCE_PCLK3)
3932 {
3933 frequency = HAL_RCC_GetPCLK3Freq();
3934 }
3935 else if (srcclk == RCC_LPUART1CLKSOURCE_PLL2Q)
3936 {
3937 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3938 frequency = pll2_clocks.PLL2_Q_Frequency;
3939 }
3940 #if defined(RCC_LPUART1CLKSOURCE_PLL3Q)
3941 else if (srcclk == RCC_LPUART1CLKSOURCE_PLL3Q)
3942 {
3943 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3944 frequency = pll3_clocks.PLL3_Q_Frequency;
3945 }
3946 #endif /* RCC_LPUART1CLKSOURCE_PLL3Q */
3947 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI))
3948 {
3949 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3950 }
3951 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_CSI))
3952 {
3953 frequency = CSI_VALUE;
3954 }
3955 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE))
3956 {
3957 frequency = LSE_VALUE;
3958 }
3959 /* Clock not enabled for LPUART1 */
3960 else
3961 {
3962 frequency = 0U;
3963 }
3964 break;
3965
3966 case RCC_PERIPHCLK_ADCDAC:
3967 /* Get the current ADCDAC source */
3968 srcclk = __HAL_RCC_GET_ADCDAC_SOURCE();
3969
3970 if (srcclk == RCC_ADCDACCLKSOURCE_HCLK)
3971 {
3972 frequency = HAL_RCC_GetHCLKFreq();
3973 }
3974 else if (srcclk == RCC_ADCDACCLKSOURCE_SYSCLK)
3975 {
3976 frequency = HAL_RCC_GetSysClockFreq();
3977 }
3978 else if (srcclk == RCC_ADCDACCLKSOURCE_PLL2R)
3979 {
3980 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3981 frequency = pll2_clocks.PLL2_R_Frequency;
3982 }
3983 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSE))
3984 {
3985 frequency = HSE_VALUE;
3986 }
3987 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSI))
3988 {
3989 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
3990 }
3991 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_CSI))
3992 {
3993 frequency = CSI_VALUE;
3994 }
3995 /* Clock not enabled for ADCDAC */
3996 else
3997 {
3998 frequency = 0U;
3999 }
4000 break;
4001
4002
4003 case RCC_PERIPHCLK_DAC_LP:
4004 /* Get the current DAC low-power source */
4005 srcclk = __HAL_RCC_GET_DAC_LP_SOURCE();
4006
4007 if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_DACLPCLKSOURCE_LSE))
4008 {
4009 frequency = LSE_VALUE;
4010 }
4011 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_DACLPCLKSOURCE_LSI))
4012 {
4013 frequency = LSI_VALUE;
4014 }
4015
4016 /* Clock not enabled for DAC */
4017 else
4018 {
4019 frequency = 0U;
4020 }
4021 break;
4022
4023 case RCC_PERIPHCLK_I2C1:
4024 /* Get the current I2C1 source */
4025 srcclk = __HAL_RCC_GET_I2C1_SOURCE();
4026
4027 if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
4028 {
4029 frequency = HAL_RCC_GetPCLK1Freq();
4030 }
4031 #if defined(RCC_I2C1CLKSOURCE_PLL3R)
4032 else if (srcclk == RCC_I2C1CLKSOURCE_PLL3R)
4033 {
4034 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4035 frequency = pll3_clocks.PLL3_R_Frequency;
4036 }
4037 #else
4038 else if (srcclk == RCC_I2C1CLKSOURCE_PLL2R)
4039 {
4040 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4041 frequency = pll2_clocks.PLL2_R_Frequency;
4042 }
4043 #endif /* RCC_I2C1CLKSOURCE_PLL3R */
4044 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI))
4045 {
4046 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4047 }
4048 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_CSI))
4049 {
4050 frequency = CSI_VALUE;
4051 }
4052 /* Clock not enabled for I2C1 */
4053 else
4054 {
4055 frequency = 0U;
4056 }
4057 break;
4058
4059 case RCC_PERIPHCLK_I2C2:
4060 /* Get the current I2C2 source */
4061 srcclk = __HAL_RCC_GET_I2C2_SOURCE();
4062
4063 if (srcclk == RCC_I2C2CLKSOURCE_PCLK1)
4064 {
4065 frequency = HAL_RCC_GetPCLK1Freq();
4066 }
4067 #if defined(RCC_I2C2CLKSOURCE_PLL3R)
4068 else if (srcclk == RCC_I2C2CLKSOURCE_PLL3R)
4069 {
4070 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4071 frequency = pll3_clocks.PLL3_R_Frequency;
4072 }
4073 #else
4074 else if (srcclk == RCC_I2C2CLKSOURCE_PLL2R)
4075 {
4076 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4077 frequency = pll2_clocks.PLL2_R_Frequency;
4078 }
4079 #endif /* RCC_I2C2CLKSOURCE_PLL3R */
4080 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI))
4081 {
4082 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4083 }
4084 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_CSI))
4085 {
4086 frequency = CSI_VALUE;
4087 }
4088 /* Clock not enabled for I2C2 */
4089 else
4090 {
4091 frequency = 0U;
4092 }
4093 break;
4094
4095 #if defined(I2C3)
4096 case RCC_PERIPHCLK_I2C3:
4097 /* Get the current I2C3 source */
4098 srcclk = __HAL_RCC_GET_I2C3_SOURCE();
4099
4100 if (srcclk == RCC_I2C3CLKSOURCE_PCLK3)
4101 {
4102 frequency = HAL_RCC_GetPCLK3Freq();
4103 }
4104 else if (srcclk == RCC_I2C3CLKSOURCE_PLL3R)
4105 {
4106 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4107 frequency = pll3_clocks.PLL3_R_Frequency;
4108 }
4109 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C3CLKSOURCE_HSI))
4110 {
4111 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4112 }
4113 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I2C3CLKSOURCE_CSI))
4114 {
4115 frequency = CSI_VALUE;
4116 }
4117 /* Clock not enabled for I2C3 */
4118 else
4119 {
4120 frequency = 0U;
4121 }
4122 break;
4123 #endif /* I2C3 */
4124
4125 #if defined(I2C4)
4126 case RCC_PERIPHCLK_I2C4:
4127 /* Get the current I2C4 source */
4128 srcclk = __HAL_RCC_GET_I2C4_SOURCE();
4129
4130 if (srcclk == RCC_I2C4CLKSOURCE_PCLK3)
4131 {
4132 frequency = HAL_RCC_GetPCLK3Freq();
4133 }
4134 else if (srcclk == RCC_I2C4CLKSOURCE_PLL3R)
4135 {
4136 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4137 frequency = pll3_clocks.PLL3_R_Frequency;
4138 }
4139 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI))
4140 {
4141 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4142 }
4143 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_CSI))
4144 {
4145 frequency = CSI_VALUE;
4146 }
4147 /* Clock not enabled for I2C4 */
4148 else
4149 {
4150 frequency = 0U;
4151 }
4152 break;
4153 #endif /* I2C4 */
4154
4155 case RCC_PERIPHCLK_I3C1:
4156 /* Get the current I3C1 source */
4157 srcclk = __HAL_RCC_GET_I3C1_SOURCE();
4158
4159 if (srcclk == RCC_I3C1CLKSOURCE_PCLK1)
4160 {
4161 frequency = HAL_RCC_GetPCLK1Freq();
4162 }
4163 #if defined(RCC_I3C1CLKSOURCE_PLL3R)
4164 else if (srcclk == RCC_I3C1CLKSOURCE_PLL3R)
4165 {
4166 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4167 frequency = pll3_clocks.PLL3_R_Frequency;
4168 }
4169 #else
4170 else if (srcclk == RCC_I3C1CLKSOURCE_PLL2R)
4171 {
4172 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4173 frequency = pll2_clocks.PLL2_R_Frequency;
4174 }
4175 #endif /* RCC_I3C1CLKSOURCE_PLL3R */
4176 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I3C1CLKSOURCE_HSI))
4177 {
4178 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4179 }
4180 /* Clock not enabled for I3C1 */
4181 else
4182 {
4183 frequency = 0U;
4184 }
4185 break;
4186
4187 #if defined(I3C2)
4188 case RCC_PERIPHCLK_I3C2:
4189 /* Get the current I3C2 source */
4190 srcclk = __HAL_RCC_GET_I3C2_SOURCE();
4191
4192 if (srcclk == RCC_I3C2CLKSOURCE_PCLK3)
4193 {
4194 frequency = HAL_RCC_GetPCLK3Freq();
4195 }
4196 else if (srcclk == RCC_I3C2CLKSOURCE_PLL2R)
4197 {
4198 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4199 frequency = pll2_clocks.PLL2_R_Frequency;
4200 }
4201 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I3C2CLKSOURCE_HSI))
4202 {
4203 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4204 }
4205 /* Clock not enabled for I3C2 */
4206 else
4207 {
4208 frequency = 0U;
4209 }
4210 break;
4211 #endif /* I3C2*/
4212
4213 case RCC_PERIPHCLK_LPTIM1:
4214 /* Get the current LPTIM1 source */
4215 srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
4216
4217 switch (srcclk)
4218 {
4219 case RCC_LPTIM1CLKSOURCE_PCLK3:
4220 {
4221 frequency = HAL_RCC_GetPCLK3Freq();
4222 break;
4223 }
4224 case RCC_LPTIM1CLKSOURCE_PLL2P:
4225 {
4226 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4227 frequency = pll2_clocks.PLL2_P_Frequency;
4228 break;
4229 }
4230 #if defined(RCC_LPTIM1CLKSOURCE_PLL3R)
4231 case RCC_LPTIM1CLKSOURCE_PLL3R:
4232 {
4233 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4234 frequency = pll3_clocks.PLL3_R_Frequency;
4235 break;
4236 }
4237 #endif /* RCC_LPTIM1CLKSOURCE_PLL3R */
4238 case RCC_LPTIM1CLKSOURCE_LSE:
4239 {
4240 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
4241 {
4242 frequency = LSE_VALUE;
4243 }
4244 else
4245 {
4246 frequency = 0;
4247 }
4248 break;
4249 }
4250 case RCC_LPTIM1CLKSOURCE_LSI:
4251 {
4252 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY))
4253 {
4254 frequency = LSI_VALUE;
4255 }
4256 else
4257 {
4258 frequency = 0;
4259 }
4260 break;
4261 }
4262 case RCC_LPTIM1CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM1 */
4263 {
4264 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4265
4266 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4267 {
4268 /* In Case the CKPER Source is HSI */
4269 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4270 }
4271
4272 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4273 {
4274 /* In Case the CKPER Source is CSI */
4275 frequency = CSI_VALUE;
4276 }
4277
4278 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4279 {
4280 /* In Case the CKPER Source is HSE */
4281 frequency = HSE_VALUE;
4282 }
4283
4284 else
4285 {
4286 /* In Case the CKPER is disabled*/
4287 frequency = 0;
4288 }
4289
4290 break;
4291 }
4292 default :
4293 {
4294 frequency = 0U;
4295 break;
4296 }
4297 }
4298 break;
4299
4300 case RCC_PERIPHCLK_LPTIM2:
4301 /* Get the current LPTIM2 source */
4302 srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
4303
4304 switch (srcclk)
4305 {
4306 case RCC_LPTIM2CLKSOURCE_PCLK1:
4307 {
4308 frequency = HAL_RCC_GetPCLK1Freq();
4309 break;
4310 }
4311 case RCC_LPTIM2CLKSOURCE_PLL2P:
4312 {
4313 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4314 frequency = pll2_clocks.PLL2_P_Frequency;
4315 break;
4316 }
4317 #if defined(RCC_LPTIM2CLKSOURCE_PLL3R)
4318 case RCC_LPTIM2CLKSOURCE_PLL3R:
4319 {
4320 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4321 frequency = pll3_clocks.PLL3_R_Frequency;
4322 break;
4323 }
4324 #endif /* RCC_LPTIM2CLKSOURCE_PLL3R */
4325 case RCC_LPTIM2CLKSOURCE_LSE:
4326 {
4327 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
4328 {
4329 frequency = LSE_VALUE;
4330 }
4331 else
4332 {
4333 frequency = 0;
4334 }
4335 break;
4336 }
4337 case RCC_LPTIM2CLKSOURCE_LSI:
4338 {
4339 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY))
4340 {
4341 frequency = LSI_VALUE;
4342 }
4343 else
4344 {
4345 frequency = 0;
4346 }
4347 break;
4348 }
4349 case RCC_LPTIM2CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM2 */
4350 {
4351 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4352
4353 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4354 {
4355 /* In Case the CKPER Source is HSI */
4356 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4357 }
4358
4359 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4360 {
4361 /* In Case the CKPER Source is CSI */
4362 frequency = CSI_VALUE;
4363 }
4364
4365 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4366 {
4367 /* In Case the CKPER Source is HSE */
4368 frequency = HSE_VALUE;
4369 }
4370
4371 else
4372 {
4373 /* In Case the CKPER is disabled*/
4374 frequency = 0;
4375 }
4376
4377 break;
4378 }
4379 default :
4380 {
4381 frequency = 0U;
4382 break;
4383 }
4384 }
4385 break;
4386
4387 #if defined(LPTIM3)
4388 case RCC_PERIPHCLK_LPTIM3:
4389 /* Get the current LPTIM3 source */
4390 srcclk = __HAL_RCC_GET_LPTIM3_SOURCE();
4391
4392 switch (srcclk)
4393 {
4394 case RCC_LPTIM3CLKSOURCE_PCLK3:
4395 {
4396 frequency = HAL_RCC_GetPCLK3Freq();
4397 break;
4398 }
4399 case RCC_LPTIM3CLKSOURCE_PLL2P:
4400 {
4401 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4402 frequency = pll2_clocks.PLL2_P_Frequency;
4403 break;
4404 }
4405 case RCC_LPTIM3CLKSOURCE_PLL3R:
4406 {
4407 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4408 frequency = pll3_clocks.PLL3_R_Frequency;
4409 break;
4410 }
4411 case RCC_LPTIM3CLKSOURCE_LSE:
4412 {
4413 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
4414 {
4415 frequency = LSE_VALUE;
4416 }
4417 else
4418 {
4419 frequency = 0;
4420 }
4421 break;
4422 }
4423 case RCC_LPTIM3CLKSOURCE_LSI:
4424 {
4425 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY))
4426 {
4427 frequency = LSI_VALUE;
4428 }
4429 else
4430 {
4431 frequency = 0;
4432 }
4433 break;
4434 }
4435 case RCC_LPTIM3CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM3 */
4436 {
4437 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4438
4439 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4440 {
4441 /* In Case the CKPER Source is HSI */
4442 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4443 }
4444
4445 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4446 {
4447 /* In Case the CKPER Source is CSI */
4448 frequency = CSI_VALUE;
4449 }
4450
4451 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4452 {
4453 /* In Case the CKPER Source is HSE */
4454 frequency = HSE_VALUE;
4455 }
4456
4457 else
4458 {
4459 /* In Case the CKPER is disabled*/
4460 frequency = 0;
4461 }
4462
4463 break;
4464 }
4465 default :
4466 {
4467 frequency = 0U;
4468 break;
4469 }
4470 }
4471 break;
4472 #endif /* LPTIM3 */
4473
4474 #if defined(LPTIM4)
4475 case RCC_PERIPHCLK_LPTIM4:
4476 /* Get the current LPTIM4 source */
4477 srcclk = __HAL_RCC_GET_LPTIM4_SOURCE();
4478
4479 switch (srcclk)
4480 {
4481 case RCC_LPTIM4CLKSOURCE_PCLK3:
4482 {
4483 frequency = HAL_RCC_GetPCLK3Freq();
4484 break;
4485 }
4486 case RCC_LPTIM4CLKSOURCE_PLL2P:
4487 {
4488 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4489 frequency = pll2_clocks.PLL2_P_Frequency;
4490 break;
4491 }
4492 case RCC_LPTIM4CLKSOURCE_PLL3R:
4493 {
4494 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4495 frequency = pll3_clocks.PLL3_R_Frequency;
4496 break;
4497 }
4498 case RCC_LPTIM4CLKSOURCE_LSE:
4499 {
4500 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
4501 {
4502 frequency = LSE_VALUE;
4503 }
4504 else
4505 {
4506 frequency = 0;
4507 }
4508 break;
4509 }
4510 case RCC_LPTIM4CLKSOURCE_LSI:
4511 {
4512 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY))
4513 {
4514 frequency = LSI_VALUE;
4515 }
4516 else
4517 {
4518 frequency = 0;
4519 }
4520 break;
4521 }
4522 case RCC_LPTIM4CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM4 */
4523 {
4524 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4525
4526 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4527 {
4528 /* In Case the CKPER Source is HSI */
4529 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4530 }
4531
4532 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4533 {
4534 /* In Case the CKPER Source is CSI */
4535 frequency = CSI_VALUE;
4536 }
4537
4538 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4539 {
4540 /* In Case the CKPER Source is HSE */
4541 frequency = HSE_VALUE;
4542 }
4543
4544 else
4545 {
4546 /* In Case the CKPER is disabled*/
4547 frequency = 0;
4548 }
4549
4550 break;
4551 }
4552 default :
4553 {
4554 frequency = 0U;
4555 break;
4556 }
4557 }
4558 break;
4559 #endif /* LPTIM4 */
4560
4561 #if defined(LPTIM5)
4562 case RCC_PERIPHCLK_LPTIM5:
4563 /* Get the current LPTIM5 source */
4564 srcclk = __HAL_RCC_GET_LPTIM5_SOURCE();
4565
4566 switch (srcclk)
4567 {
4568 case RCC_LPTIM5CLKSOURCE_PCLK3:
4569 {
4570 frequency = HAL_RCC_GetPCLK3Freq();
4571 break;
4572 }
4573 case RCC_LPTIM5CLKSOURCE_PLL2P:
4574 {
4575 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4576 frequency = pll2_clocks.PLL2_P_Frequency;
4577 break;
4578 }
4579 case RCC_LPTIM5CLKSOURCE_PLL3R:
4580 {
4581 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4582 frequency = pll3_clocks.PLL3_R_Frequency;
4583 break;
4584 }
4585 case RCC_LPTIM5CLKSOURCE_LSE:
4586 {
4587 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
4588 {
4589 frequency = LSE_VALUE;
4590 }
4591 else
4592 {
4593 frequency = 0;
4594 }
4595 break;
4596 }
4597 case RCC_LPTIM5CLKSOURCE_LSI:
4598 {
4599 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY))
4600 {
4601 frequency = LSI_VALUE;
4602 }
4603 else
4604 {
4605 frequency = 0;
4606 }
4607 break;
4608 }
4609 case RCC_LPTIM5CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM5 */
4610 {
4611 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4612
4613 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4614 {
4615 /* In Case the CKPER Source is HSI */
4616 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4617 }
4618
4619 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4620 {
4621 /* In Case the CKPER Source is CSI */
4622 frequency = CSI_VALUE;
4623 }
4624
4625 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4626 {
4627 /* In Case the CKPER Source is HSE */
4628 frequency = HSE_VALUE;
4629 }
4630
4631 else
4632 {
4633 /* In Case the CKPER is disabled*/
4634 frequency = 0;
4635 }
4636
4637 break;
4638 }
4639 default :
4640 {
4641 frequency = 0U;
4642 break;
4643 }
4644 }
4645 break;
4646 #endif /* LPTIM5 */
4647
4648 #if defined(LPTIM6)
4649 case RCC_PERIPHCLK_LPTIM6:
4650 /* Get the current LPTIM6 source */
4651 srcclk = __HAL_RCC_GET_LPTIM6_SOURCE();
4652
4653 switch (srcclk)
4654 {
4655 case RCC_LPTIM6CLKSOURCE_PCLK3:
4656 {
4657 frequency = HAL_RCC_GetPCLK3Freq();
4658 break;
4659 }
4660 case RCC_LPTIM6CLKSOURCE_PLL2P:
4661 {
4662 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4663 frequency = pll2_clocks.PLL2_P_Frequency;
4664 break;
4665 }
4666 case RCC_LPTIM6CLKSOURCE_PLL3R:
4667 {
4668 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4669 frequency = pll3_clocks.PLL3_R_Frequency;
4670 break;
4671 }
4672 case RCC_LPTIM6CLKSOURCE_LSE:
4673 {
4674 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))
4675 {
4676 frequency = LSE_VALUE;
4677 }
4678 else
4679 {
4680 frequency = 0;
4681 }
4682 break;
4683 }
4684 case RCC_LPTIM6CLKSOURCE_LSI:
4685 {
4686 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY))
4687 {
4688 frequency = LSI_VALUE;
4689 }
4690 else
4691 {
4692 frequency = 0;
4693 }
4694 break;
4695 }
4696 case RCC_LPTIM6CLKSOURCE_CLKP: /* CLKP is the clock source for LPTIM6 */
4697 {
4698 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4699
4700 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4701 {
4702 /* In Case the CKPER Source is HSI */
4703 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4704 }
4705
4706 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4707 {
4708 /* In Case the CKPER Source is CSI */
4709 frequency = CSI_VALUE;
4710 }
4711
4712 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4713 {
4714 /* In Case the CKPER Source is HSE */
4715 frequency = HSE_VALUE;
4716 }
4717
4718 else
4719 {
4720 /* In Case the CKPER is disabled*/
4721 frequency = 0;
4722 }
4723
4724 break;
4725 }
4726 default :
4727 {
4728 frequency = 0U;
4729 break;
4730 }
4731 }
4732 break;
4733 #endif /* LPTIM6 */
4734
4735 case RCC_PERIPHCLK_FDCAN:
4736 /* Get the current FDCAN kernel source */
4737 srcclk = __HAL_RCC_GET_FDCAN_SOURCE();
4738
4739 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCANCLKSOURCE_HSE))
4740 {
4741 frequency = HSE_VALUE;
4742 }
4743 else if (srcclk == RCC_FDCANCLKSOURCE_PLL1Q)
4744 {
4745 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
4746 frequency = pll1_clocks.PLL1_Q_Frequency;
4747 }
4748 else if (srcclk == RCC_FDCANCLKSOURCE_PLL2Q)
4749 {
4750 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4751 frequency = pll2_clocks.PLL2_Q_Frequency;
4752 }
4753 /* Clock not enabled for FDCAN */
4754 else
4755 {
4756 frequency = 0U;
4757 }
4758 break;
4759
4760 case RCC_PERIPHCLK_SPI1:
4761 /* Get the current SPI1 kernel source */
4762 srcclk = __HAL_RCC_GET_SPI1_SOURCE();
4763 switch (srcclk)
4764 {
4765 case RCC_SPI1CLKSOURCE_PLL1Q:
4766 {
4767 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
4768 frequency = pll1_clocks.PLL1_Q_Frequency;
4769 break;
4770 }
4771 case RCC_SPI1CLKSOURCE_PLL2P:
4772 {
4773 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4774 frequency = pll2_clocks.PLL2_P_Frequency;
4775 break;
4776 }
4777 #if defined(RCC_SPI1CLKSOURCE_PLL3P)
4778 case RCC_SPI1CLKSOURCE_PLL3P:
4779 {
4780 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4781 frequency = pll3_clocks.PLL3_P_Frequency;
4782 break;
4783 }
4784 #endif /* RCC_SPI1CLKSOURCE_PLL3P */
4785 case RCC_SPI1CLKSOURCE_PIN:
4786 {
4787 frequency = EXTERNAL_CLOCK_VALUE;
4788 break;
4789 }
4790 case RCC_SPI1CLKSOURCE_CLKP:
4791 {
4792 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4793
4794 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4795 {
4796 /* In Case the CKPER Source is HSI */
4797 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4798 }
4799
4800 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4801 {
4802 /* In Case the CKPER Source is CSI */
4803 frequency = CSI_VALUE;
4804 }
4805
4806 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4807 {
4808 /* In Case the CKPER Source is HSE */
4809 frequency = HSE_VALUE;
4810 }
4811
4812 else
4813 {
4814 /* In Case the CKPER is disabled*/
4815 frequency = 0;
4816 }
4817
4818 break;
4819 }
4820 default:
4821 {
4822 frequency = 0;
4823 break;
4824 }
4825 }
4826 break;
4827
4828 case RCC_PERIPHCLK_SPI2:
4829 /* Get the current SPI2 kernel source */
4830 srcclk = __HAL_RCC_GET_SPI2_SOURCE();
4831 switch (srcclk)
4832 {
4833 case RCC_SPI2CLKSOURCE_PLL1Q:
4834 {
4835 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
4836 frequency = pll1_clocks.PLL1_Q_Frequency;
4837 break;
4838 }
4839 case RCC_SPI2CLKSOURCE_PLL2P:
4840 {
4841 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4842 frequency = pll2_clocks.PLL2_P_Frequency;
4843 break;
4844 }
4845 #if defined(RCC_SPI2CLKSOURCE_PLL3P)
4846 case RCC_SPI2CLKSOURCE_PLL3P:
4847 {
4848 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4849 frequency = pll3_clocks.PLL3_P_Frequency;
4850 break;
4851 }
4852 #endif /* RCC_SPI2CLKSOURCE_PLL3P */
4853 case RCC_SPI2CLKSOURCE_PIN:
4854 {
4855 frequency = EXTERNAL_CLOCK_VALUE;
4856 break;
4857 }
4858 case RCC_SPI2CLKSOURCE_CLKP:
4859 {
4860 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4861
4862 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4863 {
4864 /* In Case the CKPER Source is HSI */
4865 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4866 }
4867
4868 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4869 {
4870 /* In Case the CKPER Source is CSI */
4871 frequency = CSI_VALUE;
4872 }
4873
4874 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4875 {
4876 /* In Case the CKPER Source is HSE */
4877 frequency = HSE_VALUE;
4878 }
4879
4880 else
4881 {
4882 /* In Case the CKPER is disabled*/
4883 frequency = 0;
4884 }
4885
4886 break;
4887 }
4888 default:
4889 {
4890 frequency = 0;
4891 break;
4892 }
4893 }
4894 break;
4895
4896 case RCC_PERIPHCLK_SPI3:
4897 /* Get the current SPI3 kernel source */
4898 srcclk = __HAL_RCC_GET_SPI3_SOURCE();
4899 switch (srcclk)
4900 {
4901 case RCC_SPI3CLKSOURCE_PLL1Q:
4902 {
4903 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
4904 frequency = pll1_clocks.PLL1_Q_Frequency;
4905 break;
4906 }
4907 case RCC_SPI3CLKSOURCE_PLL2P:
4908 {
4909 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4910 frequency = pll2_clocks.PLL2_P_Frequency;
4911 break;
4912 }
4913 #if defined(RCC_SPI3CLKSOURCE_PLL3P)
4914 case RCC_SPI3CLKSOURCE_PLL3P:
4915 {
4916 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4917 frequency = pll3_clocks.PLL3_P_Frequency;
4918 break;
4919 }
4920 #endif /* RCC_SPI3CLKSOURCE_PLL3P */
4921 case RCC_SPI3CLKSOURCE_PIN:
4922 {
4923 frequency = EXTERNAL_CLOCK_VALUE;
4924 break;
4925 }
4926 case RCC_SPI3CLKSOURCE_CLKP:
4927 {
4928 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
4929
4930 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
4931 {
4932 /* In Case the CKPER Source is HSI */
4933 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4934 }
4935
4936 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
4937 {
4938 /* In Case the CKPER Source is CSI */
4939 frequency = CSI_VALUE;
4940 }
4941
4942 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
4943 {
4944 /* In Case the CKPER Source is HSE */
4945 frequency = HSE_VALUE;
4946 }
4947
4948 else
4949 {
4950 /* In Case the CKPER is disabled*/
4951 frequency = 0;
4952 }
4953
4954 break;
4955 }
4956 default:
4957 {
4958 frequency = 0;
4959 break;
4960 }
4961 }
4962 break;
4963
4964 #if defined(SPI4)
4965 case RCC_PERIPHCLK_SPI4:
4966 /* Get the current SPI4 kernel source */
4967 srcclk = __HAL_RCC_GET_SPI4_SOURCE();
4968
4969 if (srcclk == RCC_SPI4CLKSOURCE_PCLK2)
4970 {
4971 frequency = HAL_RCC_GetPCLK2Freq();
4972 }
4973 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_SPI4CLKSOURCE_PLL2Q))
4974 {
4975 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
4976 frequency = pll2_clocks.PLL2_Q_Frequency;
4977 }
4978 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_SPI4CLKSOURCE_PLL3Q))
4979 {
4980 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
4981 frequency = pll3_clocks.PLL3_Q_Frequency;
4982 }
4983 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_SPI4CLKSOURCE_HSI))
4984 {
4985 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
4986 }
4987 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_SPI4CLKSOURCE_CSI))
4988 {
4989 frequency = CSI_VALUE;
4990 }
4991 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_SPI4CLKSOURCE_HSE))
4992 {
4993 frequency = HSE_VALUE;
4994 }
4995 /* Clock not enabled for SPI4 */
4996 else
4997 {
4998 frequency = 0U;
4999 }
5000
5001 break;
5002 #endif /* SPI4 */
5003
5004 #if defined(SPI5)
5005 case RCC_PERIPHCLK_SPI5:
5006 /* Get the current SPI5 kernel source */
5007 srcclk = __HAL_RCC_GET_SPI5_SOURCE();
5008
5009 if (srcclk == RCC_SPI5CLKSOURCE_PCLK3)
5010 {
5011 frequency = HAL_RCC_GetPCLK3Freq();
5012 }
5013 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_SPI5CLKSOURCE_PLL2Q))
5014 {
5015 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
5016 frequency = pll2_clocks.PLL2_Q_Frequency;
5017 }
5018 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_SPI5CLKSOURCE_PLL3Q))
5019 {
5020 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
5021 frequency = pll3_clocks.PLL3_Q_Frequency;
5022 }
5023 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_SPI5CLKSOURCE_HSI))
5024 {
5025 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
5026 }
5027 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_SPI5CLKSOURCE_CSI))
5028 {
5029 frequency = CSI_VALUE;
5030 }
5031 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_SPI5CLKSOURCE_HSE))
5032 {
5033 frequency = HSE_VALUE;
5034 }
5035 /* Clock not enabled for SPI5 */
5036 else
5037 {
5038 frequency = 0U;
5039 }
5040
5041 break;
5042 #endif /* SPI5 */
5043
5044 #if defined(SPI6)
5045 case RCC_PERIPHCLK_SPI6:
5046 /* Get the current SPI6 kernel source */
5047 srcclk = __HAL_RCC_GET_SPI6_SOURCE();
5048
5049 if (srcclk == RCC_SPI6CLKSOURCE_PCLK2)
5050 {
5051 frequency = HAL_RCC_GetPCLK2Freq();
5052 }
5053 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_SPI6CLKSOURCE_PLL2Q))
5054 {
5055 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
5056 frequency = pll2_clocks.PLL2_Q_Frequency;
5057 }
5058 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_SPI6CLKSOURCE_PLL3Q))
5059 {
5060 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
5061 frequency = pll3_clocks.PLL3_Q_Frequency;
5062 }
5063 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_SPI6CLKSOURCE_HSI))
5064 {
5065 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
5066 }
5067 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_SPI6CLKSOURCE_CSI))
5068 {
5069 frequency = CSI_VALUE;
5070 }
5071 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_SPI6CLKSOURCE_HSE))
5072 {
5073 frequency = HSE_VALUE;
5074 }
5075 /* Clock not enabled for SPI6 */
5076 else
5077 {
5078 frequency = 0U;
5079 }
5080
5081 break;
5082 #endif /* SPI6 */
5083
5084 #if defined(OCTOSPI1)
5085 case RCC_PERIPHCLK_OSPI:
5086 /* Get the current OSPI kernel source */
5087 srcclk = __HAL_RCC_GET_OSPI_SOURCE();
5088
5089 switch (srcclk)
5090 {
5091 case RCC_OSPICLKSOURCE_HCLK:
5092 {
5093 frequency = HAL_RCC_GetHCLKFreq();
5094 break;
5095 }
5096 case RCC_OSPICLKSOURCE_PLL1Q:
5097 {
5098 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
5099 frequency = pll1_clocks.PLL1_Q_Frequency;
5100 break;
5101 }
5102 case RCC_OSPICLKSOURCE_PLL2R:
5103 {
5104 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
5105 frequency = pll2_clocks.PLL2_R_Frequency;
5106 break;
5107 }
5108 case RCC_OSPICLKSOURCE_CLKP:
5109 {
5110 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
5111
5112 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
5113 {
5114 /* In Case the CKPER Source is HSI */
5115 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> RCC_CR_HSIDIV_Pos));
5116 }
5117
5118 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
5119 {
5120 /* In Case the CKPER Source is CSI */
5121 frequency = CSI_VALUE;
5122 }
5123
5124 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
5125 {
5126 /* In Case the CKPER Source is HSE */
5127 frequency = HSE_VALUE;
5128 }
5129
5130 else
5131 {
5132 /* In Case the CKPER is disabled*/
5133 frequency = 0U;
5134 }
5135
5136 break;
5137 }
5138 default:
5139 {
5140 frequency = 0U;
5141 break;
5142 }
5143 }
5144 break;
5145 #endif /* OCTOSPI1*/
5146
5147 #if defined(CEC)
5148 case RCC_PERIPHCLK_CEC:
5149 /* Get the current CEC source */
5150 srcclk = __HAL_RCC_GET_CEC_SOURCE();
5151
5152 if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_CECCLKSOURCE_LSE))
5153 {
5154 frequency = LSE_VALUE;
5155 }
5156 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_CECCLKSOURCE_LSI))
5157 {
5158 frequency = LSI_VALUE;
5159 }
5160 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (srcclk == RCC_CECCLKSOURCE_CSI_DIV122))
5161 {
5162 frequency = CSI_VALUE / 122U;
5163 }
5164
5165 /* Clock not enabled for CEC */
5166 else
5167 {
5168 frequency = 0U;
5169 }
5170 break;
5171 #endif /* CEC */
5172
5173 case RCC_PERIPHCLK_RNG:
5174 /* Get the current RNG source */
5175 srcclk = __HAL_RCC_GET_RNG_SOURCE();
5176
5177 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48))
5178 {
5179 frequency = HSI48_VALUE;
5180 }
5181 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) && (srcclk == RCC_RNGCLKSOURCE_PLL1Q))
5182 {
5183 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
5184 frequency = pll1_clocks.PLL1_Q_Frequency;
5185 }
5186 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RNGCLKSOURCE_LSE))
5187 {
5188 frequency = LSE_VALUE;
5189 }
5190 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_RNGCLKSOURCE_LSI))
5191 {
5192 frequency = LSI_VALUE;
5193 }
5194
5195 /* Clock not enabled for RNG */
5196 else
5197 {
5198 frequency = 0U;
5199 }
5200 break;
5201
5202 case RCC_PERIPHCLK_USB:
5203 /* Get the current USB kernel source */
5204 srcclk = __HAL_RCC_GET_USB_SOURCE();
5205
5206 if (srcclk == RCC_USBCLKSOURCE_PLL1Q)
5207 {
5208 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
5209 frequency = pll1_clocks.PLL1_Q_Frequency;
5210 break;
5211 }
5212 #if defined(RCC_USBCLKSOURCE_PLL3Q)
5213 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) && (srcclk == RCC_USBCLKSOURCE_PLL3Q))
5214 {
5215 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
5216 frequency = pll3_clocks.PLL3_Q_Frequency;
5217 }
5218 #else
5219 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) && (srcclk == RCC_USBCLKSOURCE_PLL2Q))
5220 {
5221 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
5222 frequency = pll2_clocks.PLL2_Q_Frequency;
5223 }
5224 #endif /* RCC_USBCLKSOURCE_PLL3 */
5225 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_USBCLKSOURCE_HSI48))
5226 {
5227 frequency = HSI48_VALUE;
5228 }
5229 /* Clock not enabled for USB */
5230 else
5231 {
5232 frequency = 0U;
5233 }
5234
5235 break;
5236
5237
5238 default:
5239 frequency = 0U;
5240 break;
5241 }
5242 }
5243
5244 return (frequency);
5245 }
5246
5247 /**
5248 * @}
5249 */
5250
5251 /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
5252 * @brief Extended Clock management functions
5253 *
5254 @verbatim
5255 ===============================================================================
5256 ##### Extended clock management functions #####
5257 ===============================================================================
5258 [..]
5259 This subsection provides a set of functions allowing to control the
5260 activation or deactivation of PLL2, PLL3, LSE CSS,
5261 Low speed clock output and clock after wake-up from STOP mode.
5262 @endverbatim
5263 * @{
5264 */
5265
5266 /**
5267 * @brief Initialize and Enable the PLL2 according to the specified
5268 * parameters in the RCC_PLL2InitTypeDef.
5269 * @param pPLL2Init pointer to an RCC_PLL2InitTypeDef structure that
5270 * contains the configuration information for the PLL2
5271 * @retval HAL status
5272 */
HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef * pPLL2Init)5273 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *pPLL2Init)
5274 {
5275 uint32_t tickstart;
5276 HAL_StatusTypeDef status = HAL_OK;
5277
5278 /* check for PLL2 Parameters used to output PLL2CLK */
5279 assert_param(IS_RCC_PLL2_SOURCE(pPLL2Init->PLL2Source));
5280 assert_param(IS_RCC_PLL2_DIVM_VALUE(pPLL2Init->PLL2M));
5281 assert_param(IS_RCC_PLL2_MULN_VALUE(pPLL2Init->PLL2N));
5282 assert_param(IS_RCC_PLL2_DIVP_VALUE(pPLL2Init->PLL2P));
5283 assert_param(IS_RCC_PLL2_DIVQ_VALUE(pPLL2Init->PLL2Q));
5284 assert_param(IS_RCC_PLL2_DIVR_VALUE(pPLL2Init->PLL2R));
5285 assert_param(IS_RCC_PLL2_CLOCKOUT_VALUE(pPLL2Init->PLL2ClockOut));
5286 assert_param(IS_RCC_PLL2_VCIRGE_VALUE(pPLL2Init->PLL2RGE));
5287 assert_param(IS_RCC_PLL2_VCORGE_VALUE(pPLL2Init->PLL2VCOSEL));
5288 assert_param(IS_RCC_PLL2_FRACN_VALUE(pPLL2Init->PLL2FRACN));
5289
5290 /* Disable the PLL2 */
5291 __HAL_RCC_PLL2_DISABLE();
5292
5293 /* Get Start Tick*/
5294 tickstart = HAL_GetTick();
5295
5296 /* Wait till PLL2 is ready to be updated */
5297 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
5298 {
5299 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
5300 {
5301 status = HAL_TIMEOUT;
5302 break;
5303 }
5304 }
5305
5306 if (status == HAL_OK)
5307 {
5308 /* Make sure PLL2Source is ready */
5309 status = RCCEx_PLLSource_Enable(pPLL2Init->PLL2Source);
5310
5311 if (status == HAL_OK)
5312 {
5313 /* Configure the PLL2 clock source, multiplication factor N, */
5314 /* and division factors M, P, Q and R */
5315 __HAL_RCC_PLL2_CONFIG(pPLL2Init->PLL2Source, pPLL2Init->PLL2M, pPLL2Init->PLL2N,
5316 pPLL2Init->PLL2P, pPLL2Init->PLL2Q, pPLL2Init->PLL2R);
5317
5318 /* Disable PLL2FRACN . */
5319 __HAL_RCC_PLL2_FRACN_DISABLE();
5320
5321 /* Configure PLL2 FRACN */
5322 __HAL_RCC_PLL2_FRACN_CONFIG(pPLL2Init->PLL2FRACN);
5323
5324 /* Enable PLL2FRACN */
5325 __HAL_RCC_PLL2_FRACN_ENABLE();
5326
5327 /* Select PLL2 input reference frequency range: VCI */
5328 __HAL_RCC_PLL2_VCIRANGE(pPLL2Init->PLL2RGE);
5329
5330 /* Select PLL2 output frequency range : VCO */
5331 __HAL_RCC_PLL2_VCORANGE(pPLL2Init->PLL2VCOSEL);
5332
5333 /* Configure the PLL2 Clock output(s) */
5334 __HAL_RCC_PLL2_CLKOUT_ENABLE(pPLL2Init->PLL2ClockOut);
5335
5336 /* Enable the PLL2 again by setting PLL2ON to 1*/
5337 __HAL_RCC_PLL2_ENABLE();
5338
5339 /* Get Start Tick*/
5340 tickstart = HAL_GetTick();
5341
5342 /* Wait till PLL2 is ready */
5343 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == 0U)
5344 {
5345 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
5346 {
5347 status = HAL_TIMEOUT;
5348 break;
5349 }
5350 }
5351 }
5352 }
5353
5354 return status;
5355 }
5356
5357 /**
5358 * @brief Disable PLL2.
5359 * @retval HAL status
5360 */
HAL_RCCEx_DisablePLL2(void)5361 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
5362 {
5363 uint32_t tickstart;
5364 HAL_StatusTypeDef status = HAL_OK;
5365
5366 /* Disable the PLL2 */
5367 __HAL_RCC_PLL2_DISABLE();
5368
5369 /* Get Start Tick*/
5370 tickstart = HAL_GetTick();
5371
5372 /* Wait till PLL2 is disabled */
5373 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
5374 {
5375 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
5376 {
5377 status = HAL_TIMEOUT;
5378 break;
5379 }
5380 }
5381
5382 /* To save power, disable the PLL2 Source, FRACN and Clock outputs */
5383 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN | RCC_PLL2CFGR_PLL2QEN | RCC_PLL2CFGR_PLL2REN | RCC_PLL2CFGR_PLL2SRC |
5384 RCC_PLL2CFGR_PLL2FRACEN);
5385
5386 return status;
5387 }
5388
5389 #if defined(RCC_CR_PLL3ON)
5390 /**
5391 * @brief Initialize and Enable the PLL3 according to the specified
5392 * parameters in the RCC_PLL3InitTypeDef.
5393 * @param pPLL3Init pointer to an RCC_PLL3InitTypeDef structure that
5394 * contains the configuration information for the PLL3
5395 * @retval HAL status.
5396 */
HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef * pPLL3Init)5397 HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(RCC_PLL3InitTypeDef *pPLL3Init)
5398 {
5399 uint32_t tickstart;
5400 HAL_StatusTypeDef status = HAL_OK;
5401
5402 /* check for PLL3 Parameters used to output PLL3CLK */
5403 assert_param(IS_RCC_PLL3_SOURCE(pPLL3Init->PLL3Source));
5404 assert_param(IS_RCC_PLL3_DIVM_VALUE(pPLL3Init->PLL3M));
5405 assert_param(IS_RCC_PLL3_MULN_VALUE(pPLL3Init->PLL3N));
5406 assert_param(IS_RCC_PLL3_DIVP_VALUE(pPLL3Init->PLL3P));
5407 assert_param(IS_RCC_PLL3_DIVQ_VALUE(pPLL3Init->PLL3Q));
5408 assert_param(IS_RCC_PLL3_DIVR_VALUE(pPLL3Init->PLL3R));
5409 assert_param(IS_RCC_PLL3_CLOCKOUT_VALUE(pPLL3Init->PLL3ClockOut));
5410 assert_param(IS_RCC_PLL3_VCIRGE_VALUE(pPLL3Init->PLL3RGE));
5411 assert_param(IS_RCC_PLL3_VCORGE_VALUE(pPLL3Init->PLL3VCOSEL));
5412 assert_param(IS_RCC_PLL3_FRACN_VALUE(pPLL3Init->PLL3FRACN));
5413
5414 /* Disable the PLL3 */
5415 __HAL_RCC_PLL3_DISABLE();
5416
5417 /* Get Start Tick*/
5418 tickstart = HAL_GetTick();
5419
5420 /* Wait till PLL3 is ready to be updated */
5421 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
5422 {
5423 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
5424 {
5425 status = HAL_TIMEOUT;
5426 break;
5427 }
5428 }
5429
5430 if (status == HAL_OK)
5431 {
5432 /* Make sure PLL3Source is ready */
5433 status = RCCEx_PLLSource_Enable(pPLL3Init->PLL3Source);
5434
5435 if (status == HAL_OK)
5436 {
5437 /* Configure the PLL3 clock source, multiplication factor N, */
5438 /* and division factors M and P */
5439 __HAL_RCC_PLL3_CONFIG(pPLL3Init->PLL3Source, pPLL3Init->PLL3M, pPLL3Init->PLL3N, pPLL3Init->PLL3P,
5440 pPLL3Init->PLL3Q, pPLL3Init->PLL3R);
5441
5442 /* Disable PLL3FRACN . */
5443 __HAL_RCC_PLL3_FRACN_DISABLE();
5444
5445 /* Configure PLL3 FRACN */
5446 __HAL_RCC_PLL3_FRACN_CONFIG(pPLL3Init->PLL3FRACN);
5447
5448 /* Enable PLL3FRACN . */
5449 __HAL_RCC_PLL3_FRACN_ENABLE();
5450
5451 /* Select PLL3 input reference frequency range: VCI */
5452 __HAL_RCC_PLL3_VCIRANGE(pPLL3Init->PLL3RGE);
5453
5454 /* Select PLL3 output frequency range : VCO */
5455 __HAL_RCC_PLL3_VCORANGE(pPLL3Init->PLL3VCOSEL);
5456
5457 /* Configure the PLL3 Clock output(s) */
5458 __HAL_RCC_PLL3_CLKOUT_ENABLE(pPLL3Init->PLL3ClockOut);
5459
5460 /* Enable the PLL3 again by setting PLL3ON to 1*/
5461 __HAL_RCC_PLL3_ENABLE();
5462
5463 /* Get Start Tick*/
5464 tickstart = HAL_GetTick();
5465
5466 /* Wait till PLL3 is ready */
5467 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == 0U)
5468 {
5469 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
5470 {
5471 status = HAL_TIMEOUT;
5472 break;
5473 }
5474 }
5475 }
5476 }
5477
5478 return status;
5479 }
5480
5481
5482 /**
5483 * @brief Disable PLL3.
5484 * @retval HAL status.
5485 */
HAL_RCCEx_DisablePLL3(void)5486 HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void)
5487 {
5488 uint32_t tickstart;
5489 HAL_StatusTypeDef status = HAL_OK;
5490
5491 /* Disable the PLL3 */
5492 __HAL_RCC_PLL3_DISABLE();
5493
5494 /* Get Start Tick*/
5495 tickstart = HAL_GetTick();
5496
5497 /* Wait till PLL3 is ready */
5498 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
5499 {
5500 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
5501 {
5502 status = HAL_TIMEOUT;
5503 break;
5504 }
5505 }
5506
5507 /* To save power, disable the PLL3 Source and Clock outputs */
5508 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN | RCC_PLL3CFGR_PLL3QEN | RCC_PLL3CFGR_PLL3REN | RCC_PLL3CFGR_PLL3SRC |
5509 RCC_PLL3CFGR_PLL3FRACEN);
5510
5511 return status;
5512 }
5513 #endif /* RCC_CR_PLL3ON */
5514
5515 /**
5516 * @brief Configure the oscillator clock source for wakeup from Stop and HSE CSS backup clock.
5517 * @param WakeUpClk Wakeup clock
5518 * This parameter can be one of the following values:
5519 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection
5520 * @arg @ref RCC_STOP_WAKEUPCLOCK_CSI CSI oscillator selection
5521 * @note This function shall not be called after the Clock Security System on HSE has been
5522 * enabled.
5523 * @retval None
5524 */
HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)5525 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
5526 {
5527 assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
5528
5529 __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
5530 }
5531
5532 /**
5533 * @brief Configure the oscillator Kernel clock source for wakeup from Stop
5534 * @param WakeUpClk: Kernel Wakeup clock
5535 * This parameter can be one of the following values:
5536 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
5537 * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection
5538 * @retval None
5539 */
HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)5540 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
5541 {
5542 assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
5543
5544 __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
5545 }
5546
5547 /**
5548 * @brief Enable the LSE Clock Security System.
5549 * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
5550 * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
5551 * clock with HAL_RCCEx_PeriphCLKConfig().
5552 * @retval None
5553 */
HAL_RCCEx_EnableLSECSS(void)5554 void HAL_RCCEx_EnableLSECSS(void)
5555 {
5556 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
5557 }
5558
5559 /**
5560 * @brief Disable the LSE Clock Security System.
5561 * @note LSE Clock Security System can only be disabled after a LSE failure detection.
5562 * @retval None
5563 */
HAL_RCCEx_DisableLSECSS(void)5564 void HAL_RCCEx_DisableLSECSS(void)
5565 {
5566 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
5567 }
5568
5569 /**
5570 * @brief Handle the RCC LSE Clock Security System interrupt request.
5571 * @retval None
5572 */
HAL_RCCEx_LSECSS_IRQHandler(void)5573 void HAL_RCCEx_LSECSS_IRQHandler(void)
5574 {
5575 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) != 0U)
5576 {
5577 /* RCC LSE Clock Security System interrupt user callback */
5578 HAL_RCCEx_LSECSS_Callback();
5579 }
5580 }
5581
5582 /**
5583 * @brief RCCEx LSE Clock Security System interrupt callback.
5584 * @retval none
5585 */
HAL_RCCEx_LSECSS_Callback(void)5586 __weak void HAL_RCCEx_LSECSS_Callback(void)
5587 {
5588 /* NOTE : This function should not be modified, when the callback is needed,
5589 the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
5590 */
5591 }
5592
5593 /**
5594 * @brief Select the Low Speed Microcontroller Clock source to output on LSCO pin (PB2).
5595 * @param LSCOSource specifies the Low Speed clock source to output.
5596 * This parameter can be one of the following values:
5597 * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
5598 * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
5599 * @retval None
5600 */
HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)5601 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
5602 {
5603 GPIO_InitTypeDef GPIO_InitStruct;
5604 FlagStatus backupchanged = RESET;
5605
5606 /* Check the parameters */
5607 assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
5608
5609 /* LSCO Pin Clock Enable */
5610 __LSCO_CLK_ENABLE();
5611
5612 /* Configure the LSCO pin in analog mode */
5613 GPIO_InitStruct.Pin = LSCO_PIN;
5614 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
5615 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
5616 GPIO_InitStruct.Pull = GPIO_NOPULL;
5617 HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct);
5618
5619 /* Update LSCOSEL clock source in Backup Domain control register */
5620 if (HAL_IS_BIT_CLR(PWR->DBPCR, PWR_DBPCR_DBP))
5621 {
5622 HAL_PWR_EnableBkUpAccess();
5623 backupchanged = SET;
5624 }
5625
5626 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
5627
5628 if (backupchanged == SET)
5629 {
5630 HAL_PWR_DisableBkUpAccess();
5631 }
5632 }
5633
5634 /**
5635 * @brief Disable the Low Speed Microcontroller Clock Output.
5636 * @retval None
5637 */
HAL_RCCEx_DisableLSCO(void)5638 void HAL_RCCEx_DisableLSCO(void)
5639 {
5640 FlagStatus backupchanged = RESET;
5641
5642 /* Update LSCOEN bit in Backup Domain control register */
5643 if (HAL_IS_BIT_CLR(PWR->DBPCR, PWR_DBPCR_DBP))
5644 {
5645 /* Enable access to the backup domain */
5646 HAL_PWR_EnableBkUpAccess();
5647 backupchanged = SET;
5648 }
5649
5650 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
5651
5652 /* Restore previous configuration */
5653 if (backupchanged == SET)
5654 {
5655 /* Disable access to the backup domain */
5656 HAL_PWR_DisableBkUpAccess();
5657 }
5658 }
5659
5660 /**
5661 * @}
5662 */
5663
5664 #if defined(CRS)
5665
5666 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
5667 * @brief Extended Clock Recovery System Control functions
5668 *
5669 @verbatim
5670 ===============================================================================
5671 ##### Extended Clock Recovery System Control functions #####
5672 ===============================================================================
5673 [..]
5674 For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
5675
5676 (#) In System clock config, HSI48 needs to be enabled
5677
5678 (#) Enable CRS clock in IP MSP init which will use CRS functions
5679
5680 (#) Call CRS functions as follows:
5681 (##) Prepare synchronization configuration necessary for HSI48 calibration
5682 (+++) Default values can be set for frequency Error Measurement (reload and error limit)
5683 and also HSI48 oscillator smooth trimming.
5684 (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
5685 directly reload value with target and synchronization frequencies values
5686 (##) Call function HAL_RCCEx_CRSConfig which
5687 (+++) Resets CRS registers to their default values.
5688 (+++) Configures CRS registers with synchronization configuration
5689 (+++) Enables automatic calibration and frequency error counter feature
5690 Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
5691 periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
5692 provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
5693 precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
5694 should be used as SYNC signal.
5695
5696 (##) A polling function is provided to wait for complete synchronization
5697 (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
5698 (+++) According to CRS status, user can decide to adjust again the calibration or continue
5699 application if synchronization is OK
5700
5701 (#) User can retrieve information related to synchronization in calling function
5702 HAL_RCCEx_CRSGetSynchronizationInfo()
5703
5704 (#) Regarding synchronization status and synchronization information, user can try a new calibration
5705 in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
5706 Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
5707 it means that the actual frequency is lower than the target (and so, that the TRIM value should be
5708 incremented), while when it is detected during the upcounting phase it means that the actual frequency
5709 is higher (and that the TRIM value should be decremented).
5710
5711 (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
5712 through CRS Handler (CRS_IRQn/CRS_IRQHandler)
5713 (++) Call function HAL_RCCEx_CRSConfig()
5714 (++) Enable CRS_IRQn (thanks to NVIC functions)
5715 (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
5716 (++) Implement CRS status management in the following user callbacks called from
5717 HAL_RCCEx_CRS_IRQHandler():
5718 (+++) HAL_RCCEx_CRS_SyncOkCallback()
5719 (+++) HAL_RCCEx_CRS_SyncWarnCallback()
5720 (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
5721 (+++) HAL_RCCEx_CRS_ErrorCallback()
5722
5723 (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
5724 This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
5725
5726 @endverbatim
5727 * @{
5728 */
5729
5730 /**
5731 * @brief Start automatic synchronization for polling mode
5732 * @param pInit Pointer on RCC_CRSInitTypeDef structure
5733 * @retval None
5734 */
HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef * pInit)5735 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
5736 {
5737 uint32_t value;
5738
5739 /* Check the parameters */
5740 assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
5741 assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
5742 assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
5743 assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
5744 assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
5745 assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
5746
5747 /* CONFIGURATION */
5748
5749 /* Before configuration, reset CRS registers to their default values*/
5750 __HAL_RCC_CRS_FORCE_RESET();
5751 __HAL_RCC_CRS_RELEASE_RESET();
5752
5753 /* Set the SYNCDIV[2:0] bits according to Prescaler value */
5754 /* Set the SYNCSRC[1:0] bits according to Source value */
5755 /* Set the SYNCSPOL bit according to Polarity value */
5756 value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
5757 /* Set the RELOAD[15:0] bits according to ReloadValue value */
5758 value |= pInit->ReloadValue;
5759 /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
5760 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
5761 WRITE_REG(CRS->CFGR, value);
5762
5763 /* Adjust HSI48 oscillator smooth trimming */
5764 /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
5765 MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
5766
5767 /* START AUTOMATIC SYNCHRONIZATION*/
5768
5769 /* Enable Automatic trimming & Frequency error counter */
5770 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
5771 }
5772
5773 /**
5774 * @brief Generate the software synchronization event
5775 * @retval None
5776 */
HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)5777 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
5778 {
5779 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
5780 }
5781
5782 /**
5783 * @brief Return synchronization info
5784 * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
5785 * @retval None
5786 */
HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef * pSynchroInfo)5787 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
5788 {
5789 /* Check the parameter */
5790 assert_param(pSynchroInfo != (void *)NULL);
5791
5792 /* Get the reload value */
5793 pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
5794
5795 /* Get HSI48 oscillator smooth trimming */
5796 pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
5797
5798 /* Get Frequency error capture */
5799 pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
5800
5801 /* Get Frequency error direction */
5802 pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
5803 }
5804
5805 /**
5806 * @brief Wait for CRS Synchronization status.
5807 * @param Timeout Duration of the timeout
5808 * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
5809 * frequency.
5810 * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
5811 * @retval Combination of Synchronization status
5812 * This parameter can be a combination of the following values:
5813 * @arg @ref RCC_CRS_TIMEOUT
5814 * @arg @ref RCC_CRS_SYNCOK
5815 * @arg @ref RCC_CRS_SYNCWARN
5816 * @arg @ref RCC_CRS_SYNCERR
5817 * @arg @ref RCC_CRS_SYNCMISS
5818 * @arg @ref RCC_CRS_TRIMOVF
5819 */
HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)5820 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
5821 {
5822 uint32_t crsstatus = RCC_CRS_NONE;
5823 uint32_t tickstart;
5824
5825 /* Get timeout */
5826 tickstart = HAL_GetTick();
5827
5828 /* Wait for CRS flag or timeout detection */
5829 do
5830 {
5831 if (Timeout != HAL_MAX_DELAY)
5832 {
5833 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
5834 {
5835 crsstatus = RCC_CRS_TIMEOUT;
5836 }
5837 }
5838 /* Check CRS SYNCOK flag */
5839 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
5840 {
5841 /* CRS SYNC event OK */
5842 crsstatus |= RCC_CRS_SYNCOK;
5843
5844 /* Clear CRS SYNC event OK bit */
5845 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
5846 }
5847
5848 /* Check CRS SYNCWARN flag */
5849 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
5850 {
5851 /* CRS SYNC warning */
5852 crsstatus |= RCC_CRS_SYNCWARN;
5853
5854 /* Clear CRS SYNCWARN bit */
5855 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
5856 }
5857
5858 /* Check CRS TRIM overflow flag */
5859 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
5860 {
5861 /* CRS SYNC Error */
5862 crsstatus |= RCC_CRS_TRIMOVF;
5863
5864 /* Clear CRS Error bit */
5865 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
5866 }
5867
5868 /* Check CRS Error flag */
5869 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
5870 {
5871 /* CRS SYNC Error */
5872 crsstatus |= RCC_CRS_SYNCERR;
5873
5874 /* Clear CRS Error bit */
5875 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
5876 }
5877
5878 /* Check CRS SYNC Missed flag */
5879 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
5880 {
5881 /* CRS SYNC Missed */
5882 crsstatus |= RCC_CRS_SYNCMISS;
5883
5884 /* Clear CRS SYNC Missed bit */
5885 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
5886 }
5887
5888 /* Check CRS Expected SYNC flag */
5889 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
5890 {
5891 /* frequency error counter reached a zero value */
5892 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
5893 }
5894 } while (RCC_CRS_NONE == crsstatus);
5895
5896 return crsstatus;
5897 }
5898
5899 /**
5900 * @brief Handle the Clock Recovery System interrupt request.
5901 * @retval None
5902 */
HAL_RCCEx_CRS_IRQHandler(void)5903 void HAL_RCCEx_CRS_IRQHandler(void)
5904 {
5905 uint32_t crserror = RCC_CRS_NONE;
5906 /* Get current IT flags and IT sources values */
5907 uint32_t itflags = READ_REG(CRS->ISR);
5908 uint32_t itsources = READ_REG(CRS->CR);
5909
5910 /* Check CRS SYNCOK flag */
5911 if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
5912 {
5913 /* Clear CRS SYNC event OK flag */
5914 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
5915
5916 /* user callback */
5917 HAL_RCCEx_CRS_SyncOkCallback();
5918 }
5919 /* Check CRS SYNCWARN flag */
5920 else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
5921 {
5922 /* Clear CRS SYNCWARN flag */
5923 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
5924
5925 /* user callback */
5926 HAL_RCCEx_CRS_SyncWarnCallback();
5927 }
5928 /* Check CRS Expected SYNC flag */
5929 else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
5930 {
5931 /* frequency error counter reached a zero value */
5932 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
5933
5934 /* user callback */
5935 HAL_RCCEx_CRS_ExpectedSyncCallback();
5936 }
5937 /* Check CRS Error flags */
5938 else
5939 {
5940 if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
5941 {
5942 if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
5943 {
5944 crserror |= RCC_CRS_SYNCERR;
5945 }
5946 if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
5947 {
5948 crserror |= RCC_CRS_SYNCMISS;
5949 }
5950 if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
5951 {
5952 crserror |= RCC_CRS_TRIMOVF;
5953 }
5954
5955 /* Clear CRS Error flags */
5956 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
5957
5958 /* user error callback */
5959 HAL_RCCEx_CRS_ErrorCallback(crserror);
5960 }
5961 }
5962 }
5963
5964 /**
5965 * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
5966 * @retval none
5967 */
HAL_RCCEx_CRS_SyncOkCallback(void)5968 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
5969 {
5970 /* NOTE : This function should not be modified, when the callback is needed,
5971 the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
5972 */
5973 }
5974
5975 /**
5976 * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
5977 * @retval none
5978 */
HAL_RCCEx_CRS_SyncWarnCallback(void)5979 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
5980 {
5981 /* NOTE : This function should not be modified, when the callback is needed,
5982 the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
5983 */
5984 }
5985
5986 /**
5987 * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
5988 * @retval none
5989 */
HAL_RCCEx_CRS_ExpectedSyncCallback(void)5990 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
5991 {
5992 /* NOTE : This function should not be modified, when the callback is needed,
5993 the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
5994 */
5995 }
5996
5997 /**
5998 * @brief RCCEx Clock Recovery System Error interrupt callback.
5999 * @param Error Combination of Error status.
6000 * This parameter can be a combination of the following values:
6001 * @arg @ref RCC_CRS_SYNCERR
6002 * @arg @ref RCC_CRS_SYNCMISS
6003 * @arg @ref RCC_CRS_TRIMOVF
6004 * @retval none
6005 */
HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)6006 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
6007 {
6008 /* Prevent unused argument(s) compilation warning */
6009 UNUSED(Error);
6010
6011 /* NOTE : This function should not be modified, when the callback is needed,
6012 the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
6013 */
6014 }
6015
6016 /**
6017 * @}
6018 */
6019
6020 #endif /* CRS */
6021
6022 /**
6023 * @}
6024 */
6025
6026 /** @addtogroup RCCEx_Private_Functions
6027 * @{
6028 */
6029
6030 /**
6031 * @brief Enable PLLx source clock and check ready flag
6032 * @param PllSource contains the selected PLLx source clock (HSE, HSI or CSI)
6033 * @retval HAL status
6034 */
RCCEx_PLLSource_Enable(uint32_t PllSource)6035 static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource)
6036 {
6037 uint32_t tickstart;
6038 HAL_StatusTypeDef status = HAL_OK;
6039
6040 switch (PllSource)
6041 {
6042 case RCC_PLLSOURCE_CSI:
6043 /* Check whether CSI in not ready and enable it */
6044 if (READ_BIT(RCC->CR, RCC_CR_CSIRDY) == 0U)
6045 {
6046 /* Enable the Internal Low power oscillator (CSI). */
6047 __HAL_RCC_CSI_ENABLE();
6048
6049 /* Get timeout */
6050 tickstart = HAL_GetTick();
6051
6052 /* Wait till CSI is ready */
6053 while (READ_BIT(RCC->CR, RCC_CR_CSIRDY) == 0U)
6054 {
6055 if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
6056 {
6057 status = HAL_TIMEOUT;
6058 break;
6059 }
6060 }
6061 }
6062 break;
6063
6064 case RCC_PLLSOURCE_HSI:
6065 /* Check whether HSI in not ready and enable it */
6066 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
6067 {
6068 /* Enable the Internal High Speed oscillator (HSI). */
6069 __HAL_RCC_HSI_ENABLE();
6070
6071 /* Get timeout */
6072 tickstart = HAL_GetTick();
6073
6074 /* Wait till HSI is ready */
6075 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
6076 {
6077 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
6078 {
6079 status = HAL_TIMEOUT;
6080 break;
6081 }
6082 }
6083 }
6084 break;
6085
6086 case RCC_PLLSOURCE_HSE:
6087 /* Check whether HSE in not ready and enable it */
6088 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
6089 {
6090 /* Enable the External High Speed oscillator (HSE). */
6091 SET_BIT(RCC->CR, RCC_CR_HSEON);
6092
6093 /* Get Start Tick*/
6094 tickstart = HAL_GetTick();
6095
6096 /* Wait till HSE is ready */
6097 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
6098 {
6099 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
6100 {
6101 status = HAL_TIMEOUT;
6102 break;
6103 }
6104 }
6105 }
6106 break;
6107
6108 default:
6109 status = HAL_ERROR;
6110 break;
6111 }
6112
6113 return status;
6114 }
6115
6116 /**
6117 * @brief Configure the PLL2 VCI/VCO ranges, multiplication and division factors and its output clock(s)
6118 * @param pll2 pointer to an RCC_PLL2InitTypeDef structure that
6119 * contains the configuration parameters M, N, FRACN, VCI/VCO ranges as well as PLL2 output clocks dividers
6120 * @note PLL2 is temporary disabled to apply new parameters
6121 * @retval HAL status
6122 */
RCCEx_PLL2_Config(RCC_PLL2InitTypeDef * pll2)6123 static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2)
6124 {
6125
6126 uint32_t tickstart;
6127 assert_param(IS_RCC_PLL2_SOURCE(pll2->PLL2Source));
6128 assert_param(IS_RCC_PLL2_DIVM_VALUE(pll2->PLL2M));
6129 assert_param(IS_RCC_PLL2_MULN_VALUE(pll2->PLL2N));
6130 assert_param(IS_RCC_PLL2_DIVP_VALUE(pll2->PLL2P));
6131 assert_param(IS_RCC_PLL2_DIVQ_VALUE(pll2->PLL2Q));
6132 assert_param(IS_RCC_PLL2_DIVR_VALUE(pll2->PLL2R));
6133 assert_param(IS_RCC_PLL2_CLOCKOUT_VALUE(pll2->PLL2ClockOut));
6134 assert_param(IS_RCC_PLL2_VCIRGE_VALUE(pll2->PLL2RGE));
6135 assert_param(IS_RCC_PLL2_VCORGE_VALUE(pll2->PLL2VCOSEL));
6136 assert_param(IS_RCC_PLL2_FRACN_VALUE(pll2->PLL2FRACN));
6137
6138 /* Disable PLL2. */
6139 __HAL_RCC_PLL2_DISABLE();
6140
6141 /* Get Start Tick*/
6142 tickstart = HAL_GetTick();
6143
6144 /* Wait till PLL2 is disabled */
6145 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
6146 {
6147 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
6148 {
6149 return HAL_TIMEOUT;
6150 }
6151 }
6152
6153 /* Configure PLL2 multiplication and division factors. */
6154 __HAL_RCC_PLL2_CONFIG(pll2->PLL2Source,
6155 pll2->PLL2M,
6156 pll2->PLL2N,
6157 pll2->PLL2P,
6158 pll2->PLL2Q,
6159 pll2->PLL2R);
6160
6161 /* Select PLL2 input reference frequency range: VCI */
6162 __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE);
6163
6164 /* Select PLL2 output frequency range : VCO */
6165 __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL);
6166
6167 /* Configure the PLL2 Clock output(s) */
6168 __HAL_RCC_PLL2CLKOUT_ENABLE(pll2->PLL2ClockOut);
6169
6170 /* Disable PLL2FRACN . */
6171 __HAL_RCC_PLL2FRACN_DISABLE();
6172
6173 /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
6174 __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
6175
6176 /* Enable PLL2FRACN . */
6177 __HAL_RCC_PLL2FRACN_ENABLE();
6178
6179 /* Enable PLL2. */
6180 __HAL_RCC_PLL2_ENABLE();
6181
6182 /* Get Start Tick*/
6183 tickstart = HAL_GetTick();
6184
6185 /* Wait till PLL2 is ready */
6186 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
6187 {
6188 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
6189 {
6190 return HAL_TIMEOUT;
6191 }
6192 }
6193 return HAL_OK;
6194
6195 }
6196
6197 #if defined(RCC_CR_PLL3ON)
6198 /**
6199 * @brief Configure the PLL3 VCI/VCO ranges, multiplication and division factors and its output clock(s)
6200 * @param pll3 pointer to an RCC_PLL3InitTypeDef structure that
6201 * contains the configuration parameters M, N, FRACN, VCI/VCO ranges as well as PLL3 output clocks dividers
6202 * @note PLL3 is temporary disabled to apply new parameters
6203 * @retval HAL status.
6204 */
RCCEx_PLL3_Config(RCC_PLL3InitTypeDef * pll3)6205 static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3)
6206 {
6207
6208 uint32_t tickstart;
6209 assert_param(IS_RCC_PLL3_SOURCE(pll3->PLL3Source));
6210 assert_param(IS_RCC_PLL3_DIVM_VALUE(pll3->PLL3M));
6211 assert_param(IS_RCC_PLL3_MULN_VALUE(pll3->PLL3N));
6212 assert_param(IS_RCC_PLL3_DIVP_VALUE(pll3->PLL3P));
6213 assert_param(IS_RCC_PLL3_DIVQ_VALUE(pll3->PLL3Q));
6214 assert_param(IS_RCC_PLL3_DIVR_VALUE(pll3->PLL3R));
6215 assert_param(IS_RCC_PLL3_CLOCKOUT_VALUE(pll3->PLL3ClockOut));
6216 assert_param(IS_RCC_PLL3_VCIRGE_VALUE(pll3->PLL3RGE));
6217 assert_param(IS_RCC_PLL3_VCORGE_VALUE(pll3->PLL3VCOSEL));
6218 assert_param(IS_RCC_PLL3_FRACN_VALUE(pll3->PLL3FRACN));
6219
6220 /* Disable PLL3. */
6221 __HAL_RCC_PLL3_DISABLE();
6222
6223 /* Get Start Tick*/
6224 tickstart = HAL_GetTick();
6225
6226 /* Wait till PLL3 is disabled */
6227 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
6228 {
6229 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
6230 {
6231 return HAL_TIMEOUT;
6232 }
6233 }
6234
6235 /* Configure PLL3 multiplication and division factors. */
6236 __HAL_RCC_PLL3_CONFIG(pll3->PLL3Source,
6237 pll3->PLL3M,
6238 pll3->PLL3N,
6239 pll3->PLL3P,
6240 pll3->PLL3Q,
6241 pll3->PLL3R);
6242
6243 /* Select PLL3 input reference frequency range: VCI */
6244 __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
6245
6246 /* Select PLL3 output frequency range : VCO */
6247 __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL);
6248
6249 /* Configure the PLL3 Clock output(s) */
6250 __HAL_RCC_PLL3CLKOUT_ENABLE(pll3->PLL3ClockOut);
6251
6252 /* Disable PLL3FRACN . */
6253 __HAL_RCC_PLL3FRACN_DISABLE();
6254
6255 /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
6256 __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
6257
6258 /* Enable PLL3FRACN . */
6259 __HAL_RCC_PLL3FRACN_ENABLE();
6260
6261 /* Enable PLL3. */
6262 __HAL_RCC_PLL3_ENABLE();
6263
6264 /* Get Start Tick*/
6265 tickstart = HAL_GetTick();
6266
6267 /* Wait till PLL3 is ready */
6268 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
6269 {
6270 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
6271 {
6272 return HAL_TIMEOUT;
6273 }
6274 }
6275 return HAL_OK;
6276 }
6277 #endif /* RCC_CR_PLL3ON */
6278
6279 /**
6280 * @}
6281 */
6282
6283 #endif /* HAL_RCC_MODULE_ENABLED */
6284 /**
6285 * @}
6286 */
6287
6288 /**
6289 * @}
6290 */
6291
