1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_lptim.c
4 * @author MCD Application Team
5 * @brief LPTIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Low Power Timer (LPTIM) peripheral:
8 * + Initialization and de-initialization functions.
9 * + Start/Stop operation functions in polling mode.
10 * + Start/Stop operation functions in interrupt mode.
11 * + Reading operation functions.
12 * + Peripheral State functions.
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2022 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### How to use this driver #####
28 ==============================================================================
29 [..]
30 The LPTIM HAL driver can be used as follows:
31
32 (#)Initialize the LPTIM low level resources by implementing the
33 HAL_LPTIM_MspInit():
34 (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
35 (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
36 (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
37 (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
38 (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
39
40 (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
41 configures mainly:
42 (++) The instance: LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5 or LPTIM6.
43 (++) Clock: the counter clock.
44 (+++) Source : it can be either the ULPTIM input (IN1) or one of
45 the internal clock; (APB, LSE, LSI or CSI).
46 (+++) Prescaler: select the clock divider.
47 (++) UltraLowPowerClock : To be used only if the ULPTIM is selected
48 as counter clock source.
49 (+++) Polarity: polarity of the active edge for the counter unit
50 if the ULPTIM input is selected.
51 (+++) SampleTime: clock sampling time to configure the clock glitch
52 filter.
53 (++) Trigger: How the counter start.
54 (+++) Source: trigger can be software or one of the hardware triggers.
55 (+++) ActiveEdge : only for hardware trigger.
56 (+++) SampleTime : trigger sampling time to configure the trigger
57 glitch filter.
58 (++) OutputPolarity : 2 opposite polarities are possible.
59 (++) UpdateMode: specifies whether the update of the autoreload and
60 the compare values is done immediately or after the end of current
61 period.
62 (++) Input1Source: Source selected for input1 (GPIO or comparator output).
63 (++) Input2Source: Source selected for input2 (GPIO or comparator output).
64 Input2 is used only for encoder feature so is used only for LPTIM1 instance.
65
66 (#)Six modes are available:
67
68 (++) PWM Mode: To generate a PWM signal with specified period and pulse,
69 call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
70 mode.
71
72 (++) One Pulse Mode: To generate pulse with specified width in response
73 to a stimulus, call HAL_LPTIM_OnePulse_Start() or
74 HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
75
76 (++) Set once Mode: In this mode, the output changes the level (from
77 low level to high level if the output polarity is configured high, else
78 the opposite) when a compare match occurs. To start this mode, call
79 HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
80 interruption mode.
81
82 (++) Encoder Mode: To use the encoder interface call
83 HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
84 interruption mode. Only available for LPTIM1 instance.
85
86 (++) Time out Mode: an active edge on one selected trigger input rests
87 the counter. The first trigger event will start the timer, any
88 successive trigger event will reset the counter and the timer will
89 restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
90 HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
91
92 (++) Counter Mode: counter can be used to count external events on
93 the LPTIM Input1 or it can be used to count internal clock cycles.
94 To start this mode, call HAL_LPTIM_Counter_Start() or
95 HAL_LPTIM_Counter_Start_IT() for interruption mode.
96
97
98 (#) User can stop any process by calling the corresponding API:
99 HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
100 already started in interruption mode.
101
102 (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
103
104 *** Callback registration ***
105 =============================================
106 [..]
107 The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
108 allows the user to configure dynamically the driver callbacks.
109 [..]
110 Use Function HAL_LPTIM_RegisterCallback() to register a callback.
111 HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
112 the Callback ID and a pointer to the user callback function.
113 [..]
114 Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the
115 default weak function.
116 HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
117 and the Callback ID.
118 [..]
119 These functions allow to register/unregister following callbacks:
120
121 (+) MspInitCallback : LPTIM Base Msp Init Callback.
122 (+) MspDeInitCallback : LPTIM Base Msp DeInit Callback.
123 (+) CompareMatchCallback : Compare match Callback.
124 (+) AutoReloadMatchCallback : Auto-reload match Callback.
125 (+) TriggerCallback : External trigger event detection Callback.
126 (+) CompareWriteCallback : Compare register write complete Callback.
127 (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
128 (+) DirectionUpCallback : Up-counting direction change Callback.
129 (+) DirectionDownCallback : Down-counting direction change Callback.
130 (+) UpdateEventCallback : Update event detection Callback.
131 (+) RepCounterWriteCallback : Repetition counter register write complete Callback.
132
133 [..]
134 By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
135 all interrupt callbacks are set to the corresponding weak functions:
136 examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback().
137
138 [..]
139 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
140 functionalities in the Init/DeInit only when these callbacks are null
141 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
142 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
143
144 [..]
145 Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
146 Exception done MspInit/MspDeInit that can be registered/unregistered
147 in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
148 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
149 In that case first register the MspInit/MspDeInit user callbacks
150 using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
151
152 [..]
153 When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
154 not defined, the callback registration feature is not available and all callbacks
155 are set to the corresponding weak functions.
156
157 @endverbatim
158 ******************************************************************************
159 */
160
161 /* Includes ------------------------------------------------------------------*/
162 #include "stm32h5xx_hal.h"
163
164 /** @addtogroup STM32H5xx_HAL_Driver
165 * @{
166 */
167
168 /** @defgroup LPTIM LPTIM
169 * @brief LPTIM HAL module driver.
170 * @{
171 */
172
173 #ifdef HAL_LPTIM_MODULE_ENABLED
174
175 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5) || defined (LPTIM6)
176
177 /* Private typedef -----------------------------------------------------------*/
178 /* Private define ------------------------------------------------------------*/
179 /** @addtogroup LPTIM_Private_Constants
180 * @{
181 */
182 #define TIMEOUT 1000UL /* Timeout is 1s */
183 /**
184 * @}
185 */
186
187 /* Private macro -------------------------------------------------------------*/
188 /* Private variables ---------------------------------------------------------*/
189 /* Private function prototypes -----------------------------------------------*/
190 static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig);
191 static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig);
192 static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig);
193 static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig);
194 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
195 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
196 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
197 static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag);
198 void LPTIM_DMAError(DMA_HandleTypeDef *hdma);
199 void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
200 void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
201 void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma);
202 void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma);
203 HAL_StatusTypeDef LPTIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
204 uint32_t length);
205
206 /* Exported functions --------------------------------------------------------*/
207
208 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
209 * @{
210 */
211
212 /** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
213 * @brief Initialization and Configuration functions.
214 *
215 @verbatim
216 ==============================================================================
217 ##### Initialization and de-initialization functions #####
218 ==============================================================================
219 [..] This section provides functions allowing to:
220 (+) Initialize the LPTIM according to the specified parameters in the
221 LPTIM_InitTypeDef and initialize the associated handle.
222 (+) DeInitialize the LPTIM peripheral.
223 (+) Initialize the LPTIM MSP.
224 (+) DeInitialize the LPTIM MSP.
225
226 @endverbatim
227 * @{
228 */
229
230 /**
231 * @brief Initialize the LPTIM according to the specified parameters in the
232 * LPTIM_InitTypeDef and initialize the associated handle.
233 * @param hlptim LPTIM handle
234 * @retval HAL status
235 */
HAL_LPTIM_Init(LPTIM_HandleTypeDef * hlptim)236 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
237 {
238 uint32_t tmpcfgr;
239
240 /* Check the LPTIM handle allocation */
241 if (hlptim == NULL)
242 {
243 return HAL_ERROR;
244 }
245
246 /* Check the parameters */
247 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
248 assert_param(IS_LPTIM_PERIOD(hlptim->Init.Period));
249
250 assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
251 assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
252 if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
253 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
254 {
255 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
256 assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
257 }
258 assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
259 if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
260 {
261 assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
262 assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
263 }
264 assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
265 assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
266 assert_param(IS_LPTIM_REPETITION(hlptim->Init.RepetitionCounter));
267
268 if (hlptim->State == HAL_LPTIM_STATE_RESET)
269 {
270 /* Allocate lock resource and initialize it */
271 hlptim->Lock = HAL_UNLOCKED;
272
273 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
274 /* Reset interrupt callbacks to legacy weak callbacks */
275 LPTIM_ResetCallback(hlptim);
276
277 if (hlptim->MspInitCallback == NULL)
278 {
279 hlptim->MspInitCallback = HAL_LPTIM_MspInit;
280 }
281
282 /* Init the low level hardware : GPIO, CLOCK, NVIC */
283 hlptim->MspInitCallback(hlptim);
284 #else
285 /* Init the low level hardware : GPIO, CLOCK, NVIC */
286 HAL_LPTIM_MspInit(hlptim);
287 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
288 }
289
290 /* Change the LPTIM state */
291 hlptim->State = HAL_LPTIM_STATE_BUSY;
292
293 /* Enable the Peripheral */
294 __HAL_LPTIM_ENABLE(hlptim);
295
296 /* Clear flag */
297 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK);
298
299 /* Set the repetition counter */
300 __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter);
301
302 /* Wait for the completion of the write operation to the LPTIM_RCR register */
303 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_REPOK) == HAL_TIMEOUT)
304 {
305 return HAL_TIMEOUT;
306 }
307
308
309 /* Clear flag */
310 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
311
312 /* Set LPTIM Period */
313 __HAL_LPTIM_AUTORELOAD_SET(hlptim, hlptim->Init.Period);
314
315 /* Wait for the completion of the write operation to the LPTIM_ARR register */
316 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
317 {
318 return HAL_TIMEOUT;
319 }
320
321 /* Disable the Peripheral */
322 __HAL_LPTIM_DISABLE(hlptim);
323
324 /* Get the LPTIMx CFGR value */
325 tmpcfgr = hlptim->Instance->CFGR;
326
327 if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
328 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
329 {
330 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
331 }
332 if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
333 {
334 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
335 }
336
337 /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
338 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
339 LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
340
341 /* Set initialization parameters */
342 tmpcfgr |= (hlptim->Init.Clock.Source |
343 hlptim->Init.Clock.Prescaler |
344 hlptim->Init.UpdateMode |
345 hlptim->Init.CounterSource);
346
347 /* Glitch filters for internal triggers and external inputs are configured
348 * only if an internal clock source is provided to the LPTIM
349 */
350 if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
351 {
352 tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
353 hlptim->Init.UltraLowPowerClock.SampleTime);
354 }
355
356 /* Configure LPTIM external clock polarity and digital filter */
357 if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
358 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
359 {
360 tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
361 hlptim->Init.UltraLowPowerClock.SampleTime);
362 }
363
364 /* Configure LPTIM external trigger */
365 if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
366 {
367 /* Enable External trigger and set the trigger source */
368 tmpcfgr |= (hlptim->Init.Trigger.Source |
369 hlptim->Init.Trigger.ActiveEdge |
370 hlptim->Init.Trigger.SampleTime);
371 }
372
373 /* Write to LPTIMx CFGR */
374 hlptim->Instance->CFGR = tmpcfgr;
375
376 /* Configure LPTIM input sources */
377 if ((hlptim->Instance == LPTIM1) || (hlptim->Instance == LPTIM2))
378 {
379 /* Check LPTIM Input1 and Input2 sources */
380 assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
381 assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance, hlptim->Init.Input2Source));
382
383 /* Configure LPTIM Input1 and Input2 sources */
384 hlptim->Instance->CFGR2 = (hlptim->Init.Input1Source | hlptim->Init.Input2Source);
385 }
386 else
387 {
388 /* Check LPTIM2 Input1 source */
389 assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
390
391 /* Configure LPTIM2 Input1 source */
392 hlptim->Instance->CFGR2 = hlptim->Init.Input1Source;
393 }
394
395 /* Initialize the LPTIM channels state */
396 LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_READY);
397
398 /* Change the LPTIM state */
399 hlptim->State = HAL_LPTIM_STATE_READY;
400
401 /* Return function status */
402 return HAL_OK;
403 }
404
405 /**
406 * @brief DeInitialize the LPTIM peripheral.
407 * @param hlptim LPTIM handle
408 * @retval HAL status
409 */
HAL_LPTIM_DeInit(LPTIM_HandleTypeDef * hlptim)410 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
411 {
412 /* Check the LPTIM handle allocation */
413 if (hlptim == NULL)
414 {
415 return HAL_ERROR;
416 }
417
418 /* Change the LPTIM state */
419 hlptim->State = HAL_LPTIM_STATE_BUSY;
420
421 __HAL_LPTIM_ENABLE(hlptim);
422 if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
423 {
424 hlptim->Instance->CCMR1 = 0;
425 }
426
427 /* Clear flag */
428 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
429
430 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, 0);
431 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
432 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
433 {
434 return HAL_TIMEOUT;
435 }
436
437 if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
438 {
439 /* Clear flag */
440 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
441
442 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, 0);
443 /* Wait for the completion of the write operation to the LPTIM_CCR2 register */
444 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) == HAL_TIMEOUT)
445 {
446 return HAL_TIMEOUT;
447 }
448 }
449
450 /* Clear flag */
451 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
452
453 __HAL_LPTIM_AUTORELOAD_SET(hlptim, 0);
454
455 /* Wait for the completion of the write operation to the LPTIM_ARR register */
456 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
457 {
458 return HAL_TIMEOUT;
459 }
460
461 /* Disable the LPTIM Peripheral Clock */
462 __HAL_LPTIM_DISABLE(hlptim);
463
464 hlptim->Instance->CFGR = 0;
465 hlptim->Instance->CFGR2 = 0;
466
467 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
468 if (hlptim->MspDeInitCallback == NULL)
469 {
470 hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
471 }
472
473 /* DeInit the low level hardware: CLOCK, NVIC.*/
474 hlptim->MspDeInitCallback(hlptim);
475 #else
476 /* DeInit the low level hardware: CLOCK, NVIC.*/
477 HAL_LPTIM_MspDeInit(hlptim);
478 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
479
480 /* Change the LPTIM channels state */
481 LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_RESET);
482
483 /* Change the LPTIM state */
484 hlptim->State = HAL_LPTIM_STATE_RESET;
485
486 /* Release Lock */
487 __HAL_UNLOCK(hlptim);
488
489 /* Return function status */
490 return HAL_OK;
491 }
492
493 /**
494 * @brief Initialize the LPTIM MSP.
495 * @param hlptim LPTIM handle
496 * @retval None
497 */
HAL_LPTIM_MspInit(LPTIM_HandleTypeDef * hlptim)498 __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
499 {
500 /* Prevent unused argument(s) compilation warning */
501 UNUSED(hlptim);
502
503 /* NOTE : This function should not be modified, when the callback is needed,
504 the HAL_LPTIM_MspInit could be implemented in the user file
505 */
506 }
507
508 /**
509 * @brief DeInitialize LPTIM MSP.
510 * @param hlptim LPTIM handle
511 * @retval None
512 */
HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef * hlptim)513 __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
514 {
515 /* Prevent unused argument(s) compilation warning */
516 UNUSED(hlptim);
517
518 /* NOTE : This function should not be modified, when the callback is needed,
519 the HAL_LPTIM_MspDeInit could be implemented in the user file
520 */
521 }
522
523 /**
524 * @}
525 */
526
527 /** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
528 * @brief Start-Stop operation functions.
529 *
530 @verbatim
531 ==============================================================================
532 ##### LPTIM Start Stop operation functions #####
533 ==============================================================================
534 [..] This section provides functions allowing to:
535 (+) Start the PWM mode.
536 (+) Stop the PWM mode.
537 (+) Start the One pulse mode.
538 (+) Stop the One pulse mode.
539 (+) Start the Set once mode.
540 (+) Stop the Set once mode.
541 (+) Start the Encoder mode.
542 (+) Stop the Encoder mode.
543 (+) Start the Timeout mode.
544 (+) Stop the Timeout mode.
545 (+) Start the Counter mode.
546 (+) Stop the Counter mode.
547
548
549 @endverbatim
550 * @{
551 */
552
553 /**
554 * @brief Start the LPTIM PWM generation.
555 * @param hlptim LPTIM handle
556 * @param Channel LPTIM Channel to be enabled
557 * This parameter can be one of the following values:
558 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
559 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
560 * @retval HAL status
561 */
HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)562 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
563 {
564 /* Check the parameters */
565 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
566
567 /* Check LPTIM channel state */
568 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
569 {
570 return HAL_ERROR;
571 }
572
573 /* Set the LPTIM state */
574 hlptim->State = HAL_LPTIM_STATE_BUSY;
575
576 /* Set the LPTIM channel state */
577 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
578
579 /* Reset WAVE bit to set PWM mode */
580 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
581
582 /* Enable the Peripheral */
583 __HAL_LPTIM_ENABLE(hlptim);
584
585 /* Enable LPTIM signal on the corresponding output pin */
586 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
587
588 /* Start timer in continuous mode */
589 __HAL_LPTIM_START_CONTINUOUS(hlptim);
590
591 /* Change the LPTIM state */
592 hlptim->State = HAL_LPTIM_STATE_READY;
593
594 /* Return function status */
595 return HAL_OK;
596 }
597
598 /**
599 * @brief Stop the LPTIM PWM generation.
600 * @param hlptim LPTIM handle
601 * @param Channel LPTIM Channel to be disabled
602 * This parameter can be one of the following values:
603 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
604 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
605 * @retval HAL status
606 */
HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)607 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
608 {
609 /* Check the parameters */
610 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
611
612 /* Change the LPTIM state */
613 hlptim->State = HAL_LPTIM_STATE_BUSY;
614
615 /* Disable LPTIM signal from the corresponding output pin */
616 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
617
618 /* Disable the Peripheral */
619 __HAL_LPTIM_DISABLE(hlptim);
620
621 /* Set the LPTIM channel state */
622 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
623
624 /* Set the LPTIM state */
625 hlptim->State = HAL_LPTIM_STATE_READY;
626
627 /* Return function status */
628 return HAL_OK;
629 }
630
631 /**
632 * @brief Start the LPTIM PWM generation in interrupt mode.
633 * @param hlptim LPTIM handle
634 * @param Channel LPTIM Channel to be enabled
635 * This parameter can be one of the following values:
636 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
637 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
638 * @retval HAL status
639 */
HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)640 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
641 {
642 /* Check the parameters */
643 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
644
645 /* Check LPTIM channel state */
646 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
647 {
648 return HAL_ERROR;
649 }
650
651 /* Set the LPTIM state */
652 hlptim->State = HAL_LPTIM_STATE_BUSY;
653
654 /* Set the LPTIM channel state */
655 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
656
657 /* Reset WAVE bit to set PWM mode */
658 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
659
660 /* Enable the Peripheral */
661 __HAL_LPTIM_ENABLE(hlptim);
662 /* Clear flag */
663 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
664
665 switch (Channel)
666 {
667 case LPTIM_CHANNEL_1:
668 /* Enable interrupt */
669 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
670 LPTIM_IT_UPDATE);
671 break;
672 case LPTIM_CHANNEL_2:
673 /* Enable interrupt */
674 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
675 LPTIM_IT_UPDATE);
676 break;
677 default:
678 break;
679 }
680
681 /* Wait for the completion of the write operation to the LPTIM_DIER register */
682 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
683 {
684 return HAL_TIMEOUT;
685 }
686
687 /* If external trigger source is used, then enable external trigger interrupt */
688 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
689 {
690 /* Clear flag */
691 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
692
693 /* Enable external trigger interrupt */
694 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
695
696 /* Wait for the completion of the write operation to the LPTIM_DIER register */
697 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
698 {
699 return HAL_TIMEOUT;
700 }
701 }
702
703 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
704
705 /* Start timer in continuous mode */
706 __HAL_LPTIM_START_CONTINUOUS(hlptim);
707
708 /* Change the LPTIM state */
709 hlptim->State = HAL_LPTIM_STATE_READY;
710
711 /* Return function status */
712 return HAL_OK;
713 }
714
715 /**
716 * @brief Stop the LPTIM PWM generation in interrupt mode.
717 * @param hlptim LPTIM handle
718 * @param Channel LPTIM Channel to be disabled
719 * This parameter can be one of the following values:
720 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
721 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
722 * @retval HAL status
723 */
HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)724 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
725 {
726 /* Check the parameters */
727 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
728
729 /* Change the LPTIM state */
730 hlptim->State = HAL_LPTIM_STATE_BUSY;
731
732 /* Disable LPTIM signal from the corresponding output pin */
733 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
734
735 /* Disable the Peripheral */
736 __HAL_LPTIM_DISABLE(hlptim);
737
738 /* Enable the Peripheral */
739 __HAL_LPTIM_ENABLE(hlptim);
740
741 /* Clear flag */
742 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
743
744 switch (Channel)
745 {
746 case LPTIM_CHANNEL_1:
747 /* Disable interrupt */
748 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
749 LPTIM_IT_UPDATE);
750 break;
751 case LPTIM_CHANNEL_2:
752 /* Disable interrupt */
753 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
754 LPTIM_IT_UPDATE);
755 break;
756 default:
757 break;
758 }
759
760 /* Wait for the completion of the write operation to the LPTIM_DIER register */
761 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
762 {
763 return HAL_TIMEOUT;
764 }
765
766 /* If external trigger source is used, then enable external trigger interrupt */
767 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
768 {
769 /* Clear flag */
770 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
771
772 /* Enable external trigger interrupt */
773 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
774
775 /* Wait for the completion of the write operation to the LPTIM_DIER register */
776 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
777 {
778 return HAL_TIMEOUT;
779 }
780 }
781
782 /* Disable the Peripheral */
783 __HAL_LPTIM_DISABLE(hlptim);
784
785 /* Set the LPTIM channel state */
786 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
787
788 /* Set the LPTIM state */
789 hlptim->State = HAL_LPTIM_STATE_READY;
790
791 /* Return function status */
792 return HAL_OK;
793 }
794
795 /**
796 * @brief Start the LPTIM PWM generation in DMA mode.
797 * @param hlptim LPTIM handle
798 * @param Channel LPTIM Channel to be enabled
799 * This parameter can be one of the following values:
800 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
801 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
802 * @param pData The destination Buffer address
803 * @param Length The length of data to be transferred from LPTIM peripheral to memory
804 * @retval HAL status
805 */
HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel,const uint32_t * pData,uint32_t Length)806 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, const uint32_t *pData,
807 uint32_t Length)
808 {
809 DMA_HandleTypeDef *hdma;
810
811 /* Check the parameters */
812 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
813 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
814
815 if ((pData == NULL) || (Length == 0U))
816 {
817 return HAL_ERROR;
818 }
819
820 /* Check LPTIM channel state */
821 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
822 {
823 return HAL_ERROR;
824 }
825
826 /* Set the LPTIM state */
827 hlptim->State = HAL_LPTIM_STATE_BUSY;
828
829 /* Set the LPTIM channel state */
830 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
831
832 /* Reset WAVE bit to set PWM mode */
833 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
834
835 /* Enable the Peripheral */
836 __HAL_LPTIM_ENABLE(hlptim);
837
838 /* Enable update event DMA request */
839 __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_UPDATE);
840
841 /* Wait for the completion of the write operation to the LPTIM_DIER register */
842 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
843 {
844 return HAL_TIMEOUT;
845 }
846
847 switch (Channel)
848 {
849 case LPTIM_CHANNEL_1:
850 /* Set the DMA update event callbacks */
851 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMAUpdateEventCplt;
852 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt;
853
854 /* Set the DMA error callback */
855 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError;
856
857 /* Enable the DMA Channel */
858 hdma = hlptim->hdma[LPTIM_DMA_ID_CC1];
859 if (LPTIM_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR1, Length) != HAL_OK)
860 {
861 /* Return error status */
862 return HAL_ERROR;
863 }
864 break;
865 case LPTIM_CHANNEL_2:
866 /* Set the DMA update event callbacks */
867 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMAUpdateEventCplt;
868 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt;
869
870 /* Set the DMA error callback */
871 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError;
872
873 /* Enable the DMA Channel */
874 hdma = hlptim->hdma[LPTIM_DMA_ID_CC2];
875 if (LPTIM_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR2, Length) != HAL_OK)
876 {
877 /* Return error status */
878 return HAL_ERROR;
879 }
880 break;
881 default:
882 break;
883 }
884
885 /* Enable LPTIM signal on the corresponding output pin */
886 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
887
888 /* Start timer in continuous mode */
889 __HAL_LPTIM_START_CONTINUOUS(hlptim);
890
891 /* Change the LPTIM state */
892 hlptim->State = HAL_LPTIM_STATE_READY;
893
894 /* Return function status */
895 return HAL_OK;
896 }
897
898 /**
899 * @brief Stop the LPTIM PWM generation in DMA mode.
900 * @param hlptim LPTIM handle
901 * @param Channel LPTIM Channel to be disabled
902 * This parameter can be one of the following values:
903 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
904 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
905 * @retval HAL status
906 */
HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)907 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
908 {
909 /* Check the parameters */
910 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
911 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
912
913 /* Change the LPTIM state */
914 hlptim->State = HAL_LPTIM_STATE_BUSY;
915
916 /* Disable update event DMA request */
917 __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_UPDATE);
918
919 switch (Channel)
920 {
921 case LPTIM_CHANNEL_1:
922 /* Disable update event DMA request */
923 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]);
924 break;
925 case LPTIM_CHANNEL_2:
926 /* Disable update event DMA request */
927 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]);
928 break;
929 default:
930 break;
931 }
932
933 /* Disable LPTIM signal from the corresponding output pin */
934 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
935
936 /* Disable the Peripheral */
937 __HAL_LPTIM_DISABLE(hlptim);
938
939 /* Set the LPTIM channel state */
940 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
941
942 /* Set the LPTIM state */
943 hlptim->State = HAL_LPTIM_STATE_READY;
944
945 /* Return function status */
946 return HAL_OK;
947 }
948
949 /**
950 * @brief Start the LPTIM One pulse generation.
951 * @param hlptim LPTIM handle
952 * @param Channel LPTIM Channel to be enabled
953 * This parameter can be one of the following values:
954 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
955 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
956 * @retval HAL status
957 */
HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)958 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
959 {
960 /* Check the parameters */
961 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
962
963 /* Check LPTIM channel state */
964 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
965 {
966 return HAL_ERROR;
967 }
968
969 /* Set the LPTIM state */
970 hlptim->State = HAL_LPTIM_STATE_BUSY;
971
972 /* Set the LPTIM channel state */
973 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
974
975 /* Reset WAVE bit to set one pulse mode */
976 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
977
978 /* Enable the Peripheral */
979 __HAL_LPTIM_ENABLE(hlptim);
980
981 /* Enable LPTIM signal on the corresponding output pin */
982 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
983
984 /* Start timer in single (one shot) mode */
985 __HAL_LPTIM_START_SINGLE(hlptim);
986
987 /* Change the LPTIM state */
988 hlptim->State = HAL_LPTIM_STATE_READY;
989
990 /* Return function status */
991 return HAL_OK;
992 }
993
994 /**
995 * @brief Stop the LPTIM One pulse generation.
996 * @param hlptim LPTIM handle
997 * @param Channel LPTIM Channel to be disabled
998 * This parameter can be one of the following values:
999 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1000 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1001 * @retval HAL status
1002 */
HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1003 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1004 {
1005 /* Check the parameters */
1006 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1007
1008 /* Set the LPTIM state */
1009 hlptim->State = HAL_LPTIM_STATE_BUSY;
1010
1011 /* Disable LPTIM signal on the corresponding output pin */
1012 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1013
1014 /* Disable the Peripheral */
1015 __HAL_LPTIM_DISABLE(hlptim);
1016
1017 /* Set the LPTIM channel state */
1018 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1019
1020 /* Set the LPTIM state */
1021 hlptim->State = HAL_LPTIM_STATE_READY;
1022
1023 /* Return function status */
1024 return HAL_OK;
1025 }
1026
1027 /**
1028 * @brief Start the LPTIM One pulse generation in interrupt mode.
1029 * @param hlptim LPTIM handle
1030 * @param Channel LPTIM Channel to be enabled
1031 * This parameter can be one of the following values:
1032 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1033 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1034 * @retval HAL status
1035 */
HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1036 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1037 {
1038 /* Check the parameters */
1039 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1040
1041 /* Check LPTIM channel state */
1042 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1043 {
1044 return HAL_ERROR;
1045 }
1046
1047 /* Set the LPTIM state */
1048 hlptim->State = HAL_LPTIM_STATE_BUSY;
1049
1050 /* Set the LPTIM channel state */
1051 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1052
1053 /* Reset WAVE bit to set one pulse mode */
1054 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
1055
1056 /* Enable the Peripheral */
1057 __HAL_LPTIM_ENABLE(hlptim);
1058
1059 /* Clear flag */
1060 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1061
1062 switch (Channel)
1063 {
1064 case LPTIM_CHANNEL_1:
1065 /* Enable interrupt */
1066 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1067 LPTIM_IT_UPDATE);
1068 break;
1069 case LPTIM_CHANNEL_2:
1070 /* Enable interrupt */
1071 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1072 LPTIM_IT_UPDATE);
1073 break;
1074 default:
1075 break;
1076 }
1077
1078 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1079 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1080 {
1081 return HAL_TIMEOUT;
1082 }
1083
1084 /* If external trigger source is used, then enable external trigger interrupt */
1085 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1086 {
1087 /* Clear flag */
1088 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1089 /* Enable external trigger interrupt */
1090 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1091 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1092 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1093 {
1094 return HAL_TIMEOUT;
1095 }
1096 }
1097
1098 /* Enable LPTIM signal on the corresponding output pin */
1099 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1100
1101 /* Start timer in single (one shot) mode */
1102 __HAL_LPTIM_START_SINGLE(hlptim);
1103
1104 /* Change the LPTIM state */
1105 hlptim->State = HAL_LPTIM_STATE_READY;
1106
1107 /* Return function status */
1108 return HAL_OK;
1109 }
1110
1111 /**
1112 * @brief Stop the LPTIM One pulse generation in interrupt mode.
1113 * @param hlptim LPTIM handle
1114 * @param Channel LPTIM Channel to be disabled
1115 * This parameter can be one of the following values:
1116 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1117 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1118 * @retval HAL status
1119 */
HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1120 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1121 {
1122 /* Check the parameters */
1123 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1124
1125 /* Set the LPTIM state */
1126 hlptim->State = HAL_LPTIM_STATE_BUSY;
1127
1128 /* Disable LPTIM signal on the corresponding output pin */
1129 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1130
1131 /* Disable the Peripheral */
1132 __HAL_LPTIM_DISABLE(hlptim);
1133
1134
1135 /* Enable the Peripheral */
1136 __HAL_LPTIM_ENABLE(hlptim);
1137
1138 /* Clear flag */
1139 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1140
1141 switch (Channel)
1142 {
1143 case LPTIM_CHANNEL_1:
1144 /* Disable interrupt */
1145 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1146 LPTIM_IT_UPDATE);
1147 break;
1148 case LPTIM_CHANNEL_2:
1149 /* Disable interrupt */
1150 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1151 LPTIM_IT_UPDATE);
1152 break;
1153 default:
1154 break;
1155 }
1156
1157 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1158 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1159 {
1160 return HAL_TIMEOUT;
1161 }
1162
1163 /* If external trigger source is used, then enable external trigger interrupt */
1164 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1165 {
1166 /* Clear flag */
1167 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1168 /* Enable external trigger interrupt */
1169 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1170 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1171 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1172 {
1173 return HAL_TIMEOUT;
1174 }
1175 }
1176
1177 /* Disable the Peripheral */
1178 __HAL_LPTIM_DISABLE(hlptim);
1179
1180 /* Set the LPTIM channel state */
1181 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1182
1183 /* Set the LPTIM state */
1184 hlptim->State = HAL_LPTIM_STATE_READY;
1185
1186 /* Return function status */
1187 return HAL_OK;
1188 }
1189
1190 /**
1191 * @brief Start the LPTIM in Set once mode.
1192 * @param hlptim LPTIM handle
1193 * @param Channel LPTIM Channel to be enabled
1194 * This parameter can be one of the following values:
1195 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1196 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1197 * @retval HAL status
1198 */
HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1199 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1200 {
1201 /* Check the parameters */
1202 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1203
1204 /* Check LPTIM channel state */
1205 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1206 {
1207 return HAL_ERROR;
1208 }
1209
1210 /* Set the LPTIM state */
1211 hlptim->State = HAL_LPTIM_STATE_BUSY;
1212
1213 /* Set the LPTIM channel state */
1214 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1215
1216 /* Set WAVE bit to enable the set once mode */
1217 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
1218
1219 /* Enable the Peripheral */
1220 __HAL_LPTIM_ENABLE(hlptim);
1221
1222 /* Enable LPTIM signal on the corresponding output pin */
1223 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1224
1225 /* Start timer in single (one shot) mode */
1226 __HAL_LPTIM_START_SINGLE(hlptim);
1227
1228 /* Change the LPTIM state */
1229 hlptim->State = HAL_LPTIM_STATE_READY;
1230
1231 /* Return function status */
1232 return HAL_OK;
1233 }
1234
1235 /**
1236 * @brief Stop the LPTIM Set once mode.
1237 * @param hlptim LPTIM handle
1238 * @param Channel LPTIM Channel to be disabled
1239 * This parameter can be one of the following values:
1240 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1241 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1242 * @retval HAL status
1243 */
HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1244 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1245 {
1246 /* Check the parameters */
1247 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1248
1249 /* Set the LPTIM state */
1250 hlptim->State = HAL_LPTIM_STATE_BUSY;
1251
1252 /* Disable LPTIM signal on the corresponding output pin */
1253 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1254
1255 /* Disable the Peripheral */
1256 __HAL_LPTIM_DISABLE(hlptim);
1257
1258 /* Set the LPTIM channel state */
1259 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1260
1261 /* Set the LPTIM state */
1262 hlptim->State = HAL_LPTIM_STATE_READY;
1263
1264 /* Return function status */
1265 return HAL_OK;
1266 }
1267
1268 /**
1269 * @brief Start the LPTIM Set once mode in interrupt mode.
1270 * @param hlptim LPTIM handle
1271 * @param Channel LPTIM Channel to be enabled
1272 * This parameter can be one of the following values:
1273 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1274 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1275 * @retval HAL status
1276 */
HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1277 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1278 {
1279 /* Check the parameters */
1280 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1281
1282 /* Check LPTIM channel state */
1283 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1284 {
1285 return HAL_ERROR;
1286 }
1287
1288 /* Set the LPTIM state */
1289 hlptim->State = HAL_LPTIM_STATE_BUSY;
1290
1291 /* Set the LPTIM channel state */
1292 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1293
1294 /* Set WAVE bit to enable the set once mode */
1295 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
1296
1297 /* Enable the Peripheral */
1298 __HAL_LPTIM_ENABLE(hlptim);
1299
1300 /* Clear flag */
1301 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1302
1303 switch (Channel)
1304 {
1305 case LPTIM_CHANNEL_1:
1306 /* Enable interrupt */
1307 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE);
1308 break;
1309 case LPTIM_CHANNEL_2:
1310 /* Enable interrupt */
1311 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE);
1312 break;
1313 default:
1314 break;
1315 }
1316
1317 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1318 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1319 {
1320 return HAL_TIMEOUT;
1321 }
1322
1323 /* If external trigger source is used, then enable external trigger interrupt */
1324 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1325 {
1326 /* Clear flag */
1327 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1328 /* Enable external trigger interrupt */
1329 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1330 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1331 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1332 {
1333 return HAL_TIMEOUT;
1334 }
1335 }
1336
1337 /* Enable LPTIM signal on the corresponding output pin */
1338 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1339
1340 /* Start timer in single (one shot) mode */
1341 __HAL_LPTIM_START_SINGLE(hlptim);
1342
1343 /* Change the LPTIM state */
1344 hlptim->State = HAL_LPTIM_STATE_READY;
1345
1346 /* Return function status */
1347 return HAL_OK;
1348 }
1349
1350 /**
1351 * @brief Stop the LPTIM Set once mode in interrupt mode.
1352 * @param hlptim LPTIM handle
1353 * @param Channel LPTIM Channel to be disabled
1354 * This parameter can be one of the following values:
1355 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1356 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1357 * @retval HAL status
1358 */
HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1359 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1360 {
1361 /* Check the parameters */
1362 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1363
1364 /* Set the LPTIM state */
1365 hlptim->State = HAL_LPTIM_STATE_BUSY;
1366
1367 /* Disable LPTIM signal on the corresponding output pin */
1368 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1369
1370 /* Disable the Peripheral */
1371 __HAL_LPTIM_DISABLE(hlptim);
1372
1373 /* Enable the Peripheral */
1374 __HAL_LPTIM_ENABLE(hlptim);
1375
1376 /* Clear flag */
1377 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1378
1379 switch (Channel)
1380 {
1381 case LPTIM_CHANNEL_1:
1382 /* Disable interrupt */
1383 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM);
1384 break;
1385 case LPTIM_CHANNEL_2:
1386 /* Disable interrupt */
1387 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM);
1388 break;
1389 default:
1390 break;
1391 }
1392
1393 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1394 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1395 {
1396 return HAL_TIMEOUT;
1397 }
1398
1399 /* If external trigger source is used, then enable external trigger interrupt */
1400 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1401 {
1402 /* Clear flag */
1403 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1404 /* Enable external trigger interrupt */
1405 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1406
1407 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1408 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1409 {
1410 return HAL_TIMEOUT;
1411 }
1412 }
1413
1414 /* Disable the Peripheral */
1415 __HAL_LPTIM_DISABLE(hlptim);
1416
1417 /* Set the LPTIM channel state */
1418 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1419
1420 /* Set the LPTIM state */
1421 hlptim->State = HAL_LPTIM_STATE_READY;
1422
1423 /* Return function status */
1424 return HAL_OK;
1425 }
1426
1427 /**
1428 * @brief Start the Encoder interface.
1429 * @param hlptim LPTIM handle
1430 * @retval HAL status
1431 */
HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef * hlptim)1432 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim)
1433 {
1434 uint32_t tmpcfgr;
1435
1436 /* Check the parameters */
1437 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1438 assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
1439 assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
1440 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
1441
1442 /* Set the LPTIM state */
1443 hlptim->State = HAL_LPTIM_STATE_BUSY;
1444
1445 /* Get the LPTIMx CFGR value */
1446 tmpcfgr = hlptim->Instance->CFGR;
1447
1448 /* Clear CKPOL bits */
1449 tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
1450
1451 /* Set Input polarity */
1452 tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
1453
1454 /* Write to LPTIMx CFGR */
1455 hlptim->Instance->CFGR = tmpcfgr;
1456
1457 /* Set ENC bit to enable the encoder interface */
1458 hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
1459
1460 /* Enable the Peripheral */
1461 __HAL_LPTIM_ENABLE(hlptim);
1462
1463 /* Start timer in continuous mode */
1464 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1465
1466 /* Change the LPTIM state */
1467 hlptim->State = HAL_LPTIM_STATE_READY;
1468
1469 /* Return function status */
1470 return HAL_OK;
1471 }
1472
1473 /**
1474 * @brief Stop the Encoder interface.
1475 * @param hlptim LPTIM handle
1476 * @retval HAL status
1477 */
HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef * hlptim)1478 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
1479 {
1480 /* Check the parameters */
1481 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1482
1483 /* Set the LPTIM state */
1484 hlptim->State = HAL_LPTIM_STATE_BUSY;
1485
1486 /* Disable the Peripheral */
1487 __HAL_LPTIM_DISABLE(hlptim);
1488
1489 /* Reset ENC bit to disable the encoder interface */
1490 hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
1491
1492 /* Change the LPTIM state */
1493 hlptim->State = HAL_LPTIM_STATE_READY;
1494
1495 /* Return function status */
1496 return HAL_OK;
1497 }
1498
1499 /**
1500 * @brief Start the Encoder interface in interrupt mode.
1501 * @param hlptim LPTIM handle
1502 * @retval HAL status
1503 */
HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef * hlptim)1504 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim)
1505 {
1506 uint32_t tmpcfgr;
1507
1508 /* Check the parameters */
1509 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1510 assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
1511 assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
1512 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
1513
1514 /* Set the LPTIM state */
1515 hlptim->State = HAL_LPTIM_STATE_BUSY;
1516
1517 /* Configure edge sensitivity for encoder mode */
1518 /* Get the LPTIMx CFGR value */
1519 tmpcfgr = hlptim->Instance->CFGR;
1520
1521 /* Clear CKPOL bits */
1522 tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
1523
1524 /* Set Input polarity */
1525 tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
1526
1527 /* Write to LPTIMx CFGR */
1528 hlptim->Instance->CFGR = tmpcfgr;
1529
1530 /* Set ENC bit to enable the encoder interface */
1531 hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
1532
1533 /* Enable the Peripheral */
1534 __HAL_LPTIM_ENABLE(hlptim);
1535
1536 /* Clear flag */
1537 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1538
1539 /* Enable "switch to up/down direction" interrupt */
1540 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN);
1541
1542 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1543 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1544 {
1545 return HAL_TIMEOUT;
1546 }
1547
1548
1549 /* Start timer in continuous mode */
1550 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1551
1552 /* Change the LPTIM state */
1553 hlptim->State = HAL_LPTIM_STATE_READY;
1554
1555 /* Return function status */
1556 return HAL_OK;
1557 }
1558
1559 /**
1560 * @brief Stop the Encoder interface in interrupt mode.
1561 * @param hlptim LPTIM handle
1562 * @retval HAL status
1563 */
HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef * hlptim)1564 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
1565 {
1566 /* Check the parameters */
1567 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1568
1569 /* Set the LPTIM state */
1570 hlptim->State = HAL_LPTIM_STATE_BUSY;
1571
1572 /* Disable the Peripheral */
1573 __HAL_LPTIM_DISABLE(hlptim);
1574
1575 /* Reset ENC bit to disable the encoder interface */
1576 hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
1577 /* Enable the Peripheral */
1578 __HAL_LPTIM_ENABLE(hlptim);
1579
1580 /* Clear flag */
1581 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1582
1583 /* Disable "switch to down/up direction" interrupt */
1584 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN);
1585
1586 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1587 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1588 {
1589 return HAL_TIMEOUT;
1590 }
1591
1592 /* Disable the Peripheral */
1593 __HAL_LPTIM_DISABLE(hlptim);
1594
1595 /* Change the LPTIM state */
1596 hlptim->State = HAL_LPTIM_STATE_READY;
1597
1598 /* Return function status */
1599 return HAL_OK;
1600 }
1601
1602 /**
1603 * @brief Start the Timeout function.
1604 * @note The first trigger event will start the timer, any successive
1605 * trigger event will reset the counter and the timer restarts.
1606 * @param hlptim LPTIM handle
1607 * @param Timeout Specifies the TimeOut value to reset the counter.
1608 * This parameter must be a value between 0x0000 and 0xFFFF.
1609 * @retval HAL status
1610 */
HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Timeout)1611 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout)
1612 {
1613 /* Check the parameters */
1614 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1615 assert_param(IS_LPTIM_PULSE(Timeout));
1616
1617 /* Set the LPTIM state */
1618 hlptim->State = HAL_LPTIM_STATE_BUSY;
1619
1620 /* Set TIMOUT bit to enable the timeout function */
1621 hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
1622
1623 /* Enable the Peripheral */
1624 __HAL_LPTIM_ENABLE(hlptim);
1625
1626 /* Clear flag */
1627 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
1628
1629 /* Load the Timeout value in the compare register */
1630 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout);
1631
1632 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
1633 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
1634 {
1635 return HAL_TIMEOUT;
1636 }
1637
1638 /* Start timer in continuous mode */
1639 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1640
1641 /* Change the LPTIM state */
1642 hlptim->State = HAL_LPTIM_STATE_READY;
1643
1644 /* Return function status */
1645 return HAL_OK;
1646 }
1647
1648 /**
1649 * @brief Stop the Timeout function.
1650 * @param hlptim LPTIM handle
1651 * @retval HAL status
1652 */
HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef * hlptim)1653 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
1654 {
1655 /* Check the parameters */
1656 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1657
1658 /* Set the LPTIM state */
1659 hlptim->State = HAL_LPTIM_STATE_BUSY;
1660
1661 /* Disable the Peripheral */
1662 __HAL_LPTIM_DISABLE(hlptim);
1663
1664 /* Reset TIMOUT bit to enable the timeout function */
1665 hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
1666
1667 /* Change the LPTIM state */
1668 hlptim->State = HAL_LPTIM_STATE_READY;
1669
1670 /* Return function status */
1671 return HAL_OK;
1672 }
1673
1674 /**
1675 * @brief Start the Timeout function in interrupt mode.
1676 * @note The first trigger event will start the timer, any successive
1677 * trigger event will reset the counter and the timer restarts.
1678 * @param hlptim LPTIM handle
1679 * @param Timeout Specifies the TimeOut value to reset the counter.
1680 * This parameter must be a value between 0x0000 and 0xFFFF.
1681 * @retval HAL status
1682 */
HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Timeout)1683 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout)
1684 {
1685 /* Check the parameters */
1686 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1687 assert_param(IS_LPTIM_PULSE(Timeout));
1688
1689 /* Set the LPTIM state */
1690 hlptim->State = HAL_LPTIM_STATE_BUSY;
1691
1692 /* Set TIMOUT bit to enable the timeout function */
1693 hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
1694
1695 /* Enable the Peripheral */
1696 __HAL_LPTIM_ENABLE(hlptim);
1697
1698 /* Clear flag */
1699 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1700
1701 /* Enable Compare match CH1 interrupt */
1702 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1);
1703
1704 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1705 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1706 {
1707 return HAL_TIMEOUT;
1708 }
1709
1710 /* Clear flag */
1711 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
1712
1713 /* Load the Timeout value in the compare register */
1714 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout);
1715
1716 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
1717 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
1718 {
1719 return HAL_TIMEOUT;
1720 }
1721
1722 /* Start timer in continuous mode */
1723 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1724
1725 /* Change the LPTIM state */
1726 hlptim->State = HAL_LPTIM_STATE_READY;
1727
1728 /* Return function status */
1729 return HAL_OK;
1730 }
1731
1732 /**
1733 * @brief Stop the Timeout function in interrupt mode.
1734 * @param hlptim LPTIM handle
1735 * @retval HAL status
1736 */
HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef * hlptim)1737 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
1738 {
1739 /* Check the parameters */
1740 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1741
1742 /* Set the LPTIM state */
1743 hlptim->State = HAL_LPTIM_STATE_BUSY;
1744
1745 /* Disable the Peripheral */
1746 __HAL_LPTIM_DISABLE(hlptim);
1747
1748 /* Reset TIMOUT bit to enable the timeout function */
1749 hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
1750
1751 /* Enable the Peripheral */
1752 __HAL_LPTIM_ENABLE(hlptim);
1753
1754 /* Clear flag */
1755 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1756
1757 /* Disable Compare match CH1 interrupt */
1758 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1);
1759
1760 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1761 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1762 {
1763 return HAL_TIMEOUT;
1764 }
1765
1766 /* Disable the Peripheral */
1767 __HAL_LPTIM_DISABLE(hlptim);
1768
1769 /* Change the LPTIM state */
1770 hlptim->State = HAL_LPTIM_STATE_READY;
1771
1772 /* Return function status */
1773 return HAL_OK;
1774 }
1775
1776 /**
1777 * @brief Start the Counter mode.
1778 * @param hlptim LPTIM handle
1779 * @retval HAL status
1780 */
HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef * hlptim)1781 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim)
1782 {
1783 /* Check the parameters */
1784 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1785
1786 /* Set the LPTIM state */
1787 hlptim->State = HAL_LPTIM_STATE_BUSY;
1788
1789 /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
1790 if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
1791 && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
1792 {
1793 /* Check if clock is prescaled */
1794 assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
1795 /* Set clock prescaler to 0 */
1796 hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
1797 }
1798
1799 /* Enable the Peripheral */
1800 __HAL_LPTIM_ENABLE(hlptim);
1801
1802 /* Start timer in continuous mode */
1803 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1804
1805 /* Change the LPTIM state */
1806 hlptim->State = HAL_LPTIM_STATE_READY;
1807
1808 /* Return function status */
1809 return HAL_OK;
1810 }
1811
1812 /**
1813 * @brief Stop the Counter mode.
1814 * @param hlptim LPTIM handle
1815 * @retval HAL status
1816 */
HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef * hlptim)1817 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
1818 {
1819 /* Check the parameters */
1820 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1821
1822 /* Set the LPTIM state */
1823 hlptim->State = HAL_LPTIM_STATE_BUSY;
1824
1825 /* Disable the Peripheral */
1826 __HAL_LPTIM_DISABLE(hlptim);
1827
1828 /* Change the LPTIM state */
1829 hlptim->State = HAL_LPTIM_STATE_READY;
1830
1831 /* Return function status */
1832 return HAL_OK;
1833 }
1834
1835 /**
1836 * @brief Start the Counter mode in interrupt mode.
1837 * @param hlptim LPTIM handle
1838 * @retval HAL status
1839 */
HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef * hlptim)1840 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim)
1841 {
1842 /* Check the parameters */
1843 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1844
1845 /* Set the LPTIM state */
1846 hlptim->State = HAL_LPTIM_STATE_BUSY;
1847
1848 /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
1849 if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
1850 && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
1851 {
1852 /* Check if clock is prescaled */
1853 assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
1854 /* Set clock prescaler to 0 */
1855 hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
1856 }
1857
1858 /* Enable the Peripheral */
1859 __HAL_LPTIM_ENABLE(hlptim);
1860
1861 /* Clear flag */
1862 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1863
1864 /* Enable interrupt */
1865 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE);
1866
1867 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1868 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1869 {
1870 return HAL_TIMEOUT;
1871 }
1872
1873 /* Start timer in continuous mode */
1874 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1875
1876 /* Change the LPTIM state */
1877 hlptim->State = HAL_LPTIM_STATE_READY;
1878
1879 /* Return function status */
1880 return HAL_OK;
1881 }
1882
1883 /**
1884 * @brief Stop the Counter mode in interrupt mode.
1885 * @param hlptim LPTIM handle
1886 * @retval HAL status
1887 */
HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef * hlptim)1888 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
1889 {
1890 /* Check the parameters */
1891 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1892
1893 /* Set the LPTIM state */
1894 hlptim->State = HAL_LPTIM_STATE_BUSY;
1895
1896 /* Disable the Peripheral */
1897 __HAL_LPTIM_DISABLE(hlptim);
1898
1899
1900 /* Enable the Peripheral */
1901 __HAL_LPTIM_ENABLE(hlptim);
1902
1903 /* Clear flag */
1904 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1905
1906 /* Disable interrupt */
1907 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE);
1908
1909 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1910 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1911 {
1912 return HAL_TIMEOUT;
1913 }
1914
1915 /* Disable the Peripheral */
1916 __HAL_LPTIM_DISABLE(hlptim);
1917
1918 /* Change the LPTIM state */
1919 hlptim->State = HAL_LPTIM_STATE_READY;
1920
1921 /* Return function status */
1922 return HAL_OK;
1923 }
1924
1925 /**
1926 * @brief Starts the LPTIM Input Capture measurement.
1927 * @param hlptim LPTIM Input Capture handle
1928 * @param Channel LPTIM Channels to be enabled
1929 * This parameter can be one of the following values:
1930 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
1931 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
1932 * @retval HAL status
1933 */
HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1934 HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1935 {
1936 /* Check the parameters */
1937 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
1938 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1939
1940 /* Check LPTIM channel state */
1941 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1942 {
1943 return HAL_ERROR;
1944 }
1945
1946 /* Set the LPTIM state */
1947 hlptim->State = HAL_LPTIM_STATE_BUSY;
1948
1949 /* Set the LPTIM channel state */
1950 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1951
1952 /* Enable the Peripheral */
1953 __HAL_LPTIM_ENABLE(hlptim);
1954
1955 /* Start timer in continuous mode */
1956 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1957
1958 /* Enable capture */
1959 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1960
1961 /* Change the LPTIM state */
1962 hlptim->State = HAL_LPTIM_STATE_READY;
1963
1964 /* Return function status */
1965 return HAL_OK;
1966 }
1967
1968 /**
1969 * @brief Stops the LPTIM Input Capture measurement.
1970 * @param hlptim LPTIM Input Capture handle
1971 * @param Channel LPTIM Channels to be disabled
1972 * This parameter can be one of the following values:
1973 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
1974 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
1975 * @retval HAL status
1976 */
HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1977 HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1978 {
1979 /* Check the parameters */
1980 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
1981 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1982
1983 /* Set the LPTIM state */
1984 hlptim->State = HAL_LPTIM_STATE_BUSY;
1985
1986 /* Disable capture */
1987 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1988
1989 /* Disable the Peripheral */
1990 __HAL_LPTIM_DISABLE(hlptim);
1991
1992 /* Set the LPTIM channel state */
1993 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1994
1995 /* Set the LPTIM state */
1996 hlptim->State = HAL_LPTIM_STATE_READY;
1997
1998 /* Return function status */
1999 return HAL_OK;
2000 }
2001
2002 /**
2003 * @brief Starts the LPTIM Input Capture measurement in interrupt mode.
2004 * @param hlptim LPTIM Input Capture handle
2005 * @param Channel LPTIM Channels to be enabled
2006 * This parameter can be one of the following values:
2007 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2008 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2009 * @retval HAL status
2010 */
HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2011 HAL_StatusTypeDef HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2012 {
2013 /* Check the parameters */
2014 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
2015 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2016
2017 /* Check LPTIM channel state */
2018 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
2019 {
2020 return HAL_ERROR;
2021 }
2022
2023 /* Set the LPTIM state */
2024 hlptim->State = HAL_LPTIM_STATE_BUSY;
2025
2026 /* Set the LPTIM channel state */
2027 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
2028
2029 /* Enable the Peripheral */
2030 __HAL_LPTIM_ENABLE(hlptim);
2031
2032 switch (Channel)
2033 {
2034 case LPTIM_CHANNEL_1:
2035 /* Enable Capture/Compare 1 interrupt */
2036 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1);
2037 break;
2038 case LPTIM_CHANNEL_2:
2039 /* Disable Capture/Compare 2 interrupt */
2040 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC2);
2041 break;
2042 default:
2043 break;
2044 }
2045
2046 /* Wait for the completion of the write operation to the LPTIM_DIER register */
2047 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
2048 {
2049 return HAL_TIMEOUT;
2050 }
2051
2052 /* Start timer in continuous mode */
2053 __HAL_LPTIM_START_CONTINUOUS(hlptim);
2054
2055 /* Enable capture */
2056 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
2057
2058 /* Set the LPTIM state */
2059 hlptim->State = HAL_LPTIM_STATE_READY;
2060
2061 /* Return function status */
2062 return HAL_OK;
2063 }
2064
2065 /**
2066 * @brief Stops the LPTIM Input Capture measurement in interrupt mode.
2067 * @param hlptim LPTIM Input Capture handle
2068 * @param Channel LPTIM Channels to be disabled
2069 * This parameter can be one of the following values:
2070 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2071 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2072 * @retval HAL status
2073 */
HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2074 HAL_StatusTypeDef HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2075 {
2076 /* Check the parameters */
2077 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
2078 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2079
2080 /* Set the LPTIM state */
2081 hlptim->State = HAL_LPTIM_STATE_BUSY;
2082
2083 switch (Channel)
2084 {
2085 case LPTIM_CHANNEL_1:
2086 /* Disable Capture/Compare 1 interrupt */
2087 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1);
2088 break;
2089 case LPTIM_CHANNEL_2:
2090 /* Disable Capture/Compare 2 interrupt */
2091 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC2);
2092 break;
2093 default:
2094 return HAL_ERROR;
2095 break;
2096 }
2097 /* Disable capture */
2098 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
2099
2100 /* Disable the Peripheral */
2101 __HAL_LPTIM_DISABLE(hlptim);
2102
2103 /* Set the LPTIM channel state */
2104 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
2105
2106 /* Set the LPTIM state */
2107 hlptim->State = HAL_LPTIM_STATE_READY;
2108
2109 /* Return function status */
2110 return HAL_OK;
2111 }
2112
2113 /**
2114 * @brief Starts the LPTIM Input Capture measurement in DMA mode.
2115 * @param hlptim LPTIM Input Capture handle
2116 * @param Channel LPTIM Channels to be enabled
2117 * This parameter can be one of the following values:
2118 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2119 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2120 * @param pData The destination Buffer address
2121 * @param Length The length of data to be transferred from LPTIM peripheral to memory
2122 * @retval HAL status
2123 */
HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel,uint32_t * pData,uint32_t Length)2124 HAL_StatusTypeDef HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData,
2125 uint32_t Length)
2126 {
2127 DMA_HandleTypeDef *hdma;
2128
2129 /* Check the parameters */
2130 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
2131 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2132
2133 if ((pData == NULL) || (Length == 0U))
2134 {
2135 return HAL_ERROR;
2136 }
2137
2138 /* Check LPTIM channel state */
2139 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
2140 {
2141 return HAL_ERROR;
2142 }
2143
2144 /* Set the LPTIM state */
2145 hlptim->State = HAL_LPTIM_STATE_BUSY;
2146
2147 /* Set the LPTIM channel state */
2148 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
2149
2150 /* Enable the Peripheral */
2151 __HAL_LPTIM_ENABLE(hlptim);
2152
2153 switch (Channel)
2154 {
2155 case LPTIM_CHANNEL_1:
2156 /* Set the DMA capture callbacks */
2157 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMACaptureCplt;
2158 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt;
2159
2160 /* Set the DMA error callback */
2161 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError;
2162
2163 /* Enable the DMA Channel */
2164 hdma = hlptim->hdma[LPTIM_DMA_ID_CC1];
2165 if (LPTIM_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
2166 {
2167 /* Return error status */
2168 return HAL_ERROR;
2169 }
2170
2171 /* Enable Capture/Compare 1 DMA request */
2172 __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC1);
2173 break;
2174
2175 case LPTIM_CHANNEL_2:
2176 /* Set the DMA capture callbacks */
2177 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMACaptureCplt;
2178 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt;
2179
2180 /* Set the DMA error callback */
2181 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError;
2182
2183 /* Enable the DMA Channel */
2184 hdma = hlptim->hdma[LPTIM_DMA_ID_CC2];
2185 if (LPTIM_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
2186 {
2187 /* Return error status */
2188 return HAL_ERROR;
2189 }
2190
2191 /* Enable Capture/Compare 2 DMA request */
2192 __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC2);
2193 break;
2194
2195 default:
2196 break;
2197 }
2198
2199 /* Wait for the completion of the write operation to the LPTIM_DIER register */
2200 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
2201 {
2202 return HAL_TIMEOUT;
2203 }
2204
2205 /* Start timer in continuous mode */
2206 __HAL_LPTIM_START_CONTINUOUS(hlptim);
2207
2208 /* Enable capture */
2209 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
2210
2211 /* Set the LPTIM state */
2212 hlptim->State = HAL_LPTIM_STATE_READY;
2213
2214 /* Return function status */
2215 return HAL_OK;
2216 }
2217
2218 /**
2219 * @brief Stops the LPTIM Input Capture measurement in DMA mode.
2220 * @param hlptim LPTIM Input Capture handle
2221 * @param Channel LPTIM Channels to be disabled
2222 * This parameter can be one of the following values:
2223 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2224 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2225 * @retval HAL status
2226 */
HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2227 HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2228 {
2229 /* Check the parameters */
2230 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
2231 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2232
2233 /* Set the LPTIM state */
2234 hlptim->State = HAL_LPTIM_STATE_BUSY;
2235
2236 switch (Channel)
2237 {
2238 case LPTIM_CHANNEL_1:
2239 /* Disable Capture/Compare 1 DMA request */
2240 __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC1);
2241 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]);
2242 break;
2243
2244 case LPTIM_CHANNEL_2:
2245 /* Disable Capture/Compare 2 DMA request */
2246 __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC2);
2247 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]);
2248 break;
2249 default:
2250 return HAL_ERROR;
2251 break;
2252 }
2253
2254 /* Disable capture */
2255 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
2256
2257 /* Disable the Peripheral */
2258 __HAL_LPTIM_DISABLE(hlptim);
2259
2260 /* Set the LPTIM channel state */
2261 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
2262
2263 /* Set the LPTIM state */
2264 hlptim->State = HAL_LPTIM_STATE_READY;
2265
2266 /* Return function status */
2267 return HAL_OK;
2268 }
2269 /**
2270 * @}
2271 */
2272
2273 /** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
2274 * @brief Read operation functions.
2275 *
2276 @verbatim
2277 ==============================================================================
2278 ##### LPTIM Read operation functions #####
2279 ==============================================================================
2280 [..] This section provides LPTIM Reading functions.
2281 (+) Read the counter value.
2282 (+) Read the period (Auto-reload) value.
2283 (+) Read the pulse (Compare)value.
2284 @endverbatim
2285 * @{
2286 */
2287
2288 /**
2289 * @brief Return the current counter value.
2290 * @param hlptim LPTIM handle
2291 * @retval Counter value.
2292 */
HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef * hlptim)2293 uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim)
2294 {
2295 /* Check the parameters */
2296 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
2297
2298 return (hlptim->Instance->CNT);
2299 }
2300
2301 /**
2302 * @brief Return the current Autoreload (Period) value.
2303 * @param hlptim LPTIM handle
2304 * @retval Autoreload value.
2305 */
HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef * hlptim)2306 uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim)
2307 {
2308 /* Check the parameters */
2309 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
2310
2311 return (hlptim->Instance->ARR);
2312 }
2313
2314 /**
2315 * @brief Return the current Compare (Pulse) value.
2316 * @param hlptim LPTIM handle
2317 * @param Channel LPTIM Channel to be selected
2318 * This parameter can be one of the following values:
2319 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2320 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2321 * @retval Compare value.
2322 */
HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2323 uint32_t HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2324 {
2325 uint32_t tmpccr;
2326
2327 /* Check the parameters */
2328 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2329
2330 switch (Channel)
2331 {
2332 case LPTIM_CHANNEL_1:
2333 tmpccr = hlptim->Instance->CCR1;
2334 break;
2335 case LPTIM_CHANNEL_2:
2336 tmpccr = hlptim->Instance->CCR2;
2337 break;
2338 default:
2339 tmpccr = 0;
2340 break;
2341 }
2342 return tmpccr;
2343 }
2344
2345 /**
2346 * @brief LPTimer Input Capture Get Offset(in counter step unit)
2347 * @note The real capture value corresponding to the input capture trigger can be calculated using
2348 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
2349 * The Offset value is depending on the glitch filter value for the channel
2350 * and the value of the prescaler for the kernel clock.
2351 * Please check Errata Sheet V1_8 for more details under "variable latency
2352 * on input capture channel" section.
2353 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
2354 * the configuration information for LPTIM module.
2355 * @param Channel This parameter can be one of the following values:
2356 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2357 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2358 * @retval The offset value
2359 */
HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2360 uint8_t HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2361 {
2362
2363 uint8_t offset ;
2364 uint32_t prescaler;
2365 uint32_t filter ;
2366
2367 /* Get prescaler value */
2368 prescaler = LL_LPTIM_GetPrescaler(hlptim->Instance);
2369
2370 /* Get filter value */
2371 filter = LL_LPTIM_IC_GetFilter(hlptim->Instance, Channel);
2372
2373 /* Get offset value */
2374 offset = LL_LPTIM_IC_GET_OFFSET(prescaler, filter);
2375
2376 /* return offset value */
2377 return offset;
2378 }
2379
2380 /**
2381 * @}
2382 */
2383 /** @defgroup LPTIM_Exported_Functions_Group5 LPTIM Config function
2384 * @brief Config channel
2385 *
2386 @verbatim
2387 ==============================================================================
2388 ##### LPTIM Config function #####
2389 ==============================================================================
2390 [..] This section provides LPTIM Config function.
2391 (+) Configure channel: Output Compare mode, Period, Polarity.
2392 @endverbatim
2393 * @{
2394 */
2395
2396 /**
2397 * @brief
2398 * @param hlptim LPTIM handle
2399 * @param sConfig The output configuration structure
2400 * @param Channel LPTIM Channel to be configured
2401 * This parameter can be one of the following values:
2402 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2403 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2404 * @retval HAL status
2405 */
HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef * hlptim,const LPTIM_OC_ConfigTypeDef * sConfig,uint32_t Channel)2406 HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig,
2407 uint32_t Channel)
2408 {
2409 HAL_StatusTypeDef status;
2410 /* Check the parameters */
2411 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2412 assert_param(IS_LPTIM_OC_POLARITY(sConfig->OCPolarity));
2413 assert_param(IS_LPTIM_PULSE(sConfig->Pulse));
2414
2415 hlptim->State = HAL_LPTIM_STATE_BUSY;
2416
2417 switch (Channel)
2418 {
2419 case LPTIM_CHANNEL_1:
2420 {
2421 /* Check the parameters */
2422 assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance));
2423
2424 /* Configure the LPTIM Channel 1 in Output Compare */
2425 status = LPTIM_OC1_SetConfig(hlptim, sConfig);
2426 if (status != HAL_OK)
2427 {
2428 return status;
2429 }
2430 break;
2431 }
2432 case LPTIM_CHANNEL_2:
2433 {
2434 /* Check the parameters */
2435 assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance));
2436
2437 /* Configure the LPTIM Channel 2 in Output Compare */
2438 status = LPTIM_OC2_SetConfig(hlptim, sConfig);
2439 if (status != HAL_OK)
2440 {
2441 return status;
2442 }
2443 break;
2444 }
2445 default:
2446 break;
2447 }
2448
2449 /* Change the LPTIM state */
2450 hlptim->State = HAL_LPTIM_STATE_READY;
2451
2452 /* Return function status */
2453 return HAL_OK;
2454 }
2455
2456 /**
2457 * @brief
2458 * @param hlptim LPTIM handle
2459 * @param sConfig The input configuration structure
2460 * @param Channel LPTIM Channel to be configured
2461 * This parameter can be one of the following values:
2462 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2463 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2464 * @retval HAL status
2465 */
HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef * hlptim,const LPTIM_IC_ConfigTypeDef * sConfig,uint32_t Channel)2466 HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig,
2467 uint32_t Channel)
2468 {
2469 /* Check the parameters */
2470 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2471 assert_param(IS_LPTIM_IC_PRESCALER(sConfig->ICPrescaler));
2472 assert_param(IS_LPTIM_IC_POLARITY(sConfig->ICPolarity));
2473 assert_param(IS_LPTIM_IC_FILTER(sConfig->ICFilter));
2474
2475 hlptim->State = HAL_LPTIM_STATE_BUSY;
2476
2477 switch (Channel)
2478 {
2479 case LPTIM_CHANNEL_1:
2480 {
2481 /* Check the parameters */
2482 assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance));
2483 assert_param(IS_LPTIM_IC1_SOURCE(hlptim->Instance, sConfig->ICInputSource));
2484
2485 /* Configure the LPTIM Channel 1 in Input Capture */
2486 LPTIM_IC1_SetConfig(hlptim, sConfig);
2487 break;
2488 }
2489 case LPTIM_CHANNEL_2:
2490 {
2491 /* Check the parameters */
2492 assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance));
2493 assert_param(IS_LPTIM_IC2_SOURCE(hlptim->Instance, sConfig->ICInputSource));
2494
2495 /* Configure the LPTIM Channel 2 in Input Capture */
2496 LPTIM_IC2_SetConfig(hlptim, sConfig);
2497 break;
2498 }
2499 default:
2500 break;
2501 }
2502
2503 /* Change the LPTIM state */
2504 hlptim->State = HAL_LPTIM_STATE_READY;
2505 /* Return function status */
2506 return HAL_OK;
2507 }
2508 /**
2509 * @}
2510 */
2511
2512 /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
2513 * @brief LPTIM IRQ handler.
2514 *
2515 @verbatim
2516 ==============================================================================
2517 ##### LPTIM IRQ handler and callbacks #####
2518 ==============================================================================
2519 [..] This section provides LPTIM IRQ handler and callback functions called within
2520 the IRQ handler:
2521 (+) LPTIM interrupt request handler
2522 (+) Compare match Callback
2523 (+) Auto-reload match Callback
2524 (+) External trigger event detection Callback
2525 (+) Compare register write complete Callback
2526 (+) Auto-reload register write complete Callback
2527 (+) Up-counting direction change Callback
2528 (+) Down-counting direction change Callback
2529
2530 @endverbatim
2531 * @{
2532 */
2533
2534 /**
2535 * @brief Handle LPTIM interrupt request.
2536 * @param hlptim LPTIM handle
2537 * @retval None
2538 */
HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef * hlptim)2539 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
2540 {
2541 /* Capture Compare 1 interrupt */
2542 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1) != RESET)
2543 {
2544 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1) != RESET)
2545 {
2546 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1);
2547 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
2548
2549 /* Input capture event */
2550 if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC1SEL) != 0x00U)
2551 {
2552 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2553 hlptim->IC_CaptureCallback(hlptim);
2554 #else
2555 HAL_LPTIM_IC_CaptureCallback(hlptim);
2556 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2557 }
2558 /* Output compare event */
2559 else
2560 {
2561 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2562 hlptim->CompareMatchCallback(hlptim);
2563 #else
2564 HAL_LPTIM_CompareMatchCallback(hlptim);
2565 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2566 }
2567 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2568 }
2569 }
2570
2571 /* Capture Compare 2 interrupt */
2572 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2) != RESET)
2573 {
2574 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2) != RESET)
2575 {
2576 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2);
2577 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
2578
2579 /* Input capture event */
2580 if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC2SEL) != 0x00U)
2581 {
2582 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2583 hlptim->IC_CaptureCallback(hlptim);
2584 #else
2585 HAL_LPTIM_IC_CaptureCallback(hlptim);
2586 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2587 }
2588 /* Output compare event */
2589 else
2590 {
2591 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2592 hlptim->CompareMatchCallback(hlptim);
2593 #else
2594 HAL_LPTIM_CompareMatchCallback(hlptim);
2595 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2596 }
2597 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2598 }
2599 }
2600
2601 /* Over Capture 1 interrupt */
2602 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1O) != RESET)
2603 {
2604 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1O) != RESET)
2605 {
2606 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1O);
2607 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
2608
2609 /* Over capture event */
2610 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2611 hlptim->IC_OverCaptureCallback(hlptim);
2612 #else
2613 HAL_LPTIM_IC_OverCaptureCallback(hlptim);
2614 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2615 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2616 }
2617 }
2618
2619 /* Over Capture 2 interrupt */
2620 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2O) != RESET)
2621 {
2622 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2O) != RESET)
2623 {
2624 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2O);
2625 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
2626
2627 /* Over capture event */
2628 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2629 hlptim->IC_OverCaptureCallback(hlptim);
2630 #else
2631 HAL_LPTIM_IC_OverCaptureCallback(hlptim);
2632 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2633 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2634 }
2635 }
2636
2637 /* Autoreload match interrupt */
2638 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
2639 {
2640 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
2641 {
2642 /* Clear Autoreload match flag */
2643 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
2644
2645 /* Autoreload match Callback */
2646 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2647 hlptim->AutoReloadMatchCallback(hlptim);
2648 #else
2649 HAL_LPTIM_AutoReloadMatchCallback(hlptim);
2650 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2651 }
2652 }
2653
2654 /* Trigger detected interrupt */
2655 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
2656 {
2657 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
2658 {
2659 /* Clear Trigger detected flag */
2660 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
2661
2662 /* Trigger detected callback */
2663 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2664 hlptim->TriggerCallback(hlptim);
2665 #else
2666 HAL_LPTIM_TriggerCallback(hlptim);
2667 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2668 }
2669 }
2670
2671 /* Compare write interrupt */
2672 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP1OK) != RESET)
2673 {
2674 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP1OK) != RESET)
2675 {
2676 /* Clear Compare write flag */
2677 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
2678 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
2679 /* Compare write Callback */
2680 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2681 hlptim->CompareWriteCallback(hlptim);
2682 #else
2683 HAL_LPTIM_CompareWriteCallback(hlptim);
2684 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2685 }
2686 }
2687
2688 /* Compare write interrupt */
2689 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP2OK) != RESET)
2690 {
2691 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP2OK) != RESET)
2692 {
2693 /* Clear Compare write flag */
2694 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
2695 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
2696 /* Compare write Callback */
2697 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2698 hlptim->CompareWriteCallback(hlptim);
2699 #else
2700 HAL_LPTIM_CompareWriteCallback(hlptim);
2701 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2702 }
2703 }
2704
2705 /* Autoreload write interrupt */
2706 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
2707 {
2708 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
2709 {
2710 /* Clear Autoreload write flag */
2711 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
2712
2713 /* Autoreload write Callback */
2714 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2715 hlptim->AutoReloadWriteCallback(hlptim);
2716 #else
2717 HAL_LPTIM_AutoReloadWriteCallback(hlptim);
2718 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2719 }
2720 }
2721
2722 /* Direction counter changed from Down to Up interrupt */
2723 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
2724 {
2725 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
2726 {
2727 /* Clear Direction counter changed from Down to Up flag */
2728 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
2729
2730 /* Direction counter changed from Down to Up Callback */
2731 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2732 hlptim->DirectionUpCallback(hlptim);
2733 #else
2734 HAL_LPTIM_DirectionUpCallback(hlptim);
2735 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2736 }
2737 }
2738
2739 /* Direction counter changed from Up to Down interrupt */
2740 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
2741 {
2742 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
2743 {
2744 /* Clear Direction counter changed from Up to Down flag */
2745 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
2746
2747 /* Direction counter changed from Up to Down Callback */
2748 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2749 hlptim->DirectionDownCallback(hlptim);
2750 #else
2751 HAL_LPTIM_DirectionDownCallback(hlptim);
2752 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2753 }
2754 }
2755
2756 /* Repetition counter underflowed (or contains zero) and the LPTIM counter
2757 overflowed */
2758 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UPDATE) != RESET)
2759 {
2760 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UPDATE) != RESET)
2761 {
2762 /* Clear update event flag */
2763 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UPDATE);
2764
2765 /* Update event Callback */
2766 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2767 hlptim->UpdateEventCallback(hlptim);
2768 #else
2769 HAL_LPTIM_UpdateEventCallback(hlptim);
2770 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2771 }
2772 }
2773
2774 /* Successful APB bus write to repetition counter register */
2775 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_REPOK) != RESET)
2776 {
2777 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_REPOK) != RESET)
2778 {
2779 /* Clear successful APB bus write to repetition counter flag */
2780 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK);
2781
2782 /* Successful APB bus write to repetition counter Callback */
2783 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2784 hlptim->RepCounterWriteCallback(hlptim);
2785 #else
2786 HAL_LPTIM_RepCounterWriteCallback(hlptim);
2787 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2788 }
2789 }
2790 }
2791
2792 /**
2793 * @brief Compare match callback in non-blocking mode.
2794 * @param hlptim LPTIM handle
2795 * @retval None
2796 */
HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef * hlptim)2797 __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
2798 {
2799 /* Prevent unused argument(s) compilation warning */
2800 UNUSED(hlptim);
2801
2802 /* NOTE : This function should not be modified, when the callback is needed,
2803 the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
2804 */
2805 }
2806
2807 /**
2808 * @brief Autoreload match callback in non-blocking mode.
2809 * @param hlptim LPTIM handle
2810 * @retval None
2811 */
HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef * hlptim)2812 __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
2813 {
2814 /* Prevent unused argument(s) compilation warning */
2815 UNUSED(hlptim);
2816
2817 /* NOTE : This function should not be modified, when the callback is needed,
2818 the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
2819 */
2820 }
2821
2822 /**
2823 * @brief Trigger detected callback in non-blocking mode.
2824 * @param hlptim LPTIM handle
2825 * @retval None
2826 */
HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef * hlptim)2827 __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
2828 {
2829 /* Prevent unused argument(s) compilation warning */
2830 UNUSED(hlptim);
2831
2832 /* NOTE : This function should not be modified, when the callback is needed,
2833 the HAL_LPTIM_TriggerCallback could be implemented in the user file
2834 */
2835 }
2836
2837 /**
2838 * @brief Compare write callback in non-blocking mode.
2839 * @param hlptim LPTIM handle
2840 * @retval None
2841 */
HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef * hlptim)2842 __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
2843 {
2844 /* Prevent unused argument(s) compilation warning */
2845 UNUSED(hlptim);
2846
2847 /* NOTE : This function should not be modified, when the callback is needed,
2848 the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
2849 */
2850 }
2851
2852 /**
2853 * @brief Autoreload write callback in non-blocking mode.
2854 * @param hlptim LPTIM handle
2855 * @retval None
2856 */
HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef * hlptim)2857 __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
2858 {
2859 /* Prevent unused argument(s) compilation warning */
2860 UNUSED(hlptim);
2861
2862 /* NOTE : This function should not be modified, when the callback is needed,
2863 the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
2864 */
2865 }
2866
2867 /**
2868 * @brief Direction counter changed from Down to Up callback in non-blocking mode.
2869 * @param hlptim LPTIM handle
2870 * @retval None
2871 */
HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef * hlptim)2872 __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
2873 {
2874 /* Prevent unused argument(s) compilation warning */
2875 UNUSED(hlptim);
2876
2877 /* NOTE : This function should not be modified, when the callback is needed,
2878 the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
2879 */
2880 }
2881
2882 /**
2883 * @brief Direction counter changed from Up to Down callback in non-blocking mode.
2884 * @param hlptim LPTIM handle
2885 * @retval None
2886 */
HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef * hlptim)2887 __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
2888 {
2889 /* Prevent unused argument(s) compilation warning */
2890 UNUSED(hlptim);
2891
2892 /* NOTE : This function should not be modified, when the callback is needed,
2893 the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
2894 */
2895 }
2896
2897 /**
2898 * @brief Repetition counter underflowed (or contains zero) and LPTIM counter overflowed callback in non-blocking mode.
2899 * @param hlptim LPTIM handle
2900 * @retval None
2901 */
HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef * hlptim)2902 __weak void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim)
2903 {
2904 /* Prevent unused argument(s) compilation warning */
2905 UNUSED(hlptim);
2906
2907 /* NOTE : This function should not be modified, when the callback is needed,
2908 the HAL_LPTIM_UpdateEventCallback could be implemented in the user file
2909 */
2910 }
2911
2912 /**
2913 * @brief Successful APB bus write to repetition counter register callback in non-blocking mode.
2914 * @param hlptim LPTIM handle
2915 * @retval None
2916 */
HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef * hlptim)2917 __weak void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim)
2918 {
2919 /* Prevent unused argument(s) compilation warning */
2920 UNUSED(hlptim);
2921
2922 /* NOTE : This function should not be modified, when the callback is needed,
2923 the HAL_LPTIM_RepCounterWriteCallback could be implemented in the user file
2924 */
2925 }
2926
2927 /**
2928 * @brief Input Capture callback in non-blocking mode
2929 * @param hlptim LPTIM handle
2930 * @retval None
2931 */
HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef * hlptim)2932 __weak void HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef *hlptim)
2933 {
2934 /* Prevent unused argument(s) compilation warning */
2935 UNUSED(hlptim);
2936
2937 /* NOTE : This function should not be modified, when the callback is needed,
2938 the HAL_LPTIM_IC_CaptureCallback could be implemented in the user file
2939 */
2940 }
2941
2942 /**
2943 * @brief Over Capture callback in non-blocking mode
2944 * @param hlptim LPTIM handle
2945 * @retval None
2946 */
HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef * hlptim)2947 __weak void HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef *hlptim)
2948 {
2949 /* Prevent unused argument(s) compilation warning */
2950 UNUSED(hlptim);
2951
2952 /* NOTE : This function should not be modified, when the callback is needed,
2953 the HAL_LPTIM_IC_OverCaptureCallback could be implemented in the user file
2954 */
2955 }
2956
2957 /**
2958 * @brief Input Capture half complete callback in non-blocking mode
2959 * @param hlptim LPTIM IC handle
2960 * @retval None
2961 */
HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef * hlptim)2962 __weak void HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef *hlptim)
2963 {
2964 /* Prevent unused argument(s) compilation warning */
2965 UNUSED(hlptim);
2966
2967 /* NOTE : This function should not be modified, when the callback is needed,
2968 the HAL_LPTIM_IC_CaptureHalfCpltCallback could be implemented in the user file
2969 */
2970 }
2971
2972 /**
2973 * @brief Update event half complete callback in non-blocking mode
2974 * @param hlptim LPTIM handle
2975 * @retval None
2976 */
HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef * hlptim)2977 __weak void HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef *hlptim)
2978 {
2979 /* Prevent unused argument(s) compilation warning */
2980 UNUSED(hlptim);
2981
2982 /* NOTE : This function should not be modified, when the callback is needed,
2983 the HAL_LPTIM_UpdateEventHalfCpltCallback could be implemented in the user file
2984 */
2985 }
2986
2987 /**
2988 * @brief Error callback in non-blocking mode
2989 * @param hlptim LPTIM handle
2990 * @retval None
2991 */
HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef * hlptim)2992 __weak void HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef *hlptim)
2993 {
2994 /* Prevent unused argument(s) compilation warning */
2995 UNUSED(hlptim);
2996
2997 /* NOTE : This function should not be modified, when the callback is needed,
2998 the HAL_LPTIM_ErrorCallback could be implemented in the user file
2999 */
3000 }
3001
3002
3003 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3004 /**
3005 * @brief Register a User LPTIM callback to be used instead of the weak predefined callback
3006 * @param hlptim LPTIM handle
3007 * @param CallbackID ID of the callback to be registered
3008 * This parameter can be one of the following values:
3009 * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
3010 * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
3011 * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
3012 * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
3013 * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
3014 * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
3015 * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
3016 * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
3017 * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
3018 * @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID
3019 * @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID
3020 * @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID
3021 * @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID Input Capture Callback ID
3022 * @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
3023 * @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID Over Capture Callback ID
3024 * @arg @ref HAL_LPTIM_ERROR_CB_ID Error Callback ID
3025 * @param pCallback pointer to the callback function
3026 * @retval status
3027 */
HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef * hlptim,HAL_LPTIM_CallbackIDTypeDef CallbackID,pLPTIM_CallbackTypeDef pCallback)3028 HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim,
3029 HAL_LPTIM_CallbackIDTypeDef CallbackID,
3030 pLPTIM_CallbackTypeDef pCallback)
3031 {
3032 HAL_StatusTypeDef status = HAL_OK;
3033
3034 if (pCallback == NULL)
3035 {
3036 return HAL_ERROR;
3037 }
3038
3039 if (hlptim->State == HAL_LPTIM_STATE_READY)
3040 {
3041 switch (CallbackID)
3042 {
3043 case HAL_LPTIM_MSPINIT_CB_ID :
3044 hlptim->MspInitCallback = pCallback;
3045 break;
3046
3047 case HAL_LPTIM_MSPDEINIT_CB_ID :
3048 hlptim->MspDeInitCallback = pCallback;
3049 break;
3050
3051 case HAL_LPTIM_COMPARE_MATCH_CB_ID :
3052 hlptim->CompareMatchCallback = pCallback;
3053 break;
3054
3055 case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
3056 hlptim->AutoReloadMatchCallback = pCallback;
3057 break;
3058
3059 case HAL_LPTIM_TRIGGER_CB_ID :
3060 hlptim->TriggerCallback = pCallback;
3061 break;
3062
3063 case HAL_LPTIM_COMPARE_WRITE_CB_ID :
3064 hlptim->CompareWriteCallback = pCallback;
3065 break;
3066
3067 case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
3068 hlptim->AutoReloadWriteCallback = pCallback;
3069 break;
3070
3071 case HAL_LPTIM_DIRECTION_UP_CB_ID :
3072 hlptim->DirectionUpCallback = pCallback;
3073 break;
3074
3075 case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
3076 hlptim->DirectionDownCallback = pCallback;
3077 break;
3078
3079 case HAL_LPTIM_UPDATE_EVENT_CB_ID :
3080 hlptim->UpdateEventCallback = pCallback;
3081 break;
3082
3083 case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID :
3084 hlptim->RepCounterWriteCallback = pCallback;
3085 break;
3086
3087 case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID :
3088 hlptim->UpdateEventHalfCpltCallback = pCallback;
3089 break;
3090
3091 case HAL_LPTIM_IC_CAPTURE_CB_ID :
3092 hlptim->IC_CaptureCallback = pCallback;
3093 break;
3094
3095 case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID :
3096 hlptim->IC_CaptureHalfCpltCallback = pCallback;
3097 break;
3098
3099 case HAL_LPTIM_OVER_CAPTURE_CB_ID :
3100 hlptim->IC_OverCaptureCallback = pCallback;
3101 break;
3102
3103 case HAL_LPTIM_ERROR_CB_ID :
3104 hlptim->ErrorCallback = pCallback;
3105 break;
3106
3107 default :
3108 /* Return error status */
3109 status = HAL_ERROR;
3110 break;
3111 }
3112 }
3113 else if (hlptim->State == HAL_LPTIM_STATE_RESET)
3114 {
3115 switch (CallbackID)
3116 {
3117 case HAL_LPTIM_MSPINIT_CB_ID :
3118 hlptim->MspInitCallback = pCallback;
3119 break;
3120
3121 case HAL_LPTIM_MSPDEINIT_CB_ID :
3122 hlptim->MspDeInitCallback = pCallback;
3123 break;
3124
3125 default :
3126 /* Return error status */
3127 status = HAL_ERROR;
3128 break;
3129 }
3130 }
3131 else
3132 {
3133 /* Return error status */
3134 status = HAL_ERROR;
3135 }
3136
3137 return status;
3138 }
3139
3140 /**
3141 * @brief Unregister a LPTIM callback
3142 * LLPTIM callback is redirected to the weak predefined callback
3143 * @param hlptim LPTIM handle
3144 * @param CallbackID ID of the callback to be unregistered
3145 * This parameter can be one of the following values:
3146 * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
3147 * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
3148 * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
3149 * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
3150 * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
3151 * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
3152 * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
3153 * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
3154 * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
3155 * @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID
3156 * @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID
3157 * @retval status
3158 */
HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef * hlptim,HAL_LPTIM_CallbackIDTypeDef CallbackID)3159 HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim,
3160 HAL_LPTIM_CallbackIDTypeDef CallbackID)
3161 {
3162 HAL_StatusTypeDef status = HAL_OK;
3163
3164 if (hlptim->State == HAL_LPTIM_STATE_READY)
3165 {
3166 switch (CallbackID)
3167 {
3168 case HAL_LPTIM_MSPINIT_CB_ID :
3169 /* Legacy weak MspInit Callback */
3170 hlptim->MspInitCallback = HAL_LPTIM_MspInit;
3171 break;
3172
3173 case HAL_LPTIM_MSPDEINIT_CB_ID :
3174 /* Legacy weak Msp DeInit Callback */
3175 hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
3176 break;
3177
3178 case HAL_LPTIM_COMPARE_MATCH_CB_ID :
3179 /* Legacy weak Compare match Callback */
3180 hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
3181 break;
3182
3183 case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
3184 /* Legacy weak Auto-reload match Callback */
3185 hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
3186 break;
3187
3188 case HAL_LPTIM_TRIGGER_CB_ID :
3189 /* Legacy weak External trigger event detection Callback */
3190 hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
3191 break;
3192
3193 case HAL_LPTIM_COMPARE_WRITE_CB_ID :
3194 /* Legacy weak Compare register write complete Callback */
3195 hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
3196 break;
3197
3198 case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
3199 /* Legacy weak Auto-reload register write complete Callback */
3200 hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
3201 break;
3202
3203 case HAL_LPTIM_DIRECTION_UP_CB_ID :
3204 /* Legacy weak Up-counting direction change Callback */
3205 hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
3206 break;
3207
3208 case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
3209 /* Legacy weak Down-counting direction change Callback */
3210 hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
3211 break;
3212
3213 case HAL_LPTIM_UPDATE_EVENT_CB_ID :
3214 /* Legacy weak Update event detection Callback */
3215 hlptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback;
3216 break;
3217
3218 case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID :
3219 /* Legacy weak Repetition counter register write complete Callback */
3220 hlptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback;
3221 break;
3222
3223 case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID :
3224 /* Legacy weak Update event half complete detection Callback */
3225 hlptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback;
3226 break;
3227
3228 case HAL_LPTIM_IC_CAPTURE_CB_ID :
3229 /* Legacy weak IC Capture Callback */
3230 hlptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback;
3231 break;
3232
3233 case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID :
3234 /* Legacy weak IC Capture half complete Callback */
3235 hlptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback;
3236 break;
3237
3238 case HAL_LPTIM_OVER_CAPTURE_CB_ID :
3239 /* Legacy weak IC over capture Callback */
3240 hlptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback;
3241 break;
3242
3243 default :
3244 /* Return error status */
3245 status = HAL_ERROR;
3246 break;
3247 }
3248 }
3249 else if (hlptim->State == HAL_LPTIM_STATE_RESET)
3250 {
3251 switch (CallbackID)
3252 {
3253 case HAL_LPTIM_MSPINIT_CB_ID :
3254 /* Legacy weak MspInit Callback */
3255 hlptim->MspInitCallback = HAL_LPTIM_MspInit;
3256 break;
3257
3258 case HAL_LPTIM_MSPDEINIT_CB_ID :
3259 /* Legacy weak Msp DeInit Callback */
3260 hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
3261 break;
3262
3263 default :
3264 /* Return error status */
3265 status = HAL_ERROR;
3266 break;
3267 }
3268 }
3269 else
3270 {
3271 /* Return error status */
3272 status = HAL_ERROR;
3273 }
3274
3275 return status;
3276 }
3277 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3278
3279 /**
3280 * @}
3281 */
3282
3283 /** @defgroup LPTIM_Group5 Peripheral State functions
3284 * @brief Peripheral State functions.
3285 *
3286 @verbatim
3287 ==============================================================================
3288 ##### Peripheral State functions #####
3289 ==============================================================================
3290 [..]
3291 This subsection permits to get in run-time the status of the peripheral.
3292
3293 @endverbatim
3294 * @{
3295 */
3296
3297 /**
3298 * @brief Return the LPTIM handle state.
3299 * @param hlptim LPTIM handle
3300 * @retval HAL state
3301 */
HAL_LPTIM_GetState(LPTIM_HandleTypeDef * hlptim)3302 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
3303 {
3304 /* Return LPTIM handle state */
3305 return hlptim->State;
3306 }
3307
3308 /**
3309 * @}
3310 */
3311
3312
3313 /**
3314 * @}
3315 */
3316
3317 /* Private functions ---------------------------------------------------------*/
3318
3319 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
3320 * @{
3321 */
3322 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3323 /**
3324 * @brief Reset interrupt callbacks to the legacy weak callbacks.
3325 * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains
3326 * the configuration information for LPTIM module.
3327 * @retval None
3328 */
LPTIM_ResetCallback(LPTIM_HandleTypeDef * lptim)3329 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
3330 {
3331 /* Reset the LPTIM callback to the legacy weak callbacks */
3332 lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
3333 lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
3334 lptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
3335 lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
3336 lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
3337 lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
3338 lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
3339 lptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback;
3340 lptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback;
3341 lptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback;
3342 lptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback;
3343 lptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback;
3344 lptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback;
3345 lptim->ErrorCallback = HAL_LPTIM_ErrorCallback;
3346 }
3347 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3348
3349 /**
3350 * @brief LPTimer Wait for flag set
3351 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3352 * the configuration information for LPTIM module.
3353 * @param flag The lptim flag
3354 * @retval HAL status
3355 */
LPTIM_WaitForFlag(LPTIM_HandleTypeDef * hlptim,uint32_t flag)3356 static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag)
3357 {
3358 HAL_StatusTypeDef result = HAL_OK;
3359 uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
3360 do
3361 {
3362 count--;
3363 if (count == 0UL)
3364 {
3365 result = HAL_TIMEOUT;
3366 }
3367 } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
3368
3369 return result;
3370 }
3371
3372 /**
3373 * @brief LPTIM DMA error callback
3374 * @param hdma pointer to DMA handle.
3375 * @retval None
3376 */
LPTIM_DMAError(DMA_HandleTypeDef * hdma)3377 void LPTIM_DMAError(DMA_HandleTypeDef *hdma)
3378 {
3379 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3380
3381 hlptim->State = HAL_LPTIM_STATE_READY;
3382
3383 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3384 hlptim->ErrorCallback(hlptim);
3385 #else
3386 HAL_LPTIM_ErrorCallback(hlptim);
3387 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3388 }
3389
3390 /**
3391 * @brief LPTIM DMA Capture complete callback.
3392 * @param hdma pointer to DMA handle.
3393 * @retval None
3394 */
LPTIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)3395 void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
3396 {
3397 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3398
3399 hlptim->State = HAL_LPTIM_STATE_READY;
3400
3401 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3402 {
3403 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3404 }
3405 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3406 {
3407 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3408 }
3409 else
3410 {
3411 /* nothing to do */
3412 }
3413
3414 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3415 hlptim->IC_CaptureCallback(hlptim);
3416 #else
3417 HAL_LPTIM_IC_CaptureCallback(hlptim);
3418 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3419
3420 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3421 }
3422
3423 /**
3424 * @brief LPTIM DMA Capture half complete callback.
3425 * @param hdma pointer to DMA handle.
3426 * @retval None
3427 */
LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)3428 void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
3429 {
3430 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3431
3432 hlptim->State = HAL_LPTIM_STATE_READY;
3433
3434 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3435 {
3436 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3437 }
3438 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3439 {
3440 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3441 }
3442 else
3443 {
3444 /* nothing to do */
3445 }
3446
3447 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3448 hlptim->IC_CaptureHalfCpltCallback(hlptim);
3449 #else
3450 HAL_LPTIM_IC_CaptureHalfCpltCallback(hlptim);
3451 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3452
3453 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3454 }
3455
3456 /**
3457 * @brief LPTIM DMA Update event complete callback.
3458 * @param hdma pointer to DMA handle.
3459 * @retval None
3460 */
LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef * hdma)3461 void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma)
3462 {
3463 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3464
3465 hlptim->State = HAL_LPTIM_STATE_READY;
3466
3467 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3468 {
3469 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3470 }
3471 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3472 {
3473 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3474 }
3475 else
3476 {
3477 /* nothing to do */
3478 }
3479
3480 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3481 hlptim->UpdateEventCallback(hlptim);
3482 #else
3483 HAL_LPTIM_UpdateEventCallback(hlptim);
3484 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3485
3486 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3487 }
3488
3489 /**
3490 * @brief LPTIM DMA Capture half complete callback.
3491 * @param hdma pointer to DMA handle.
3492 * @retval None
3493 */
LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef * hdma)3494 void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma)
3495 {
3496 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3497
3498 hlptim->State = HAL_LPTIM_STATE_READY;
3499
3500 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3501 {
3502 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3503 }
3504 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3505 {
3506 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3507 }
3508 else
3509 {
3510 /* nothing to do */
3511 }
3512
3513 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3514 hlptim->UpdateEventHalfCpltCallback(hlptim);
3515 #else
3516 HAL_LPTIM_UpdateEventHalfCpltCallback(hlptim);
3517 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3518
3519 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3520 }
3521 /**
3522 * @brief LPTimer Output Compare 1 configuration
3523 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3524 * the configuration information for LPTIM module.
3525 * @param sConfig The output configuration structure
3526 * @retval None
3527 */
LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_OC_ConfigTypeDef * sConfig)3528 static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig)
3529 {
3530 uint32_t tmpccmr1;
3531 #if !defined(LPTIM4)
3532 #else
3533 uint32_t tmpcfgr;
3534 #endif /* !LPTIM4 */
3535
3536 tmpccmr1 = hlptim->Instance->CCMR1;
3537 tmpccmr1 &= ~(LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_CC1SEL_Msk);
3538
3539 #if defined(LPTIM4)
3540 if (hlptim->Instance == LPTIM4)
3541 {
3542 tmpcfgr = hlptim->Instance->CFGR;
3543 tmpcfgr &= ~LPTIM_CFGR_WAVPOL_Msk;
3544 tmpcfgr |= sConfig->OCPolarity << LPTIM_CFGR_WAVPOL_Pos;
3545
3546 /* Write to CFGR register */
3547 hlptim->Instance->CFGR = tmpcfgr;
3548 }
3549 else
3550 #endif /* LPTIM4 */
3551 {
3552 tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC1P_Pos;
3553 }
3554
3555 /* Enable the Peripheral */
3556 __HAL_LPTIM_ENABLE(hlptim);
3557
3558 /* Clear flag */
3559 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
3560
3561 /* Write to CCR1 register */
3562 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, sConfig->Pulse);
3563
3564 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
3565 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
3566 {
3567 return HAL_TIMEOUT;
3568 }
3569
3570 /* Disable the Peripheral */
3571 __HAL_LPTIM_DISABLE(hlptim);
3572
3573 /* Write to CCMR1 register */
3574 hlptim->Instance->CCMR1 = tmpccmr1;
3575
3576 return HAL_OK;
3577 }
3578
3579 /**
3580 * @brief LPTimer Output Compare 2 configuration
3581 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3582 * the configuration information for LPTIM module.
3583 * @param sConfig The output configuration structure
3584 * @retval None
3585 */
LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_OC_ConfigTypeDef * sConfig)3586 static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig)
3587 {
3588 uint32_t tmpccmr1;
3589
3590 tmpccmr1 = hlptim->Instance->CCMR1;
3591 tmpccmr1 &= ~(LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_CC2SEL_Msk);
3592 tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC2P_Pos;
3593
3594 /* Enable the Peripheral */
3595 __HAL_LPTIM_ENABLE(hlptim);
3596
3597 /* Clear flag */
3598 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
3599
3600 /* Write to CCR2 register */
3601 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, sConfig->Pulse);
3602
3603 /* Wait for the completion of the write operation to the LPTIM_CCR2 register */
3604 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) != HAL_OK)
3605 {
3606 return HAL_TIMEOUT;
3607 }
3608
3609 /* Disable the Peripheral */
3610 __HAL_LPTIM_DISABLE(hlptim);
3611
3612 /* Write to CCMR1 register */
3613 hlptim->Instance->CCMR1 = tmpccmr1;
3614
3615 return HAL_OK;
3616 }
3617
3618 /**
3619 * @brief LPTimer Input Capture 1 configuration
3620 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3621 * the configuration information for LPTIM module.
3622 * @param sConfig The input configuration structure
3623 * @retval None
3624 */
LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_IC_ConfigTypeDef * sConfig)3625 static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig)
3626 {
3627 uint32_t tmpccmr1;
3628 uint32_t tmpcfgr2;
3629
3630 tmpccmr1 = hlptim->Instance->CCMR1;
3631 tmpccmr1 &= ~(LPTIM_CCMR1_IC1PSC_Msk | LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_IC1F_Msk);
3632 tmpccmr1 |= sConfig->ICPrescaler |
3633 sConfig->ICPolarity |
3634 sConfig->ICFilter |
3635 LPTIM_CCMR1_CC1SEL;
3636
3637 tmpcfgr2 = hlptim->Instance->CFGR2;
3638 tmpcfgr2 &= ~(LPTIM_CFGR2_IC1SEL_Msk);
3639 tmpcfgr2 |= sConfig->ICInputSource;
3640
3641 /* Write to CCMR1 register */
3642 hlptim->Instance->CCMR1 = tmpccmr1;
3643
3644 /* Write to CFGR2 register */
3645 hlptim->Instance->CFGR2 = tmpcfgr2;
3646 }
3647
3648 /**
3649 * @brief LPTimer Input Capture 2 configuration
3650 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3651 * the configuration information for LPTIM module.
3652 * @param sConfig The input configuration structure
3653 * @retval None
3654 */
LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_IC_ConfigTypeDef * sConfig)3655 static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig)
3656 {
3657 uint32_t tmpccmr1;
3658 uint32_t tmpcfgr2;
3659
3660 tmpccmr1 = hlptim->Instance->CCMR1;
3661 tmpccmr1 &= ~(LPTIM_CCMR1_IC2PSC_Msk | LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_IC2F_Msk);
3662 tmpccmr1 |= (sConfig->ICPrescaler << (LPTIM_CCMR1_IC2PSC_Pos - LPTIM_CCMR1_IC1PSC_Pos)) |
3663 (sConfig->ICPolarity << (LPTIM_CCMR1_CC2P_Pos - LPTIM_CCMR1_CC1P_Pos)) |
3664 (sConfig->ICFilter << (LPTIM_CCMR1_IC2F_Pos - LPTIM_CCMR1_IC1F_Pos)) |
3665 LPTIM_CCMR1_CC2SEL;
3666
3667 tmpcfgr2 = hlptim->Instance->CFGR2;
3668 tmpcfgr2 &= ~(LPTIM_CFGR2_IC2SEL_Msk);
3669 tmpcfgr2 |= sConfig->ICInputSource;
3670
3671 /* Write to CCMR1 register */
3672 hlptim->Instance->CCMR1 = tmpccmr1;
3673
3674 /* Write to CFGR2 register */
3675 hlptim->Instance->CFGR2 = tmpcfgr2;
3676 }
3677
3678 /**
3679 * @brief Start the DMA data transfer.
3680 * @param hdma DMA handle
3681 * @param src The source memory Buffer address.
3682 * @param dst The destination memory Buffer address.
3683 * @param length The size of a source block transfer in byte.
3684 * @retval HAL status
3685 */
LPTIM_DMA_Start_IT(DMA_HandleTypeDef * hdma,uint32_t src,uint32_t dst,uint32_t length)3686 HAL_StatusTypeDef LPTIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
3687 uint32_t length)
3688 {
3689 HAL_StatusTypeDef status;
3690
3691 /* Enable the DMA channel */
3692 if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3693 {
3694 if ((hdma->LinkedListQueue != 0U) && (hdma->LinkedListQueue->Head != 0U))
3695 {
3696 /* Enable the DMA channel */
3697 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = length;
3698 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)src;
3699 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)dst;
3700
3701 status = HAL_DMAEx_List_Start_IT(hdma);
3702 }
3703 else
3704 {
3705 status = HAL_ERROR;
3706 }
3707 }
3708 else
3709 {
3710 status = HAL_DMA_Start_IT(hdma, src, dst, length);
3711 }
3712
3713 return status;
3714 }
3715 /**
3716 * @}
3717 */
3718 #endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 || LPTIM6 */
3719
3720 #endif /* HAL_LPTIM_MODULE_ENABLED */
3721 /**
3722 * @}
3723 */
3724
3725 /**
3726 * @}
3727 */
3728
