1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_dac_ex.c
4 * @author MCD Application Team
5 * @brief Extended DAC HAL module driver.
6 * This file provides firmware functions to manage the extended
7 * functionalities of the DAC peripheral.
8 *
9 *
10 ******************************************************************************
11 * @attention
12 *
13 * Copyright (c) 2022 STMicroelectronics.
14 * All rights reserved.
15 *
16 * This software is licensed under terms that can be found in the LICENSE file
17 * in the root directory of this software component.
18 * If no LICENSE file comes with this software, it is provided AS-IS.
19 *
20 ******************************************************************************
21 @verbatim
22 ==============================================================================
23 ##### How to use this driver #####
24 ==============================================================================
25 [..]
26
27 *** Dual mode IO operation ***
28 ==============================
29 [..]
30 (+) Use HAL_DACEx_DualStart() to enable both channel and start conversion
31 for dual mode operation.
32 If software trigger is selected, using HAL_DACEx_DualStart() will start
33 the conversion of the value previously set by HAL_DACEx_DualSetValue().
34 (+) Use HAL_DACEx_DualStop() to disable both channel and stop conversion
35 for dual mode operation.
36 (+) Use HAL_DACEx_DualStart_DMA() to enable both channel and start conversion
37 for dual mode operation using DMA to feed DAC converters.
38 First issued trigger will start the conversion of the value previously
39 set by HAL_DACEx_DualSetValue().
40 The same callbacks that are used in single mode are called in dual mode to notify
41 transfer completion (half complete or complete), errors or underrun.
42 (+) Use HAL_DACEx_DualStop_DMA() to disable both channel and stop conversion
43 for dual mode operation using DMA to feed DAC converters.
44 (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
45 Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
46 HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
47 Channel 1 and Channel 2.
48
49 *** Signal generation operation ***
50 ===================================
51 [..]
52 (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
53 (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
54
55 (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
56 (+) HAL_DACEx_SetUserTrimming to set user trimming value.
57 (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
58 after reset, user setting if HAL_DACEx_SetUserTrimming have been used
59 at least one time after reset).
60
61 @endverbatim
62 ******************************************************************************
63 */
64
65
66 /* Includes ------------------------------------------------------------------*/
67 #include "stm32h5xx_hal.h"
68
69 /** @addtogroup STM32H5xx_HAL_Driver
70 * @{
71 */
72
73 #ifdef HAL_DAC_MODULE_ENABLED
74
75 #if defined(DAC1)
76
77 /** @defgroup DACEx DACEx
78 * @brief DAC Extended HAL module driver
79 * @{
80 */
81
82 /* Private typedef -----------------------------------------------------------*/
83 /* Private define ------------------------------------------------------------*/
84
85 /* Delay for DAC minimum trimming time. */
86 /* Note: minimum time needed between two calibration steps */
87 /* The delay below is specified under conditions: */
88 /* - DAC channel output buffer enabled */
89 /* Literal set to maximum value (refer to device datasheet, */
90 /* electrical characteristics, parameter "tTRIM"). */
91 /* Unit: us */
92 #define DAC_DELAY_TRIM_US (50UL) /*!< Delay for DAC minimum trimming time */
93
94 /* Private macro -------------------------------------------------------------*/
95 /* Private variables ---------------------------------------------------------*/
96 /* Private function prototypes -----------------------------------------------*/
97 /* Exported functions --------------------------------------------------------*/
98
99 /** @defgroup DACEx_Exported_Functions DACEx Exported Functions
100 * @{
101 */
102
103 /** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
104 * @brief Extended IO operation functions
105 *
106 @verbatim
107 ==============================================================================
108 ##### Extended features functions #####
109 ==============================================================================
110 [..] This section provides functions allowing to:
111 (+) Start conversion.
112 (+) Stop conversion.
113 (+) Start conversion and enable DMA transfer.
114 (+) Stop conversion and disable DMA transfer.
115 (+) Get result of conversion.
116 (+) Get result of dual mode conversion.
117
118 @endverbatim
119 * @{
120 */
121
122
123 /**
124 * @brief Enables DAC and starts conversion of both channels.
125 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
126 * the configuration information for the specified DAC.
127 * @retval HAL status
128 */
HAL_DACEx_DualStart(DAC_HandleTypeDef * hdac)129 HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
130 {
131 uint32_t tmp_swtrig = 0UL;
132 __IO uint32_t wait_loop_index;
133
134 /* Check the DAC peripheral handle */
135 if (hdac == NULL)
136 {
137 return HAL_ERROR;
138 }
139
140
141 /* Process locked */
142 __HAL_LOCK(hdac);
143
144 /* Change DAC state */
145 hdac->State = HAL_DAC_STATE_BUSY;
146
147 /* Enable the Peripheral */
148 __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
149 __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
150 /* Ensure minimum wait before using peripheral after enabling it */
151 /* Wait loop initialization and execution */
152 /* Note: Variable divided by 2 to compensate partially */
153 /* CPU processing cycles, scaling in us split to not */
154 /* exceed 32 bits register capacity and handle low frequency. */
155 wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
156 while (wait_loop_index != 0UL)
157 {
158 wait_loop_index--;
159 }
160
161 /* Check if software trigger enabled */
162 if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
163 {
164 tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
165 }
166 if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)))
167 {
168 tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
169 }
170 /* Enable the selected DAC software conversion*/
171 SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig);
172
173 /* Change DAC state */
174 hdac->State = HAL_DAC_STATE_READY;
175
176 /* Process unlocked */
177 __HAL_UNLOCK(hdac);
178
179 /* Return function status */
180 return HAL_OK;
181 }
182
183 /**
184 * @brief Disables DAC and stop conversion of both channels.
185 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
186 * the configuration information for the specified DAC.
187 * @retval HAL status
188 */
HAL_DACEx_DualStop(DAC_HandleTypeDef * hdac)189 HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
190 {
191 /* Check the DAC peripheral handle */
192 if (hdac == NULL)
193 {
194 return HAL_ERROR;
195 }
196
197
198 /* Disable the Peripheral */
199 __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
200 __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
201
202 /* Change DAC state */
203 hdac->State = HAL_DAC_STATE_READY;
204
205 /* Return function status */
206 return HAL_OK;
207 }
208
209 /**
210 * @brief Enables DAC and starts conversion of both channel 1 and 2 of the same DAC.
211 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
212 * the configuration information for the specified DAC.
213 * @param Channel The DAC channel that will request data from DMA.
214 * This parameter can be one of the following values:
215 * @arg DAC_CHANNEL_1: DAC Channel1 selected
216 * @arg DAC_CHANNEL_2: DAC Channel2 selected
217 * @param pData The destination peripheral Buffer address.
218 * @param Length The length of data to be transferred from memory to DAC peripheral
219 * @param Alignment Specifies the data alignment for DAC channel.
220 * This parameter can be one of the following values:
221 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
222 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
223 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
224 * @retval HAL status
225 */
HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef * hdac,uint32_t Channel,const uint32_t * pData,uint32_t Length,uint32_t Alignment)226 HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
227 const uint32_t *pData, uint32_t Length, uint32_t Alignment)
228 {
229 HAL_StatusTypeDef status;
230 uint32_t tmpreg = 0UL;
231 __IO uint32_t wait_loop_index;
232 uint32_t LengthInBytes;
233
234 /* Check the DAC peripheral handle */
235 if (hdac == NULL)
236 {
237 return HAL_ERROR;
238 }
239
240 /* Check the parameters */
241 assert_param(IS_DAC_CHANNEL(Channel));
242 assert_param(IS_DAC_ALIGN(Alignment));
243
244 /* Process locked */
245 __HAL_LOCK(hdac);
246
247 /* Change DAC state */
248 hdac->State = HAL_DAC_STATE_BUSY;
249
250 if (Channel == DAC_CHANNEL_1)
251 {
252 /* Set the DMA transfer complete callback for channel1 */
253 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
254
255 /* Set the DMA half transfer complete callback for channel1 */
256 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
257
258 /* Set the DMA error callback for channel1 */
259 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
260
261 /* Enable the selected DAC channel1 DMA request */
262 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
263 }
264 else
265 {
266 /* Set the DMA transfer complete callback for channel2 */
267 hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
268
269 /* Set the DMA half transfer complete callback for channel2 */
270 hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
271
272 /* Set the DMA error callback for channel2 */
273 hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
274
275 /* Enable the selected DAC channel2 DMA request */
276 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
277 }
278
279 switch (Alignment)
280 {
281 case DAC_ALIGN_12B_R:
282 /* Get DHR12R1 address */
283 tmpreg = (uint32_t)&hdac->Instance->DHR12RD;
284 break;
285 case DAC_ALIGN_12B_L:
286 /* Get DHR12L1 address */
287 tmpreg = (uint32_t)&hdac->Instance->DHR12LD;
288 break;
289 case DAC_ALIGN_8B_R:
290 /* Get DHR8R1 address */
291 tmpreg = (uint32_t)&hdac->Instance->DHR8RD;
292 break;
293 default:
294 break;
295 }
296
297 /* Enable the DMA channel */
298 if (Channel == DAC_CHANNEL_1)
299 {
300 /* Enable the DAC DMA underrun interrupt */
301 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
302
303 /* Length should be converted to number of bytes */
304 LengthInBytes = Length * 4U;
305
306 /* Check linkedlist mode */
307 if ((hdac->DMA_Handle1->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
308 {
309 if ((hdac->DMA_Handle1->LinkedListQueue != NULL) && (hdac->DMA_Handle1->LinkedListQueue->Head != NULL))
310 {
311 /* Set DMA data size */
312 hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = LengthInBytes;
313
314 /* Set DMA source address */
315 hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
316
317 /* Set DMA destination address */
318 hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = tmpreg;
319
320 /* Enable the DMA channel */
321 status = HAL_DMAEx_List_Start_IT(hdac->DMA_Handle1);
322 }
323 else
324 {
325 /* Return error status */
326 return HAL_ERROR;
327 }
328 }
329 else
330 {
331 /* Enable the DMA channel */
332 status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, LengthInBytes);
333 }
334 }
335 else
336 {
337 /* Enable the DAC DMA underrun interrupt */
338 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
339
340 /* Length should be converted to number of bytes */
341 LengthInBytes = Length * 4U;
342
343 /* Check linkedlist mode */
344 if ((hdac->DMA_Handle2->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
345 {
346 if ((hdac->DMA_Handle2->LinkedListQueue != NULL) && (hdac->DMA_Handle2->LinkedListQueue->Head != NULL))
347 {
348 /* Set DMA data size */
349 hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = LengthInBytes;
350
351 /* Set DMA source address */
352 hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
353
354 /* Set DMA destination address */
355 hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = tmpreg;
356
357 /* Enable the DMA channel */
358 status = HAL_DMAEx_List_Start_IT(hdac->DMA_Handle2);
359 }
360 else
361 {
362 /* Return error status */
363 return HAL_ERROR;
364 }
365 }
366 else
367 {
368 /* Enable the DMA channel */
369 status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, LengthInBytes);
370 }
371 }
372
373 /* Process Unlocked */
374 __HAL_UNLOCK(hdac);
375
376 if (status == HAL_OK)
377 {
378 /* Enable the Peripheral */
379 __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
380 __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
381 /* Ensure minimum wait before using peripheral after enabling it */
382 /* Wait loop initialization and execution */
383 /* Note: Variable divided by 2 to compensate partially */
384 /* CPU processing cycles, scaling in us split to not */
385 /* exceed 32 bits register capacity and handle low frequency. */
386 wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
387 while (wait_loop_index != 0UL)
388 {
389 wait_loop_index--;
390 }
391 }
392 else
393 {
394 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
395 }
396
397 /* Return function status */
398 return status;
399 }
400
401 /**
402 * @brief Disables DAC and stop conversion both channel.
403 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
404 * the configuration information for the specified DAC.
405 * @param Channel The DAC channel that requests data from DMA.
406 * This parameter can be one of the following values:
407 * @arg DAC_CHANNEL_1: DAC Channel1 selected
408 * @arg DAC_CHANNEL_2: DAC Channel2 selected
409 * @retval HAL status
410 */
HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef * hdac,uint32_t Channel)411 HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
412 {
413 HAL_StatusTypeDef status;
414
415 /* Check the DAC peripheral handle */
416 if (hdac == NULL)
417 {
418 return HAL_ERROR;
419 }
420
421
422 /* Disable the selected DAC channel DMA request */
423 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2 | DAC_CR_DMAEN1);
424
425 /* Disable the Peripheral */
426 __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
427 __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
428
429 /* Disable the DMA channel */
430
431 /* Channel1 is used */
432 if (Channel == DAC_CHANNEL_1)
433 {
434 /* Disable the DMA channel */
435 status = HAL_DMA_Abort(hdac->DMA_Handle1);
436
437 /* Disable the DAC DMA underrun interrupt */
438 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
439 }
440 else
441 {
442 /* Disable the DMA channel */
443 status = HAL_DMA_Abort(hdac->DMA_Handle2);
444
445 /* Disable the DAC DMA underrun interrupt */
446 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
447 }
448
449 /* Check if DMA Channel effectively disabled */
450 if (status != HAL_OK)
451 {
452 /* Update DAC state machine to error */
453 hdac->State = HAL_DAC_STATE_ERROR;
454 }
455 else
456 {
457 /* Change DAC state */
458 hdac->State = HAL_DAC_STATE_READY;
459 }
460
461 /* Return function status */
462 return status;
463 }
464
465
466 /**
467 * @brief Enable or disable the selected DAC channel wave generation.
468 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
469 * the configuration information for the specified DAC.
470 * @param Channel The selected DAC channel.
471 * This parameter can be one of the following values:
472 * @arg DAC_CHANNEL_1: DAC Channel1 selected
473 * @arg DAC_CHANNEL_2: DAC Channel2 selected
474 * @param Amplitude Select max triangle amplitude.
475 * This parameter can be one of the following values:
476 * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
477 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
478 * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
479 * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
480 * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
481 * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
482 * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
483 * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
484 * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
485 * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
486 * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
487 * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
488 * @retval HAL status
489 */
HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef * hdac,uint32_t Channel,uint32_t Amplitude)490 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
491 {
492 /* Check the DAC peripheral handle */
493 if (hdac == NULL)
494 {
495 return HAL_ERROR;
496 }
497
498 /* Check the parameters */
499 assert_param(IS_DAC_CHANNEL(Channel));
500 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
501
502 /* Process locked */
503 __HAL_LOCK(hdac);
504
505 /* Change DAC state */
506 hdac->State = HAL_DAC_STATE_BUSY;
507
508 /* Enable the triangle wave generation for the selected DAC channel */
509 MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
510 (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
511
512 /* Change DAC state */
513 hdac->State = HAL_DAC_STATE_READY;
514
515 /* Process unlocked */
516 __HAL_UNLOCK(hdac);
517
518 /* Return function status */
519 return HAL_OK;
520 }
521
522 /**
523 * @brief Enable or disable the selected DAC channel wave generation.
524 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
525 * the configuration information for the specified DAC.
526 * @param Channel The selected DAC channel.
527 * This parameter can be one of the following values:
528 * @arg DAC_CHANNEL_1: DAC Channel1 selected
529 * @arg DAC_CHANNEL_2: DAC Channel2 selected
530 * @param Amplitude Unmask DAC channel LFSR for noise wave generation.
531 * This parameter can be one of the following values:
532 * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
533 * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
534 * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
535 * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
536 * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
537 * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
538 * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
539 * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
540 * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
541 * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
542 * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
543 * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
544 * @retval HAL status
545 */
HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef * hdac,uint32_t Channel,uint32_t Amplitude)546 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
547 {
548 /* Check the DAC peripheral handle */
549 if (hdac == NULL)
550 {
551 return HAL_ERROR;
552 }
553
554 /* Check the parameters */
555 assert_param(IS_DAC_CHANNEL(Channel));
556 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
557
558 /* Process locked */
559 __HAL_LOCK(hdac);
560
561 /* Change DAC state */
562 hdac->State = HAL_DAC_STATE_BUSY;
563
564 /* Enable the noise wave generation for the selected DAC channel */
565 MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
566 (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
567
568 /* Change DAC state */
569 hdac->State = HAL_DAC_STATE_READY;
570
571 /* Process unlocked */
572 __HAL_UNLOCK(hdac);
573
574 /* Return function status */
575 return HAL_OK;
576 }
577
578
579 /**
580 * @brief Set the specified data holding register value for dual DAC channel.
581 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
582 * the configuration information for the specified DAC.
583 * @param Alignment Specifies the data alignment for dual channel DAC.
584 * This parameter can be one of the following values:
585 * DAC_ALIGN_8B_R: 8bit right data alignment selected
586 * DAC_ALIGN_12B_L: 12bit left data alignment selected
587 * DAC_ALIGN_12B_R: 12bit right data alignment selected
588 * @param Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
589 * @param Data2 Data for DAC Channel2 to be loaded in the selected data holding register.
590 * @note In dual mode, a unique register access is required to write in both
591 * DAC channels at the same time.
592 * @retval HAL status
593 */
HAL_DACEx_DualSetValue(DAC_HandleTypeDef * hdac,uint32_t Alignment,uint32_t Data1,uint32_t Data2)594 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
595 {
596 uint32_t data;
597 uint32_t tmp;
598
599 /* Check the DAC peripheral handle */
600 if (hdac == NULL)
601 {
602 return HAL_ERROR;
603 }
604
605 /* Check the parameters */
606 assert_param(IS_DAC_ALIGN(Alignment));
607 assert_param(IS_DAC_DATA(Data1));
608 assert_param(IS_DAC_DATA(Data2));
609
610 /* Calculate and set dual DAC data holding register value */
611 if (Alignment == DAC_ALIGN_8B_R)
612 {
613 data = ((uint32_t)Data2 << 8U) | Data1;
614 }
615 else
616 {
617 data = ((uint32_t)Data2 << 16U) | Data1;
618 }
619
620 tmp = (uint32_t)hdac->Instance;
621 tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
622
623 /* Set the dual DAC selected data holding register */
624 *(__IO uint32_t *)tmp = data;
625
626 /* Return function status */
627 return HAL_OK;
628 }
629
630 /**
631 * @brief Conversion complete callback in non-blocking mode for Channel2.
632 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
633 * the configuration information for the specified DAC.
634 * @retval None
635 */
HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef * hdac)636 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
637 {
638 /* Prevent unused argument(s) compilation warning */
639 UNUSED(hdac);
640
641 /* NOTE : This function should not be modified, when the callback is needed,
642 the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
643 */
644 }
645
646 /**
647 * @brief Conversion half DMA transfer callback in non-blocking mode for Channel2.
648 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
649 * the configuration information for the specified DAC.
650 * @retval None
651 */
HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef * hdac)652 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
653 {
654 /* Prevent unused argument(s) compilation warning */
655 UNUSED(hdac);
656
657 /* NOTE : This function should not be modified, when the callback is needed,
658 the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
659 */
660 }
661
662 /**
663 * @brief Error DAC callback for Channel2.
664 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
665 * the configuration information for the specified DAC.
666 * @retval None
667 */
HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef * hdac)668 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
669 {
670 /* Prevent unused argument(s) compilation warning */
671 UNUSED(hdac);
672
673 /* NOTE : This function should not be modified, when the callback is needed,
674 the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
675 */
676 }
677
678 /**
679 * @brief DMA underrun DAC callback for Channel2.
680 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
681 * the configuration information for the specified DAC.
682 * @retval None
683 */
HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef * hdac)684 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
685 {
686 /* Prevent unused argument(s) compilation warning */
687 UNUSED(hdac);
688
689 /* NOTE : This function should not be modified, when the callback is needed,
690 the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
691 */
692 }
693
694
695 /**
696 * @brief Run the self calibration of one DAC channel.
697 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
698 * the configuration information for the specified DAC.
699 * @param sConfig DAC channel configuration structure.
700 * @param Channel The selected DAC channel.
701 * This parameter can be one of the following values:
702 * @arg DAC_CHANNEL_1: DAC Channel1 selected
703 * @arg DAC_CHANNEL_2: DAC Channel2 selected
704 * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
705 * @retval HAL status
706 * @note Calibration runs about 7 ms.
707 */
HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef * hdac,DAC_ChannelConfTypeDef * sConfig,uint32_t Channel)708 HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
709 {
710 HAL_StatusTypeDef status = HAL_OK;
711
712 uint32_t trimmingvalue;
713 uint32_t delta;
714 __IO uint32_t wait_loop_index;
715
716 /* store/restore channel configuration structure purpose */
717 uint32_t oldmodeconfiguration;
718
719 /* Check the parameters */
720 assert_param(IS_DAC_CHANNEL(Channel));
721
722 /* Check the DAC handle allocation */
723 /* Check if DAC running */
724 if ((hdac == NULL) || (sConfig == NULL))
725 {
726 status = HAL_ERROR;
727 }
728 else if (hdac->State == HAL_DAC_STATE_BUSY)
729 {
730 status = HAL_ERROR;
731 }
732 else
733 {
734 /* Process locked */
735 __HAL_LOCK(hdac);
736
737 /* Store configuration */
738 oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << (Channel & 0x10UL)));
739
740 /* Disable the selected DAC channel */
741 CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL)));
742 /* Wait for ready bit to be de-asserted */
743 HAL_Delay(1);
744
745 /* Set mode in MCR for calibration */
746 MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U);
747
748 /* Enable the selected DAC channel calibration */
749 /* i.e. set DAC_CR_CENx bit */
750 SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
751
752 /* Init trimming counter */
753 /* Medium value */
754 trimmingvalue = 16UL;
755 delta = 8UL;
756 while (delta != 0UL)
757 {
758 /* Set candidate trimming */
759 MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
760
761 /* Wait minimum time needed between two calibration steps (OTRIM) */
762 /* Wait loop initialization and execution */
763 /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
764 /* 32 bits register capacity and handle low frequency. */
765 wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
766 while(wait_loop_index != 0UL)
767 {
768 wait_loop_index--;
769 }
770
771 if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))
772 {
773 /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
774 trimmingvalue -= delta;
775 }
776 else
777 {
778 /* DAC_SR_CAL_FLAGx is LOW try lower trimming */
779 trimmingvalue += delta;
780 }
781 delta >>= 1UL;
782 }
783
784 /* Still need to check if right calibration is current value or one step below */
785 /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1 */
786 /* Set candidate trimming */
787 MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
788
789 /* Wait minimum time needed between two calibration steps (OTRIM) */
790 /* Wait loop initialization and execution */
791 /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
792 /* 32 bits register capacity and handle low frequency. */
793 wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
794 while(wait_loop_index != 0UL)
795 {
796 wait_loop_index--;
797 }
798
799 if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
800 {
801 /* Trimming is actually one value more */
802 trimmingvalue++;
803 /* Set right trimming */
804 MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
805 }
806
807 /* Disable the selected DAC channel calibration */
808 /* i.e. clear DAC_CR_CENx bit */
809 CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
810
811 sConfig->DAC_TrimmingValue = trimmingvalue;
812 sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
813
814 /* Restore configuration */
815 MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration);
816
817 /* Process unlocked */
818 __HAL_UNLOCK(hdac);
819 }
820
821 return status;
822 }
823
824 /**
825 * @brief Set the trimming mode and trimming value (user trimming mode applied).
826 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
827 * the configuration information for the specified DAC.
828 * @param sConfig DAC configuration structure updated with new DAC trimming value.
829 * @param Channel The selected DAC channel.
830 * This parameter can be one of the following values:
831 * @arg DAC_CHANNEL_1: DAC Channel1 selected
832 * @arg DAC_CHANNEL_2: DAC Channel2 selected
833 * @param NewTrimmingValue DAC new trimming value
834 * @retval HAL status
835 */
HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef * hdac,DAC_ChannelConfTypeDef * sConfig,uint32_t Channel,uint32_t NewTrimmingValue)836 HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
837 uint32_t NewTrimmingValue)
838 {
839 HAL_StatusTypeDef status = HAL_OK;
840
841 /* Check the parameters */
842 assert_param(IS_DAC_CHANNEL(Channel));
843 assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
844
845 /* Check the DAC handle and channel configuration struct allocation */
846 if ((hdac == NULL) || (sConfig == NULL))
847 {
848 status = HAL_ERROR;
849 }
850 else
851 {
852 /* Process locked */
853 __HAL_LOCK(hdac);
854
855 /* Set new trimming */
856 MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL)));
857
858 /* Update trimming mode */
859 sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
860 sConfig->DAC_TrimmingValue = NewTrimmingValue;
861
862 /* Process unlocked */
863 __HAL_UNLOCK(hdac);
864 }
865 return status;
866 }
867
868 /**
869 * @brief Return the DAC trimming value.
870 * @param hdac DAC handle
871 * @param Channel The selected DAC channel.
872 * This parameter can be one of the following values:
873 * @arg DAC_CHANNEL_1: DAC Channel1 selected
874 * @arg DAC_CHANNEL_2: DAC Channel2 selected
875 * @retval Trimming value : range: 0->31
876 *
877 */
HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef * hdac,uint32_t Channel)878 uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel)
879 {
880 /* Check the parameter */
881 assert_param(IS_DAC_CHANNEL(Channel));
882
883 /* Retrieve trimming */
884 return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL));
885 }
886
887 /**
888 * @}
889 */
890
891 /** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
892 * @brief Extended Peripheral Control functions
893 *
894 @verbatim
895 ==============================================================================
896 ##### Peripheral Control functions #####
897 ==============================================================================
898 [..] This section provides functions allowing to:
899 (+) Set the specified data holding register value for DAC channel.
900
901 @endverbatim
902 * @{
903 */
904
905
906 /**
907 * @brief Return the last data output value of the selected DAC channel.
908 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
909 * the configuration information for the specified DAC.
910 * @retval The selected DAC channel data output value.
911 */
HAL_DACEx_DualGetValue(const DAC_HandleTypeDef * hdac)912 uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac)
913 {
914 uint32_t tmp = 0UL;
915
916 tmp |= hdac->Instance->DOR1;
917
918 tmp |= hdac->Instance->DOR2 << 16UL;
919
920 /* Returns the DAC channel data output register value */
921 return tmp;
922 }
923
924
925 /**
926 * @}
927 */
928 /**
929 * @}
930 */
931
932 /* Private functions ---------------------------------------------------------*/
933 /** @defgroup DACEx_Private_Functions DACEx private functions
934 * @brief Extended private functions
935 * @{
936 */
937
938
939 /**
940 * @brief DMA conversion complete callback.
941 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
942 * the configuration information for the specified DMA module.
943 * @retval None
944 */
DAC_DMAConvCpltCh2(DMA_HandleTypeDef * hdma)945 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
946 {
947 DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
948
949 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
950 hdac->ConvCpltCallbackCh2(hdac);
951 #else
952 HAL_DACEx_ConvCpltCallbackCh2(hdac);
953 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
954
955 hdac->State = HAL_DAC_STATE_READY;
956 }
957
958 /**
959 * @brief DMA half transfer complete callback.
960 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
961 * the configuration information for the specified DMA module.
962 * @retval None
963 */
DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef * hdma)964 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
965 {
966 DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
967 /* Conversion complete callback */
968 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
969 hdac->ConvHalfCpltCallbackCh2(hdac);
970 #else
971 HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
972 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
973 }
974
975 /**
976 * @brief DMA error callback.
977 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
978 * the configuration information for the specified DMA module.
979 * @retval None
980 */
DAC_DMAErrorCh2(DMA_HandleTypeDef * hdma)981 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
982 {
983 DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
984
985 /* Set DAC error code to DMA error */
986 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
987
988 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
989 hdac->ErrorCallbackCh2(hdac);
990 #else
991 HAL_DACEx_ErrorCallbackCh2(hdac);
992 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
993
994 hdac->State = HAL_DAC_STATE_READY;
995 }
996
997
998 /**
999 * @}
1000 */
1001
1002 /**
1003 * @}
1004 */
1005
1006 #endif /* DAC1 */
1007
1008 #endif /* HAL_DAC_MODULE_ENABLED */
1009
1010 /**
1011 * @}
1012 */
1013
