1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the CORTEX:
8 * + Initialization and Configuration functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2022 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 @verbatim
23 ==============================================================================
24 ##### How to use this driver #####
25 ==============================================================================
26
27 [..]
28 *** How to configure Interrupts using CORTEX HAL driver ***
29 ===========================================================
30 [..]
31 This section provides functions allowing to configure the NVIC interrupts (IRQ).
32 The Cortex-M33 exceptions are managed by CMSIS functions.
33
34 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
35 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
36 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
37
38 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
39 The pending IRQ priority will be managed only by the sub priority.
40
41 -@- IRQ priority order (sorted by highest to lowest priority):
42 (+@) Lowest pre-emption priority
43 (+@) Lowest sub priority
44 (+@) Lowest hardware priority (IRQ number)
45
46 [..]
47 *** How to configure SysTick using CORTEX HAL driver ***
48 ========================================================
49 [..]
50 Setup SysTick Timer for time base.
51
52 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
53 is a CMSIS function that:
54 (++) Configures the SysTick Reload register with value passed as function parameter.
55 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
56 (++) Resets the SysTick Counter register.
57 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
58 (++) Enables the SysTick Interrupt.
59 (++) Starts the SysTick Counter.
60
61 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
62 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
63 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
64 inside the stm32h5xx_hal_cortex.h file.
65
66 (+) You can change the SysTick IRQ priority by calling the
67 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
68 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
69
70 (+) To adjust the SysTick time base, use the following formula:
71
72 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
73 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
74 (++) Reload Value should not exceed 0xFFFFFF
75
76 [..]
77 *** How to configure MPU (secure and non secure) using CORTEX HAL driver ***
78 ===========================================================
79 [..]
80 This section provides functions allowing to Enable and configure the MPU secure and non-secure.
81
82 (#) Enable the MPU using HAL_MPU_Enable() function.
83 (#) Disable the MPU using HAL_MPU_Disable() function.
84 (#) Enable the MPU using HAL_MPU_Enable_NS() function to address the non secure MPU.
85 (#) Disable the MPU using HAL_MPU_Disable_NS() function to address the non secure MPU.
86 (#) Configure the MPU region using HAL_MPU_ConfigRegion()
87 and HAL_MPU_ConfigRegion_NS() to address the non secure MPU.
88 (#) Configure the MPU Memory attributes using HAL_MPU_ConfigMemoryAttributes()
89 and HAL_MPU_ConfigMemoryAttributes_NS() to address the non secure MPU.
90
91 @endverbatim
92 ******************************************************************************
93
94 The table below gives the allowed values of the pre-emption priority and subpriority according
95 to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
96
97 ========================================================================================================================
98 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
99 ========================================================================================================================
100 NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority
101 | | | 4 bits for subpriority
102 ------------------------------------------------------------------------------------------------------------------------
103 NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority
104 | | | 3 bits for subpriority
105 ------------------------------------------------------------------------------------------------------------------------
106 NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
107 | | | 2 bits for subpriority
108 ------------------------------------------------------------------------------------------------------------------------
109 NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
110 | | | 1 bit for subpriority
111 ------------------------------------------------------------------------------------------------------------------------
112 NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
113 | | | 0 bit for subpriority
114 ========================================================================================================================
115 */
116
117 /* Includes ------------------------------------------------------------------*/
118 #include "stm32h5xx_hal.h"
119
120 /** @addtogroup STM32H5xx_HAL_Driver
121 * @{
122 */
123
124 /** @addtogroup CORTEX
125 * @{
126 */
127
128 #ifdef HAL_CORTEX_MODULE_ENABLED
129
130 /* Private types -------------------------------------------------------------*/
131 /* Private variables ---------------------------------------------------------*/
132 /* Private constants ---------------------------------------------------------*/
133 /* Private macros ------------------------------------------------------------*/
134 /* Private functions ---------------------------------------------------------*/
135 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
136 * @{
137 */
138 static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const pMPU_RegionInit);
139 static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit);
140 /**
141 * @}
142 */
143 /* Exported functions --------------------------------------------------------*/
144
145 /** @addtogroup CORTEX_Exported_Functions
146 * @{
147 */
148
149
150 /** @addtogroup CORTEX_Exported_Functions_Group1
151 * @brief NVIC functions
152 *
153 @verbatim
154 ==============================================================================
155 ##### NVIC functions #####
156 ==============================================================================
157 [..]
158 This section provides the CORTEX HAL driver functions for NVIC functionalities
159
160 @endverbatim
161 * @{
162 */
163
164
165 /**
166 * @brief Set the priority grouping field (pre-emption priority and subpriority)
167 * using the required unlock sequence.
168 * @param PriorityGroup: The priority grouping bits length.
169 * This parameter can be one of the following values:
170 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
171 * 4 bits for subpriority
172 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
173 * 3 bits for subpriority
174 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
175 * 2 bits for subpriority
176 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
177 * 1 bit for subpriority
178 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
179 * 0 bit for subpriority
180 * @note When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
181 * The pending IRQ priority will be managed only by the subpriority.
182 * @retval None
183 */
HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)184 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
185 {
186 /* Check the parameters */
187 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
188
189 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
190 NVIC_SetPriorityGrouping(PriorityGroup);
191 }
192
193 /**
194 * @brief Set the priority of an interrupt.
195 * @param IRQn: External interrupt number.
196 * This parameter can be an enumerator of IRQn_Type enumeration
197 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
198 * CMSIS device file (stm32h5xxxx.h))
199 * @param PreemptPriority: The pre-emption priority for the IRQn channel.
200 * This parameter can be a value between 0 and 15
201 * A lower priority value indicates a higher priority
202 * @param SubPriority: the subpriority level for the IRQ channel.
203 * This parameter can be a value between 0 and 15
204 * A lower priority value indicates a higher priority.
205 * @retval None
206 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)207 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
208 {
209 uint32_t prioritygroup;
210
211 /* Check the parameters */
212 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
213 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
214
215 prioritygroup = NVIC_GetPriorityGrouping();
216
217 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
218 }
219
220 /**
221 * @brief Enable a device specific interrupt in the NVIC interrupt controller.
222 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
223 * function should be called before.
224 * @param IRQn External interrupt number.
225 * This parameter can be an enumerator of IRQn_Type enumeration
226 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
227 * CMSIS device file (stm32h5xxxx.h))
228 * @retval None
229 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)230 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
231 {
232 /* Check the parameters */
233 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
234
235 /* Enable interrupt */
236 NVIC_EnableIRQ(IRQn);
237 }
238
239 /**
240 * @brief Disable a device specific interrupt in the NVIC interrupt controller.
241 * @param IRQn External interrupt number.
242 * This parameter can be an enumerator of IRQn_Type enumeration
243 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
244 * CMSIS device file (stm32h5xxxx.h))
245 * @retval None
246 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)247 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
248 {
249 /* Check the parameters */
250 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
251
252 /* Disable interrupt */
253 NVIC_DisableIRQ(IRQn);
254 }
255
256 /**
257 * @brief Initiate a system reset request to reset the MCU.
258 * @retval None
259 */
HAL_NVIC_SystemReset(void)260 void HAL_NVIC_SystemReset(void)
261 {
262 /* System Reset */
263 NVIC_SystemReset();
264 }
265
266 /**
267 * @brief Get the priority grouping field from the NVIC Interrupt Controller.
268 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
269 */
HAL_NVIC_GetPriorityGrouping(void)270 uint32_t HAL_NVIC_GetPriorityGrouping(void)
271 {
272 /* Get the PRIGROUP[10:8] field value */
273 return NVIC_GetPriorityGrouping();
274 }
275
276 /**
277 * @brief Get the priority of an interrupt.
278 * @param IRQn: External interrupt number.
279 * This parameter can be an enumerator of IRQn_Type enumeration
280 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
281 * CMSIS device file (stm32h5xxxx.h))
282 * @param PriorityGroup: the priority grouping bits length.
283 * This parameter can be one of the following values:
284 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
285 * 4 bits for subpriority
286 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
287 * 3 bits for subpriority
288 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
289 * 2 bits for subpriority
290 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
291 * 1 bit for subpriority
292 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
293 * 0 bit for subpriority
294 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
295 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
296 * @retval None
297 */
HAL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)298 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority,
299 uint32_t *const pSubPriority)
300 {
301 /* Check the parameters */
302 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
303 /* Get priority for Cortex-M system or device specific interrupts */
304 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
305 }
306
307 /**
308 * @brief Set Pending bit of an external interrupt.
309 * @param IRQn External interrupt number
310 * This parameter can be an enumerator of IRQn_Type enumeration
311 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
312 * CMSIS device file (stm32h5xxxx.h))
313 * @retval None
314 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)315 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
316 {
317 /* Set interrupt pending */
318 NVIC_SetPendingIRQ(IRQn);
319 }
320
321 /**
322 * @brief Get Pending Interrupt (read the pending register in the NVIC
323 * and return the pending bit for the specified interrupt).
324 * @param IRQn External interrupt number.
325 * This parameter can be an enumerator of IRQn_Type enumeration
326 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
327 * CMSIS device file (stm32h5xxxx.h))
328 * @retval status: - 0 Interrupt status is not pending.
329 * - 1 Interrupt status is pending.
330 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)331 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
332 {
333 /* Return 1 if pending else 0 */
334 return NVIC_GetPendingIRQ(IRQn);
335 }
336
337 /**
338 * @brief Clear the pending bit of an external interrupt.
339 * @param IRQn External interrupt number.
340 * This parameter can be an enumerator of IRQn_Type enumeration
341 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
342 * CMSIS device file (stm32h5xxxx.h))
343 * @retval None
344 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)345 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
346 {
347 /* Clear pending interrupt */
348 NVIC_ClearPendingIRQ(IRQn);
349 }
350
351 /**
352 * @brief Get active interrupt (read the active register in NVIC and return the active bit).
353 * @param IRQn External interrupt number
354 * This parameter can be an enumerator of IRQn_Type enumeration
355 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
356 * CMSIS device file (stm32h5xxxx.h))
357 * @retval status: - 0 Interrupt status is not pending.
358 * - 1 Interrupt status is pending.
359 */
HAL_NVIC_GetActive(IRQn_Type IRQn)360 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
361 {
362 /* Return 1 if active else 0 */
363 return NVIC_GetActive(IRQn);
364 }
365
366 /**
367 * @}
368 */
369
370
371 /** @addtogroup CORTEX_Exported_Functions_Group2
372 * @brief SYSTICK functions
373 *
374 @verbatim
375 ==============================================================================
376 ##### SYSTICK functions #####
377 ==============================================================================
378 [..]
379 This section provides the CORTEX HAL driver functions for SYSTICK functionalities
380
381
382 @endverbatim
383 * @{
384 */
385
386 /**
387 * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
388 * Counter is in free running mode to generate periodic interrupts.
389 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
390 * @retval status: - 0 Function succeeded.
391 * - 1 Function failed.
392 */
HAL_SYSTICK_Config(uint32_t TicksNumb)393 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
394 {
395 return SysTick_Config(TicksNumb);
396 }
397
398 /**
399 * @brief Configure the SysTick clock source.
400 * @param CLKSource: specifies the SysTick clock source.
401 * This parameter can be one of the following values:
402 * @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source.
403 * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source.
404 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
405 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
406 * @retval None
407 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)408 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
409 {
410 /* Check the parameters */
411 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
412 switch (CLKSource)
413 {
414 /* Select HCLK as Systick clock source */
415 case SYSTICK_CLKSOURCE_HCLK:
416 SET_BIT(SysTick->CTRL, SYSTICK_CLKSOURCE_HCLK);
417 break;
418 /* Select HCLK_DIV8 as Systick clock source */
419 case SYSTICK_CLKSOURCE_HCLK_DIV8:
420 CLEAR_BIT(SysTick->CTRL, SYSTICK_CLKSOURCE_HCLK);
421 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SYSTICKSEL, (0x00000000U));
422 break;
423 /* Select LSI as Systick clock source */
424 case SYSTICK_CLKSOURCE_LSI:
425 CLEAR_BIT(SysTick->CTRL, SYSTICK_CLKSOURCE_HCLK);
426 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SYSTICKSEL, RCC_CCIPR4_SYSTICKSEL_0);
427 break;
428 /* Select LSE as Systick clock source */
429 case SYSTICK_CLKSOURCE_LSE:
430 CLEAR_BIT(SysTick->CTRL, SYSTICK_CLKSOURCE_HCLK);
431 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_SYSTICKSEL, RCC_CCIPR4_SYSTICKSEL_1);
432 break;
433 default:
434 /* Nothing to do */
435 break;
436 }
437 }
438
439 /**
440 * @brief Handle SYSTICK interrupt request.
441 * @retval None
442 */
HAL_SYSTICK_IRQHandler(void)443 void HAL_SYSTICK_IRQHandler(void)
444 {
445 HAL_SYSTICK_Callback();
446 }
447
448 /**
449 * @brief SYSTICK callback.
450 * @retval None
451 */
HAL_SYSTICK_Callback(void)452 __weak void HAL_SYSTICK_Callback(void)
453 {
454 /* NOTE : This function should not be modified, when the callback is needed,
455 the HAL_SYSTICK_Callback could be implemented in the user file
456 */
457 }
458
459 /**
460 * @}
461 */
462
463 /** @addtogroup CORTEX_Exported_Functions_Group3
464 * @brief MPU functions
465 *
466 @verbatim
467 ==============================================================================
468 ##### MPU functions #####
469 ==============================================================================
470 [..]
471 This section provides the CORTEX HAL driver functions for MPU functionalities
472
473
474 @endverbatim
475 * @{
476 */
477
478 /**
479 * @brief Enable the MPU.
480 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
481 * NMI, FAULTMASK and privileged access to the default memory
482 * This parameter can be one of the following values:
483 * @arg MPU_HFNMI_PRIVDEF_NONE
484 * @arg MPU_HARDFAULT_NMI
485 * @arg MPU_PRIVILEGED_DEFAULT
486 * @arg MPU_HFNMI_PRIVDEF
487 * @retval None
488 */
HAL_MPU_Enable(uint32_t MPU_Control)489 void HAL_MPU_Enable(uint32_t MPU_Control)
490 {
491 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
492
493 /* Enable the MPU */
494 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
495
496 /* Enable fault exceptions */
497 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
498
499 /* Follow ARM recommendation with */
500 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
501 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
502 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
503 }
504
505 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
506 /**
507 * @brief Enable the non-secure MPU.
508 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
509 * NMI, FAULTMASK and privileged access to the default memory
510 * This parameter can be one of the following values:
511 * @arg MPU_HFNMI_PRIVDEF_NONE
512 * @arg MPU_HARDFAULT_NMI
513 * @arg MPU_PRIVILEGED_DEFAULT
514 * @arg MPU_HFNMI_PRIVDEF
515 * @retval None
516 */
HAL_MPU_Enable_NS(uint32_t MPU_Control)517 void HAL_MPU_Enable_NS(uint32_t MPU_Control)
518 {
519 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
520
521 /* Enable the MPU */
522 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
523
524 /* Enable fault exceptions */
525 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
526
527 /* Follow ARM recommendation with */
528 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
529 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
530 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
531 }
532 #endif /* __ARM_FEATURE_CMSE */
533
534 /**
535 * @brief Disable the MPU.
536 * @retval None
537 */
HAL_MPU_Disable(void)538 void HAL_MPU_Disable(void)
539 {
540 __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
541
542 /* Disable fault exceptions */
543 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
544
545 /* Disable the MPU */
546 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
547
548 /* Follow ARM recommendation with */
549 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
550 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
551 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
552 }
553
554 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
555 /**
556 * @brief Disable the non-secure MPU.
557 * @retval None
558 */
HAL_MPU_Disable_NS(void)559 void HAL_MPU_Disable_NS(void)
560 {
561 __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
562
563 /* Disable fault exceptions */
564 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
565
566 /* Disable the MPU */
567 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
568
569 /* Follow ARM recommendation with */
570 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
571 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
572 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
573 }
574 #endif /* __ARM_FEATURE_CMSE */
575
576 /**
577 * @brief Initialize and configure the Region and the memory to be protected.
578 * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains
579 * the initialization and configuration information.
580 * @retval None
581 */
HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef * const pMPU_RegionInit)582 void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit)
583 {
584 MPU_ConfigRegion(MPU, pMPU_RegionInit);
585 }
586
587 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
588 /**
589 * @brief Initialize and configure the Region and the memory to be protected for non-secure MPU.
590 * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains
591 * the initialization and configuration information.
592 * @retval None
593 */
HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef * const pMPU_RegionInit)594 void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit)
595 {
596 MPU_ConfigRegion(MPU_NS, pMPU_RegionInit);
597 }
598 #endif /* __ARM_FEATURE_CMSE */
599
600 /**
601 * @brief Initialize and configure the memory attributes.
602 * @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains
603 * the initialization and configuration information.
604 * @retval None
605 */
HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef * const pMPU_AttributesInit)606 void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit)
607 {
608 MPU_ConfigMemoryAttributes(MPU, pMPU_AttributesInit);
609 }
610
611 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
612 /**
613 * @brief Initialize and configure the memory attributes for non-secure MPU.
614 * @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains
615 * the initialization and configuration information.
616 * @retval None
617 */
HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef * const pMPU_AttributesInit)618 void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit)
619 {
620 MPU_ConfigMemoryAttributes(MPU_NS, pMPU_AttributesInit);
621 }
622 #endif /* __ARM_FEATURE_CMSE */
623
624 /**
625 * @}
626 */
627
628 /**
629 * @}
630 */
631
632 /** @addtogroup CORTEX_Private_Functions
633 * @{
634 */
635 /**
636 * @brief Initialize and configure the Region and the memory to be protected for MPU.
637 * @param MPUx: Pointer to MPU_Type structure
638 * This parameter can be one of the following values:
639 * @arg MPU
640 * @arg MPU_NS
641 * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains
642 * the initialization and configuration information.
643 * @retval None
644 */
MPU_ConfigRegion(MPU_Type * MPUx,const MPU_Region_InitTypeDef * const pMPU_RegionInit)645 static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const pMPU_RegionInit)
646 {
647 /* Check the parameters */
648 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
649 assert_param(IS_MPU_INSTANCE(MPUx));
650 #endif /* __ARM_FEATURE_CMSE */
651 assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number));
652 assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable));
653
654 /* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */
655 __DMB();
656
657 /* Set the Region number */
658 MPUx->RNR = pMPU_RegionInit->Number;
659
660 if (pMPU_RegionInit->Enable != MPU_REGION_DISABLE)
661 {
662 /* Check the parameters */
663 assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec));
664 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission));
665 assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable));
666
667 MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) |
668 ((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) |
669 ((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) |
670 ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos));
671
672 MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) |
673 ((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) |
674 ((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos));
675 }
676 else
677 {
678 MPUx->RBAR = 0U;
679 MPUx->RLAR = 0U;
680 }
681 }
682
683 /**
684 * @brief Initialize and configure the memory attributes for MPU.
685 * @param MPUx: Pointer to MPU_Type structure
686 * This parameter can be one of the following values:
687 * @arg MPU
688 * @arg MPU_NS
689 * @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains
690 * the initialization and configuration information.
691 * @retval None
692 */
MPU_ConfigMemoryAttributes(MPU_Type * MPUx,const MPU_Attributes_InitTypeDef * const pMPU_AttributesInit)693 static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit)
694 {
695 __IO uint32_t *p_mair;
696 uint32_t attr_values;
697 uint32_t attr_number;
698
699 /* Check the parameters */
700 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
701 assert_param(IS_MPU_INSTANCE(MPUx));
702 #endif /* __ARM_FEATURE_CMSE */
703 assert_param(IS_MPU_ATTRIBUTES_NUMBER(pMPU_AttributesInit->Number));
704 /* No need to check Attributes value as all 0x0..0xFF possible */
705
706 /* Follow ARM recommendation with Data Memory Barrier prior to MPUx configuration */
707 __DMB();
708
709 if (pMPU_AttributesInit->Number < MPU_ATTRIBUTES_NUMBER4)
710 {
711 /* Program MPU_MAIR0 */
712 p_mair = &(MPUx->MAIR0);
713 attr_number = pMPU_AttributesInit->Number;
714 }
715 else
716 {
717 /* Program MPU_MAIR1 */
718 p_mair = &(MPUx->MAIR1);
719 attr_number = (uint32_t)pMPU_AttributesInit->Number - 4U;
720 }
721
722 attr_values = *(p_mair);
723 attr_values &= ~(0xFFUL << (attr_number * 8U));
724 *(p_mair) = attr_values | ((uint32_t)pMPU_AttributesInit->Attributes << (attr_number * 8U));
725 }
726 /**
727 * @}
728 */
729
730 #endif /* HAL_CORTEX_MODULE_ENABLED */
731 /**
732 * @}
733 */
734
735 /**
736 * @}
737 */
738
