1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_adc_ex.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Converter (ADC)
7 * peripheral:
8 * + Peripheral Control functions
9 * Other functions (generic functions) are available in file
10 * "stm32h5xx_hal_adc.c".
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2022 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 [..]
25 (@) Sections "ADC peripheral features" and "How to use this driver" are
26 available in file of generic functions "stm32h5xx_hal_adc.c".
27 [..]
28 @endverbatim
29 ******************************************************************************
30 */
31
32 /* Includes ------------------------------------------------------------------*/
33 #include "stm32h5xx_hal.h"
34
35 /** @addtogroup STM32H5xx_HAL_Driver
36 * @{
37 */
38
39 /** @defgroup ADCEx ADCEx
40 * @brief ADC Extended HAL module driver
41 * @{
42 */
43
44 #ifdef HAL_ADC_MODULE_ENABLED
45
46 /* Private typedef -----------------------------------------------------------*/
47 /* Private define ------------------------------------------------------------*/
48
49 /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
50 * @{
51 */
52
53 #define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
54 ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
55 ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can
56 be updated anytime once the ADC is enabled */
57
58 /* Fixed timeout value for ADC calibration. */
59 /* Fixed timeout value for ADC calibration. */
60 /* Values defined to be higher than worst cases: low clock frequency, */
61 /* maximum prescalers. */
62 /* Ex of profile low frequency : f_ADC at 0.125 Mhz (minimum value */
63 /* according to Data sheet), calibration_time MAX = 165010 / f_ADC */
64 /* 165010 / 125000 = 1.32s */
65 /* At maximum CPU speed (480 MHz), this means */
66 /* 1.32 * 480 MHz = 633600000 CPU cycles */
67 #define ADC_CALIBRATION_TIMEOUT (633600000UL) /*!< ADC calibration time-out value */
68
69 /**
70 * @}
71 */
72
73 /* Private macro -------------------------------------------------------------*/
74 /* Private variables ---------------------------------------------------------*/
75 /* Private function prototypes -----------------------------------------------*/
76 /* Exported functions --------------------------------------------------------*/
77
78 /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
79 * @{
80 */
81
82 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
83 * @brief Extended IO operation functions
84 *
85 @verbatim
86 ===============================================================================
87 ##### IO operation functions #####
88 ===============================================================================
89 [..] This section provides functions allowing to:
90
91 (+) Perform the ADC self-calibration for single or differential ending.
92 (+) Get calibration factors for single or differential ending.
93 (+) Set calibration factors for single or differential ending.
94
95 (+) Start conversion of ADC group injected.
96 (+) Stop conversion of ADC group injected.
97 (+) Poll for conversion complete on ADC group injected.
98 (+) Get result of ADC group injected channel conversion.
99 (+) Start conversion of ADC group injected and enable interruptions.
100 (+) Stop conversion of ADC group injected and disable interruptions.
101
102 (+) When multimode feature is available, start multimode and enable DMA transfer.
103 (+) Stop multimode and disable ADC DMA transfer.
104 (+) Get result of multimode conversion.
105
106 @endverbatim
107 * @{
108 */
109
110 /**
111 * @brief Perform an ADC automatic self-calibration
112 * Calibration prerequisite: ADC must be disabled (execute this
113 * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
114 * @param hadc ADC handle
115 * @param SingleDiff Selection of single-ended or differential input
116 * This parameter can be one of the following values:
117 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
118 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
119 * @retval HAL status
120 */
HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef * hadc,uint32_t SingleDiff)121 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
122 {
123 HAL_StatusTypeDef tmp_hal_status;
124 __IO uint32_t wait_loop_index = 0UL;
125
126 /* Check the parameters */
127 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
128 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
129
130 /* Process locked */
131 __HAL_LOCK(hadc);
132
133 /* Calibration prerequisite: ADC must be disabled. */
134
135 /* Disable the ADC (if not already disabled) */
136 tmp_hal_status = ADC_Disable(hadc);
137
138 /* Check if ADC is effectively disabled */
139 if (tmp_hal_status == HAL_OK)
140 {
141 /* Set ADC state */
142 ADC_STATE_CLR_SET(hadc->State,
143 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
144 HAL_ADC_STATE_BUSY_INTERNAL);
145
146 /* Start ADC calibration in mode single-ended or differential */
147 LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
148
149 /* Wait for calibration completion */
150 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
151 {
152 wait_loop_index++;
153 if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
154 {
155 /* Update ADC state machine to error */
156 ADC_STATE_CLR_SET(hadc->State,
157 HAL_ADC_STATE_BUSY_INTERNAL,
158 HAL_ADC_STATE_ERROR_INTERNAL);
159
160 /* Process unlocked */
161 __HAL_UNLOCK(hadc);
162
163 return HAL_ERROR;
164 }
165 }
166
167 /* Set ADC state */
168 ADC_STATE_CLR_SET(hadc->State,
169 HAL_ADC_STATE_BUSY_INTERNAL,
170 HAL_ADC_STATE_READY);
171 }
172 else
173 {
174 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
175
176 /* Note: No need to update variable "tmp_hal_status" here: already set */
177 /* to state "HAL_ERROR" by function disabling the ADC. */
178 }
179
180 /* Process unlocked */
181 __HAL_UNLOCK(hadc);
182
183 /* Return function status */
184 return tmp_hal_status;
185 }
186
187 /**
188 * @brief Get the calibration factor.
189 * @param hadc ADC handle.
190 * @param SingleDiff This parameter can be only:
191 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
192 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
193 * @retval Calibration value.
194 */
HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef * hadc,uint32_t SingleDiff)195 uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
196 {
197 /* Check the parameters */
198 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
199 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
200
201 /* Return the selected ADC calibration value */
202 return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff);
203 }
204
205 /**
206 * @brief Set the calibration factor to overwrite automatic conversion result.
207 * ADC must be enabled and no conversion is ongoing.
208 * @param hadc ADC handle
209 * @param SingleDiff This parameter can be only:
210 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
211 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
212 * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
213 * @retval HAL state
214 */
HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef * hadc,uint32_t SingleDiff,uint32_t CalibrationFactor)215 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
216 uint32_t CalibrationFactor)
217 {
218 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
219 uint32_t tmp_adc_is_conversion_on_going_regular;
220 uint32_t tmp_adc_is_conversion_on_going_injected;
221
222 /* Check the parameters */
223 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
224 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
225 assert_param(IS_ADC_CALFACT(CalibrationFactor));
226
227 /* Process locked */
228 __HAL_LOCK(hadc);
229
230 /* Verification of hardware constraints before modifying the calibration */
231 /* factors register: ADC must be enabled, no conversion on going. */
232 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
233 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
234
235 if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
236 && (tmp_adc_is_conversion_on_going_regular == 0UL)
237 && (tmp_adc_is_conversion_on_going_injected == 0UL)
238 )
239 {
240 /* Set the selected ADC calibration value */
241 LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor);
242 }
243 else
244 {
245 /* Update ADC state machine */
246 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
247 /* Update ADC error code */
248 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
249
250 /* Update ADC state machine to error */
251 tmp_hal_status = HAL_ERROR;
252 }
253
254 /* Process unlocked */
255 __HAL_UNLOCK(hadc);
256
257 /* Return function status */
258 return tmp_hal_status;
259 }
260
261 /**
262 * @brief Enable ADC, start conversion of injected group.
263 * @note Interruptions enabled in this function: None.
264 * @note Case of multimode enabled when multimode feature is available:
265 * HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
266 * then for ADC master.
267 * For ADC slave, ADC is enabled only (conversion is not started).
268 * For ADC master, ADC is enabled and multimode conversion is started.
269 * @param hadc ADC handle.
270 * @retval HAL status
271 */
HAL_ADCEx_InjectedStart(ADC_HandleTypeDef * hadc)272 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
273 {
274 HAL_StatusTypeDef tmp_hal_status;
275 uint32_t tmp_config_injected_queue;
276 #if defined(ADC_MULTIMODE_SUPPORT)
277 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
278 #endif /* ADC_MULTIMODE_SUPPORT */
279
280 /* Check the parameters */
281 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
282
283 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
284 {
285 return HAL_BUSY;
286 }
287 else
288 {
289 /* In case of software trigger detection enabled, JQDIS must be set
290 (which can be done only if ADSTART and JADSTART are both cleared).
291 If JQDIS is not set at that point, returns an error
292 - since software trigger detection is disabled. User needs to
293 resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
294 - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
295 the queue is empty */
296 tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
297
298 if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
299 && (tmp_config_injected_queue == 0UL)
300 )
301 {
302 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
303 return HAL_ERROR;
304 }
305
306 /* Process locked */
307 __HAL_LOCK(hadc);
308
309 /* Enable the ADC peripheral */
310 tmp_hal_status = ADC_Enable(hadc);
311
312 /* Start conversion if ADC is effectively enabled */
313 if (tmp_hal_status == HAL_OK)
314 {
315 /* Check if a regular conversion is ongoing */
316 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
317 {
318 /* Reset ADC error code field related to injected conversions only */
319 CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
320 }
321 else
322 {
323 /* Set ADC error code to none */
324 ADC_CLEAR_ERRORCODE(hadc);
325 }
326
327 /* Set ADC state */
328 /* - Clear state bitfield related to injected group conversion results */
329 /* - Set state bitfield related to injected operation */
330 ADC_STATE_CLR_SET(hadc->State,
331 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
332 HAL_ADC_STATE_INJ_BUSY);
333
334 #if defined(ADC_MULTIMODE_SUPPORT)
335 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
336 - if ADC instance is master or if multimode feature is not available
337 - if multimode setting is disabled (ADC instance slave in independent mode) */
338 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
339 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
340 )
341 {
342 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
343 }
344 #endif /* ADC_MULTIMODE_SUPPORT */
345
346 /* Clear ADC group injected group conversion flag */
347 /* (To ensure of no unknown state from potential previous ADC operations) */
348 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
349
350 /* Process unlocked */
351 /* Unlock before starting ADC conversions: in case of potential */
352 /* interruption, to let the process to ADC IRQ Handler. */
353 __HAL_UNLOCK(hadc);
354
355 /* Enable conversion of injected group, if automatic injected conversion */
356 /* is disabled. */
357 /* If software start has been selected, conversion starts immediately. */
358 /* If external trigger has been selected, conversion will start at next */
359 /* trigger event. */
360 /* Case of multimode enabled (when multimode feature is available): */
361 /* if ADC is slave, */
362 /* - ADC is enabled only (conversion is not started), */
363 /* - if multimode only concerns regular conversion, ADC is enabled */
364 /* and conversion is started. */
365 /* If ADC is master or independent, */
366 /* - ADC is enabled and conversion is started. */
367 #if defined(ADC_MULTIMODE_SUPPORT)
368 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
369 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
370 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
371 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
372 )
373 {
374 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
375 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
376 {
377 LL_ADC_INJ_StartConversion(hadc->Instance);
378 }
379 }
380 else
381 {
382 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
383 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
384 }
385 #else
386 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
387 {
388 /* Start ADC group injected conversion */
389 LL_ADC_INJ_StartConversion(hadc->Instance);
390 }
391 #endif /* ADC_MULTIMODE_SUPPORT */
392
393 }
394 else
395 {
396 /* Process unlocked */
397 __HAL_UNLOCK(hadc);
398 }
399
400 /* Return function status */
401 return tmp_hal_status;
402 }
403 }
404
405 /**
406 * @brief Stop conversion of injected channels. Disable ADC peripheral if
407 * no regular conversion is on going.
408 * @note If ADC must be disabled and if conversion is on going on
409 * regular group, function HAL_ADC_Stop must be used to stop both
410 * injected and regular groups, and disable the ADC.
411 * @note If injected group mode auto-injection is enabled,
412 * function HAL_ADC_Stop must be used.
413 * @note In case of multimode enabled (when multimode feature is available),
414 * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
415 * For ADC master, conversion is stopped and ADC is disabled.
416 * For ADC slave, ADC is disabled only (conversion stop of ADC master
417 * has already stopped conversion of ADC slave).
418 * @param hadc ADC handle.
419 * @retval HAL status
420 */
HAL_ADCEx_InjectedStop(ADC_HandleTypeDef * hadc)421 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
422 {
423 HAL_StatusTypeDef tmp_hal_status;
424
425 /* Check the parameters */
426 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
427
428 /* Process locked */
429 __HAL_LOCK(hadc);
430
431 /* 1. Stop potential conversion on going on injected group only. */
432 tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
433
434 /* Disable ADC peripheral if injected conversions are effectively stopped */
435 /* and if no conversion on regular group is on-going */
436 if (tmp_hal_status == HAL_OK)
437 {
438 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
439 {
440 /* 2. Disable the ADC peripheral */
441 tmp_hal_status = ADC_Disable(hadc);
442
443 /* Check if ADC is effectively disabled */
444 if (tmp_hal_status == HAL_OK)
445 {
446 /* Set ADC state */
447 ADC_STATE_CLR_SET(hadc->State,
448 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
449 HAL_ADC_STATE_READY);
450 }
451 }
452 /* Conversion on injected group is stopped, but ADC not disabled since */
453 /* conversion on regular group is still running. */
454 else
455 {
456 /* Set ADC state */
457 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
458 }
459 }
460
461 /* Process unlocked */
462 __HAL_UNLOCK(hadc);
463
464 /* Return function status */
465 return tmp_hal_status;
466 }
467
468 /**
469 * @brief Wait for injected group conversion to be completed.
470 * @param hadc ADC handle
471 * @param Timeout Timeout value in millisecond.
472 * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is
473 * checked and cleared depending on AUTDLY bit status.
474 * @retval HAL status
475 */
HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)476 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
477 {
478 uint32_t tickstart;
479 uint32_t tmp_flag_end;
480 uint32_t tmp_adc_inj_is_trigger_source_sw_start;
481 uint32_t tmp_adc_reg_is_trigger_source_sw_start;
482 uint32_t tmp_cfgr;
483 #if defined(ADC_MULTIMODE_SUPPORT)
484 const ADC_TypeDef *tmpADC_Master;
485 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
486 #endif /* ADC_MULTIMODE_SUPPORT */
487
488 /* Check the parameters */
489 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
490
491 /* If end of sequence selected */
492 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
493 {
494 tmp_flag_end = ADC_FLAG_JEOS;
495 }
496 else /* end of conversion selected */
497 {
498 tmp_flag_end = ADC_FLAG_JEOC;
499 }
500
501 /* Get timeout */
502 tickstart = HAL_GetTick();
503
504 /* Wait until End of Conversion or Sequence flag is raised */
505 while ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
506 {
507 /* Check if timeout is disabled (set to infinite wait) */
508 if (Timeout != HAL_MAX_DELAY)
509 {
510 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
511 {
512 /* New check to avoid false timeout detection in case of preemption */
513 if ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
514 {
515 /* Update ADC state machine to timeout */
516 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
517
518 /* Process unlocked */
519 __HAL_UNLOCK(hadc);
520
521 return HAL_TIMEOUT;
522 }
523 }
524 }
525 }
526
527 /* Retrieve ADC configuration */
528 tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
529 tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
530 /* Get relevant register CFGR in ADC instance of ADC master or slave */
531 /* in function of multimode state (for devices with multimode */
532 /* available). */
533 #if defined(ADC_MULTIMODE_SUPPORT)
534 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
535 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
536 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
537 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
538 )
539 {
540 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
541 }
542 else
543 {
544 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
545 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
546 }
547 #else
548 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
549 #endif /* ADC_MULTIMODE_SUPPORT */
550
551 /* Update ADC state machine */
552 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
553
554 /* Determine whether any further conversion upcoming on group injected */
555 /* by external trigger or by automatic injected conversion */
556 /* from group regular. */
557 if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
558 ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
559 ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
560 (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
561 {
562 /* Check whether end of sequence is reached */
563 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
564 {
565 /* Particular case if injected contexts queue is enabled: */
566 /* when the last context has been fully processed, JSQR is reset */
567 /* by the hardware. Even if no injected conversion is planned to come */
568 /* (queue empty, triggers are ignored), it can start again */
569 /* immediately after setting a new context (JADSTART is still set). */
570 /* Therefore, state of HAL ADC injected group is kept to busy. */
571 if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
572 {
573 /* Set ADC state */
574 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
575
576 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
577 {
578 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
579 }
580 }
581 }
582 }
583
584 /* Clear polled flag */
585 if (tmp_flag_end == ADC_FLAG_JEOS)
586 {
587 /* Clear end of sequence JEOS flag of injected group if low power feature */
588 /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
589 /* For injected groups, no new conversion will start before JEOS is */
590 /* cleared. */
591 if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
592 {
593 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
594 }
595 }
596 else
597 {
598 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
599 }
600
601 /* Return API HAL status */
602 return HAL_OK;
603 }
604
605 /**
606 * @brief Enable ADC, start conversion of injected group with interruption.
607 * @note Interruptions enabled in this function according to initialization
608 * setting : JEOC (end of conversion) or JEOS (end of sequence)
609 * @note Case of multimode enabled (when multimode feature is enabled):
610 * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
611 * then for ADC master.
612 * For ADC slave, ADC is enabled only (conversion is not started).
613 * For ADC master, ADC is enabled and multimode conversion is started.
614 * @param hadc ADC handle.
615 * @retval HAL status.
616 */
HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef * hadc)617 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
618 {
619 HAL_StatusTypeDef tmp_hal_status;
620 uint32_t tmp_config_injected_queue;
621 #if defined(ADC_MULTIMODE_SUPPORT)
622 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
623 #endif /* ADC_MULTIMODE_SUPPORT */
624
625 /* Check the parameters */
626 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
627
628 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
629 {
630 return HAL_BUSY;
631 }
632 else
633 {
634 /* In case of software trigger detection enabled, JQDIS must be set
635 (which can be done only if ADSTART and JADSTART are both cleared).
636 If JQDIS is not set at that point, returns an error
637 - since software trigger detection is disabled. User needs to
638 resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
639 - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
640 the queue is empty */
641 tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
642
643 if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
644 && (tmp_config_injected_queue == 0UL)
645 )
646 {
647 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
648 return HAL_ERROR;
649 }
650
651 /* Process locked */
652 __HAL_LOCK(hadc);
653
654 /* Enable the ADC peripheral */
655 tmp_hal_status = ADC_Enable(hadc);
656
657 /* Start conversion if ADC is effectively enabled */
658 if (tmp_hal_status == HAL_OK)
659 {
660 /* Check if a regular conversion is ongoing */
661 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
662 {
663 /* Reset ADC error code field related to injected conversions only */
664 CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
665 }
666 else
667 {
668 /* Set ADC error code to none */
669 ADC_CLEAR_ERRORCODE(hadc);
670 }
671
672 /* Set ADC state */
673 /* - Clear state bitfield related to injected group conversion results */
674 /* - Set state bitfield related to injected operation */
675 ADC_STATE_CLR_SET(hadc->State,
676 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
677 HAL_ADC_STATE_INJ_BUSY);
678
679 #if defined(ADC_MULTIMODE_SUPPORT)
680 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
681 - if ADC instance is master or if multimode feature is not available
682 - if multimode setting is disabled (ADC instance slave in independent mode) */
683 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
684 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
685 )
686 {
687 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
688 }
689 #endif /* ADC_MULTIMODE_SUPPORT */
690
691 /* Clear ADC group injected group conversion flag */
692 /* (To ensure of no unknown state from potential previous ADC operations) */
693 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
694
695 /* Process unlocked */
696 /* Unlock before starting ADC conversions: in case of potential */
697 /* interruption, to let the process to ADC IRQ Handler. */
698 __HAL_UNLOCK(hadc);
699
700 /* Enable ADC Injected context queue overflow interrupt if this feature */
701 /* is enabled. */
702 if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL)
703 {
704 __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
705 }
706
707 /* Enable ADC end of conversion interrupt */
708 switch (hadc->Init.EOCSelection)
709 {
710 case ADC_EOC_SEQ_CONV:
711 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
712 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
713 break;
714 /* case ADC_EOC_SINGLE_CONV */
715 default:
716 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
717 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
718 break;
719 }
720
721 /* Enable conversion of injected group, if automatic injected conversion */
722 /* is disabled. */
723 /* If software start has been selected, conversion starts immediately. */
724 /* If external trigger has been selected, conversion will start at next */
725 /* trigger event. */
726 /* Case of multimode enabled (when multimode feature is available): */
727 /* if ADC is slave, */
728 /* - ADC is enabled only (conversion is not started), */
729 /* - if multimode only concerns regular conversion, ADC is enabled */
730 /* and conversion is started. */
731 /* If ADC is master or independent, */
732 /* - ADC is enabled and conversion is started. */
733 #if defined(ADC_MULTIMODE_SUPPORT)
734 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
735 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
736 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
737 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
738 )
739 {
740 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
741 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
742 {
743 LL_ADC_INJ_StartConversion(hadc->Instance);
744 }
745 }
746 else
747 {
748 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
749 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
750 }
751 #else
752 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
753 {
754 /* Start ADC group injected conversion */
755 LL_ADC_INJ_StartConversion(hadc->Instance);
756 }
757 #endif /* ADC_MULTIMODE_SUPPORT */
758
759 }
760 else
761 {
762 /* Process unlocked */
763 __HAL_UNLOCK(hadc);
764 }
765
766 /* Return function status */
767 return tmp_hal_status;
768 }
769 }
770
771 /**
772 * @brief Stop conversion of injected channels, disable interruption of
773 * end-of-conversion. Disable ADC peripheral if no regular conversion
774 * is on going.
775 * @note If ADC must be disabled and if conversion is on going on
776 * regular group, function HAL_ADC_Stop must be used to stop both
777 * injected and regular groups, and disable the ADC.
778 * @note If injected group mode auto-injection is enabled,
779 * function HAL_ADC_Stop must be used.
780 * @note Case of multimode enabled (when multimode feature is available):
781 * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
782 * then for ADC slave.
783 * For ADC master, conversion is stopped and ADC is disabled.
784 * For ADC slave, ADC is disabled only (conversion stop of ADC master
785 * has already stopped conversion of ADC slave).
786 * @note In case of auto-injection mode, HAL_ADC_Stop() must be used.
787 * @param hadc ADC handle
788 * @retval HAL status
789 */
HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef * hadc)790 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
791 {
792 HAL_StatusTypeDef tmp_hal_status;
793
794 /* Check the parameters */
795 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
796
797 /* Process locked */
798 __HAL_LOCK(hadc);
799
800 /* 1. Stop potential conversion on going on injected group only. */
801 tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
802
803 /* Disable ADC peripheral if injected conversions are effectively stopped */
804 /* and if no conversion on the other group (regular group) is intended to */
805 /* continue. */
806 if (tmp_hal_status == HAL_OK)
807 {
808 /* Disable ADC end of conversion interrupt for injected channels */
809 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
810
811 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
812 {
813 /* 2. Disable the ADC peripheral */
814 tmp_hal_status = ADC_Disable(hadc);
815
816 /* Check if ADC is effectively disabled */
817 if (tmp_hal_status == HAL_OK)
818 {
819 /* Set ADC state */
820 ADC_STATE_CLR_SET(hadc->State,
821 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
822 HAL_ADC_STATE_READY);
823 }
824 }
825 /* Conversion on injected group is stopped, but ADC not disabled since */
826 /* conversion on regular group is still running. */
827 else
828 {
829 /* Set ADC state */
830 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
831 }
832 }
833
834 /* Process unlocked */
835 __HAL_UNLOCK(hadc);
836
837 /* Return function status */
838 return tmp_hal_status;
839 }
840
841 #if defined(ADC_MULTIMODE_SUPPORT)
842 /**
843 * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
844 * @note Multimode must have been previously configured using
845 * HAL_ADCEx_MultiModeConfigChannel() function.
846 * Interruptions enabled in this function:
847 * overrun, DMA half transfer, DMA transfer complete.
848 * Each of these interruptions has its dedicated callback function.
849 * @note State field of Slave ADC handle is not updated in this configuration:
850 * user should not rely on it for information related to Slave regular
851 * conversions.
852 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
853 * @param pData Destination Buffer address.
854 * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
855 * @retval HAL status
856 */
HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)857 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
858 {
859 HAL_StatusTypeDef tmp_hal_status;
860 ADC_HandleTypeDef tmp_hadc_slave;
861 ADC_Common_TypeDef *tmpADC_Common;
862 uint32_t length_bytes;
863 DMA_NodeConfTypeDef node_conf;
864
865 /* Check the parameters */
866 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
867 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
868 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
869 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
870
871 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
872 {
873 return HAL_BUSY;
874 }
875 else
876 {
877 /* Process locked */
878 __HAL_LOCK(hadc);
879
880 /* Temporary handle minimum initialization */
881 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
882 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
883
884 /* Set a temporary handle of the ADC slave associated to the ADC master */
885 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
886
887 if (tmp_hadc_slave.Instance == NULL)
888 {
889 /* Set ADC state */
890 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
891
892 /* Process unlocked */
893 __HAL_UNLOCK(hadc);
894
895 return HAL_ERROR;
896 }
897
898 /* Enable the ADC peripherals: master and slave (in case if not already */
899 /* enabled previously) */
900 tmp_hal_status = ADC_Enable(hadc);
901 if (tmp_hal_status == HAL_OK)
902 {
903 tmp_hal_status = ADC_Enable(&tmp_hadc_slave);
904 }
905
906 /* Start multimode conversion of ADCs pair */
907 if (tmp_hal_status == HAL_OK)
908 {
909 /* Set ADC state */
910 ADC_STATE_CLR_SET(hadc->State,
911 (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP),
912 HAL_ADC_STATE_REG_BUSY);
913
914 /* Set ADC error code to none */
915 ADC_CLEAR_ERRORCODE(hadc);
916
917 /* Set the DMA transfer complete callback */
918 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
919
920 /* Set the DMA half transfer complete callback */
921 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
922
923 /* Set the DMA error callback */
924 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
925
926 /* Pointer to the common control register */
927 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
928
929 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
930 /* start (in case of SW start): */
931
932 /* Clear regular group conversion flag and overrun flag */
933 /* (To ensure of no unknown state from potential previous ADC operations) */
934 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
935
936 /* Process unlocked */
937 /* Unlock before starting ADC conversions: in case of potential */
938 /* interruption, to let the process to ADC IRQ Handler. */
939 __HAL_UNLOCK(hadc);
940
941 /* Enable ADC overrun interrupt */
942 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
943
944 /* Check linkedlist mode */
945 if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
946 {
947 if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL))
948 {
949 /* Length should be converted to number of bytes */
950 if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hadc->DMA_Handle->LinkedListQueue->Head) != HAL_OK)
951 {
952 return HAL_ERROR;
953 }
954
955 /* Length should be converted to number of bytes */
956 if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
957 {
958 /* Word -> Bytes */
959 length_bytes = Length * 4U;
960 }
961 else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
962 {
963 /* Halfword -> Bytes */
964 length_bytes = Length * 2U;
965 }
966 else /* Bytes */
967 {
968 /* Same size already expressed in Bytes */
969 length_bytes = Length;
970 }
971
972 hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)length_bytes;
973 hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
974 (uint32_t)&tmpADC_Common->CDR;
975 hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
976 tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle);
977 }
978 else
979 {
980 return HAL_ERROR;
981 }
982 }
983 else
984 {
985 /* Length should be converted to number of bytes */
986 if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
987 {
988 /* Word -> Bytes */
989 length_bytes = Length * 4U;
990 }
991 else if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
992 {
993 /* Halfword -> Bytes */
994 length_bytes = Length * 2U;
995 }
996 else /* Bytes */
997 {
998 /* Same size already expressed in Bytes */
999 length_bytes = Length;
1000 }
1001
1002 /* Start the DMA channel */
1003 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, \
1004 length_bytes);
1005 }
1006
1007 /* Enable conversion of regular group. */
1008 /* If software start has been selected, conversion starts immediately. */
1009 /* If external trigger has been selected, conversion will start at next */
1010 /* trigger event. */
1011 /* Start ADC group regular conversion */
1012 LL_ADC_REG_StartConversion(hadc->Instance);
1013 }
1014 else
1015 {
1016 /* Process unlocked */
1017 __HAL_UNLOCK(hadc);
1018 }
1019
1020 /* Return function status */
1021 return tmp_hal_status;
1022 }
1023 }
1024
1025 /**
1026 * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
1027 * @note Multimode is kept enabled after this function. MultiMode DMA bits
1028 * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
1029 * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
1030 * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
1031 * resort to HAL_ADCEx_DisableMultiMode() API.
1032 * @note In case of DMA configured in circular mode, function
1033 * HAL_ADC_Stop_DMA() must be called after this function with handle of
1034 * ADC slave, to properly disable the DMA channel.
1035 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
1036 * @retval HAL status
1037 */
HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef * hadc)1038 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
1039 {
1040 HAL_StatusTypeDef tmp_hal_status;
1041 uint32_t tickstart;
1042 ADC_HandleTypeDef tmp_hadc_slave;
1043 uint32_t tmp_hadc_slave_conversion_on_going;
1044 HAL_StatusTypeDef tmp_hadc_slave_disable_status;
1045
1046 /* Check the parameters */
1047 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1048
1049 /* Process locked */
1050 __HAL_LOCK(hadc);
1051
1052 /* 1. Stop potential multimode conversion on going, on regular and injected groups */
1053 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
1054
1055 /* Disable ADC peripheral if conversions are effectively stopped */
1056 if (tmp_hal_status == HAL_OK)
1057 {
1058 /* Temporary handle minimum initialization */
1059 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
1060 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
1061
1062 /* Set a temporary handle of the ADC slave associated to the ADC master */
1063 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
1064
1065 if (tmp_hadc_slave.Instance == NULL)
1066 {
1067 /* Update ADC state machine to error */
1068 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1069
1070 /* Process unlocked */
1071 __HAL_UNLOCK(hadc);
1072
1073 return HAL_ERROR;
1074 }
1075
1076 /* Procedure to disable the ADC peripheral: wait for conversions */
1077 /* effectively stopped (ADC master and ADC slave), then disable ADC */
1078
1079 /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
1080 tickstart = HAL_GetTick();
1081
1082 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1083 while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1084 || (tmp_hadc_slave_conversion_on_going == 1UL)
1085 )
1086 {
1087 if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
1088 {
1089 /* New check to avoid false timeout detection in case of preemption */
1090 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1091 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1092 || (tmp_hadc_slave_conversion_on_going == 1UL)
1093 )
1094 {
1095 /* Update ADC state machine to error */
1096 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1097
1098 /* Process unlocked */
1099 __HAL_UNLOCK(hadc);
1100
1101 return HAL_ERROR;
1102 }
1103 }
1104
1105 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1106 }
1107
1108 /* Disable the DMA channel (in case of DMA in circular mode or stop */
1109 /* while DMA transfer is on going) */
1110 /* Note: DMA channel of ADC slave should be stopped after this function */
1111 /* with HAL_ADC_Stop_DMA() API. */
1112 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1113
1114 /* Check if DMA channel effectively disabled */
1115 if (tmp_hal_status == HAL_ERROR)
1116 {
1117 /* Update ADC state machine to error */
1118 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1119 }
1120
1121 /* Disable ADC overrun interrupt */
1122 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1123
1124 /* 2. Disable the ADC peripherals: master and slave */
1125 /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
1126 /* memory a potential failing status. */
1127 if (tmp_hal_status == HAL_OK)
1128 {
1129 tmp_hadc_slave_disable_status = ADC_Disable(&tmp_hadc_slave);
1130 if ((ADC_Disable(hadc) == HAL_OK) &&
1131 (tmp_hadc_slave_disable_status == HAL_OK))
1132 {
1133 tmp_hal_status = HAL_OK;
1134 }
1135 }
1136 else
1137 {
1138 /* In case of error, attempt to disable ADC master and slave without status assert */
1139 (void) ADC_Disable(hadc);
1140 (void) ADC_Disable(&tmp_hadc_slave);
1141 }
1142
1143 /* Set ADC state (ADC master) */
1144 ADC_STATE_CLR_SET(hadc->State,
1145 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1146 HAL_ADC_STATE_READY);
1147 }
1148
1149 /* Process unlocked */
1150 __HAL_UNLOCK(hadc);
1151
1152 /* Return function status */
1153 return tmp_hal_status;
1154 }
1155
1156 /**
1157 * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration.
1158 * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
1159 * @retval The converted data values.
1160 */
HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef * hadc)1161 uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc)
1162 {
1163 const ADC_Common_TypeDef *tmpADC_Common;
1164
1165 /* Check the parameters */
1166 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1167
1168 /* Prevent unused argument(s) compilation warning if no assert_param check */
1169 /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */
1170 UNUSED(hadc);
1171
1172 /* Pointer to the common control register */
1173 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
1174
1175 /* Return the multi mode conversion value */
1176 return tmpADC_Common->CDR;
1177 }
1178 #endif /* ADC_MULTIMODE_SUPPORT */
1179
1180 /**
1181 * @brief Get ADC injected group conversion result.
1182 * @note Reading register JDRx automatically clears ADC flag JEOC
1183 * (ADC group injected end of unitary conversion).
1184 * @note This function does not clear ADC flag JEOS
1185 * (ADC group injected end of sequence conversion)
1186 * Occurrence of flag JEOS rising:
1187 * - If sequencer is composed of 1 rank, flag JEOS is equivalent
1188 * to flag JEOC.
1189 * - If sequencer is composed of several ranks, during the scan
1190 * sequence flag JEOC only is raised, at the end of the scan sequence
1191 * both flags JEOC and EOS are raised.
1192 * Flag JEOS must not be cleared by this function because
1193 * it would not be compliant with low power features
1194 * (feature low power auto-wait, not available on all STM32 series).
1195 * To clear this flag, either use function:
1196 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
1197 * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
1198 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
1199 * @param hadc ADC handle
1200 * @param InjectedRank the converted ADC injected rank.
1201 * This parameter can be one of the following values:
1202 * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
1203 * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
1204 * @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
1205 * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
1206 * @retval ADC group injected conversion data
1207 */
HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef * hadc,uint32_t InjectedRank)1208 uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
1209 {
1210 uint32_t tmp_jdr;
1211
1212 /* Check the parameters */
1213 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1214 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
1215
1216 /* Get ADC converted value */
1217 switch (InjectedRank)
1218 {
1219 case ADC_INJECTED_RANK_4:
1220 tmp_jdr = hadc->Instance->JDR4;
1221 break;
1222 case ADC_INJECTED_RANK_3:
1223 tmp_jdr = hadc->Instance->JDR3;
1224 break;
1225 case ADC_INJECTED_RANK_2:
1226 tmp_jdr = hadc->Instance->JDR2;
1227 break;
1228 case ADC_INJECTED_RANK_1:
1229 default:
1230 tmp_jdr = hadc->Instance->JDR1;
1231 break;
1232 }
1233
1234 /* Return ADC converted value */
1235 return tmp_jdr;
1236 }
1237
1238 /**
1239 * @brief Injected conversion complete callback in non-blocking mode.
1240 * @param hadc ADC handle
1241 * @retval None
1242 */
HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef * hadc)1243 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
1244 {
1245 /* Prevent unused argument(s) compilation warning */
1246 UNUSED(hadc);
1247
1248 /* NOTE : This function should not be modified. When the callback is needed,
1249 function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
1250 */
1251 }
1252
1253 /**
1254 * @brief Injected context queue overflow callback.
1255 * @note This callback is called if injected context queue is enabled
1256 (parameter "QueueInjectedContext" in injected channel configuration)
1257 and if a new injected context is set when queue is full (maximum 2
1258 contexts).
1259 * @param hadc ADC handle
1260 * @retval None
1261 */
HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef * hadc)1262 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
1263 {
1264 /* Prevent unused argument(s) compilation warning */
1265 UNUSED(hadc);
1266
1267 /* NOTE : This function should not be modified. When the callback is needed,
1268 function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
1269 */
1270 }
1271
1272 /**
1273 * @brief Analog watchdog 2 callback in non-blocking mode.
1274 * @param hadc ADC handle
1275 * @retval None
1276 */
HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef * hadc)1277 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
1278 {
1279 /* Prevent unused argument(s) compilation warning */
1280 UNUSED(hadc);
1281
1282 /* NOTE : This function should not be modified. When the callback is needed,
1283 function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
1284 */
1285 }
1286
1287 /**
1288 * @brief Analog watchdog 3 callback in non-blocking mode.
1289 * @param hadc ADC handle
1290 * @retval None
1291 */
HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef * hadc)1292 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
1293 {
1294 /* Prevent unused argument(s) compilation warning */
1295 UNUSED(hadc);
1296
1297 /* NOTE : This function should not be modified. When the callback is needed,
1298 function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
1299 */
1300 }
1301
1302
1303 /**
1304 * @brief End Of Sampling callback in non-blocking mode.
1305 * @param hadc ADC handle
1306 * @retval None
1307 */
HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef * hadc)1308 __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
1309 {
1310 /* Prevent unused argument(s) compilation warning */
1311 UNUSED(hadc);
1312
1313 /* NOTE : This function should not be modified. When the callback is needed,
1314 function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
1315 */
1316 }
1317
1318 /**
1319 * @brief Stop ADC conversion of regular group (and injected channels in
1320 * case of auto_injection mode), disable ADC peripheral if no
1321 * conversion is on going on injected group.
1322 * @param hadc ADC handle
1323 * @retval HAL status.
1324 */
HAL_ADCEx_RegularStop(ADC_HandleTypeDef * hadc)1325 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
1326 {
1327 HAL_StatusTypeDef tmp_hal_status;
1328
1329 /* Check the parameters */
1330 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1331
1332 /* Process locked */
1333 __HAL_LOCK(hadc);
1334
1335 /* 1. Stop potential regular conversion on going */
1336 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1337
1338 /* Disable ADC peripheral if regular conversions are effectively stopped
1339 and if no injected conversions are on-going */
1340 if (tmp_hal_status == HAL_OK)
1341 {
1342 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1343 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1344
1345 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1346 {
1347 /* 2. Disable the ADC peripheral */
1348 tmp_hal_status = ADC_Disable(hadc);
1349
1350 /* Check if ADC is effectively disabled */
1351 if (tmp_hal_status == HAL_OK)
1352 {
1353 /* Set ADC state */
1354 ADC_STATE_CLR_SET(hadc->State,
1355 HAL_ADC_STATE_INJ_BUSY,
1356 HAL_ADC_STATE_READY);
1357 }
1358 }
1359 /* Conversion on injected group is stopped, but ADC not disabled since */
1360 /* conversion on regular group is still running. */
1361 else
1362 {
1363 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1364 }
1365 }
1366
1367 /* Process unlocked */
1368 __HAL_UNLOCK(hadc);
1369
1370 /* Return function status */
1371 return tmp_hal_status;
1372 }
1373
1374
1375 /**
1376 * @brief Stop ADC conversion of ADC groups regular and injected,
1377 * disable interrution of end-of-conversion,
1378 * disable ADC peripheral if no conversion is on going
1379 * on injected group.
1380 * @param hadc ADC handle
1381 * @retval HAL status.
1382 */
HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef * hadc)1383 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
1384 {
1385 HAL_StatusTypeDef tmp_hal_status;
1386
1387 /* Check the parameters */
1388 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1389
1390 /* Process locked */
1391 __HAL_LOCK(hadc);
1392
1393 /* 1. Stop potential regular conversion on going */
1394 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1395
1396 /* Disable ADC peripheral if conversions are effectively stopped
1397 and if no injected conversion is on-going */
1398 if (tmp_hal_status == HAL_OK)
1399 {
1400 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1401 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1402
1403 /* Disable all regular-related interrupts */
1404 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1405
1406 /* 2. Disable ADC peripheral if no injected conversions are on-going */
1407 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1408 {
1409 tmp_hal_status = ADC_Disable(hadc);
1410 /* if no issue reported */
1411 if (tmp_hal_status == HAL_OK)
1412 {
1413 /* Set ADC state */
1414 ADC_STATE_CLR_SET(hadc->State,
1415 HAL_ADC_STATE_INJ_BUSY,
1416 HAL_ADC_STATE_READY);
1417 }
1418 }
1419 else
1420 {
1421 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1422 }
1423 }
1424
1425 /* Process unlocked */
1426 __HAL_UNLOCK(hadc);
1427
1428 /* Return function status */
1429 return tmp_hal_status;
1430 }
1431
1432 /**
1433 * @brief Stop ADC conversion of regular group (and injected group in
1434 * case of auto_injection mode), disable ADC DMA transfer, disable
1435 * ADC peripheral if no conversion is on going
1436 * on injected group.
1437 * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
1438 * For multimode (when multimode feature is available),
1439 * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
1440 * @param hadc ADC handle
1441 * @retval HAL status.
1442 */
HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef * hadc)1443 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
1444 {
1445 HAL_StatusTypeDef tmp_hal_status;
1446
1447 /* Check the parameters */
1448 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1449
1450 /* Process locked */
1451 __HAL_LOCK(hadc);
1452
1453 /* 1. Stop potential regular conversion on going */
1454 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1455
1456 /* Disable ADC peripheral if conversions are effectively stopped
1457 and if no injected conversion is on-going */
1458 if (tmp_hal_status == HAL_OK)
1459 {
1460 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1461 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1462
1463 /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
1464 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
1465
1466 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
1467 /* while DMA transfer is on going) */
1468 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1469
1470 /* Check if DMA channel effectively disabled */
1471 if (tmp_hal_status != HAL_OK)
1472 {
1473 /* Update ADC state machine to error */
1474 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1475 }
1476
1477 /* Disable ADC overrun interrupt */
1478 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1479
1480 /* 2. Disable the ADC peripheral */
1481 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
1482 /* to keep in memory a potential failing status. */
1483 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1484 {
1485 if (tmp_hal_status == HAL_OK)
1486 {
1487 tmp_hal_status = ADC_Disable(hadc);
1488 }
1489 else
1490 {
1491 (void)ADC_Disable(hadc);
1492 }
1493
1494 /* Check if ADC is effectively disabled */
1495 if (tmp_hal_status == HAL_OK)
1496 {
1497 /* Set ADC state */
1498 ADC_STATE_CLR_SET(hadc->State,
1499 HAL_ADC_STATE_INJ_BUSY,
1500 HAL_ADC_STATE_READY);
1501 }
1502 }
1503 else
1504 {
1505 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1506 }
1507 }
1508
1509 /* Process unlocked */
1510 __HAL_UNLOCK(hadc);
1511
1512 /* Return function status */
1513 return tmp_hal_status;
1514 }
1515
1516 #if defined(ADC_MULTIMODE_SUPPORT)
1517 /**
1518 * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected
1519 * conversion is on-going.
1520 * @note Multimode is kept enabled after this function. Multimode DMA bits
1521 * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
1522 * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
1523 * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
1524 * resort to HAL_ADCEx_DisableMultiMode() API.
1525 * @note In case of DMA configured in circular mode, function
1526 * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
1527 * ADC slave, to properly disable the DMA channel.
1528 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
1529 * @retval HAL status
1530 */
HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef * hadc)1531 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
1532 {
1533 HAL_StatusTypeDef tmp_hal_status;
1534 uint32_t tickstart;
1535 ADC_HandleTypeDef tmp_hadc_slave;
1536 uint32_t tmp_hadc_slave_conversion_on_going;
1537
1538 /* Check the parameters */
1539 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1540
1541 /* Process locked */
1542 __HAL_LOCK(hadc);
1543
1544
1545 /* 1. Stop potential multimode conversion on going, on regular groups */
1546 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1547
1548 /* Disable ADC peripheral if conversions are effectively stopped */
1549 if (tmp_hal_status == HAL_OK)
1550 {
1551 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1552 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1553
1554 /* Temporary handle minimum initialization */
1555 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
1556 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
1557
1558 /* Set a temporary handle of the ADC slave associated to the ADC master */
1559 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
1560
1561 if (tmp_hadc_slave.Instance == NULL)
1562 {
1563 /* Update ADC state machine to error */
1564 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1565
1566 /* Process unlocked */
1567 __HAL_UNLOCK(hadc);
1568
1569 return HAL_ERROR;
1570 }
1571
1572 /* Procedure to disable the ADC peripheral: wait for conversions */
1573 /* effectively stopped (ADC master and ADC slave), then disable ADC */
1574
1575 /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
1576 tickstart = HAL_GetTick();
1577
1578 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1579 while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1580 || (tmp_hadc_slave_conversion_on_going == 1UL)
1581 )
1582 {
1583 if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
1584 {
1585 /* New check to avoid false timeout detection in case of preemption */
1586 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1587 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1588 || (tmp_hadc_slave_conversion_on_going == 1UL)
1589 )
1590 {
1591 /* Update ADC state machine to error */
1592 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1593
1594 /* Process unlocked */
1595 __HAL_UNLOCK(hadc);
1596
1597 return HAL_ERROR;
1598 }
1599 }
1600
1601 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
1602 }
1603
1604 /* Disable the DMA channel (in case of DMA in circular mode or stop */
1605 /* while DMA transfer is on going) */
1606 /* Note: DMA channel of ADC slave should be stopped after this function */
1607 /* with HAL_ADCEx_RegularStop_DMA() API. */
1608 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1609
1610 /* Check if DMA channel effectively disabled */
1611 if (tmp_hal_status != HAL_OK)
1612 {
1613 /* Update ADC state machine to error */
1614 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1615 }
1616
1617 /* Disable ADC overrun interrupt */
1618 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1619
1620 /* 2. Disable the ADC peripherals: master and slave if no injected */
1621 /* conversion is on-going. */
1622 /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
1623 /* memory a potential failing status. */
1624 if (tmp_hal_status == HAL_OK)
1625 {
1626 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1627 {
1628 tmp_hal_status = ADC_Disable(hadc);
1629 if (tmp_hal_status == HAL_OK)
1630 {
1631 if (LL_ADC_INJ_IsConversionOngoing((&tmp_hadc_slave)->Instance) == 0UL)
1632 {
1633 tmp_hal_status = ADC_Disable(&tmp_hadc_slave);
1634 }
1635 }
1636 }
1637
1638 if (tmp_hal_status == HAL_OK)
1639 {
1640 /* Both Master and Slave ADC's could be disabled. Update Master State */
1641 /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
1642 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
1643 }
1644 else
1645 {
1646 /* injected (Master or Slave) conversions are still on-going,
1647 no Master State change */
1648 }
1649 }
1650 }
1651
1652 /* Process unlocked */
1653 __HAL_UNLOCK(hadc);
1654
1655 /* Return function status */
1656 return tmp_hal_status;
1657 }
1658 #endif /* ADC_MULTIMODE_SUPPORT */
1659
1660 /**
1661 * @}
1662 */
1663
1664 /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
1665 * @brief ADC Extended Peripheral Control functions
1666 *
1667 @verbatim
1668 ===============================================================================
1669 ##### Peripheral Control functions #####
1670 ===============================================================================
1671 [..] This section provides functions allowing to:
1672 (+) Configure channels on injected group
1673 (+) Configure multimode when multimode feature is available
1674 (+) Enable or Disable Injected Queue
1675 (+) Disable ADC voltage regulator
1676 (+) Enter ADC deep-power-down mode
1677
1678 @endverbatim
1679 * @{
1680 */
1681
1682 /**
1683 * @brief Configure a channel to be assigned to ADC group injected.
1684 * @note Possibility to update parameters on the fly:
1685 * This function initializes injected group, following calls to this
1686 * function can be used to reconfigure some parameters of structure
1687 * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
1688 * The setting of these parameters is conditioned to ADC state:
1689 * Refer to comments of structure "ADC_InjectionConfTypeDef".
1690 * @note In case of usage of internal measurement channels:
1691 * Vbat/VrefInt/TempSensor.
1692 * These internal paths can be disabled using function
1693 * HAL_ADC_DeInit().
1694 * @note Caution: For Injected Context Queue use, a context must be fully
1695 * defined before start of injected conversion. All channels are configured
1696 * consecutively for the same ADC instance. Therefore, the number of calls to
1697 * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
1698 * InjectedNbrOfConversion for each context.
1699 * - Example 1: If 1 context is intended to be used (or if there is no use of the
1700 * Injected Queue Context feature) and if the context contains 3 injected ranks
1701 * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
1702 * called once for each channel (i.e. 3 times) before starting a conversion.
1703 * This function must not be called to configure a 4th injected channel:
1704 * it would start a new context into context queue.
1705 * - Example 2: If 2 contexts are intended to be used and each of them contains
1706 * 3 injected ranks (InjectedNbrOfConversion = 3),
1707 * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
1708 * for each context (3 channels x 2 contexts = 6 calls). Conversion can
1709 * start once the 1st context is set, that is after the first three
1710 * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
1711 * @param hadc ADC handle
1712 * @param pConfigInjected Structure of ADC injected group and ADC channel for
1713 * injected group.
1714 * @retval HAL status
1715 */
HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef * hadc,const ADC_InjectionConfTypeDef * pConfigInjected)1716 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
1717 const ADC_InjectionConfTypeDef *pConfigInjected)
1718 {
1719 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1720 uint32_t tmp_offset_shifted;
1721 uint32_t tmp_config_internal_channel;
1722 uint32_t tmp_adc_is_conversion_on_going_regular;
1723 uint32_t tmp_adc_is_conversion_on_going_injected;
1724 __IO uint32_t wait_loop_index = 0;
1725
1726 uint32_t tmp_jsqr_context_queue_being_built = 0U;
1727
1728 /* Check the parameters */
1729 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1730 assert_param(IS_ADC_SAMPLE_TIME(pConfigInjected->InjectedSamplingTime));
1731 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfigInjected->InjectedSingleDiff));
1732 assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->AutoInjectedConv));
1733 assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->QueueInjectedContext));
1734 assert_param(IS_ADC_EXTTRIGINJEC_EDGE(pConfigInjected->ExternalTrigInjecConvEdge));
1735 assert_param(IS_ADC_EXTTRIGINJEC(pConfigInjected->ExternalTrigInjecConv));
1736 assert_param(IS_ADC_OFFSET_NUMBER(pConfigInjected->InjectedOffsetNumber));
1737 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
1738 assert_param(IS_ADC_OFFSET_SIGN(pConfigInjected->InjectedOffsetSign));
1739 assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedOffsetSaturation));
1740 assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjecOversamplingMode));
1741
1742 if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
1743 {
1744 assert_param(IS_ADC_INJECTED_RANK(pConfigInjected->InjectedRank));
1745 assert_param(IS_ADC_INJECTED_NB_CONV(pConfigInjected->InjectedNbrOfConversion));
1746 assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedDiscontinuousConvMode));
1747 }
1748
1749
1750 /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
1751 ignored (considered as reset) */
1752 assert_param(!((pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
1753 && (pConfigInjected->InjecOversamplingMode == ENABLE)));
1754
1755 /* JDISCEN and JAUTO bits can't be set at the same time */
1756 assert_param(!((pConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
1757 && (pConfigInjected->AutoInjectedConv == ENABLE)));
1758
1759 /* DISCEN and JAUTO bits can't be set at the same time */
1760 assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE)));
1761
1762 /* Verification of channel number */
1763 if (pConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
1764 {
1765 assert_param(IS_ADC_CHANNEL(hadc, pConfigInjected->InjectedChannel));
1766 }
1767 else
1768 {
1769 assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfigInjected->InjectedChannel));
1770 }
1771
1772 /* Process locked */
1773 __HAL_LOCK(hadc);
1774
1775 /* Configuration of injected group sequencer: */
1776 /* Hardware constraint: Must fully define injected context register JSQR */
1777 /* before make it entering into injected sequencer queue. */
1778 /* */
1779 /* - if scan mode is disabled: */
1780 /* * Injected channels sequence length is set to 0x00: 1 channel */
1781 /* converted (channel on injected rank 1) */
1782 /* Parameter "InjectedNbrOfConversion" is discarded. */
1783 /* * Injected context register JSQR setting is simple: register is fully */
1784 /* defined on one call of this function (for injected rank 1) and can */
1785 /* be entered into queue directly. */
1786 /* - if scan mode is enabled: */
1787 /* * Injected channels sequence length is set to parameter */
1788 /* "InjectedNbrOfConversion". */
1789 /* * Injected context register JSQR setting more complex: register is */
1790 /* fully defined over successive calls of this function, for each */
1791 /* injected channel rank. It is entered into queue only when all */
1792 /* injected ranks have been set. */
1793 /* Note: Scan mode is not present by hardware on this device, but used */
1794 /* by software for alignment over all STM32 devices. */
1795
1796 if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
1797 (pConfigInjected->InjectedNbrOfConversion == 1U))
1798 {
1799 /* Configuration of context register JSQR: */
1800 /* - number of ranks in injected group sequencer: fixed to 1st rank */
1801 /* (scan mode disabled, only rank 1 used) */
1802 /* - external trigger to start conversion */
1803 /* - external trigger polarity */
1804 /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
1805
1806 if (pConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
1807 {
1808 /* Enable external trigger if trigger selection is different of */
1809 /* software start. */
1810 /* Note: This configuration keeps the hardware feature of parameter */
1811 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
1812 /* software start. */
1813 if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
1814 {
1815 tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
1816 | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
1817 | pConfigInjected->ExternalTrigInjecConvEdge
1818 );
1819 }
1820 else
1821 {
1822 tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
1823 }
1824
1825 MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_jsqr_context_queue_being_built);
1826 /* For debug and informative reasons, hadc handle saves JSQR setting */
1827 hadc->InjectionConfig.ContextQueue = tmp_jsqr_context_queue_being_built;
1828
1829 }
1830 }
1831 else
1832 {
1833 /* Case of scan mode enabled, several channels to set into injected group */
1834 /* sequencer. */
1835 /* */
1836 /* Procedure to define injected context register JSQR over successive */
1837 /* calls of this function, for each injected channel rank: */
1838 /* 1. Start new context and set parameters related to all injected */
1839 /* channels: injected sequence length and trigger. */
1840
1841 /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
1842 /* call of the context under setting */
1843 if (hadc->InjectionConfig.ChannelCount == 0U)
1844 {
1845 /* Initialize number of channels that will be configured on the context */
1846 /* being built */
1847 hadc->InjectionConfig.ChannelCount = pConfigInjected->InjectedNbrOfConversion;
1848 /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
1849 call, this context will be written in JSQR register at the last call.
1850 At this point, the context is merely reset */
1851 hadc->InjectionConfig.ContextQueue = 0x00000000U;
1852
1853 /* Configuration of context register JSQR: */
1854 /* - number of ranks in injected group sequencer */
1855 /* - external trigger to start conversion */
1856 /* - external trigger polarity */
1857
1858 /* Enable external trigger if trigger selection is different of */
1859 /* software start. */
1860 /* Note: This configuration keeps the hardware feature of parameter */
1861 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
1862 /* software start. */
1863 if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
1864 {
1865 tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U)
1866 | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
1867 | pConfigInjected->ExternalTrigInjecConvEdge
1868 );
1869 }
1870 else
1871 {
1872 tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U));
1873 }
1874
1875 }
1876
1877 /* 2. Continue setting of context under definition with parameter */
1878 /* related to each channel: channel rank sequence */
1879 /* Clear the old JSQx bits for the selected rank */
1880 tmp_jsqr_context_queue_being_built &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, pConfigInjected->InjectedRank);
1881
1882 /* Set the JSQx bits for the selected rank */
1883 tmp_jsqr_context_queue_being_built |= ADC_JSQR_RK(pConfigInjected->InjectedChannel, pConfigInjected->InjectedRank);
1884
1885 /* Decrease channel count */
1886 hadc->InjectionConfig.ChannelCount--;
1887
1888 /* 3. tmp_jsqr_context_queue_being_built is fully built for this HAL_ADCEx_InjectedConfigChannel()
1889 call, aggregate the setting to those already built during the previous
1890 HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */
1891 hadc->InjectionConfig.ContextQueue |= tmp_jsqr_context_queue_being_built;
1892
1893 /* 4. End of context setting: if this is the last channel set, then write context
1894 into register JSQR and make it enter into queue */
1895 if (hadc->InjectionConfig.ChannelCount == 0U)
1896 {
1897 MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
1898 }
1899 }
1900
1901 /* Parameters update conditioned to ADC state: */
1902 /* Parameters that can be updated when ADC is disabled or enabled without */
1903 /* conversion on going on injected group: */
1904 /* - Injected context queue: Queue disable (active context is kept) or */
1905 /* enable (context decremented, up to 2 contexts queued) */
1906 /* - Injected discontinuous mode: can be enabled only if auto-injected */
1907 /* mode is disabled. */
1908 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1909 {
1910 if (pConfigInjected->InjectedChannel == ADC_CHANNEL_0)
1911 {
1912 LL_ADC_EnableChannel0_GPIO(hadc->Instance);
1913 }
1914
1915 /* If auto-injected mode is disabled: no constraint */
1916 if (pConfigInjected->AutoInjectedConv == DISABLE)
1917 {
1918 MODIFY_REG(hadc->Instance->CFGR,
1919 ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
1920 ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext) |
1921 ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
1922 }
1923 /* If auto-injected mode is enabled: Injected discontinuous setting is */
1924 /* discarded. */
1925 else
1926 {
1927 MODIFY_REG(hadc->Instance->CFGR,
1928 ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
1929 ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext));
1930 }
1931
1932 }
1933
1934 /* Parameters update conditioned to ADC state: */
1935 /* Parameters that can be updated when ADC is disabled or enabled without */
1936 /* conversion on going on regular and injected groups: */
1937 /* - Automatic injected conversion: can be enabled if injected group */
1938 /* external triggers are disabled. */
1939 /* - Channel sampling time */
1940 /* - Channel offset */
1941 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
1942 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
1943
1944 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
1945 && (tmp_adc_is_conversion_on_going_injected == 0UL)
1946 )
1947 {
1948 /* If injected group external triggers are disabled (set to injected */
1949 /* software start): no constraint */
1950 if ((pConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
1951 || (pConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
1952 {
1953 if (pConfigInjected->AutoInjectedConv == ENABLE)
1954 {
1955 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
1956 }
1957 else
1958 {
1959 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
1960 }
1961 }
1962 /* If Automatic injected conversion was intended to be set and could not */
1963 /* due to injected group external triggers enabled, error is reported. */
1964 else
1965 {
1966 if (pConfigInjected->AutoInjectedConv == ENABLE)
1967 {
1968 /* Update ADC state machine to error */
1969 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1970
1971 tmp_hal_status = HAL_ERROR;
1972 }
1973 else
1974 {
1975 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
1976 }
1977 }
1978
1979 if (pConfigInjected->InjecOversamplingMode == ENABLE)
1980 {
1981 assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio));
1982 assert_param(IS_ADC_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift));
1983
1984 /* JOVSE must be reset in case of triggered regular mode */
1985 assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)
1986 == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
1987
1988 /* Configuration of Injected Oversampler: */
1989 /* - Oversampling Ratio */
1990 /* - Right bit shift */
1991
1992 /* Enable OverSampling mode */
1993 MODIFY_REG(hadc->Instance->CFGR2,
1994 ADC_CFGR2_JOVSE |
1995 ADC_CFGR2_OVSR |
1996 ADC_CFGR2_OVSS,
1997 ADC_CFGR2_JOVSE |
1998 pConfigInjected->InjecOversampling.Ratio |
1999 pConfigInjected->InjecOversampling.RightBitShift
2000 );
2001 }
2002 else
2003 {
2004 /* Disable Regular OverSampling */
2005 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
2006 }
2007
2008 /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
2009 if (pConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5)
2010 {
2011 /* Set sampling time of the selected ADC channel */
2012 LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
2013
2014 /* Set ADC sampling time common configuration */
2015 LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
2016 }
2017 else
2018 {
2019 /* Set sampling time of the selected ADC channel */
2020 LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel,
2021 pConfigInjected->InjectedSamplingTime);
2022
2023 /* Set ADC sampling time common configuration */
2024 LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
2025 }
2026
2027 /* Configure the offset: offset enable/disable, channel, offset value */
2028
2029 /* Shift the offset with respect to the selected ADC resolution. */
2030 /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
2031 tmp_offset_shifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, pConfigInjected->InjectedOffset);
2032
2033 if (pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
2034 {
2035 /* Set ADC selected offset number */
2036 LL_ADC_SetOffset(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedChannel,
2037 tmp_offset_shifted);
2038
2039 /* Set ADC selected offset sign & saturation */
2040 LL_ADC_SetOffsetSign(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedOffsetSign);
2041 LL_ADC_SetOffsetSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber,
2042 (pConfigInjected->InjectedOffsetSaturation == ENABLE) ?
2043 LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE);
2044 }
2045 else
2046 {
2047 /* Scan each offset register to check if the selected channel is targeted. */
2048 /* If this is the case, the corresponding offset number is disabled. */
2049 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
2050 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
2051 {
2052 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
2053 }
2054 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
2055 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
2056 {
2057 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
2058 }
2059 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
2060 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
2061 {
2062 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
2063 }
2064 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
2065 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
2066 {
2067 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
2068 }
2069 }
2070
2071 }
2072
2073 /* Parameters update conditioned to ADC state: */
2074 /* Parameters that can be updated only when ADC is disabled: */
2075 /* - Single or differential mode */
2076 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2077 {
2078 /* Set mode single-ended or differential input of the selected ADC channel */
2079 LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfigInjected->InjectedChannel, pConfigInjected->InjectedSingleDiff);
2080
2081 /* Configuration of differential mode */
2082 /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
2083 if (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
2084 {
2085 /* Set sampling time of the selected ADC channel */
2086 LL_ADC_SetChannelSamplingTime(hadc->Instance,
2087 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
2088 (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
2089 (uint32_t)pConfigInjected->InjectedChannel)
2090 + 1UL) & 0x1FUL)),
2091 pConfigInjected->InjectedSamplingTime);
2092 }
2093
2094 }
2095
2096 /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
2097 /* internal measurement paths enable: If internal channel selected, */
2098 /* enable dedicated internal buffers and path. */
2099 /* Note: these internal measurement paths can be disabled using */
2100 /* HAL_ADC_DeInit(). */
2101
2102 if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfigInjected->InjectedChannel))
2103 {
2104 tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2105
2106 /* If the requested internal measurement path has already been enabled, */
2107 /* bypass the configuration processing. */
2108 if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
2109 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
2110 {
2111 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
2112 {
2113 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2114 LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
2115
2116 /* Delay for temperature sensor stabilization time */
2117 /* Wait loop initialization and execution */
2118 /* Note: Variable divided by 2 to compensate partially */
2119 /* CPU processing cycles, scaling in us split to not */
2120 /* exceed 32 bits register capacity and handle low frequency. */
2121 wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL)
2122 * (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL));
2123 while (wait_loop_index != 0UL)
2124 {
2125 wait_loop_index--;
2126 }
2127 }
2128 }
2129 else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
2130 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
2131 {
2132 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
2133 {
2134 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2135 LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
2136 }
2137 }
2138 else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
2139 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
2140 {
2141 if (ADC_VREFINT_INSTANCE(hadc))
2142 {
2143 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2144 LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
2145 }
2146 }
2147 else if (pConfigInjected->InjectedChannel == ADC_CHANNEL_VDDCORE)
2148 {
2149 if (ADC_VDDCORE_INSTANCE(hadc))
2150 {
2151 LL_ADC_EnableChannelVDDcore(hadc->Instance);
2152 }
2153 }
2154 else
2155 {
2156 /* nothing to do */
2157 }
2158 }
2159
2160 /* Process unlocked */
2161 __HAL_UNLOCK(hadc);
2162
2163 /* Return function status */
2164 return tmp_hal_status;
2165 }
2166
2167 #if defined(ADC_MULTIMODE_SUPPORT)
2168 /**
2169 * @brief Enable ADC multimode and configure multimode parameters
2170 * @note Possibility to update parameters on the fly:
2171 * This function initializes multimode parameters, following
2172 * calls to this function can be used to reconfigure some parameters
2173 * of structure "ADC_MultiModeTypeDef" on the fly, without resetting
2174 * the ADCs.
2175 * The setting of these parameters is conditioned to ADC state.
2176 * For parameters constraints, see comments of structure
2177 * "ADC_MultiModeTypeDef".
2178 * @note To move back configuration from multimode to single mode, ADC must
2179 * be reset (using function HAL_ADC_Init() ).
2180 * @param hadc Master ADC handle
2181 * @param pMultimode Structure of ADC multimode configuration
2182 * @retval HAL status
2183 */
HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef * hadc,const ADC_MultiModeTypeDef * pMultimode)2184 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode)
2185 {
2186 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2187 ADC_Common_TypeDef *tmpADC_Common;
2188 ADC_HandleTypeDef tmp_hadc_slave;
2189 uint32_t tmp_hadc_slave_conversion_on_going;
2190
2191 /* Check the parameters */
2192 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
2193 assert_param(IS_ADC_MULTIMODE(pMultimode->Mode));
2194 if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
2195 {
2196 assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode));
2197 assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
2198 }
2199
2200 /* Process locked */
2201 __HAL_LOCK(hadc);
2202
2203 /* Temporary handle minimum initialization */
2204 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
2205 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
2206
2207 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
2208
2209 if (tmp_hadc_slave.Instance == NULL)
2210 {
2211 /* Update ADC state machine to error */
2212 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2213
2214 /* Process unlocked */
2215 __HAL_UNLOCK(hadc);
2216
2217 return HAL_ERROR;
2218 }
2219
2220 /* Parameters update conditioned to ADC state: */
2221 /* Parameters that can be updated when ADC is disabled or enabled without */
2222 /* conversion on going on regular group: */
2223 /* - Multimode DMA configuration */
2224 /* - Multimode DMA mode */
2225 tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
2226 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2227 && (tmp_hadc_slave_conversion_on_going == 0UL))
2228 {
2229 /* Pointer to the common control register */
2230 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
2231
2232 /* If multimode is selected, configure all multimode parameters. */
2233 /* Otherwise, reset multimode parameters (can be used in case of */
2234 /* transition from multimode to independent mode). */
2235 if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
2236 {
2237 MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
2238 pMultimode->DMAAccessMode |
2239 ADC_CCR_MULTI_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
2240
2241 /* Parameters that can be updated only when ADC is disabled: */
2242 /* - Multimode mode selection */
2243 /* - Multimode delay */
2244 /* Note: Delay range depends on selected resolution: */
2245 /* from 1 to 12 clock cycles for 12 bits */
2246 /* from 1 to 10 clock cycles for 10 bits, */
2247 /* from 1 to 8 clock cycles for 8 bits */
2248 /* from 1 to 6 clock cycles for 6 bits */
2249 /* If a higher delay is selected, it will be clipped to maximum delay */
2250 /* range */
2251 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
2252 {
2253 MODIFY_REG(tmpADC_Common->CCR,
2254 ADC_CCR_DUAL |
2255 ADC_CCR_DELAY,
2256 pMultimode->Mode |
2257 pMultimode->TwoSamplingDelay
2258 );
2259 }
2260 }
2261 else /* ADC_MODE_INDEPENDENT */
2262 {
2263 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
2264
2265 /* Parameters that can be updated only when ADC is disabled: */
2266 /* - Multimode mode selection */
2267 /* - Multimode delay */
2268 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
2269 {
2270 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
2271 }
2272 }
2273 }
2274 /* If one of the ADC sharing the same common group is enabled, no update */
2275 /* could be done on neither of the multimode structure parameters. */
2276 else
2277 {
2278 /* Update ADC state machine to error */
2279 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2280
2281 tmp_hal_status = HAL_ERROR;
2282 }
2283
2284 /* Process unlocked */
2285 __HAL_UNLOCK(hadc);
2286
2287 /* Return function status */
2288 return tmp_hal_status;
2289 }
2290 #endif /* ADC_MULTIMODE_SUPPORT */
2291
2292 /**
2293 * @brief Enable Injected Queue
2294 * @note This function resets CFGR register JQDIS bit in order to enable the
2295 * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
2296 * are both equal to 0 to ensure that no regular nor injected
2297 * conversion is ongoing.
2298 * @param hadc ADC handle
2299 * @retval HAL status
2300 */
HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef * hadc)2301 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc)
2302 {
2303 HAL_StatusTypeDef tmp_hal_status;
2304 uint32_t tmp_adc_is_conversion_on_going_regular;
2305 uint32_t tmp_adc_is_conversion_on_going_injected;
2306
2307 /* Check the parameters */
2308 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2309
2310 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2311 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2312
2313 /* Parameter can be set only if no conversion is on-going */
2314 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
2315 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2316 )
2317 {
2318 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
2319
2320 /* Update state, clear previous result related to injected queue overflow */
2321 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
2322
2323 tmp_hal_status = HAL_OK;
2324 }
2325 else
2326 {
2327 tmp_hal_status = HAL_ERROR;
2328 }
2329
2330 return tmp_hal_status;
2331 }
2332
2333 /**
2334 * @brief Disable Injected Queue
2335 * @note This function sets CFGR register JQDIS bit in order to disable the
2336 * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
2337 * are both equal to 0 to ensure that no regular nor injected
2338 * conversion is ongoing.
2339 * @param hadc ADC handle
2340 * @retval HAL status
2341 */
HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef * hadc)2342 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc)
2343 {
2344 HAL_StatusTypeDef tmp_hal_status;
2345 uint32_t tmp_adc_is_conversion_on_going_regular;
2346 uint32_t tmp_adc_is_conversion_on_going_injected;
2347
2348 /* Check the parameters */
2349 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2350
2351 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2352 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2353
2354 /* Parameter can be set only if no conversion is on-going */
2355 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
2356 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2357 )
2358 {
2359 LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE);
2360 tmp_hal_status = HAL_OK;
2361 }
2362 else
2363 {
2364 tmp_hal_status = HAL_ERROR;
2365 }
2366
2367 return tmp_hal_status;
2368 }
2369
2370 /**
2371 * @brief Disable ADC voltage regulator.
2372 * @note Disabling voltage regulator allows to save power. This operation can
2373 * be carried out only when ADC is disabled.
2374 * @note To enable again the voltage regulator, the user is expected to
2375 * resort to HAL_ADC_Init() API.
2376 * @param hadc ADC handle
2377 * @retval HAL status
2378 */
HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef * hadc)2379 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
2380 {
2381 HAL_StatusTypeDef tmp_hal_status;
2382
2383 /* Check the parameters */
2384 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2385
2386 /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
2387 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2388 {
2389 LL_ADC_DisableInternalRegulator(hadc->Instance);
2390 tmp_hal_status = HAL_OK;
2391 }
2392 else
2393 {
2394 tmp_hal_status = HAL_ERROR;
2395 }
2396
2397 return tmp_hal_status;
2398 }
2399
2400 /**
2401 * @brief Enter ADC deep-power-down mode
2402 * @note This mode is achieved in setting DEEPPWD bit and allows to save power
2403 * in reducing leakage currents. It is particularly interesting before
2404 * entering stop modes.
2405 * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the
2406 * ADC voltage regulator. This means that this API encompasses
2407 * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
2408 * calibration is lost.
2409 * @note To exit the ADC deep-power-down mode, the user is expected to
2410 * resort to HAL_ADC_Init() API as well as to relaunch a calibration
2411 * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
2412 * saved calibration factor.
2413 * @param hadc ADC handle
2414 * @retval HAL status
2415 */
HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef * hadc)2416 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
2417 {
2418 HAL_StatusTypeDef tmp_hal_status;
2419
2420 /* Check the parameters */
2421 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2422
2423 /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
2424 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2425 {
2426 LL_ADC_EnableDeepPowerDown(hadc->Instance);
2427 tmp_hal_status = HAL_OK;
2428 }
2429 else
2430 {
2431 tmp_hal_status = HAL_ERROR;
2432 }
2433
2434 return tmp_hal_status;
2435 }
2436
2437 /**
2438 * @}
2439 */
2440
2441 /**
2442 * @}
2443 */
2444
2445 #endif /* HAL_ADC_MODULE_ENABLED */
2446 /**
2447 * @}
2448 */
2449
2450 /**
2451 * @}
2452 */
2453
