1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_spi.h
4 * @author MCD Application Team
5 * @brief Header file of SPI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H5xx_LL_SPI_H
21 #define STM32H5xx_LL_SPI_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h5xx.h"
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
35
36 /** @defgroup SPI_LL SPI
37 * @{
38 */
39
40 /* Private variables ---------------------------------------------------------*/
41
42 /* Private constants ---------------------------------------------------------*/
43
44 /* Private macros ------------------------------------------------------------*/
45 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
46 * @{
47 */
48 /**
49 * @}
50 */
51
52 /* Exported types ------------------------------------------------------------*/
53 #if defined(USE_FULL_LL_DRIVER)
54 /** @defgroup SPI_LL_Exported_Types SPI Exported Types
55 * @{
56 */
57
58 /**
59 * @brief SPI Init structures definition
60 */
61 typedef struct
62 {
63 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
64 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
65
66 This feature can be modified afterwards using unitary function
67 @ref LL_SPI_SetTransferDirection().*/
68
69 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
70 This parameter can be a value of @ref SPI_LL_EC_MODE.
71
72 This feature can be modified afterwards using unitary function
73 @ref LL_SPI_SetMode().*/
74
75 uint32_t DataWidth; /*!< Specifies the SPI data width.
76 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
77
78 This feature can be modified afterwards using unitary function
79 @ref LL_SPI_SetDataWidth().*/
80
81 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
82 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
83
84 This feature can be modified afterwards using unitary function
85 @ref LL_SPI_SetClockPolarity().*/
86
87 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
88 This parameter can be a value of @ref SPI_LL_EC_PHASE.
89
90 This feature can be modified afterwards using unitary function
91 @ref LL_SPI_SetClockPhase().*/
92
93 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
94 or by software using the SSI bit.
95
96 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
97
98 This feature can be modified afterwards using unitary function
99 @ref LL_SPI_SetNSSMode().*/
100
101 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure
102 the transmit and receive SCK clock.
103 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
104 @note The communication clock is derived from the master clock.
105 The slave clock does not need to be set.
106
107 This feature can be modified afterwards using unitary function
108 @ref LL_SPI_SetBaudRatePrescaler().*/
109
110 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
111 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
112
113 This feature can be modified afterwards using unitary function
114 @ref LL_SPI_SetTransferBitOrder().*/
115
116 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
117 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
118
119 This feature can be modified afterwards using unitary functions
120 @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
121
122 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
123 This parameter must be a number between Min_Data = 0x00
124 and Max_Data = 0xFFFFFFFF.
125
126 This feature can be modified afterwards using unitary function
127 @ref LL_SPI_SetCRCPolynomial().*/
128
129 } LL_SPI_InitTypeDef;
130
131 /**
132 * @}
133 */
134 #endif /*USE_FULL_LL_DRIVER*/
135
136 /* Exported types ------------------------------------------------------------*/
137
138 /* Exported constants --------------------------------------------------------*/
139 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
140 * @{
141 */
142
143 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
144 * @brief Flags defines which can be used with LL_SPI_ReadReg function
145 * @{
146 */
147 #define LL_SPI_SR_RXP (SPI_SR_RXP)
148 #define LL_SPI_SR_TXP (SPI_SR_TXP)
149 #define LL_SPI_SR_DXP (SPI_SR_DXP)
150 #define LL_SPI_SR_EOT (SPI_SR_EOT)
151 #define LL_SPI_SR_TXTF (SPI_SR_TXTF)
152 #define LL_SPI_SR_UDR (SPI_SR_UDR)
153 #define LL_SPI_SR_CRCE (SPI_SR_CRCE)
154 #define LL_SPI_SR_MODF (SPI_SR_MODF)
155 #define LL_SPI_SR_OVR (SPI_SR_OVR)
156 #define LL_SPI_SR_TIFRE (SPI_SR_TIFRE)
157 #define LL_SPI_SR_SUSP (SPI_SR_SUSP)
158 #define LL_SPI_SR_TXC (SPI_SR_TXC)
159 #define LL_SPI_SR_RXWNE (SPI_SR_RXWNE)
160 /**
161 * @}
162 */
163
164 /** @defgroup SPI_LL_EC_IT IT Defines
165 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
166 * @{
167 */
168 #define LL_SPI_IER_RXPIE (SPI_IER_RXPIE)
169 #define LL_SPI_IER_TXPIE (SPI_IER_TXPIE)
170 #define LL_SPI_IER_DXPIE (SPI_IER_DXPIE)
171 #define LL_SPI_IER_EOTIE (SPI_IER_EOTIE)
172 #define LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE)
173 #define LL_SPI_IER_UDRIE (SPI_IER_UDRIE)
174 #define LL_SPI_IER_OVRIE (SPI_IER_OVRIE)
175 #define LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE)
176 #define LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE)
177 #define LL_SPI_IER_MODFIE (SPI_IER_MODFIE)
178 /**
179 * @}
180 */
181
182 /** @defgroup SPI_LL_EC_MODE Mode
183 * @{
184 */
185 #define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER)
186 #define LL_SPI_MODE_SLAVE (0x00000000UL)
187 /**
188 * @}
189 */
190
191 /** @defgroup SPI_LL_EC_SS_LEVEL SS Level
192 * @{
193 */
194 #define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI)
195 #define LL_SPI_SS_LEVEL_LOW (0x00000000UL)
196 /**
197 * @}
198 */
199
200 /** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness
201 * @{
202 */
203 #define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL)
204 #define LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0)
205 #define LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1)
206 #define LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1)
207 #define LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2)
208 #define LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
209 #define LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
210 #define LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
211 #define LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3)
212 #define LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0)
213 #define LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1)
214 #define LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
215 #define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)
216 #define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
217 #define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
218 #define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3\
219 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
220 /**
221 * @}
222 */
223
224 /** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness
225 * @{
226 */
227 #define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL)
228 #define LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0)
229 #define LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1)
230 #define LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1)
231 #define LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2)
232 #define LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
233 #define LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
234 #define LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
235 #define LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3)
236 #define LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0)
237 #define LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1)
238 #define LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
239 #define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)
240 #define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
241 #define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
242 #define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3\
243 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
244 /**
245 * @}
246 */
247
248 /** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All
249 * @{
250 */
251 #define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
252 #define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI)
253 /**
254 * @}
255 */
256
257 /** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All
258 * @{
259 */
260 #define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
261 #define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI)
262 /**
263 * @}
264 */
265
266 /** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register
267 * @{
268 */
269 #define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL)
270 #define LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG)
271 /**
272 * @}
273 */
274
275 /** @defgroup SPI_LL_EC_PROTOCOL Protocol
276 * @{
277 */
278 #define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL)
279 #define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0)
280 /**
281 * @}
282 */
283
284 /** @defgroup SPI_LL_EC_PHASE Phase
285 * @{
286 */
287 #define LL_SPI_PHASE_1EDGE (0x00000000UL)
288 #define LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA)
289 /**
290 * @}
291 */
292
293 /** @defgroup SPI_LL_EC_POLARITY Polarity
294 * @{
295 */
296 #define LL_SPI_POLARITY_LOW (0x00000000UL)
297 #define LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL)
298 /**
299 * @}
300 */
301
302 /** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity
303 * @{
304 */
305 #define LL_SPI_NSS_POLARITY_LOW (0x00000000UL)
306 #define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP)
307 /**
308 * @}
309 */
310
311 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
312 * @{
313 */
314 #define LL_SPI_BAUDRATEPRESCALER_BYPASS (SPI_CFG1_BPASS)
315 #define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL)
316 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0)
317 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1)
318 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
319 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2)
320 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0)
321 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1)
322 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
323 /**
324 * @}
325 */
326
327 /** @defgroup SPI_LL_EC_BIT_ORDER Bit Order
328 * @{
329 */
330 #define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST)
331 #define LL_SPI_MSB_FIRST (0x00000000UL)
332 /**
333 * @}
334 */
335
336 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
337 * @{
338 */
339 #define LL_SPI_FULL_DUPLEX (0x00000000UL)
340 #define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0)
341 #define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1)
342 #define LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1)
343 #define LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR)
344 /**
345 * @}
346 */
347
348 /** @defgroup SPI_LL_EC_DATAWIDTH Data Width
349 * @{
350 */
351 #define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
352 #define LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2)
353 #define LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
354 #define LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
355 #define LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
356 #define LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3)
357 #define LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
358 #define LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
359 #define LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
360 #define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
361 #define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
362 #define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
363 #define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3\
364 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
365 #define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4)
366 #define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)
367 #define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)
368 #define LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
369 #define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)
370 #define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
371 #define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
372 #define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4\
373 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
374 #define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)
375 #define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
376 #define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
377 #define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4\
378 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
379 #define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
380 #define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4\
381 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
382 #define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4\
383 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
384 #define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\
385 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
386 /**
387 * @}
388 */
389
390 /** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold
391 * @{
392 */
393 #define LL_SPI_FIFO_TH_01DATA (0x00000000UL)
394 #define LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0)
395 #define LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1)
396 #define LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1)
397 #define LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2)
398 #define LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
399 #define LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
400 #define LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
401 #define LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3)
402 #define LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0)
403 #define LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1)
404 #define LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
405 #define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)
406 #define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
407 #define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
408 #define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3\
409 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
410 /**
411 * @}
412 */
413
414 #if defined(USE_FULL_LL_DRIVER)
415
416 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
417 * @{
418 */
419 #define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL) /*!< CRC calculation disabled */
420 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN) /*!< CRC calculation enabled */
421 /**
422 * @}
423 */
424 #endif /* USE_FULL_LL_DRIVER */
425
426 /** @defgroup SPI_LL_EC_CRC CRC
427 * @{
428 */
429 #define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
430 #define LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2)
431 #define LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
432 #define LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
433 #define LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
434 #define LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3)
435 #define LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
436 #define LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
437 #define LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
438 #define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
439 #define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
440 #define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
441 #define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3\
442 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
443 #define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4)
444 #define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)
445 #define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)
446 #define LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
447 #define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)
448 #define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
449 #define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
450 #define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4\
451 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
452 #define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)
453 #define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
454 #define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
455 #define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4\
456 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
457 #define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
458 #define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4\
459 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
460 #define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4\
461 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
462 #define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\
463 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
464 /**
465 * @}
466 */
467
468 /** @defgroup SPI_LL_EC_NSS_MODE NSS Mode
469 * @{
470 */
471 #define LL_SPI_NSS_SOFT (SPI_CFG2_SSM)
472 #define LL_SPI_NSS_HARD_INPUT (0x00000000UL)
473 #define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE)
474 /**
475 * @}
476 */
477
478 /** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel
479 * @{
480 */
481 #define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */
482 #define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
483 #define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
484 #define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
485 /**
486 * @}
487 */
488
489 /**
490 * @}
491 */
492
493 /* Exported macro ------------------------------------------------------------*/
494 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
495 * @{
496 */
497
498 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
499 * @{
500 */
501
502 /**
503 * @brief Write a value in SPI register
504 * @param __INSTANCE__ SPI Instance
505 * @param __REG__ Register to be written
506 * @param __VALUE__ Value to be written in the register
507 * @retval None
508 */
509 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
510
511 /**
512 * @brief Read a value in SPI register
513 * @param __INSTANCE__ SPI Instance
514 * @param __REG__ Register to be read
515 * @retval Register value
516 */
517 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
518 /**
519 * @}
520 */
521
522 /**
523 * @}
524 */
525
526
527 /* Exported functions --------------------------------------------------------*/
528
529 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
530 * @{
531 */
532
533 /** @defgroup SPI_LL_EF_Configuration Configuration
534 * @{
535 */
536
537 /**
538 * @brief Enable SPI peripheral
539 * @rmtoll CR1 SPE LL_SPI_Enable
540 * @param SPIx SPI Instance
541 * @retval None
542 */
LL_SPI_Enable(SPI_TypeDef * SPIx)543 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
544 {
545 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
546 }
547
548 /**
549 * @brief Disable SPI peripheral
550 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
551 * @rmtoll CR1 SPE LL_SPI_Disable
552 * @param SPIx SPI Instance
553 * @retval None
554 */
LL_SPI_Disable(SPI_TypeDef * SPIx)555 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
556 {
557 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
558 }
559
560 /**
561 * @brief Check if SPI peripheral is enabled
562 * @rmtoll CR1 SPE LL_SPI_IsEnabled
563 * @param SPIx SPI Instance
564 * @retval State of bit (1 or 0)
565 */
LL_SPI_IsEnabled(SPI_TypeDef * SPIx)566 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
567 {
568 return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
569 }
570
571 /**
572 * @brief Swap the MOSI and MISO pin
573 * @note This configuration can not be changed when SPI is enabled.
574 * @rmtoll CFG2 IOSWP LL_SPI_EnableIOSwap
575 * @param SPIx SPI Instance
576 * @retval None
577 */
LL_SPI_EnableIOSwap(SPI_TypeDef * SPIx)578 __STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx)
579 {
580 SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
581 }
582
583 /**
584 * @brief Restore default function for MOSI and MISO pin
585 * @note This configuration can not be changed when SPI is enabled.
586 * @rmtoll CFG2 IOSWP LL_SPI_DisableIOSwap
587 * @param SPIx SPI Instance
588 * @retval None
589 */
LL_SPI_DisableIOSwap(SPI_TypeDef * SPIx)590 __STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx)
591 {
592 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
593 }
594
595 /**
596 * @brief Check if MOSI and MISO pin are swapped
597 * @rmtoll CFG2 IOSWP LL_SPI_IsEnabledIOSwap
598 * @param SPIx SPI Instance
599 * @retval State of bit (1 or 0)
600 */
LL_SPI_IsEnabledIOSwap(SPI_TypeDef * SPIx)601 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(SPI_TypeDef *SPIx)
602 {
603 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
604 }
605
606 /**
607 * @brief Enable GPIO control
608 * @note This configuration can not be changed when SPI is enabled.
609 * @rmtoll CFG2 AFCNTR LL_SPI_EnableGPIOControl
610 * @param SPIx SPI Instance
611 * @retval None
612 */
LL_SPI_EnableGPIOControl(SPI_TypeDef * SPIx)613 __STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx)
614 {
615 SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
616 }
617
618 /**
619 * @brief Disable GPIO control
620 * @note This configuration can not be changed when SPI is enabled.
621 * @rmtoll CFG2 AFCNTR LL_SPI_DisableGPIOControl
622 * @param SPIx SPI Instance
623 * @retval None
624 */
LL_SPI_DisableGPIOControl(SPI_TypeDef * SPIx)625 __STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx)
626 {
627 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
628 }
629
630 /**
631 * @brief Check if GPIO control is active
632 * @rmtoll CFG2 AFCNTR LL_SPI_IsEnabledGPIOControl
633 * @param SPIx SPI Instance
634 * @retval State of bit (1 or 0)
635 */
LL_SPI_IsEnabledGPIOControl(SPI_TypeDef * SPIx)636 __STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
637 {
638 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL);
639 }
640
641 /**
642 * @brief Set SPI Mode to Master or Slave
643 * @note This configuration can not be changed when SPI is enabled.
644 * @rmtoll CFG2 MASTER LL_SPI_SetMode
645 * @param SPIx SPI Instance
646 * @param Mode This parameter can be one of the following values:
647 * @arg @ref LL_SPI_MODE_MASTER
648 * @arg @ref LL_SPI_MODE_SLAVE
649 * @retval None
650 */
LL_SPI_SetMode(SPI_TypeDef * SPIx,uint32_t Mode)651 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
652 {
653 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode);
654 }
655
656 /**
657 * @brief Get SPI Mode (Master or Slave)
658 * @rmtoll CFG2 MASTER LL_SPI_GetMode
659 * @param SPIx SPI Instance
660 * @retval Returned value can be one of the following values:
661 * @arg @ref LL_SPI_MODE_MASTER
662 * @arg @ref LL_SPI_MODE_SLAVE
663 */
LL_SPI_GetMode(SPI_TypeDef * SPIx)664 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
665 {
666 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER));
667 }
668
669 /**
670 * @brief Configure the Idleness applied by master between active edge of SS and first send data
671 * @rmtoll CFG2 MSSI LL_SPI_SetMasterSSIdleness
672 * @param SPIx SPI Instance
673 * @param MasterSSIdleness This parameter can be one of the following values:
674 * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
675 * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
676 * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
677 * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
678 * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
679 * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
680 * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
681 * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
682 * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
683 * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
684 * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
685 * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
686 * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
687 * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
688 * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
689 * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
690 * @retval None
691 */
LL_SPI_SetMasterSSIdleness(SPI_TypeDef * SPIx,uint32_t MasterSSIdleness)692 __STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness)
693 {
694 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness);
695 }
696
697 /**
698 * @brief Get the configured Idleness applied by master
699 * @rmtoll CFG2 MSSI LL_SPI_GetMasterSSIdleness
700 * @param SPIx SPI Instance
701 * @retval Returned value can be one of the following values:
702 * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
703 * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
704 * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
705 * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
706 * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
707 * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
708 * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
709 * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
710 * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
711 * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
712 * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
713 * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
714 * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
715 * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
716 * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
717 * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
718 */
LL_SPI_GetMasterSSIdleness(SPI_TypeDef * SPIx)719 __STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(SPI_TypeDef *SPIx)
720 {
721 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI));
722 }
723
724 /**
725 * @brief Configure the idleness applied by master between data frame
726 * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
727 * @param SPIx SPI Instance
728 * @param MasterInterDataIdleness This parameter can be one of the following values:
729 * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
730 * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
731 * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
732 * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
733 * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
734 * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
735 * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
736 * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
737 * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
738 * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
739 * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
740 * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
741 * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
742 * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
743 * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
744 * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
745 * @retval None
746 */
LL_SPI_SetInterDataIdleness(SPI_TypeDef * SPIx,uint32_t MasterInterDataIdleness)747 __STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness)
748 {
749 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness);
750 }
751
752 /**
753 * @brief Get the configured inter data idleness
754 * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
755 * @param SPIx SPI Instance
756 * @retval Returned value can be one of the following values:
757 * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
758 * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
759 * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
760 * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
761 * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
762 * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
763 * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
764 * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
765 * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
766 * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
767 * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
768 * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
769 * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
770 * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
771 * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
772 * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
773 */
LL_SPI_GetInterDataIdleness(SPI_TypeDef * SPIx)774 __STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(SPI_TypeDef *SPIx)
775 {
776 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI));
777 }
778
779 /**
780 * @brief Set transfer size
781 * @note Count is the number of frame to be transferred
782 * @rmtoll CR2 TSIZE LL_SPI_SetTransferSize
783 * @param SPIx SPI Instance
784 * @param Count 0..0xFFFF
785 * @retval None
786 */
LL_SPI_SetTransferSize(SPI_TypeDef * SPIx,uint32_t Count)787 __STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count)
788 {
789 MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count);
790 }
791
792 /**
793 * @brief Get transfer size
794 * @note Count is the number of frame to be transferred
795 * @rmtoll CR2 TSIZE LL_SPI_GetTransferSize
796 * @param SPIx SPI Instance
797 * @retval 0..0xFFFF
798 */
LL_SPI_GetTransferSize(SPI_TypeDef * SPIx)799 __STATIC_INLINE uint32_t LL_SPI_GetTransferSize(SPI_TypeDef *SPIx)
800 {
801 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE));
802 }
803
804 /**
805 * @brief Lock the AF configuration of associated IOs
806 * @note Once this bit is set, the AF configuration remains locked until a hardware reset occurs.
807 * the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
808 * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock
809 * @param SPIx SPI Instance
810 * @retval None
811 */
LL_SPI_EnableIOLock(SPI_TypeDef * SPIx)812 __STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx)
813 {
814 SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK);
815 }
816
817 /**
818 * @brief Check if the AF configuration is locked.
819 * @rmtoll CR1 IOLOCK LL_SPI_IsEnabledIOLock
820 * @param SPIx SPI Instance
821 * @retval State of bit (1 or 0)
822 */
LL_SPI_IsEnabledIOLock(SPI_TypeDef * SPIx)823 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(SPI_TypeDef *SPIx)
824 {
825 return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL);
826 }
827
828 /**
829 * @brief Set Tx CRC Initialization Pattern
830 * @rmtoll CR1 TCRCINI LL_SPI_SetTxCRCInitPattern
831 * @param SPIx SPI Instance
832 * @param TXCRCInitAll This parameter can be one of the following values:
833 * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
834 * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
835 * @retval None
836 */
LL_SPI_SetTxCRCInitPattern(SPI_TypeDef * SPIx,uint32_t TXCRCInitAll)837 __STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
838 {
839 MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll);
840 }
841
842 /**
843 * @brief Get Tx CRC Initialization Pattern
844 * @rmtoll CR1 TCRCINI LL_SPI_GetTxCRCInitPattern
845 * @param SPIx SPI Instance
846 * @retval Returned value can be one of the following values:
847 * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
848 * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
849 */
LL_SPI_GetTxCRCInitPattern(SPI_TypeDef * SPIx)850 __STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(SPI_TypeDef *SPIx)
851 {
852 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI));
853 }
854
855 /**
856 * @brief Set Rx CRC Initialization Pattern
857 * @rmtoll CR1 RCRCINI LL_SPI_SetRxCRCInitPattern
858 * @param SPIx SPI Instance
859 * @param RXCRCInitAll This parameter can be one of the following values:
860 * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
861 * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
862 * @retval None
863 */
LL_SPI_SetRxCRCInitPattern(SPI_TypeDef * SPIx,uint32_t RXCRCInitAll)864 __STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll)
865 {
866 MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll);
867 }
868
869 /**
870 * @brief Get Rx CRC Initialization Pattern
871 * @rmtoll CR1 RCRCINI LL_SPI_GetRxCRCInitPattern
872 * @param SPIx SPI Instance
873 * @retval Returned value can be one of the following values:
874 * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
875 * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
876 */
LL_SPI_GetRxCRCInitPattern(SPI_TypeDef * SPIx)877 __STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(SPI_TypeDef *SPIx)
878 {
879 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI));
880 }
881
882 /**
883 * @brief Set internal SS input level ignoring what comes from PIN.
884 * @note This configuration has effect only with config LL_SPI_NSS_SOFT
885 * @rmtoll CR1 SSI LL_SPI_SetInternalSSLevel
886 * @param SPIx SPI Instance
887 * @param SSLevel This parameter can be one of the following values:
888 * @arg @ref LL_SPI_SS_LEVEL_HIGH
889 * @arg @ref LL_SPI_SS_LEVEL_LOW
890 * @retval None
891 */
LL_SPI_SetInternalSSLevel(SPI_TypeDef * SPIx,uint32_t SSLevel)892 __STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel)
893 {
894 MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel);
895 }
896
897 /**
898 * @brief Get internal SS input level
899 * @rmtoll CR1 SSI LL_SPI_GetInternalSSLevel
900 * @param SPIx SPI Instance
901 * @retval Returned value can be one of the following values:
902 * @arg @ref LL_SPI_SS_LEVEL_HIGH
903 * @arg @ref LL_SPI_SS_LEVEL_LOW
904 */
LL_SPI_GetInternalSSLevel(SPI_TypeDef * SPIx)905 __STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(SPI_TypeDef *SPIx)
906 {
907 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI));
908 }
909
910 /**
911 * @brief Enable CRC computation on 33/17 bits
912 * @rmtoll CR1 CRC33_17 LL_SPI_EnableFullSizeCRC
913 * @param SPIx SPI Instance
914 * @retval None
915 */
LL_SPI_EnableFullSizeCRC(SPI_TypeDef * SPIx)916 __STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx)
917 {
918 SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
919 }
920
921 /**
922 * @brief Disable CRC computation on 33/17 bits
923 * @rmtoll CR1 CRC33_17 LL_SPI_DisableFullSizeCRC
924 * @param SPIx SPI Instance
925 * @retval None
926 */
LL_SPI_DisableFullSizeCRC(SPI_TypeDef * SPIx)927 __STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx)
928 {
929 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
930 }
931
932 /**
933 * @brief Check if Enable CRC computation on 33/17 bits is enabled
934 * @rmtoll CR1 CRC33_17 LL_SPI_IsEnabledFullSizeCRC
935 * @param SPIx SPI Instance
936 * @retval State of bit (1 or 0)
937 */
LL_SPI_IsEnabledFullSizeCRC(SPI_TypeDef * SPIx)938 __STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(SPI_TypeDef *SPIx)
939 {
940 return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL);
941 }
942
943 /**
944 * @brief Suspend an ongoing transfer for Master configuration
945 * @rmtoll CR1 CSUSP LL_SPI_SuspendMasterTransfer
946 * @param SPIx SPI Instance
947 * @retval None
948 */
LL_SPI_SuspendMasterTransfer(SPI_TypeDef * SPIx)949 __STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx)
950 {
951 SET_BIT(SPIx->CR1, SPI_CR1_CSUSP);
952 }
953
954 /**
955 * @brief Start effective transfer on wire for Master configuration
956 * @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer
957 * @param SPIx SPI Instance
958 * @retval None
959 */
LL_SPI_StartMasterTransfer(SPI_TypeDef * SPIx)960 __STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx)
961 {
962 SET_BIT(SPIx->CR1, SPI_CR1_CSTART);
963 }
964
965 /**
966 * @brief Check if there is an unfinished master transfer
967 * @rmtoll CR1 CSTART LL_SPI_IsActiveMasterTransfer
968 * @param SPIx SPI Instance
969 * @retval State of bit (1 or 0)
970 */
LL_SPI_IsActiveMasterTransfer(SPI_TypeDef * SPIx)971 __STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(SPI_TypeDef *SPIx)
972 {
973 return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL);
974 }
975
976 /**
977 * @brief Enable Master Rx auto suspend in case of overrun
978 * @rmtoll CR1 MASRX LL_SPI_EnableMasterRxAutoSuspend
979 * @param SPIx SPI Instance
980 * @retval None
981 */
LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef * SPIx)982 __STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
983 {
984 SET_BIT(SPIx->CR1, SPI_CR1_MASRX);
985 }
986
987 /**
988 * @brief Disable Master Rx auto suspend in case of overrun
989 * @rmtoll CR1 MASRX LL_SPI_DisableMasterRxAutoSuspend
990 * @param SPIx SPI Instance
991 * @retval None
992 */
LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef * SPIx)993 __STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
994 {
995 CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX);
996 }
997
998 /**
999 * @brief Check if Master Rx auto suspend is activated
1000 * @rmtoll CR1 MASRX LL_SPI_IsEnabledMasterRxAutoSuspend
1001 * @param SPIx SPI Instance
1002 * @retval State of bit (1 or 0)
1003 */
LL_SPI_IsEnabledMasterRxAutoSuspend(SPI_TypeDef * SPIx)1004 __STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(SPI_TypeDef *SPIx)
1005 {
1006 return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL);
1007 }
1008
1009 /**
1010 * @brief Set Underrun behavior
1011 * @note This configuration can not be changed when SPI is enabled.
1012 * @rmtoll CFG1 UDRCFG LL_SPI_SetUDRConfiguration
1013 * @param SPIx SPI Instance
1014 * @param UDRConfig This parameter can be one of the following values:
1015 * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
1016 * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
1017 * @retval None
1018 */
LL_SPI_SetUDRConfiguration(SPI_TypeDef * SPIx,uint32_t UDRConfig)1019 __STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig)
1020 {
1021 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig);
1022 }
1023
1024 /**
1025 * @brief Get Underrun behavior
1026 * @rmtoll CFG1 UDRCFG LL_SPI_GetUDRConfiguration
1027 * @param SPIx SPI Instance
1028 * @retval Returned value can be one of the following values:
1029 * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
1030 * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
1031 */
LL_SPI_GetUDRConfiguration(SPI_TypeDef * SPIx)1032 __STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(SPI_TypeDef *SPIx)
1033 {
1034 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));
1035 }
1036
1037
1038 /**
1039 * @brief Set Serial protocol used
1040 * @note This configuration can not be changed when SPI is enabled.
1041 * @rmtoll CFG2 SP LL_SPI_SetStandard
1042 * @param SPIx SPI Instance
1043 * @param Standard This parameter can be one of the following values:
1044 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
1045 * @arg @ref LL_SPI_PROTOCOL_TI
1046 * @retval None
1047 */
LL_SPI_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)1048 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1049 {
1050 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard);
1051 }
1052
1053 /**
1054 * @brief Get Serial protocol used
1055 * @rmtoll CFG2 SP LL_SPI_GetStandard
1056 * @param SPIx SPI Instance
1057 * @retval Returned value can be one of the following values:
1058 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
1059 * @arg @ref LL_SPI_PROTOCOL_TI
1060 */
LL_SPI_GetStandard(SPI_TypeDef * SPIx)1061 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
1062 {
1063 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP));
1064 }
1065
1066 /**
1067 * @brief Set Clock phase
1068 * @note This configuration can not be changed when SPI is enabled.
1069 * This bit is not used in SPI TI mode.
1070 * @rmtoll CFG2 CPHA LL_SPI_SetClockPhase
1071 * @param SPIx SPI Instance
1072 * @param ClockPhase This parameter can be one of the following values:
1073 * @arg @ref LL_SPI_PHASE_1EDGE
1074 * @arg @ref LL_SPI_PHASE_2EDGE
1075 * @retval None
1076 */
LL_SPI_SetClockPhase(SPI_TypeDef * SPIx,uint32_t ClockPhase)1077 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
1078 {
1079 MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase);
1080 }
1081
1082 /**
1083 * @brief Get Clock phase
1084 * @rmtoll CFG2 CPHA LL_SPI_GetClockPhase
1085 * @param SPIx SPI Instance
1086 * @retval Returned value can be one of the following values:
1087 * @arg @ref LL_SPI_PHASE_1EDGE
1088 * @arg @ref LL_SPI_PHASE_2EDGE
1089 */
LL_SPI_GetClockPhase(SPI_TypeDef * SPIx)1090 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
1091 {
1092 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA));
1093 }
1094
1095 /**
1096 * @brief Set Clock polarity
1097 * @note This configuration can not be changed when SPI is enabled.
1098 * This bit is not used in SPI TI mode.
1099 * @rmtoll CFG2 CPOL LL_SPI_SetClockPolarity
1100 * @param SPIx SPI Instance
1101 * @param ClockPolarity This parameter can be one of the following values:
1102 * @arg @ref LL_SPI_POLARITY_LOW
1103 * @arg @ref LL_SPI_POLARITY_HIGH
1104 * @retval None
1105 */
LL_SPI_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)1106 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1107 {
1108 MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity);
1109 }
1110
1111 /**
1112 * @brief Get Clock polarity
1113 * @rmtoll CFG2 CPOL LL_SPI_GetClockPolarity
1114 * @param SPIx SPI Instance
1115 * @retval Returned value can be one of the following values:
1116 * @arg @ref LL_SPI_POLARITY_LOW
1117 * @arg @ref LL_SPI_POLARITY_HIGH
1118 */
LL_SPI_GetClockPolarity(SPI_TypeDef * SPIx)1119 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
1120 {
1121 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL));
1122 }
1123
1124 /**
1125 * @brief Set NSS polarity
1126 * @note This configuration can not be changed when SPI is enabled.
1127 * This bit is not used in SPI TI mode.
1128 * @rmtoll CFG2 SSIOP LL_SPI_SetNSSPolarity
1129 * @param SPIx SPI Instance
1130 * @param NSSPolarity This parameter can be one of the following values:
1131 * @arg @ref LL_SPI_NSS_POLARITY_LOW
1132 * @arg @ref LL_SPI_NSS_POLARITY_HIGH
1133 * @retval None
1134 */
LL_SPI_SetNSSPolarity(SPI_TypeDef * SPIx,uint32_t NSSPolarity)1135 __STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity)
1136 {
1137 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity);
1138 }
1139
1140 /**
1141 * @brief Get NSS polarity
1142 * @rmtoll CFG2 SSIOP LL_SPI_GetNSSPolarity
1143 * @param SPIx SPI Instance
1144 * @retval Returned value can be one of the following values:
1145 * @arg @ref LL_SPI_NSS_POLARITY_LOW
1146 * @arg @ref LL_SPI_NSS_POLARITY_HIGH
1147 */
LL_SPI_GetNSSPolarity(SPI_TypeDef * SPIx)1148 __STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(SPI_TypeDef *SPIx)
1149 {
1150 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));
1151 }
1152
1153 /**
1154 * @brief Set Baudrate Prescaler
1155 * @note This configuration can not be changed when SPI is enabled.
1156 * SPI BaudRate = fPCLK/Pescaler.
1157 * @rmtoll CFG1 MBR BPASS LL_SPI_SetBaudRatePrescaler
1158 * @param SPIx SPI Instance
1159 * @param Baudrate This parameter can be one of the following values:
1160 * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS
1161 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
1162 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
1163 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
1164 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
1165 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
1166 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
1167 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
1168 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
1169 * @retval None
1170 */
LL_SPI_SetBaudRatePrescaler(SPI_TypeDef * SPIx,uint32_t Baudrate)1171 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate)
1172 {
1173 MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate);
1174 }
1175
1176 /**
1177 * @brief Get Baudrate Prescaler
1178 * @rmtoll CFG1 MBR BPASS LL_SPI_GetBaudRatePrescaler
1179 * @param SPIx SPI Instance
1180 * @retval Returned value can be one of the following values:
1181 * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS
1182 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
1183 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
1184 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
1185 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
1186 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
1187 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
1188 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
1189 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
1190 */
LL_SPI_GetBaudRatePrescaler(SPI_TypeDef * SPIx)1191 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
1192 {
1193 return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS)));
1194 }
1195
1196 /**
1197 * @brief Set Transfer Bit Order
1198 * @note This configuration can not be changed when SPI is enabled.
1199 * This bit is not used in SPI TI mode.
1200 * @rmtoll CFG2 LSBFRST LL_SPI_SetTransferBitOrder
1201 * @param SPIx SPI Instance
1202 * @param BitOrder This parameter can be one of the following values:
1203 * @arg @ref LL_SPI_LSB_FIRST
1204 * @arg @ref LL_SPI_MSB_FIRST
1205 * @retval None
1206 */
LL_SPI_SetTransferBitOrder(SPI_TypeDef * SPIx,uint32_t BitOrder)1207 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
1208 {
1209 MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder);
1210 }
1211
1212 /**
1213 * @brief Get Transfer Bit Order
1214 * @rmtoll CFG2 LSBFRST LL_SPI_GetTransferBitOrder
1215 * @param SPIx SPI Instance
1216 * @retval Returned value can be one of the following values:
1217 * @arg @ref LL_SPI_LSB_FIRST
1218 * @arg @ref LL_SPI_MSB_FIRST
1219 */
LL_SPI_GetTransferBitOrder(SPI_TypeDef * SPIx)1220 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
1221 {
1222 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST));
1223 }
1224
1225 /**
1226 * @brief Set Transfer Mode
1227 * @note This configuration can not be changed when SPI is enabled except for half duplex direction
1228 * using LL_SPI_SetHalfDuplexDirection.
1229 * @rmtoll CR1 HDDIR LL_SPI_SetTransferDirection\n
1230 * CFG2 COMM LL_SPI_SetTransferDirection
1231 * @param SPIx SPI Instance
1232 * @param TransferDirection This parameter can be one of the following values:
1233 * @arg @ref LL_SPI_FULL_DUPLEX
1234 * @arg @ref LL_SPI_SIMPLEX_TX
1235 * @arg @ref LL_SPI_SIMPLEX_RX
1236 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1237 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1238 * @retval None
1239 */
LL_SPI_SetTransferDirection(SPI_TypeDef * SPIx,uint32_t TransferDirection)1240 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
1241 {
1242 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, TransferDirection & SPI_CR1_HDDIR);
1243 MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM);
1244 }
1245
1246 /**
1247 * @brief Get Transfer Mode
1248 * @rmtoll CR1 HDDIR LL_SPI_GetTransferDirection\n
1249 * CFG2 COMM LL_SPI_GetTransferDirection
1250 * @param SPIx SPI Instance
1251 * @retval Returned value can be one of the following values:
1252 * @arg @ref LL_SPI_FULL_DUPLEX
1253 * @arg @ref LL_SPI_SIMPLEX_TX
1254 * @arg @ref LL_SPI_SIMPLEX_RX
1255 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1256 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1257 */
LL_SPI_GetTransferDirection(SPI_TypeDef * SPIx)1258 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
1259 {
1260 uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
1261 uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
1262 return (Hddir | Comm);
1263 }
1264
1265 /**
1266 * @brief Set direction for Half-Duplex Mode
1267 * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
1268 * @rmtoll CR1 HDDIR LL_SPI_SetHalfDuplexDirection
1269 * @param SPIx SPI Instance
1270 * @param HalfDuplexDirection This parameter can be one of the following values:
1271 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1272 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1273 * @retval None
1274 */
LL_SPI_SetHalfDuplexDirection(SPI_TypeDef * SPIx,uint32_t HalfDuplexDirection)1275 __STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection)
1276 {
1277 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR);
1278 }
1279
1280 /**
1281 * @brief Get direction for Half-Duplex Mode
1282 * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
1283 * @rmtoll CR1 HDDIR LL_SPI_GetHalfDuplexDirection
1284 * @param SPIx SPI Instance
1285 * @retval Returned value can be one of the following values:
1286 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1287 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1288 */
LL_SPI_GetHalfDuplexDirection(SPI_TypeDef * SPIx)1289 __STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(SPI_TypeDef *SPIx)
1290 {
1291 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM);
1292 }
1293
1294 /**
1295 * @brief Set Frame Data Size
1296 * @note This configuration can not be changed when SPI is enabled.
1297 * @rmtoll CFG1 DSIZE LL_SPI_SetDataWidth
1298 * @param SPIx SPI Instance
1299 * @param DataWidth This parameter can be one of the following values:
1300 * @arg @ref LL_SPI_DATAWIDTH_4BIT
1301 * @arg @ref LL_SPI_DATAWIDTH_5BIT
1302 * @arg @ref LL_SPI_DATAWIDTH_6BIT
1303 * @arg @ref LL_SPI_DATAWIDTH_7BIT
1304 * @arg @ref LL_SPI_DATAWIDTH_8BIT
1305 * @arg @ref LL_SPI_DATAWIDTH_9BIT
1306 * @arg @ref LL_SPI_DATAWIDTH_10BIT
1307 * @arg @ref LL_SPI_DATAWIDTH_11BIT
1308 * @arg @ref LL_SPI_DATAWIDTH_12BIT
1309 * @arg @ref LL_SPI_DATAWIDTH_13BIT
1310 * @arg @ref LL_SPI_DATAWIDTH_14BIT
1311 * @arg @ref LL_SPI_DATAWIDTH_15BIT
1312 * @arg @ref LL_SPI_DATAWIDTH_16BIT
1313 * @arg @ref LL_SPI_DATAWIDTH_17BIT
1314 * @arg @ref LL_SPI_DATAWIDTH_18BIT
1315 * @arg @ref LL_SPI_DATAWIDTH_19BIT
1316 * @arg @ref LL_SPI_DATAWIDTH_20BIT
1317 * @arg @ref LL_SPI_DATAWIDTH_21BIT
1318 * @arg @ref LL_SPI_DATAWIDTH_22BIT
1319 * @arg @ref LL_SPI_DATAWIDTH_23BIT
1320 * @arg @ref LL_SPI_DATAWIDTH_24BIT
1321 * @arg @ref LL_SPI_DATAWIDTH_25BIT
1322 * @arg @ref LL_SPI_DATAWIDTH_26BIT
1323 * @arg @ref LL_SPI_DATAWIDTH_27BIT
1324 * @arg @ref LL_SPI_DATAWIDTH_28BIT
1325 * @arg @ref LL_SPI_DATAWIDTH_29BIT
1326 * @arg @ref LL_SPI_DATAWIDTH_30BIT
1327 * @arg @ref LL_SPI_DATAWIDTH_31BIT
1328 * @arg @ref LL_SPI_DATAWIDTH_32BIT
1329 * @retval None
1330 */
LL_SPI_SetDataWidth(SPI_TypeDef * SPIx,uint32_t DataWidth)1331 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
1332 {
1333 MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth);
1334 }
1335
1336 /**
1337 * @brief Get Frame Data Size
1338 * @rmtoll CFG1 DSIZE LL_SPI_GetDataWidth
1339 * @param SPIx SPI Instance
1340 * @retval Returned value can be one of the following values:
1341 * @arg @ref LL_SPI_DATAWIDTH_4BIT
1342 * @arg @ref LL_SPI_DATAWIDTH_5BIT
1343 * @arg @ref LL_SPI_DATAWIDTH_6BIT
1344 * @arg @ref LL_SPI_DATAWIDTH_7BIT
1345 * @arg @ref LL_SPI_DATAWIDTH_8BIT
1346 * @arg @ref LL_SPI_DATAWIDTH_9BIT
1347 * @arg @ref LL_SPI_DATAWIDTH_10BIT
1348 * @arg @ref LL_SPI_DATAWIDTH_11BIT
1349 * @arg @ref LL_SPI_DATAWIDTH_12BIT
1350 * @arg @ref LL_SPI_DATAWIDTH_13BIT
1351 * @arg @ref LL_SPI_DATAWIDTH_14BIT
1352 * @arg @ref LL_SPI_DATAWIDTH_15BIT
1353 * @arg @ref LL_SPI_DATAWIDTH_16BIT
1354 * @arg @ref LL_SPI_DATAWIDTH_17BIT
1355 * @arg @ref LL_SPI_DATAWIDTH_18BIT
1356 * @arg @ref LL_SPI_DATAWIDTH_19BIT
1357 * @arg @ref LL_SPI_DATAWIDTH_20BIT
1358 * @arg @ref LL_SPI_DATAWIDTH_21BIT
1359 * @arg @ref LL_SPI_DATAWIDTH_22BIT
1360 * @arg @ref LL_SPI_DATAWIDTH_23BIT
1361 * @arg @ref LL_SPI_DATAWIDTH_24BIT
1362 * @arg @ref LL_SPI_DATAWIDTH_25BIT
1363 * @arg @ref LL_SPI_DATAWIDTH_26BIT
1364 * @arg @ref LL_SPI_DATAWIDTH_27BIT
1365 * @arg @ref LL_SPI_DATAWIDTH_28BIT
1366 * @arg @ref LL_SPI_DATAWIDTH_29BIT
1367 * @arg @ref LL_SPI_DATAWIDTH_30BIT
1368 * @arg @ref LL_SPI_DATAWIDTH_31BIT
1369 * @arg @ref LL_SPI_DATAWIDTH_32BIT
1370 */
LL_SPI_GetDataWidth(SPI_TypeDef * SPIx)1371 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
1372 {
1373 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));
1374 }
1375
1376 /**
1377 * @brief Set threshold of FIFO that triggers a transfer event
1378 * @note This configuration can not be changed when SPI is enabled.
1379 * @rmtoll CFG1 FTHLV LL_SPI_SetFIFOThreshold
1380 * @param SPIx SPI Instance
1381 * @param Threshold This parameter can be one of the following values:
1382 * @arg @ref LL_SPI_FIFO_TH_01DATA
1383 * @arg @ref LL_SPI_FIFO_TH_02DATA
1384 * @arg @ref LL_SPI_FIFO_TH_03DATA
1385 * @arg @ref LL_SPI_FIFO_TH_04DATA
1386 * @arg @ref LL_SPI_FIFO_TH_05DATA
1387 * @arg @ref LL_SPI_FIFO_TH_06DATA
1388 * @arg @ref LL_SPI_FIFO_TH_07DATA
1389 * @arg @ref LL_SPI_FIFO_TH_08DATA
1390 * @arg @ref LL_SPI_FIFO_TH_09DATA
1391 * @arg @ref LL_SPI_FIFO_TH_10DATA
1392 * @arg @ref LL_SPI_FIFO_TH_11DATA
1393 * @arg @ref LL_SPI_FIFO_TH_12DATA
1394 * @arg @ref LL_SPI_FIFO_TH_13DATA
1395 * @arg @ref LL_SPI_FIFO_TH_14DATA
1396 * @arg @ref LL_SPI_FIFO_TH_15DATA
1397 * @arg @ref LL_SPI_FIFO_TH_16DATA
1398 * @retval None
1399 */
LL_SPI_SetFIFOThreshold(SPI_TypeDef * SPIx,uint32_t Threshold)1400 __STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
1401 {
1402 MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold);
1403 }
1404
1405 /**
1406 * @brief Get threshold of FIFO that triggers a transfer event
1407 * @rmtoll CFG1 FTHLV LL_SPI_GetFIFOThreshold
1408 * @param SPIx SPI Instance
1409 * @retval Returned value can be one of the following values:
1410 * @arg @ref LL_SPI_FIFO_TH_01DATA
1411 * @arg @ref LL_SPI_FIFO_TH_02DATA
1412 * @arg @ref LL_SPI_FIFO_TH_03DATA
1413 * @arg @ref LL_SPI_FIFO_TH_04DATA
1414 * @arg @ref LL_SPI_FIFO_TH_05DATA
1415 * @arg @ref LL_SPI_FIFO_TH_06DATA
1416 * @arg @ref LL_SPI_FIFO_TH_07DATA
1417 * @arg @ref LL_SPI_FIFO_TH_08DATA
1418 * @arg @ref LL_SPI_FIFO_TH_09DATA
1419 * @arg @ref LL_SPI_FIFO_TH_10DATA
1420 * @arg @ref LL_SPI_FIFO_TH_11DATA
1421 * @arg @ref LL_SPI_FIFO_TH_12DATA
1422 * @arg @ref LL_SPI_FIFO_TH_13DATA
1423 * @arg @ref LL_SPI_FIFO_TH_14DATA
1424 * @arg @ref LL_SPI_FIFO_TH_15DATA
1425 * @arg @ref LL_SPI_FIFO_TH_16DATA
1426 */
LL_SPI_GetFIFOThreshold(SPI_TypeDef * SPIx)1427 __STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(SPI_TypeDef *SPIx)
1428 {
1429 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));
1430 }
1431
1432 /**
1433 * @brief Enable CRC
1434 * @note This configuration can not be changed when SPI is enabled.
1435 * @rmtoll CFG1 CRCEN LL_SPI_EnableCRC
1436 * @param SPIx SPI Instance
1437 * @retval None
1438 */
LL_SPI_EnableCRC(SPI_TypeDef * SPIx)1439 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
1440 {
1441 SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
1442 }
1443
1444 /**
1445 * @brief Disable CRC
1446 * @rmtoll CFG1 CRCEN LL_SPI_DisableCRC
1447 * @param SPIx SPI Instance
1448 * @retval None
1449 */
LL_SPI_DisableCRC(SPI_TypeDef * SPIx)1450 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
1451 {
1452 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
1453 }
1454
1455 /**
1456 * @brief Check if CRC is enabled
1457 * @rmtoll CFG1 CRCEN LL_SPI_IsEnabledCRC
1458 * @param SPIx SPI Instance
1459 * @retval State of bit (1 or 0).
1460 */
LL_SPI_IsEnabledCRC(SPI_TypeDef * SPIx)1461 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
1462 {
1463 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);
1464 }
1465
1466 /**
1467 * @brief Set CRC Length
1468 * @note This configuration can not be changed when SPI is enabled.
1469 * @rmtoll CFG1 CRCSIZE LL_SPI_SetCRCWidth
1470 * @param SPIx SPI Instance
1471 * @param CRCLength This parameter can be one of the following values:
1472 * @arg @ref LL_SPI_CRC_4BIT
1473 * @arg @ref LL_SPI_CRC_5BIT
1474 * @arg @ref LL_SPI_CRC_6BIT
1475 * @arg @ref LL_SPI_CRC_7BIT
1476 * @arg @ref LL_SPI_CRC_8BIT
1477 * @arg @ref LL_SPI_CRC_9BIT
1478 * @arg @ref LL_SPI_CRC_10BIT
1479 * @arg @ref LL_SPI_CRC_11BIT
1480 * @arg @ref LL_SPI_CRC_12BIT
1481 * @arg @ref LL_SPI_CRC_13BIT
1482 * @arg @ref LL_SPI_CRC_14BIT
1483 * @arg @ref LL_SPI_CRC_15BIT
1484 * @arg @ref LL_SPI_CRC_16BIT
1485 * @arg @ref LL_SPI_CRC_17BIT
1486 * @arg @ref LL_SPI_CRC_18BIT
1487 * @arg @ref LL_SPI_CRC_19BIT
1488 * @arg @ref LL_SPI_CRC_20BIT
1489 * @arg @ref LL_SPI_CRC_21BIT
1490 * @arg @ref LL_SPI_CRC_22BIT
1491 * @arg @ref LL_SPI_CRC_23BIT
1492 * @arg @ref LL_SPI_CRC_24BIT
1493 * @arg @ref LL_SPI_CRC_25BIT
1494 * @arg @ref LL_SPI_CRC_26BIT
1495 * @arg @ref LL_SPI_CRC_27BIT
1496 * @arg @ref LL_SPI_CRC_28BIT
1497 * @arg @ref LL_SPI_CRC_29BIT
1498 * @arg @ref LL_SPI_CRC_30BIT
1499 * @arg @ref LL_SPI_CRC_31BIT
1500 * @arg @ref LL_SPI_CRC_32BIT
1501 * @retval None
1502 */
LL_SPI_SetCRCWidth(SPI_TypeDef * SPIx,uint32_t CRCLength)1503 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
1504 {
1505 MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength);
1506 }
1507
1508 /**
1509 * @brief Get CRC Length
1510 * @rmtoll CFG1 CRCSIZE LL_SPI_GetCRCWidth
1511 * @param SPIx SPI Instance
1512 * @retval Returned value can be one of the following values:
1513 * @arg @ref LL_SPI_CRC_4BIT
1514 * @arg @ref LL_SPI_CRC_5BIT
1515 * @arg @ref LL_SPI_CRC_6BIT
1516 * @arg @ref LL_SPI_CRC_7BIT
1517 * @arg @ref LL_SPI_CRC_8BIT
1518 * @arg @ref LL_SPI_CRC_9BIT
1519 * @arg @ref LL_SPI_CRC_10BIT
1520 * @arg @ref LL_SPI_CRC_11BIT
1521 * @arg @ref LL_SPI_CRC_12BIT
1522 * @arg @ref LL_SPI_CRC_13BIT
1523 * @arg @ref LL_SPI_CRC_14BIT
1524 * @arg @ref LL_SPI_CRC_15BIT
1525 * @arg @ref LL_SPI_CRC_16BIT
1526 * @arg @ref LL_SPI_CRC_17BIT
1527 * @arg @ref LL_SPI_CRC_18BIT
1528 * @arg @ref LL_SPI_CRC_19BIT
1529 * @arg @ref LL_SPI_CRC_20BIT
1530 * @arg @ref LL_SPI_CRC_21BIT
1531 * @arg @ref LL_SPI_CRC_22BIT
1532 * @arg @ref LL_SPI_CRC_23BIT
1533 * @arg @ref LL_SPI_CRC_24BIT
1534 * @arg @ref LL_SPI_CRC_25BIT
1535 * @arg @ref LL_SPI_CRC_26BIT
1536 * @arg @ref LL_SPI_CRC_27BIT
1537 * @arg @ref LL_SPI_CRC_28BIT
1538 * @arg @ref LL_SPI_CRC_29BIT
1539 * @arg @ref LL_SPI_CRC_30BIT
1540 * @arg @ref LL_SPI_CRC_31BIT
1541 * @arg @ref LL_SPI_CRC_32BIT
1542 */
LL_SPI_GetCRCWidth(SPI_TypeDef * SPIx)1543 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
1544 {
1545 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));
1546 }
1547
1548 /**
1549 * @brief Set NSS Mode
1550 * @note This configuration can not be changed when SPI is enabled.
1551 * This bit is not used in SPI TI mode.
1552 * @rmtoll CFG2 SSM LL_SPI_SetNSSMode\n
1553 * CFG2 SSOE LL_SPI_SetNSSMode
1554 * @param SPIx SPI Instance
1555 * @param NSS This parameter can be one of the following values:
1556 * @arg @ref LL_SPI_NSS_SOFT
1557 * @arg @ref LL_SPI_NSS_HARD_INPUT
1558 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
1559 * @retval None
1560 */
LL_SPI_SetNSSMode(SPI_TypeDef * SPIx,uint32_t NSS)1561 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
1562 {
1563 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS);
1564 }
1565
1566 /**
1567 * @brief Set NSS Mode
1568 * @rmtoll CFG2 SSM LL_SPI_GetNSSMode\n
1569 * CFG2 SSOE LL_SPI_GetNSSMode
1570 * @param SPIx SPI Instance
1571 * @retval Returned value can be one of the following values:
1572 * @arg @ref LL_SPI_NSS_SOFT
1573 * @arg @ref LL_SPI_NSS_HARD_INPUT
1574 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
1575 */
LL_SPI_GetNSSMode(SPI_TypeDef * SPIx)1576 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
1577 {
1578 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE));
1579 }
1580
1581 /**
1582 * @brief Enable NSS pulse mgt
1583 * @note This configuration can not be changed when SPI is enabled.
1584 * This bit is not used in SPI TI mode.
1585 * @rmtoll CFG2 SSOM LL_SPI_EnableNSSPulseMgt
1586 * @param SPIx SPI Instance
1587 * @retval None
1588 */
LL_SPI_EnableNSSPulseMgt(SPI_TypeDef * SPIx)1589 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
1590 {
1591 SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
1592 }
1593
1594 /**
1595 * @brief Disable NSS pulse mgt
1596 * @note This configuration can not be changed when SPI is enabled.
1597 * This bit is not used in SPI TI mode.
1598 * @rmtoll CFG2 SSOM LL_SPI_DisableNSSPulseMgt
1599 * @param SPIx SPI Instance
1600 * @retval None
1601 */
LL_SPI_DisableNSSPulseMgt(SPI_TypeDef * SPIx)1602 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
1603 {
1604 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
1605 }
1606
1607 /**
1608 * @brief Check if NSS pulse is enabled
1609 * @rmtoll CFG2 SSOM LL_SPI_IsEnabledNSSPulse
1610 * @param SPIx SPI Instance
1611 * @retval State of bit (1 or 0)
1612 */
LL_SPI_IsEnabledNSSPulse(SPI_TypeDef * SPIx)1613 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
1614 {
1615 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL);
1616 }
1617
1618 /**
1619 * @}
1620 */
1621
1622 /** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
1623 * @{
1624 */
1625
1626 /**
1627 * @brief Check if there is enough data in FIFO to read a full packet
1628 * @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP
1629 * @param SPIx SPI Instance
1630 * @retval State of bit (1 or 0)
1631 */
LL_SPI_IsActiveFlag_RXP(SPI_TypeDef * SPIx)1632 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
1633 {
1634 return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);
1635 }
1636
1637 /**
1638 * @brief Check if there is enough space in FIFO to hold a full packet
1639 * @rmtoll SR TXP LL_SPI_IsActiveFlag_TXP
1640 * @param SPIx SPI Instance
1641 * @retval State of bit (1 or 0)
1642 */
LL_SPI_IsActiveFlag_TXP(SPI_TypeDef * SPIx)1643 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
1644 {
1645 return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL);
1646 }
1647
1648 /**
1649 * @brief Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet
1650 * @rmtoll SR DXP LL_SPI_IsActiveFlag_DXP
1651 * @param SPIx SPI Instance
1652 * @retval State of bit (1 or 0)
1653 */
LL_SPI_IsActiveFlag_DXP(SPI_TypeDef * SPIx)1654 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(SPI_TypeDef *SPIx)
1655 {
1656 return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL);
1657 }
1658
1659 /**
1660 * @brief Check that end of transfer event occurred
1661 * @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT
1662 * @param SPIx SPI Instance
1663 * @retval State of bit (1 or 0).
1664 */
LL_SPI_IsActiveFlag_EOT(SPI_TypeDef * SPIx)1665 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx)
1666 {
1667 return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);
1668 }
1669
1670 /**
1671 * @brief Check that all required data has been filled in the fifo according to transfer size
1672 * @rmtoll SR TXTF LL_SPI_IsActiveFlag_TXTF
1673 * @param SPIx SPI Instance
1674 * @retval State of bit (1 or 0).
1675 */
LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef * SPIx)1676 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef *SPIx)
1677 {
1678 return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL);
1679 }
1680
1681 /**
1682 * @brief Get Underrun error flag
1683 * @rmtoll SR UDR LL_SPI_IsActiveFlag_UDR
1684 * @param SPIx SPI Instance
1685 * @retval State of bit (1 or 0).
1686 */
LL_SPI_IsActiveFlag_UDR(SPI_TypeDef * SPIx)1687 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
1688 {
1689 return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
1690 }
1691
1692 /**
1693 * @brief Get CRC error flag
1694 * @rmtoll SR CRCE LL_SPI_IsActiveFlag_CRCERR
1695 * @param SPIx SPI Instance
1696 * @retval State of bit (1 or 0).
1697 */
LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef * SPIx)1698 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
1699 {
1700 return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL);
1701 }
1702
1703 /**
1704 * @brief Get Mode fault error flag
1705 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
1706 * @param SPIx SPI Instance
1707 * @retval State of bit (1 or 0).
1708 */
LL_SPI_IsActiveFlag_MODF(SPI_TypeDef * SPIx)1709 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
1710 {
1711 return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
1712 }
1713
1714 /**
1715 * @brief Get Overrun error flag
1716 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
1717 * @param SPIx SPI Instance
1718 * @retval State of bit (1 or 0).
1719 */
LL_SPI_IsActiveFlag_OVR(SPI_TypeDef * SPIx)1720 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
1721 {
1722 return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
1723 }
1724
1725 /**
1726 * @brief Get TI Frame format error flag
1727 * @rmtoll SR TIFRE LL_SPI_IsActiveFlag_FRE
1728 * @param SPIx SPI Instance
1729 * @retval State of bit (1 or 0).
1730 */
LL_SPI_IsActiveFlag_FRE(SPI_TypeDef * SPIx)1731 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
1732 {
1733 return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL);
1734 }
1735
1736 /**
1737 * @brief Check if a suspend operation is done
1738 * @rmtoll SR SUSP LL_SPI_IsActiveFlag_SUSP
1739 * @param SPIx SPI Instance
1740 * @retval State of bit (1 or 0)
1741 */
LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef * SPIx)1742 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef *SPIx)
1743 {
1744 return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL);
1745 }
1746
1747 /**
1748 * @brief Check if last TxFIFO or CRC frame transmission is completed
1749 * @rmtoll SR TXC LL_SPI_IsActiveFlag_TXC
1750 * @param SPIx SPI Instance
1751 * @retval State of bit (1 or 0).
1752 */
LL_SPI_IsActiveFlag_TXC(SPI_TypeDef * SPIx)1753 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(SPI_TypeDef *SPIx)
1754 {
1755 return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL);
1756 }
1757
1758 /**
1759 * @brief Check if at least one 32-bit data is available in RxFIFO
1760 * @rmtoll SR RXWNE LL_SPI_IsActiveFlag_RXWNE
1761 * @param SPIx SPI Instance
1762 * @retval State of bit (1 or 0)
1763 */
LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef * SPIx)1764 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef *SPIx)
1765 {
1766 return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL);
1767 }
1768
1769 /**
1770 * @brief Get number of data framed remaining in current TSIZE
1771 * @rmtoll SR CTSIZE LL_SPI_GetRemainingDataFrames
1772 * @param SPIx SPI Instance
1773 * @retval 0..0xFFFF
1774 */
LL_SPI_GetRemainingDataFrames(SPI_TypeDef * SPIx)1775 __STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(SPI_TypeDef *SPIx)
1776 {
1777 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos);
1778 }
1779
1780 /**
1781 * @brief Get RxFIFO packing Level
1782 * @rmtoll SR RXPLVL LL_SPI_GetRxFIFOPackingLevel
1783 * @param SPIx SPI Instance
1784 * @retval Returned value can be one of the following values:
1785 * @arg @ref LL_SPI_RX_FIFO_0PACKET
1786 * @arg @ref LL_SPI_RX_FIFO_1PACKET
1787 * @arg @ref LL_SPI_RX_FIFO_2PACKET
1788 * @arg @ref LL_SPI_RX_FIFO_3PACKET
1789 */
LL_SPI_GetRxFIFOPackingLevel(SPI_TypeDef * SPIx)1790 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(SPI_TypeDef *SPIx)
1791 {
1792 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL));
1793 }
1794
1795 /**
1796 * @brief Clear End Of Transfer flag
1797 * @rmtoll IFCR EOTC LL_SPI_ClearFlag_EOT
1798 * @param SPIx SPI Instance
1799 * @retval None
1800 */
LL_SPI_ClearFlag_EOT(SPI_TypeDef * SPIx)1801 __STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx)
1802 {
1803 SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC);
1804 }
1805
1806 /**
1807 * @brief Clear TXTF flag
1808 * @rmtoll IFCR TXTFC LL_SPI_ClearFlag_TXTF
1809 * @param SPIx SPI Instance
1810 * @retval None
1811 */
LL_SPI_ClearFlag_TXTF(SPI_TypeDef * SPIx)1812 __STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx)
1813 {
1814 SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC);
1815 }
1816
1817 /**
1818 * @brief Clear Underrun error flag
1819 * @rmtoll IFCR UDRC LL_SPI_ClearFlag_UDR
1820 * @param SPIx SPI Instance
1821 * @retval None
1822 */
LL_SPI_ClearFlag_UDR(SPI_TypeDef * SPIx)1823 __STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx)
1824 {
1825 SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC);
1826 }
1827
1828 /**
1829 * @brief Clear Overrun error flag
1830 * @rmtoll IFCR OVRC LL_SPI_ClearFlag_OVR
1831 * @param SPIx SPI Instance
1832 * @retval None
1833 */
LL_SPI_ClearFlag_OVR(SPI_TypeDef * SPIx)1834 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
1835 {
1836 SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC);
1837 }
1838
1839 /**
1840 * @brief Clear CRC error flag
1841 * @rmtoll IFCR CRCEC LL_SPI_ClearFlag_CRCERR
1842 * @param SPIx SPI Instance
1843 * @retval None
1844 */
LL_SPI_ClearFlag_CRCERR(SPI_TypeDef * SPIx)1845 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
1846 {
1847 SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC);
1848 }
1849
1850 /**
1851 * @brief Clear Mode fault error flag
1852 * @rmtoll IFCR MODFC LL_SPI_ClearFlag_MODF
1853 * @param SPIx SPI Instance
1854 * @retval None
1855 */
LL_SPI_ClearFlag_MODF(SPI_TypeDef * SPIx)1856 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
1857 {
1858 SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC);
1859 }
1860
1861 /**
1862 * @brief Clear Frame format error flag
1863 * @rmtoll IFCR TIFREC LL_SPI_ClearFlag_FRE
1864 * @param SPIx SPI Instance
1865 * @retval None
1866 */
LL_SPI_ClearFlag_FRE(SPI_TypeDef * SPIx)1867 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
1868 {
1869 SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC);
1870 }
1871
1872 /**
1873 * @brief Clear SUSP flag
1874 * @rmtoll IFCR SUSPC LL_SPI_ClearFlag_SUSP
1875 * @param SPIx SPI Instance
1876 * @retval None
1877 */
LL_SPI_ClearFlag_SUSP(SPI_TypeDef * SPIx)1878 __STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx)
1879 {
1880 SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC);
1881 }
1882
1883 /**
1884 * @}
1885 */
1886
1887 /** @defgroup SPI_LL_EF_IT_Management IT_Management
1888 * @{
1889 */
1890
1891 /**
1892 * @brief Enable Rx Packet available IT
1893 * @rmtoll IER RXPIE LL_SPI_EnableIT_RXP
1894 * @param SPIx SPI Instance
1895 * @retval None
1896 */
LL_SPI_EnableIT_RXP(SPI_TypeDef * SPIx)1897 __STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx)
1898 {
1899 SET_BIT(SPIx->IER, SPI_IER_RXPIE);
1900 }
1901
1902 /**
1903 * @brief Enable Tx Packet space available IT
1904 * @rmtoll IER TXPIE LL_SPI_EnableIT_TXP
1905 * @param SPIx SPI Instance
1906 * @retval None
1907 */
LL_SPI_EnableIT_TXP(SPI_TypeDef * SPIx)1908 __STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx)
1909 {
1910 SET_BIT(SPIx->IER, SPI_IER_TXPIE);
1911 }
1912
1913 /**
1914 * @brief Enable Duplex Packet available IT
1915 * @rmtoll IER DXPIE LL_SPI_EnableIT_DXP
1916 * @param SPIx SPI Instance
1917 * @retval None
1918 */
LL_SPI_EnableIT_DXP(SPI_TypeDef * SPIx)1919 __STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx)
1920 {
1921 SET_BIT(SPIx->IER, SPI_IER_DXPIE);
1922 }
1923
1924 /**
1925 * @brief Enable End Of Transfer IT
1926 * @rmtoll IER EOTIE LL_SPI_EnableIT_EOT
1927 * @param SPIx SPI Instance
1928 * @retval None
1929 */
LL_SPI_EnableIT_EOT(SPI_TypeDef * SPIx)1930 __STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx)
1931 {
1932 SET_BIT(SPIx->IER, SPI_IER_EOTIE);
1933 }
1934
1935 /**
1936 * @brief Enable TXTF IT
1937 * @rmtoll IER TXTFIE LL_SPI_EnableIT_TXTF
1938 * @param SPIx SPI Instance
1939 * @retval None
1940 */
LL_SPI_EnableIT_TXTF(SPI_TypeDef * SPIx)1941 __STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx)
1942 {
1943 SET_BIT(SPIx->IER, SPI_IER_TXTFIE);
1944 }
1945
1946 /**
1947 * @brief Enable Underrun IT
1948 * @rmtoll IER UDRIE LL_SPI_EnableIT_UDR
1949 * @param SPIx SPI Instance
1950 * @retval None
1951 */
LL_SPI_EnableIT_UDR(SPI_TypeDef * SPIx)1952 __STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx)
1953 {
1954 SET_BIT(SPIx->IER, SPI_IER_UDRIE);
1955 }
1956
1957 /**
1958 * @brief Enable Overrun IT
1959 * @rmtoll IER OVRIE LL_SPI_EnableIT_OVR
1960 * @param SPIx SPI Instance
1961 * @retval None
1962 */
LL_SPI_EnableIT_OVR(SPI_TypeDef * SPIx)1963 __STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx)
1964 {
1965 SET_BIT(SPIx->IER, SPI_IER_OVRIE);
1966 }
1967
1968 /**
1969 * @brief Enable CRC Error IT
1970 * @rmtoll IER CRCEIE LL_SPI_EnableIT_CRCERR
1971 * @param SPIx SPI Instance
1972 * @retval None
1973 */
LL_SPI_EnableIT_CRCERR(SPI_TypeDef * SPIx)1974 __STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx)
1975 {
1976 SET_BIT(SPIx->IER, SPI_IER_CRCEIE);
1977 }
1978
1979 /**
1980 * @brief Enable TI Frame Format Error IT
1981 * @rmtoll IER TIFREIE LL_SPI_EnableIT_FRE
1982 * @param SPIx SPI Instance
1983 * @retval None
1984 */
LL_SPI_EnableIT_FRE(SPI_TypeDef * SPIx)1985 __STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx)
1986 {
1987 SET_BIT(SPIx->IER, SPI_IER_TIFREIE);
1988 }
1989
1990 /**
1991 * @brief Enable MODF IT
1992 * @rmtoll IER MODFIE LL_SPI_EnableIT_MODF
1993 * @param SPIx SPI Instance
1994 * @retval None
1995 */
LL_SPI_EnableIT_MODF(SPI_TypeDef * SPIx)1996 __STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx)
1997 {
1998 SET_BIT(SPIx->IER, SPI_IER_MODFIE);
1999 }
2000
2001 /**
2002 * @brief Disable Rx Packet available IT
2003 * @rmtoll IER RXPIE LL_SPI_DisableIT_RXP
2004 * @param SPIx SPI Instance
2005 * @retval None
2006 */
LL_SPI_DisableIT_RXP(SPI_TypeDef * SPIx)2007 __STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx)
2008 {
2009 CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE);
2010 }
2011
2012 /**
2013 * @brief Disable Tx Packet space available IT
2014 * @rmtoll IER TXPIE LL_SPI_DisableIT_TXP
2015 * @param SPIx SPI Instance
2016 * @retval None
2017 */
LL_SPI_DisableIT_TXP(SPI_TypeDef * SPIx)2018 __STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx)
2019 {
2020 CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE);
2021 }
2022
2023 /**
2024 * @brief Disable Duplex Packet available IT
2025 * @rmtoll IER DXPIE LL_SPI_DisableIT_DXP
2026 * @param SPIx SPI Instance
2027 * @retval None
2028 */
LL_SPI_DisableIT_DXP(SPI_TypeDef * SPIx)2029 __STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx)
2030 {
2031 CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE);
2032 }
2033
2034 /**
2035 * @brief Disable End Of Transfer IT
2036 * @rmtoll IER EOTIE LL_SPI_DisableIT_EOT
2037 * @param SPIx SPI Instance
2038 * @retval None
2039 */
LL_SPI_DisableIT_EOT(SPI_TypeDef * SPIx)2040 __STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx)
2041 {
2042 CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE);
2043 }
2044
2045 /**
2046 * @brief Disable TXTF IT
2047 * @rmtoll IER TXTFIE LL_SPI_DisableIT_TXTF
2048 * @param SPIx SPI Instance
2049 * @retval None
2050 */
LL_SPI_DisableIT_TXTF(SPI_TypeDef * SPIx)2051 __STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx)
2052 {
2053 CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE);
2054 }
2055
2056 /**
2057 * @brief Disable Underrun IT
2058 * @rmtoll IER UDRIE LL_SPI_DisableIT_UDR
2059 * @param SPIx SPI Instance
2060 * @retval None
2061 */
LL_SPI_DisableIT_UDR(SPI_TypeDef * SPIx)2062 __STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx)
2063 {
2064 CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE);
2065 }
2066
2067 /**
2068 * @brief Disable Overrun IT
2069 * @rmtoll IER OVRIE LL_SPI_DisableIT_OVR
2070 * @param SPIx SPI Instance
2071 * @retval None
2072 */
LL_SPI_DisableIT_OVR(SPI_TypeDef * SPIx)2073 __STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx)
2074 {
2075 CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE);
2076 }
2077
2078 /**
2079 * @brief Disable CRC Error IT
2080 * @rmtoll IER CRCEIE LL_SPI_DisableIT_CRCERR
2081 * @param SPIx SPI Instance
2082 * @retval None
2083 */
LL_SPI_DisableIT_CRCERR(SPI_TypeDef * SPIx)2084 __STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx)
2085 {
2086 CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE);
2087 }
2088
2089 /**
2090 * @brief Disable TI Frame Format Error IT
2091 * @rmtoll IER TIFREIE LL_SPI_DisableIT_FRE
2092 * @param SPIx SPI Instance
2093 * @retval None
2094 */
LL_SPI_DisableIT_FRE(SPI_TypeDef * SPIx)2095 __STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx)
2096 {
2097 CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE);
2098 }
2099
2100 /**
2101 * @brief Disable MODF IT
2102 * @rmtoll IER MODFIE LL_SPI_DisableIT_MODF
2103 * @param SPIx SPI Instance
2104 * @retval None
2105 */
LL_SPI_DisableIT_MODF(SPI_TypeDef * SPIx)2106 __STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx)
2107 {
2108 CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE);
2109 }
2110
2111 /**
2112 * @brief Check if Rx Packet available IT is enabled
2113 * @rmtoll IER RXPIE LL_SPI_IsEnabledIT_RXP
2114 * @param SPIx SPI Instance
2115 * @retval State of bit (1 or 0)
2116 */
LL_SPI_IsEnabledIT_RXP(SPI_TypeDef * SPIx)2117 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
2118 {
2119 return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL);
2120 }
2121
2122 /**
2123 * @brief Check if Tx Packet space available IT is enabled
2124 * @rmtoll IER TXPIE LL_SPI_IsEnabledIT_TXP
2125 * @param SPIx SPI Instance
2126 * @retval State of bit (1 or 0)
2127 */
LL_SPI_IsEnabledIT_TXP(SPI_TypeDef * SPIx)2128 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
2129 {
2130 return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL);
2131 }
2132
2133 /**
2134 * @brief Check if Duplex Packet available IT is enabled
2135 * @rmtoll IER DXPIE LL_SPI_IsEnabledIT_DXP
2136 * @param SPIx SPI Instance
2137 * @retval State of bit (1 or 0)
2138 */
LL_SPI_IsEnabledIT_DXP(SPI_TypeDef * SPIx)2139 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(SPI_TypeDef *SPIx)
2140 {
2141 return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL);
2142 }
2143
2144 /**
2145 * @brief Check if End Of Transfer IT is enabled
2146 * @rmtoll IER EOTIE LL_SPI_IsEnabledIT_EOT
2147 * @param SPIx SPI Instance
2148 * @retval State of bit (1 or 0)
2149 */
LL_SPI_IsEnabledIT_EOT(SPI_TypeDef * SPIx)2150 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(SPI_TypeDef *SPIx)
2151 {
2152 return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL);
2153 }
2154
2155 /**
2156 * @brief Check if TXTF IT is enabled
2157 * @rmtoll IER TXTFIE LL_SPI_IsEnabledIT_TXTF
2158 * @param SPIx SPI Instance
2159 * @retval State of bit (1 or 0)
2160 */
LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef * SPIx)2161 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef *SPIx)
2162 {
2163 return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL);
2164 }
2165
2166 /**
2167 * @brief Check if Underrun IT is enabled
2168 * @rmtoll IER UDRIE LL_SPI_IsEnabledIT_UDR
2169 * @param SPIx SPI Instance
2170 * @retval State of bit (1 or 0)
2171 */
LL_SPI_IsEnabledIT_UDR(SPI_TypeDef * SPIx)2172 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
2173 {
2174 return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL);
2175 }
2176
2177 /**
2178 * @brief Check if Overrun IT is enabled
2179 * @rmtoll IER OVRIE LL_SPI_IsEnabledIT_OVR
2180 * @param SPIx SPI Instance
2181 * @retval State of bit (1 or 0)
2182 */
LL_SPI_IsEnabledIT_OVR(SPI_TypeDef * SPIx)2183 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
2184 {
2185 return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL);
2186 }
2187
2188 /**
2189 * @brief Check if CRC Error IT is enabled
2190 * @rmtoll IER CRCEIE LL_SPI_IsEnabledIT_CRCERR
2191 * @param SPIx SPI Instance
2192 * @retval State of bit (1 or 0)
2193 */
LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef * SPIx)2194 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef *SPIx)
2195 {
2196 return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL);
2197 }
2198
2199 /**
2200 * @brief Check if TI Frame Format Error IT is enabled
2201 * @rmtoll IER TIFREIE LL_SPI_IsEnabledIT_FRE
2202 * @param SPIx SPI Instance
2203 * @retval State of bit (1 or 0)
2204 */
LL_SPI_IsEnabledIT_FRE(SPI_TypeDef * SPIx)2205 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
2206 {
2207 return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL);
2208 }
2209
2210 /**
2211 * @brief Check if MODF IT is enabled
2212 * @rmtoll IER MODFIE LL_SPI_IsEnabledIT_MODF
2213 * @param SPIx SPI Instance
2214 * @retval State of bit (1 or 0)
2215 */
LL_SPI_IsEnabledIT_MODF(SPI_TypeDef * SPIx)2216 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(SPI_TypeDef *SPIx)
2217 {
2218 return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL);
2219 }
2220
2221 /**
2222 * @}
2223 */
2224
2225 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
2226 * @{
2227 */
2228
2229 /**
2230 * @brief Enable DMA Rx
2231 * @rmtoll CFG1 RXDMAEN LL_SPI_EnableDMAReq_RX
2232 * @param SPIx SPI Instance
2233 * @retval None
2234 */
LL_SPI_EnableDMAReq_RX(SPI_TypeDef * SPIx)2235 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
2236 {
2237 SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
2238 }
2239
2240 /**
2241 * @brief Disable DMA Rx
2242 * @rmtoll CFG1 RXDMAEN LL_SPI_DisableDMAReq_RX
2243 * @param SPIx SPI Instance
2244 * @retval None
2245 */
LL_SPI_DisableDMAReq_RX(SPI_TypeDef * SPIx)2246 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
2247 {
2248 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
2249 }
2250
2251 /**
2252 * @brief Check if DMA Rx is enabled
2253 * @rmtoll CFG1 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
2254 * @param SPIx SPI Instance
2255 * @retval State of bit (1 or 0)
2256 */
LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef * SPIx)2257 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
2258 {
2259 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);
2260 }
2261
2262 /**
2263 * @brief Enable DMA Tx
2264 * @rmtoll CFG1 TXDMAEN LL_SPI_EnableDMAReq_TX
2265 * @param SPIx SPI Instance
2266 * @retval None
2267 */
LL_SPI_EnableDMAReq_TX(SPI_TypeDef * SPIx)2268 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
2269 {
2270 SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
2271 }
2272
2273 /**
2274 * @brief Disable DMA Tx
2275 * @rmtoll CFG1 TXDMAEN LL_SPI_DisableDMAReq_TX
2276 * @param SPIx SPI Instance
2277 * @retval None
2278 */
LL_SPI_DisableDMAReq_TX(SPI_TypeDef * SPIx)2279 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
2280 {
2281 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
2282 }
2283
2284 /**
2285 * @brief Check if DMA Tx is enabled
2286 * @rmtoll CFG1 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
2287 * @param SPIx SPI Instance
2288 * @retval State of bit (1 or 0)
2289 */
LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef * SPIx)2290 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
2291 {
2292 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);
2293 }
2294 /**
2295 * @brief Get the data register address used for DMA transfer
2296 * @rmtoll TXDR TXDR LL_SPI_DMA_GetTxRegAddr
2297 * @param SPIx SPI Instance
2298 * @retval Address of data register
2299 */
LL_SPI_DMA_GetTxRegAddr(SPI_TypeDef * SPIx)2300 __STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(SPI_TypeDef *SPIx)
2301 {
2302 return (uint32_t) &(SPIx->TXDR);
2303 }
2304
2305 /**
2306 * @brief Get the data register address used for DMA transfer
2307 * @rmtoll RXDR RXDR LL_SPI_DMA_GetRxRegAddr
2308 * @param SPIx SPI Instance
2309 * @retval Address of data register
2310 */
LL_SPI_DMA_GetRxRegAddr(SPI_TypeDef * SPIx)2311 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(SPI_TypeDef *SPIx)
2312 {
2313 return (uint32_t) &(SPIx->RXDR);
2314 }
2315 /**
2316 * @}
2317 */
2318
2319 /** @defgroup SPI_LL_EF_DATA_Management DATA_Management
2320 * @{
2321 */
2322
2323 /**
2324 * @brief Read Data Register
2325 * @rmtoll RXDR . LL_SPI_ReceiveData8
2326 * @param SPIx SPI Instance
2327 * @retval 0..0xFF
2328 */
LL_SPI_ReceiveData8(SPI_TypeDef * SPIx)2329 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
2330 {
2331 return (*((__IO uint8_t *)&SPIx->RXDR));
2332 }
2333
2334 /**
2335 * @brief Read Data Register
2336 * @rmtoll RXDR . LL_SPI_ReceiveData16
2337 * @param SPIx SPI Instance
2338 * @retval 0..0xFFFF
2339 */
LL_SPI_ReceiveData16(SPI_TypeDef * SPIx)2340 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
2341 {
2342 #if defined (__GNUC__)
2343 __IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR));
2344 return (*spirxdr);
2345 #else
2346 return (*((__IO uint16_t *)&SPIx->RXDR));
2347 #endif /* __GNUC__ */
2348 }
2349
2350 /**
2351 * @brief Read Data Register
2352 * @rmtoll RXDR . LL_SPI_ReceiveData32
2353 * @param SPIx SPI Instance
2354 * @retval 0..0xFFFFFFFF
2355 */
LL_SPI_ReceiveData32(SPI_TypeDef * SPIx)2356 __STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx)
2357 {
2358 return (*((__IO uint32_t *)&SPIx->RXDR));
2359 }
2360
2361 /**
2362 * @brief Write Data Register
2363 * @rmtoll TXDR . LL_SPI_TransmitData8
2364 * @param SPIx SPI Instance
2365 * @param TxData 0..0xFF
2366 * @retval None
2367 */
LL_SPI_TransmitData8(SPI_TypeDef * SPIx,uint8_t TxData)2368 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
2369 {
2370 *((__IO uint8_t *)&SPIx->TXDR) = TxData;
2371 }
2372
2373 /**
2374 * @brief Write Data Register
2375 * @rmtoll TXDR . LL_SPI_TransmitData16
2376 * @param SPIx SPI Instance
2377 * @param TxData 0..0xFFFF
2378 * @retval None
2379 */
LL_SPI_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)2380 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
2381 {
2382 #if defined (__GNUC__)
2383 __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR);
2384 *spitxdr = TxData;
2385 #else
2386 *((__IO uint16_t *)&SPIx->TXDR) = TxData;
2387 #endif /* __GNUC__ */
2388 }
2389
2390 /**
2391 * @brief Write Data Register
2392 * @rmtoll TXDR . LL_SPI_TransmitData32
2393 * @param SPIx SPI Instance
2394 * @param TxData 0..0xFFFFFFFF
2395 * @retval None
2396 */
LL_SPI_TransmitData32(SPI_TypeDef * SPIx,uint32_t TxData)2397 __STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
2398 {
2399 *((__IO uint32_t *)&SPIx->TXDR) = TxData;
2400 }
2401
2402 /**
2403 * @brief Set polynomial for CRC calcul
2404 * @rmtoll CRCPOLY CRCPOLY LL_SPI_SetCRCPolynomial
2405 * @param SPIx SPI Instance
2406 * @param CRCPoly 0..0xFFFFFFFF
2407 * @retval None
2408 */
LL_SPI_SetCRCPolynomial(SPI_TypeDef * SPIx,uint32_t CRCPoly)2409 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
2410 {
2411 WRITE_REG(SPIx->CRCPOLY, CRCPoly);
2412 }
2413
2414 /**
2415 * @brief Get polynomial for CRC calcul
2416 * @rmtoll CRCPOLY CRCPOLY LL_SPI_GetCRCPolynomial
2417 * @param SPIx SPI Instance
2418 * @retval 0..0xFFFFFFFF
2419 */
LL_SPI_GetCRCPolynomial(SPI_TypeDef * SPIx)2420 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
2421 {
2422 return (uint32_t)(READ_REG(SPIx->CRCPOLY));
2423 }
2424
2425 /**
2426 * @brief Set the underrun pattern
2427 * @rmtoll UDRDR UDRDR LL_SPI_SetUDRPattern
2428 * @param SPIx SPI Instance
2429 * @param Pattern 0..0xFFFFFFFF
2430 * @retval None
2431 */
LL_SPI_SetUDRPattern(SPI_TypeDef * SPIx,uint32_t Pattern)2432 __STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern)
2433 {
2434 WRITE_REG(SPIx->UDRDR, Pattern);
2435 }
2436
2437 /**
2438 * @brief Get the underrun pattern
2439 * @rmtoll UDRDR UDRDR LL_SPI_GetUDRPattern
2440 * @param SPIx SPI Instance
2441 * @retval 0..0xFFFFFFFF
2442 */
LL_SPI_GetUDRPattern(SPI_TypeDef * SPIx)2443 __STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(SPI_TypeDef *SPIx)
2444 {
2445 return (uint32_t)(READ_REG(SPIx->UDRDR));
2446 }
2447
2448 /**
2449 * @brief Get Rx CRC
2450 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
2451 * @param SPIx SPI Instance
2452 * @retval 0..0xFFFFFFFF
2453 */
LL_SPI_GetRxCRC(SPI_TypeDef * SPIx)2454 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
2455 {
2456 return (uint32_t)(READ_REG(SPIx->RXCRC));
2457 }
2458
2459 /**
2460 * @brief Get Tx CRC
2461 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
2462 * @param SPIx SPI Instance
2463 * @retval 0..0xFFFFFFFF
2464 */
LL_SPI_GetTxCRC(SPI_TypeDef * SPIx)2465 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
2466 {
2467 return (uint32_t)(READ_REG(SPIx->TXCRC));
2468 }
2469
2470 /**
2471 * @}
2472 */
2473
2474 #if defined(USE_FULL_LL_DRIVER)
2475 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
2476 * @{
2477 */
2478
2479 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
2480 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
2481 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
2482
2483 /**
2484 * @}
2485 */
2486 #endif /* USE_FULL_LL_DRIVER */
2487 /**
2488 * @}
2489 */
2490
2491 /** @defgroup I2S_LL I2S
2492 * @{
2493 */
2494
2495 /* Private variables ---------------------------------------------------------*/
2496 /* Private constants ---------------------------------------------------------*/
2497 /* Private macros ------------------------------------------------------------*/
2498
2499 /* Exported types ------------------------------------------------------------*/
2500 #if defined(USE_FULL_LL_DRIVER)
2501 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
2502 * @{
2503 */
2504
2505 /**
2506 * @brief I2S Init structure definition
2507 */
2508
2509 typedef struct
2510 {
2511 uint32_t Mode; /*!< Specifies the I2S operating mode.
2512 This parameter can be a value of @ref I2S_LL_EC_MODE
2513
2514 This feature can be modified afterwards using unitary function
2515 @ref LL_I2S_SetTransferMode().*/
2516
2517 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
2518 This parameter can be a value of @ref I2S_LL_EC_STANDARD
2519
2520 This feature can be modified afterwards using unitary function
2521 @ref LL_I2S_SetStandard().*/
2522
2523
2524 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
2525 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
2526
2527 This feature can be modified afterwards using unitary function
2528 @ref LL_I2S_SetDataFormat().*/
2529
2530
2531 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
2532 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
2533
2534 This feature can be modified afterwards using unitary functions
2535 @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
2536
2537
2538 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
2539 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
2540
2541 Audio Frequency can be modified afterwards using Reference manual formulas
2542 to calculate Prescaler Linear, Parity and unitary functions
2543 @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity()
2544 to set it.*/
2545
2546
2547 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
2548 This parameter can be a value of @ref I2S_LL_EC_POLARITY
2549
2550 This feature can be modified afterwards using unitary function
2551 @ref LL_I2S_SetClockPolarity().*/
2552
2553 } LL_I2S_InitTypeDef;
2554
2555 /**
2556 * @}
2557 */
2558 #endif /*USE_FULL_LL_DRIVER*/
2559
2560 /* Exported constants --------------------------------------------------------*/
2561 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
2562 * @{
2563 */
2564
2565 /** @defgroup I2S_LL_EC_DATA_FORMAT Data Format
2566 * @{
2567 */
2568 #define LL_I2S_DATAFORMAT_16B (0x00000000UL)
2569 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
2570 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
2571 #define LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0 | SPI_I2SCFGR_DATFMT)
2572 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)
2573 /**
2574 * @}
2575 */
2576
2577 /** @defgroup I2S_LL_EC_CHANNEL_LENGTH_TYPE Type of Channel Length
2578 * @{
2579 */
2580 #define LL_I2S_SLAVE_VARIABLE_CH_LENGTH (0x00000000UL)
2581 #define LL_I2S_SLAVE_FIXED_CH_LENGTH (SPI_I2SCFGR_FIXCH)
2582 /**
2583 * @}
2584 */
2585
2586 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
2587 * @{
2588 */
2589 #define LL_I2S_POLARITY_LOW (0x00000000UL)
2590 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)
2591 /**
2592 * @}
2593 */
2594
2595 /** @defgroup I2S_LL_EC_STANDARD I2S Standard
2596 * @{
2597 */
2598 #define LL_I2S_STANDARD_PHILIPS (0x00000000UL)
2599 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
2600 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
2601 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
2602 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
2603 /**
2604 * @}
2605 */
2606
2607 /** @defgroup I2S_LL_EC_MODE Operation Mode
2608 * @{
2609 */
2610 #define LL_I2S_MODE_SLAVE_TX (0x00000000UL)
2611 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
2612 #define LL_I2S_MODE_SLAVE_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2)
2613 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
2614 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_1 | SPI_I2SCFGR_I2SCFG_0)
2615 #define LL_I2S_MODE_MASTER_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
2616 /**
2617 * @}
2618 */
2619
2620 /** @defgroup I2S_LL_EC_PRESCALER_PARITY Prescaler Factor
2621 * @{
2622 */
2623 #define LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL) /*!< Odd factor: Real divider value is = I2SDIV * 2 */
2624 #define LL_I2S_PRESCALER_PARITY_ODD (0x00000001UL) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
2625 /**
2626 * @}
2627 */
2628
2629 /** @defgroup I2S_LL_EC_FIFO_TH FIFO Threshold Level
2630 * @{
2631 */
2632 #define LL_I2S_FIFO_TH_01DATA (LL_SPI_FIFO_TH_01DATA)
2633 #define LL_I2S_FIFO_TH_02DATA (LL_SPI_FIFO_TH_02DATA)
2634 #define LL_I2S_FIFO_TH_03DATA (LL_SPI_FIFO_TH_03DATA)
2635 #define LL_I2S_FIFO_TH_04DATA (LL_SPI_FIFO_TH_04DATA)
2636 #define LL_I2S_FIFO_TH_05DATA (LL_SPI_FIFO_TH_05DATA)
2637 #define LL_I2S_FIFO_TH_06DATA (LL_SPI_FIFO_TH_06DATA)
2638 #define LL_I2S_FIFO_TH_07DATA (LL_SPI_FIFO_TH_07DATA)
2639 #define LL_I2S_FIFO_TH_08DATA (LL_SPI_FIFO_TH_08DATA)
2640 /**
2641 * @}
2642 */
2643
2644 /** @defgroup I2S_LL_EC_BIT_ORDER Transmission Bit Order
2645 * @{
2646 */
2647 #define LL_I2S_LSB_FIRST (LL_SPI_LSB_FIRST)
2648 #define LL_I2S_MSB_FIRST (LL_SPI_MSB_FIRST)
2649 /**
2650 * @}
2651 */
2652
2653 #if defined(USE_FULL_LL_DRIVER)
2654
2655 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
2656 * @{
2657 */
2658 #define LL_I2S_MCLK_OUTPUT_DISABLE (0x00000000UL)
2659 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)
2660 /**
2661 * @}
2662 */
2663
2664 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
2665 * @{
2666 */
2667
2668 #define LL_I2S_AUDIOFREQ_192K 192000UL /*!< Audio Frequency configuration 192000 Hz */
2669 #define LL_I2S_AUDIOFREQ_96K 96000UL /*!< Audio Frequency configuration 96000 Hz */
2670 #define LL_I2S_AUDIOFREQ_48K 48000UL /*!< Audio Frequency configuration 48000 Hz */
2671 #define LL_I2S_AUDIOFREQ_44K 44100UL /*!< Audio Frequency configuration 44100 Hz */
2672 #define LL_I2S_AUDIOFREQ_32K 32000UL /*!< Audio Frequency configuration 32000 Hz */
2673 #define LL_I2S_AUDIOFREQ_22K 22050UL /*!< Audio Frequency configuration 22050 Hz */
2674 #define LL_I2S_AUDIOFREQ_16K 16000UL /*!< Audio Frequency configuration 16000 Hz */
2675 #define LL_I2S_AUDIOFREQ_11K 11025UL /*!< Audio Frequency configuration 11025 Hz */
2676 #define LL_I2S_AUDIOFREQ_8K 8000UL /*!< Audio Frequency configuration 8000 Hz */
2677 #define LL_I2S_AUDIOFREQ_DEFAULT 0UL /*!< Audio Freq not specified. Register I2SDIV = 0 */
2678 /**
2679 * @}
2680 */
2681 #endif /* USE_FULL_LL_DRIVER */
2682
2683 /**
2684 * @}
2685 */
2686
2687 /* Exported macro ------------------------------------------------------------*/
2688 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
2689 * @{
2690 */
2691
2692 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
2693 * @{
2694 */
2695
2696 /**
2697 * @brief Write a value in I2S register
2698 * @param __INSTANCE__ I2S Instance
2699 * @param __REG__ Register to be written
2700 * @param __VALUE__ Value to be written in the register
2701 * @retval None
2702 */
2703 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
2704
2705 /**
2706 * @brief Read a value in I2S register
2707 * @param __INSTANCE__ I2S Instance
2708 * @param __REG__ Register to be read
2709 * @retval Register value
2710 */
2711 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
2712 /**
2713 * @}
2714 */
2715
2716 /**
2717 * @}
2718 */
2719
2720
2721 /* Exported functions --------------------------------------------------------*/
2722
2723 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
2724 * @{
2725 */
2726
2727 /** @defgroup I2S_LL_EF_Configuration Configuration
2728 * @{
2729 */
2730
2731 /**
2732 * @brief Set I2S Data frame format
2733 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
2734 * I2SCFGR CHLEN LL_I2S_SetDataFormat\n
2735 * I2SCFGR DATFMT LL_I2S_SetDataFormat
2736 * @param SPIx SPI Handle
2737 * @param DataLength This parameter can be one of the following values:
2738 * @arg @ref LL_I2S_DATAFORMAT_16B
2739 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
2740 * @arg @ref LL_I2S_DATAFORMAT_24B
2741 * @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
2742 * @arg @ref LL_I2S_DATAFORMAT_32B
2743 * @retval None
2744 */
LL_I2S_SetDataFormat(SPI_TypeDef * SPIx,uint32_t DataLength)2745 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataLength)
2746 {
2747 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT, DataLength);
2748 }
2749
2750 /**
2751 * @brief Get I2S Data frame format
2752 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
2753 * I2SCFGR CHLEN LL_I2S_GetDataFormat\n
2754 * I2SCFGR DATFMT LL_I2S_GetDataFormat
2755 * @param SPIx SPI Handle
2756 * @retval Return value can be one of the following values:
2757 * @arg @ref LL_I2S_DATAFORMAT_16B
2758 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
2759 * @arg @ref LL_I2S_DATAFORMAT_24B
2760 * @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
2761 * @arg @ref LL_I2S_DATAFORMAT_32B
2762 */
LL_I2S_GetDataFormat(SPI_TypeDef * SPIx)2763 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
2764 {
2765 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT));
2766 }
2767
2768 /**
2769 * @brief Set I2S Channel Length Type
2770 * @note This feature is useful with SLAVE only
2771 * @rmtoll I2SCFGR FIXCH LL_I2S_SetChannelLengthType
2772 * @param SPIx SPI Handle
2773 * @param ChannelLengthType This parameter can be one of the following values:
2774 * @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
2775 * @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
2776 * @retval None
2777 */
LL_I2S_SetChannelLengthType(SPI_TypeDef * SPIx,uint32_t ChannelLengthType)2778 __STATIC_INLINE void LL_I2S_SetChannelLengthType(SPI_TypeDef *SPIx, uint32_t ChannelLengthType)
2779 {
2780 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH, ChannelLengthType);
2781 }
2782
2783 /**
2784 * @brief Get I2S Channel Length Type
2785 * @note This feature is useful with SLAVE only
2786 * @rmtoll I2SCFGR FIXCH LL_I2S_GetChannelLengthType
2787 * @param SPIx SPI Handle
2788 * @retval Return value can be one of the following values:
2789 * @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
2790 * @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
2791 */
LL_I2S_GetChannelLengthType(SPI_TypeDef * SPIx)2792 __STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType(SPI_TypeDef *SPIx)
2793 {
2794 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH));
2795 }
2796
2797 /**
2798 * @brief Invert the default polarity of WS signal
2799 * @rmtoll I2SCFGR WSINV LL_I2S_EnableWordSelectInversion
2800 * @param SPIx SPI Handle
2801 * @retval None
2802 */
LL_I2S_EnableWordSelectInversion(SPI_TypeDef * SPIx)2803 __STATIC_INLINE void LL_I2S_EnableWordSelectInversion(SPI_TypeDef *SPIx)
2804 {
2805 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);
2806 }
2807
2808 /**
2809 * @brief Use the default polarity of WS signal
2810 * @rmtoll I2SCFGR WSINV LL_I2S_DisableWordSelectInversion
2811 * @param SPIx SPI Handle
2812 * @retval None
2813 */
LL_I2S_DisableWordSelectInversion(SPI_TypeDef * SPIx)2814 __STATIC_INLINE void LL_I2S_DisableWordSelectInversion(SPI_TypeDef *SPIx)
2815 {
2816 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);
2817 }
2818
2819 /**
2820 * @brief Check if polarity of WS signal is inverted
2821 * @rmtoll I2SCFGR WSINV LL_I2S_IsEnabledWordSelectInversion
2822 * @param SPIx SPI Handle
2823 * @retval State of bit (1 or 0)
2824 */
LL_I2S_IsEnabledWordSelectInversion(SPI_TypeDef * SPIx)2825 __STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(SPI_TypeDef *SPIx)
2826 {
2827 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV) == (SPI_I2SCFGR_WSINV)) ? 1UL : 0UL);
2828 }
2829
2830 /**
2831 * @brief Set 2S Clock Polarity
2832 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
2833 * @param SPIx SPI Handle
2834 * @param ClockPolarity This parameter can be one of the following values:
2835 * @arg @ref LL_I2S_POLARITY_LOW
2836 * @arg @ref LL_I2S_POLARITY_HIGH
2837 * @retval None
2838 */
LL_I2S_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)2839 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
2840 {
2841 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL, ClockPolarity);
2842 }
2843
2844 /**
2845 * @brief Get 2S Clock Polarity
2846 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
2847 * @param SPIx SPI Handle
2848 * @retval Return value can be one of the following values:
2849 * @arg @ref LL_I2S_POLARITY_LOW
2850 * @arg @ref LL_I2S_POLARITY_HIGH
2851 */
LL_I2S_GetClockPolarity(SPI_TypeDef * SPIx)2852 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
2853 {
2854 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
2855 }
2856
2857 /**
2858 * @brief Set I2S standard
2859 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
2860 * I2SCFGR PCMSYNC LL_I2S_SetStandard
2861 * @param SPIx SPI Handle
2862 * @param Standard This parameter can be one of the following values:
2863 * @arg @ref LL_I2S_STANDARD_PHILIPS
2864 * @arg @ref LL_I2S_STANDARD_MSB
2865 * @arg @ref LL_I2S_STANDARD_LSB
2866 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
2867 * @arg @ref LL_I2S_STANDARD_PCM_LONG
2868 * @retval None
2869 */
LL_I2S_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)2870 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
2871 {
2872 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
2873 }
2874
2875 /**
2876 * @brief Get I2S standard
2877 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
2878 * I2SCFGR PCMSYNC LL_I2S_GetStandard
2879 * @param SPIx SPI Handle
2880 * @retval Return value can be one of the following values:
2881 * @arg @ref LL_I2S_STANDARD_PHILIPS
2882 * @arg @ref LL_I2S_STANDARD_MSB
2883 * @arg @ref LL_I2S_STANDARD_LSB
2884 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
2885 * @arg @ref LL_I2S_STANDARD_PCM_LONG
2886 */
LL_I2S_GetStandard(SPI_TypeDef * SPIx)2887 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
2888 {
2889 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
2890 }
2891
2892 /**
2893 * @brief Set I2S config
2894 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
2895 * @param SPIx SPI Handle
2896 * @param Standard This parameter can be one of the following values:
2897 * @arg @ref LL_I2S_MODE_SLAVE_TX
2898 * @arg @ref LL_I2S_MODE_SLAVE_RX
2899 * @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX
2900 * @arg @ref LL_I2S_MODE_MASTER_TX
2901 * @arg @ref LL_I2S_MODE_MASTER_RX
2902 * @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
2903 * @retval None
2904 */
LL_I2S_SetTransferMode(SPI_TypeDef * SPIx,uint32_t Standard)2905 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Standard)
2906 {
2907 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Standard);
2908 }
2909
2910 /**
2911 * @brief Get I2S config
2912 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
2913 * @param SPIx SPI Handle
2914 * @retval Return value can be one of the following values:
2915 * @arg @ref LL_I2S_MODE_SLAVE_TX
2916 * @arg @ref LL_I2S_MODE_SLAVE_RX
2917 * @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX
2918 * @arg @ref LL_I2S_MODE_MASTER_TX
2919 * @arg @ref LL_I2S_MODE_MASTER_RX
2920 * @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
2921 */
LL_I2S_GetTransferMode(SPI_TypeDef * SPIx)2922 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
2923 {
2924 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
2925 }
2926
2927 /**
2928 * @brief Select I2S mode and Enable I2S peripheral
2929 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
2930 * CR1 SPE LL_I2S_Enable
2931 * @param SPIx SPI Handle
2932 * @retval None
2933 */
LL_I2S_Enable(SPI_TypeDef * SPIx)2934 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
2935 {
2936 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
2937 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
2938 }
2939
2940 /**
2941 * @brief Disable I2S peripheral and disable I2S mode
2942 * @rmtoll CR1 SPE LL_I2S_Disable\n
2943 * I2SCFGR I2SMOD LL_I2S_Disable
2944 * @param SPIx SPI Handle
2945 * @retval None
2946 */
LL_I2S_Disable(SPI_TypeDef * SPIx)2947 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
2948 {
2949 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
2950 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
2951 }
2952
2953 /**
2954 * @brief Swap the SDO and SDI pin
2955 * @note This configuration can not be changed when I2S is enabled.
2956 * @rmtoll CFG2 IOSWP LL_I2S_EnableIOSwap
2957 * @param SPIx SPI Instance
2958 * @retval None
2959 */
LL_I2S_EnableIOSwap(SPI_TypeDef * SPIx)2960 __STATIC_INLINE void LL_I2S_EnableIOSwap(SPI_TypeDef *SPIx)
2961 {
2962 LL_SPI_EnableIOSwap(SPIx);
2963 }
2964
2965 /**
2966 * @brief Restore default function for SDO and SDI pin
2967 * @note This configuration can not be changed when I2S is enabled.
2968 * @rmtoll CFG2 IOSWP LL_I2S_DisableIOSwap
2969 * @param SPIx SPI Instance
2970 * @retval None
2971 */
LL_I2S_DisableIOSwap(SPI_TypeDef * SPIx)2972 __STATIC_INLINE void LL_I2S_DisableIOSwap(SPI_TypeDef *SPIx)
2973 {
2974 LL_SPI_DisableIOSwap(SPIx);
2975 }
2976
2977 /**
2978 * @brief Check if SDO and SDI pin are swapped
2979 * @rmtoll CFG2 IOSWP LL_I2S_IsEnabledIOSwap
2980 * @param SPIx SPI Instance
2981 * @retval State of bit (1 or 0)
2982 */
LL_I2S_IsEnabledIOSwap(SPI_TypeDef * SPIx)2983 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(SPI_TypeDef *SPIx)
2984 {
2985 return LL_SPI_IsEnabledIOSwap(SPIx);
2986 }
2987
2988 /**
2989 * @brief Enable GPIO control
2990 * @note This configuration can not be changed when I2S is enabled.
2991 * @rmtoll CFG2 AFCNTR LL_I2S_EnableGPIOControl
2992 * @param SPIx SPI Instance
2993 * @retval None
2994 */
LL_I2S_EnableGPIOControl(SPI_TypeDef * SPIx)2995 __STATIC_INLINE void LL_I2S_EnableGPIOControl(SPI_TypeDef *SPIx)
2996 {
2997 LL_SPI_EnableGPIOControl(SPIx);
2998 }
2999
3000 /**
3001 * @brief Disable GPIO control
3002 * @note This configuration can not be changed when I2S is enabled.
3003 * @rmtoll CFG2 AFCNTR LL_I2S_DisableGPIOControl
3004 * @param SPIx SPI Instance
3005 * @retval None
3006 */
LL_I2S_DisableGPIOControl(SPI_TypeDef * SPIx)3007 __STATIC_INLINE void LL_I2S_DisableGPIOControl(SPI_TypeDef *SPIx)
3008 {
3009 LL_SPI_DisableGPIOControl(SPIx);
3010 }
3011
3012 /**
3013 * @brief Check if GPIO control is active
3014 * @rmtoll CFG2 AFCNTR LL_I2S_IsEnabledGPIOControl
3015 * @param SPIx SPI Instance
3016 * @retval State of bit (1 or 0)
3017 */
LL_I2S_IsEnabledGPIOControl(SPI_TypeDef * SPIx)3018 __STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
3019 {
3020 return LL_SPI_IsEnabledGPIOControl(SPIx);
3021 }
3022
3023 /**
3024 * @brief Lock the AF configuration of associated IOs
3025 * @note Once this bit is set, the SPI_CFG2 register content can not be modified until a hardware reset occurs.
3026 * The reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
3027 * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock
3028 * @param SPIx SPI Instance
3029 * @retval None
3030 */
LL_I2S_EnableIOLock(SPI_TypeDef * SPIx)3031 __STATIC_INLINE void LL_I2S_EnableIOLock(SPI_TypeDef *SPIx)
3032 {
3033 LL_SPI_EnableIOLock(SPIx);
3034 }
3035
3036 /**
3037 * @brief Check if the the SPI_CFG2 register is locked
3038 * @rmtoll CR1 IOLOCK LL_I2S_IsEnabledIOLock
3039 * @param SPIx SPI Instance
3040 * @retval State of bit (1 or 0)
3041 */
LL_I2S_IsEnabledIOLock(SPI_TypeDef * SPIx)3042 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(SPI_TypeDef *SPIx)
3043 {
3044 return LL_SPI_IsEnabledIOLock(SPIx);
3045 }
3046
3047 /**
3048 * @brief Set Transfer Bit Order
3049 * @note This configuration can not be changed when I2S is enabled.
3050 * @rmtoll CFG2 LSBFRST LL_I2S_SetTransferBitOrder
3051 * @param SPIx SPI Instance
3052 * @param BitOrder This parameter can be one of the following values:
3053 * @arg @ref LL_I2S_LSB_FIRST
3054 * @arg @ref LL_I2S_MSB_FIRST
3055 * @retval None
3056 */
LL_I2S_SetTransferBitOrder(SPI_TypeDef * SPIx,uint32_t BitOrder)3057 __STATIC_INLINE void LL_I2S_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
3058 {
3059 LL_SPI_SetTransferBitOrder(SPIx, BitOrder);
3060 }
3061 /**
3062 * @brief Get Transfer Bit Order
3063 * @rmtoll CFG2 LSBFRST LL_I2S_GetTransferBitOrder
3064 * @param SPIx SPI Instance
3065 * @retval Returned value can be one of the following values:
3066 * @arg @ref LL_I2S_LSB_FIRST
3067 * @arg @ref LL_I2S_MSB_FIRST
3068 */
LL_I2S_GetTransferBitOrder(SPI_TypeDef * SPIx)3069 __STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(SPI_TypeDef *SPIx)
3070 {
3071 return LL_SPI_GetTransferBitOrder(SPIx);
3072 }
3073
3074 /**
3075 * @brief Start effective transfer on wire
3076 * @rmtoll CR1 CSTART LL_I2S_StartTransfer
3077 * @param SPIx SPI Instance
3078 * @retval None
3079 */
LL_I2S_StartTransfer(SPI_TypeDef * SPIx)3080 __STATIC_INLINE void LL_I2S_StartTransfer(SPI_TypeDef *SPIx)
3081 {
3082 LL_SPI_StartMasterTransfer(SPIx);
3083 }
3084
3085 /**
3086 * @brief Check if there is an unfinished transfer
3087 * @rmtoll CR1 CSTART LL_I2S_IsTransferActive
3088 * @param SPIx SPI Instance
3089 * @retval State of bit (1 or 0)
3090 */
LL_I2S_IsActiveTransfer(SPI_TypeDef * SPIx)3091 __STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(SPI_TypeDef *SPIx)
3092 {
3093 return LL_SPI_IsActiveMasterTransfer(SPIx);
3094 }
3095
3096 /**
3097 * @brief Set threshold of FIFO that triggers a transfer event
3098 * @note This configuration can not be changed when I2S is enabled.
3099 * @rmtoll CFG1 FTHLV LL_I2S_SetFIFOThreshold
3100 * @param SPIx SPI Instance
3101 * @param Threshold This parameter can be one of the following values:
3102 * @arg @ref LL_I2S_FIFO_TH_01DATA
3103 * @arg @ref LL_I2S_FIFO_TH_02DATA
3104 * @arg @ref LL_I2S_FIFO_TH_03DATA
3105 * @arg @ref LL_I2S_FIFO_TH_04DATA
3106 * @arg @ref LL_I2S_FIFO_TH_05DATA
3107 * @arg @ref LL_I2S_FIFO_TH_06DATA
3108 * @arg @ref LL_I2S_FIFO_TH_07DATA
3109 * @arg @ref LL_I2S_FIFO_TH_08DATA
3110 * @retval None
3111 */
LL_I2S_SetFIFOThreshold(SPI_TypeDef * SPIx,uint32_t Threshold)3112 __STATIC_INLINE void LL_I2S_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
3113 {
3114 LL_SPI_SetFIFOThreshold(SPIx, Threshold);
3115 }
3116
3117 /**
3118 * @brief Get threshold of FIFO that triggers a transfer event
3119 * @rmtoll CFG1 FTHLV LL_I2S_GetFIFOThreshold
3120 * @param SPIx SPI Instance
3121 * @retval Returned value can be one of the following values:
3122 * @arg @ref LL_I2S_FIFO_TH_01DATA
3123 * @arg @ref LL_I2S_FIFO_TH_02DATA
3124 * @arg @ref LL_I2S_FIFO_TH_03DATA
3125 * @arg @ref LL_I2S_FIFO_TH_04DATA
3126 * @arg @ref LL_I2S_FIFO_TH_05DATA
3127 * @arg @ref LL_I2S_FIFO_TH_06DATA
3128 * @arg @ref LL_I2S_FIFO_TH_07DATA
3129 * @arg @ref LL_I2S_FIFO_TH_08DATA
3130 */
LL_I2S_GetFIFOThreshold(SPI_TypeDef * SPIx)3131 __STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(SPI_TypeDef *SPIx)
3132 {
3133 return LL_SPI_GetFIFOThreshold(SPIx);
3134 }
3135
3136 /**
3137 * @brief Set I2S linear prescaler
3138 * @rmtoll I2SCFGR I2SDIV LL_I2S_SetPrescalerLinear
3139 * @param SPIx SPI Instance
3140 * @param PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
3141 * @note PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
3142 * @retval None
3143 */
LL_I2S_SetPrescalerLinear(SPI_TypeDef * SPIx,uint32_t PrescalerLinear)3144 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint32_t PrescalerLinear)
3145 {
3146 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos));
3147 }
3148
3149 /**
3150 * @brief Get I2S linear prescaler
3151 * @rmtoll I2SCFGR I2SDIV LL_I2S_GetPrescalerLinear
3152 * @param SPIx SPI Instance
3153 * @retval PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
3154 */
LL_I2S_GetPrescalerLinear(SPI_TypeDef * SPIx)3155 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
3156 {
3157 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV) >> SPI_I2SCFGR_I2SDIV_Pos);
3158 }
3159
3160 /**
3161 * @brief Set I2S parity prescaler
3162 * @rmtoll I2SCFGR ODD LL_I2S_SetPrescalerParity
3163 * @param SPIx SPI Instance
3164 * @param PrescalerParity This parameter can be one of the following values:
3165 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
3166 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
3167 * @retval None
3168 */
LL_I2S_SetPrescalerParity(SPI_TypeDef * SPIx,uint32_t PrescalerParity)3169 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
3170 {
3171 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_ODD, PrescalerParity << SPI_I2SCFGR_ODD_Pos);
3172 }
3173
3174 /**
3175 * @brief Get I2S parity prescaler
3176 * @rmtoll I2SCFGR ODD LL_I2S_GetPrescalerParity
3177 * @param SPIx SPI Instance
3178 * @retval Returned value can be one of the following values:
3179 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
3180 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
3181 */
LL_I2S_GetPrescalerParity(SPI_TypeDef * SPIx)3182 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
3183 {
3184 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ODD) >> SPI_I2SCFGR_ODD_Pos);
3185 }
3186
3187 /**
3188 * @brief Enable the Master Clock Output (Pin MCK)
3189 * @rmtoll I2SCFGR MCKOE LL_I2S_EnableMasterClock
3190 * @param SPIx SPI Handle
3191 * @retval None
3192 */
LL_I2S_EnableMasterClock(SPI_TypeDef * SPIx)3193 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
3194 {
3195 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);
3196 }
3197
3198 /**
3199 * @brief Disable the Master Clock Output (Pin MCK)
3200 * @rmtoll I2SCFGR MCKOE LL_I2S_DisableMasterClock
3201 * @param SPIx SPI Handle
3202 * @retval None
3203 */
LL_I2S_DisableMasterClock(SPI_TypeDef * SPIx)3204 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
3205 {
3206 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);
3207 }
3208
3209 /**
3210 * @brief Check if the master clock output (Pin MCK) is enabled
3211 * @rmtoll I2SCFGR MCKOE LL_I2S_IsEnabledMasterClock
3212 * @param SPIx SPI Instance
3213 * @retval State of bit (1 or 0)
3214 */
LL_I2S_IsEnabledMasterClock(SPI_TypeDef * SPIx)3215 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
3216 {
3217 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE) == (SPI_I2SCFGR_MCKOE)) ? 1UL : 0UL);
3218 }
3219
3220 /**
3221 * @}
3222 */
3223
3224
3225 /** @defgroup I2S_LL_EF_FLAG_Management FLAG_Management
3226 * @{
3227 */
3228
3229 /**
3230 * @brief Check if there enough data in FIFO to read a full packet
3231 * @rmtoll SR RXP LL_I2S_IsActiveFlag_RXP
3232 * @param SPIx SPI Instance
3233 * @retval State of bit (1 or 0)
3234 */
LL_I2S_IsActiveFlag_RXP(SPI_TypeDef * SPIx)3235 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
3236 {
3237 return LL_SPI_IsActiveFlag_RXP(SPIx);
3238 }
3239
3240 /**
3241 * @brief Check if there enough space in FIFO to hold a full packet
3242 * @rmtoll SR TXP LL_I2S_IsActiveFlag_TXP
3243 * @param SPIx SPI Instance
3244 * @retval State of bit (1 or 0)
3245 */
LL_I2S_IsActiveFlag_TXP(SPI_TypeDef * SPIx)3246 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
3247 {
3248 return LL_SPI_IsActiveFlag_TXP(SPIx);
3249 }
3250
3251 /**
3252 * @brief Get Underrun error flag
3253 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
3254 * @param SPIx SPI Instance
3255 * @retval State of bit (1 or 0)
3256 */
LL_I2S_IsActiveFlag_UDR(SPI_TypeDef * SPIx)3257 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
3258 {
3259 return LL_SPI_IsActiveFlag_UDR(SPIx);
3260 }
3261
3262 /**
3263 * @brief Get Overrun error flag
3264 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
3265 * @param SPIx SPI Instance
3266 * @retval State of bit (1 or 0).
3267 */
LL_I2S_IsActiveFlag_OVR(SPI_TypeDef * SPIx)3268 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
3269 {
3270 return LL_SPI_IsActiveFlag_OVR(SPIx);
3271 }
3272
3273 /**
3274 * @brief Get TI Frame format error flag
3275 * @rmtoll SR TIFRE LL_I2S_IsActiveFlag_FRE
3276 * @param SPIx SPI Instance
3277 * @retval State of bit (1 or 0).
3278 */
LL_I2S_IsActiveFlag_FRE(SPI_TypeDef * SPIx)3279 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
3280 {
3281 return LL_SPI_IsActiveFlag_FRE(SPIx);
3282 }
3283
3284 /**
3285 * @brief Clear Underrun error flag
3286 * @rmtoll IFCR UDRC LL_I2S_ClearFlag_UDR
3287 * @param SPIx SPI Instance
3288 * @retval None
3289 */
LL_I2S_ClearFlag_UDR(SPI_TypeDef * SPIx)3290 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
3291 {
3292 LL_SPI_ClearFlag_UDR(SPIx);
3293 }
3294
3295 /**
3296 * @brief Clear Overrun error flag
3297 * @rmtoll IFCR OVRC LL_I2S_ClearFlag_OVR
3298 * @param SPIx SPI Instance
3299 * @retval None
3300 */
LL_I2S_ClearFlag_OVR(SPI_TypeDef * SPIx)3301 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
3302 {
3303 LL_SPI_ClearFlag_OVR(SPIx);
3304 }
3305
3306 /**
3307 * @brief Clear Frame format error flag
3308 * @rmtoll IFCR TIFREC LL_I2S_ClearFlag_FRE
3309 * @param SPIx SPI Instance
3310 * @retval None
3311 */
LL_I2S_ClearFlag_FRE(SPI_TypeDef * SPIx)3312 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
3313 {
3314 LL_SPI_ClearFlag_FRE(SPIx);
3315 }
3316
3317 /**
3318 * @}
3319 */
3320
3321 /** @defgroup I2S_LL_EF_IT_Management IT_Management
3322 * @{
3323 */
3324
3325 /**
3326 * @brief Enable Rx Packet available IT
3327 * @rmtoll IER RXPIE LL_I2S_EnableIT_RXP
3328 * @param SPIx SPI Instance
3329 * @retval None
3330 */
LL_I2S_EnableIT_RXP(SPI_TypeDef * SPIx)3331 __STATIC_INLINE void LL_I2S_EnableIT_RXP(SPI_TypeDef *SPIx)
3332 {
3333 LL_SPI_EnableIT_RXP(SPIx);
3334 }
3335
3336 /**
3337 * @brief Enable Tx Packet space available IT
3338 * @rmtoll IER TXPIE LL_I2S_EnableIT_TXP
3339 * @param SPIx SPI Instance
3340 * @retval None
3341 */
LL_I2S_EnableIT_TXP(SPI_TypeDef * SPIx)3342 __STATIC_INLINE void LL_I2S_EnableIT_TXP(SPI_TypeDef *SPIx)
3343 {
3344 LL_SPI_EnableIT_TXP(SPIx);
3345 }
3346
3347 /**
3348 * @brief Enable Underrun IT
3349 * @rmtoll IER UDRIE LL_I2S_EnableIT_UDR
3350 * @param SPIx SPI Instance
3351 * @retval None
3352 */
LL_I2S_EnableIT_UDR(SPI_TypeDef * SPIx)3353 __STATIC_INLINE void LL_I2S_EnableIT_UDR(SPI_TypeDef *SPIx)
3354 {
3355 LL_SPI_EnableIT_UDR(SPIx);
3356 }
3357
3358 /**
3359 * @brief Enable Overrun IT
3360 * @rmtoll IER OVRIE LL_I2S_EnableIT_OVR
3361 * @param SPIx SPI Instance
3362 * @retval None
3363 */
LL_I2S_EnableIT_OVR(SPI_TypeDef * SPIx)3364 __STATIC_INLINE void LL_I2S_EnableIT_OVR(SPI_TypeDef *SPIx)
3365 {
3366 LL_SPI_EnableIT_OVR(SPIx);
3367 }
3368
3369 /**
3370 * @brief Enable TI Frame Format Error IT
3371 * @rmtoll IER TIFREIE LL_I2S_EnableIT_FRE
3372 * @param SPIx SPI Instance
3373 * @retval None
3374 */
LL_I2S_EnableIT_FRE(SPI_TypeDef * SPIx)3375 __STATIC_INLINE void LL_I2S_EnableIT_FRE(SPI_TypeDef *SPIx)
3376 {
3377 LL_SPI_EnableIT_FRE(SPIx);
3378 }
3379
3380 /**
3381 * @brief Disable Rx Packet available IT
3382 * @rmtoll IER RXPIE LL_I2S_DisableIT_RXP
3383 * @param SPIx SPI Instance
3384 * @retval None
3385 */
LL_I2S_DisableIT_RXP(SPI_TypeDef * SPIx)3386 __STATIC_INLINE void LL_I2S_DisableIT_RXP(SPI_TypeDef *SPIx)
3387 {
3388 LL_SPI_DisableIT_RXP(SPIx);
3389 }
3390
3391 /**
3392 * @brief Disable Tx Packet space available IT
3393 * @rmtoll IER TXPIE LL_I2S_DisableIT_TXP
3394 * @param SPIx SPI Instance
3395 * @retval None
3396 */
LL_I2S_DisableIT_TXP(SPI_TypeDef * SPIx)3397 __STATIC_INLINE void LL_I2S_DisableIT_TXP(SPI_TypeDef *SPIx)
3398 {
3399 LL_SPI_DisableIT_TXP(SPIx);
3400 }
3401
3402 /**
3403 * @brief Disable Underrun IT
3404 * @rmtoll IER UDRIE LL_I2S_DisableIT_UDR
3405 * @param SPIx SPI Instance
3406 * @retval None
3407 */
LL_I2S_DisableIT_UDR(SPI_TypeDef * SPIx)3408 __STATIC_INLINE void LL_I2S_DisableIT_UDR(SPI_TypeDef *SPIx)
3409 {
3410 LL_SPI_DisableIT_UDR(SPIx);
3411 }
3412
3413 /**
3414 * @brief Disable Overrun IT
3415 * @rmtoll IER OVRIE LL_I2S_DisableIT_OVR
3416 * @param SPIx SPI Instance
3417 * @retval None
3418 */
LL_I2S_DisableIT_OVR(SPI_TypeDef * SPIx)3419 __STATIC_INLINE void LL_I2S_DisableIT_OVR(SPI_TypeDef *SPIx)
3420 {
3421 LL_SPI_DisableIT_OVR(SPIx);
3422 }
3423
3424 /**
3425 * @brief Disable TI Frame Format Error IT
3426 * @rmtoll IER TIFREIE LL_I2S_DisableIT_FRE
3427 * @param SPIx SPI Instance
3428 * @retval None
3429 */
LL_I2S_DisableIT_FRE(SPI_TypeDef * SPIx)3430 __STATIC_INLINE void LL_I2S_DisableIT_FRE(SPI_TypeDef *SPIx)
3431 {
3432 LL_SPI_DisableIT_FRE(SPIx);
3433 }
3434
3435 /**
3436 * @brief Check if Rx Packet available IT is enabled
3437 * @rmtoll IER RXPIE LL_I2S_IsEnabledIT_RXP
3438 * @param SPIx SPI Instance
3439 * @retval State of bit (1 or 0)
3440 */
LL_I2S_IsEnabledIT_RXP(SPI_TypeDef * SPIx)3441 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
3442 {
3443 return LL_SPI_IsEnabledIT_RXP(SPIx);
3444 }
3445
3446 /**
3447 * @brief Check if Tx Packet space available IT is enabled
3448 * @rmtoll IER TXPIE LL_I2S_IsEnabledIT_TXP
3449 * @param SPIx SPI Instance
3450 * @retval State of bit (1 or 0)
3451 */
LL_I2S_IsEnabledIT_TXP(SPI_TypeDef * SPIx)3452 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
3453 {
3454 return LL_SPI_IsEnabledIT_TXP(SPIx);
3455 }
3456
3457 /**
3458 * @brief Check if Underrun IT is enabled
3459 * @rmtoll IER UDRIE LL_I2S_IsEnabledIT_UDR
3460 * @param SPIx SPI Instance
3461 * @retval State of bit (1 or 0)
3462 */
LL_I2S_IsEnabledIT_UDR(SPI_TypeDef * SPIx)3463 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
3464 {
3465 return LL_SPI_IsEnabledIT_UDR(SPIx);
3466 }
3467
3468 /**
3469 * @brief Check if Overrun IT is enabled
3470 * @rmtoll IER OVRIE LL_I2S_IsEnabledIT_OVR
3471 * @param SPIx SPI Instance
3472 * @retval State of bit (1 or 0)
3473 */
LL_I2S_IsEnabledIT_OVR(SPI_TypeDef * SPIx)3474 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
3475 {
3476 return LL_SPI_IsEnabledIT_OVR(SPIx);
3477 }
3478
3479 /**
3480 * @brief Check if TI Frame Format Error IT is enabled
3481 * @rmtoll IER TIFREIE LL_I2S_IsEnabledIT_FRE
3482 * @param SPIx SPI Instance
3483 * @retval State of bit (1 or 0)
3484 */
LL_I2S_IsEnabledIT_FRE(SPI_TypeDef * SPIx)3485 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
3486 {
3487 return LL_SPI_IsEnabledIT_FRE(SPIx);
3488 }
3489
3490 /**
3491 * @}
3492 */
3493
3494 /** @defgroup I2S_LL_EF_DMA_Management DMA_Management
3495 * @{
3496 */
3497
3498 /**
3499 * @brief Enable DMA Rx
3500 * @rmtoll CFG1 RXDMAEN LL_I2S_EnableDMAReq_RX
3501 * @param SPIx SPI Instance
3502 * @retval None
3503 */
LL_I2S_EnableDMAReq_RX(SPI_TypeDef * SPIx)3504 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
3505 {
3506 LL_SPI_EnableDMAReq_RX(SPIx);
3507 }
3508
3509 /**
3510 * @brief Disable DMA Rx
3511 * @rmtoll CFG1 RXDMAEN LL_I2S_DisableDMAReq_RX
3512 * @param SPIx SPI Instance
3513 * @retval None
3514 */
LL_I2S_DisableDMAReq_RX(SPI_TypeDef * SPIx)3515 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
3516 {
3517 LL_SPI_DisableDMAReq_RX(SPIx);
3518 }
3519
3520 /**
3521 * @brief Check if DMA Rx is enabled
3522 * @rmtoll CFG1 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
3523 * @param SPIx SPI Instance
3524 * @retval State of bit (1 or 0)
3525 */
LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef * SPIx)3526 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
3527 {
3528 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
3529 }
3530
3531 /**
3532 * @brief Enable DMA Tx
3533 * @rmtoll CFG1 TXDMAEN LL_I2S_EnableDMAReq_TX
3534 * @param SPIx SPI Instance
3535 * @retval None
3536 */
LL_I2S_EnableDMAReq_TX(SPI_TypeDef * SPIx)3537 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
3538 {
3539 LL_SPI_EnableDMAReq_TX(SPIx);
3540 }
3541
3542 /**
3543 * @brief Disable DMA Tx
3544 * @rmtoll CFG1 TXDMAEN LL_I2S_DisableDMAReq_TX
3545 * @param SPIx SPI Instance
3546 * @retval None
3547 */
LL_I2S_DisableDMAReq_TX(SPI_TypeDef * SPIx)3548 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
3549 {
3550 LL_SPI_DisableDMAReq_TX(SPIx);
3551 }
3552
3553 /**
3554 * @brief Check if DMA Tx is enabled
3555 * @rmtoll CFG1 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
3556 * @param SPIx SPI Instance
3557 * @retval State of bit (1 or 0)
3558 */
LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef * SPIx)3559 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
3560 {
3561 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
3562 }
3563
3564 /**
3565 * @}
3566 */
3567
3568 /** @defgroup I2S_LL_EF_DATA_Management DATA_Management
3569 * @{
3570 */
3571
3572 /**
3573 * @brief Read Data Register
3574 * @rmtoll RXDR . LL_I2S_ReceiveData16
3575 * @param SPIx SPI Instance
3576 * @retval 0..0xFFFF
3577 */
LL_I2S_ReceiveData16(SPI_TypeDef * SPIx)3578 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
3579 {
3580 return LL_SPI_ReceiveData16(SPIx);
3581 }
3582
3583 /**
3584 * @brief Read Data Register
3585 * @rmtoll RXDR . LL_I2S_ReceiveData32
3586 * @param SPIx SPI Instance
3587 * @retval 0..0xFFFFFFFF
3588 */
LL_I2S_ReceiveData32(SPI_TypeDef * SPIx)3589 __STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *SPIx)
3590 {
3591 return LL_SPI_ReceiveData32(SPIx);
3592 }
3593
3594 /**
3595 * @brief Write Data Register
3596 * @rmtoll TXDR . LL_I2S_TransmitData16
3597 * @param SPIx SPI Instance
3598 * @param TxData 0..0xFFFF
3599 * @retval None
3600 */
LL_I2S_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)3601 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
3602 {
3603 LL_SPI_TransmitData16(SPIx, TxData);
3604 }
3605
3606 /**
3607 * @brief Write Data Register
3608 * @rmtoll TXDR . LL_I2S_TransmitData32
3609 * @param SPIx SPI Instance
3610 * @param TxData 0..0xFFFFFFFF
3611 * @retval None
3612 */
LL_I2S_TransmitData32(SPI_TypeDef * SPIx,uint32_t TxData)3613 __STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
3614 {
3615 LL_SPI_TransmitData32(SPIx, TxData);
3616 }
3617
3618
3619 /**
3620 * @}
3621 */
3622
3623
3624 #if defined(USE_FULL_LL_DRIVER)
3625 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
3626 * @{
3627 */
3628
3629 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
3630 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
3631 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
3632 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
3633
3634 /**
3635 * @}
3636 */
3637 #endif /* USE_FULL_LL_DRIVER */
3638
3639 /**
3640 * @}
3641 */
3642
3643 /**
3644 * @}
3645 */
3646
3647 #endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
3648
3649 /**
3650 * @}
3651 */
3652
3653 /**
3654 * @}
3655 */
3656 #ifdef __cplusplus
3657 }
3658 #endif
3659
3660 #endif /* STM32H5xx_LL_SPI_H */
3661
