1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_rng.h
4 * @author MCD Application Team
5 * @brief Header file of RNG LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H5xx_LL_RNG_H
21 #define STM32H5xx_LL_RNG_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h5xx.h"
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (RNG)
35
36 /** @defgroup RNG_LL RNG
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private defines -----------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45
46 /* Exported types ------------------------------------------------------------*/
47 #if defined(USE_FULL_LL_DRIVER)
48 /** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
49 * @{
50 */
51
52
53 /**
54 * @brief LL RNG Init Structure Definition
55 */
56 typedef struct
57 {
58 uint32_t ClockErrorDetection; /*!< Clock error detection.
59 This parameter can be one value of @ref RNG_LL_CED.
60 This parameter can be modified using unitary
61 functions @ref LL_RNG_EnableClkErrorDetect(). */
62 } LL_RNG_InitTypeDef;
63
64 /**
65 * @}
66 */
67 #endif /* USE_FULL_LL_DRIVER */
68 /* Exported constants --------------------------------------------------------*/
69 /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
70 * @{
71 */
72
73 /** @defgroup RNG_LL_CED Clock Error Detection
74 * @{
75 */
76 #define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */
77 #define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */
78 /**
79 * @}
80 */
81 /** @defgroup RNG_LL_ARDIS Auto reset disable
82 * @{
83 */
84 #define LL_RNG_ARDIS_ENABLE 0x00000000U /*!< ARDIS enabled automatic reset to clear SECS bit*/
85 #define LL_RNG_ARDIS_DISABLE RNG_CR_ARDIS /*!< ARDIS disabled no automatic reset to clear SECS bit*/
86 /**
87 * @}
88 */
89
90 /** @defgroup RNG_LL_Clock_Divider_Factor Value used to configure an internal
91 * programmable divider acting on the incoming RNG clock
92 * @{
93 */
94 #define LL_RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */
95 #define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0) /*!< 2 RNG clock cycles per internal RNG clock */
96 #define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1) /*!< 4 RNG clock cycles per internal RNG clock */
97 #define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 8 RNG clock cycles per internal RNG clock */
98 #define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2) /*!< 16 RNG clock cycles per internal RNG clock */
99 #define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 32 RNG clock cycles per internal RNG clock */
100 #define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 64 RNG clock cycles per internal RNG clock */
101 #define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 128 RNG clock cycles per internal RNG clock */
102 #define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3) /*!< 256 RNG clock cycles per internal RNG clock */
103 #define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0) /*!< 512 RNG clock cycles per internal RNG clock */
104 #define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1) /*!< 1024 RNG clock cycles per internal RNG clock */
105 #define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 2048 RNG clock cycles per internal RNG clock */
106 #define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2) /*!< 4096 RNG clock cycles per internal RNG clock */
107 #define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 8192 RNG clock cycles per internal RNG clock */
108 #define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 16384 RNG clock cycles per internal RNG clock */
109 #define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 32768 RNG clock cycles per internal RNG clock */
110 /**
111 * @}
112 */
113
114 /** @defgroup RNG_LL_NIST_Compliance NIST Compliance configuration
115 * @{
116 */
117 #define LL_RNG_NIST_COMPLIANT (0x00000000UL) /*!< Default NIST compliant configuration*/
118 #define LL_RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */
119
120 /**
121 * @}
122 */
123
124 /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
125 * @brief Flags defines which can be used with LL_RNG_ReadReg function
126 * @{
127 */
128 #define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */
129 #define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */
130 #define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */
131 #define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */
132 #define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */
133 /**
134 * @}
135 */
136
137 /** @defgroup RNG_LL_EC_IT IT Defines
138 * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros
139 * @{
140 */
141 #define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */
142 /**
143 * @}
144 */
145
146 /**
147 * @}
148 */
149
150 /* Exported macro ------------------------------------------------------------*/
151 /** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
152 * @{
153 */
154
155 /** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
156 * @{
157 */
158
159 /**
160 * @brief Write a value in RNG register
161 * @param __INSTANCE__ RNG Instance
162 * @param __REG__ Register to be written
163 * @param __VALUE__ Value to be written in the register
164 * @retval None
165 */
166 #define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
167
168 /**
169 * @brief Read a value in RNG register
170 * @param __INSTANCE__ RNG Instance
171 * @param __REG__ Register to be read
172 * @retval Register value
173 */
174 #define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
175 /**
176 * @}
177 */
178
179 /**
180 * @}
181 */
182
183
184 /* Exported functions --------------------------------------------------------*/
185 /** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
186 * @{
187 */
188 /** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
189 * @{
190 */
191
192 /**
193 * @brief Enable Random Number Generation
194 * @rmtoll CR RNGEN LL_RNG_Enable
195 * @param RNGx RNG Instance
196 * @retval None
197 */
LL_RNG_Enable(RNG_TypeDef * RNGx)198 __STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
199 {
200 SET_BIT(RNGx->CR, RNG_CR_RNGEN);
201 }
202
203 /**
204 * @brief Disable Random Number Generation
205 * @rmtoll CR RNGEN LL_RNG_Disable
206 * @param RNGx RNG Instance
207 * @retval None
208 */
LL_RNG_Disable(RNG_TypeDef * RNGx)209 __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
210 {
211 CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
212 }
213
214 /**
215 * @brief Check if Random Number Generator is enabled
216 * @rmtoll CR RNGEN LL_RNG_IsEnabled
217 * @param RNGx RNG Instance
218 * @retval State of bit (1 or 0).
219 */
LL_RNG_IsEnabled(RNG_TypeDef * RNGx)220 __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
221 {
222 return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
223 }
224
225 /**
226 * @brief Enable Clock Error Detection
227 * @rmtoll CR CED LL_RNG_EnableClkErrorDetect
228 * @param RNGx RNG Instance
229 * @retval None
230 */
LL_RNG_EnableClkErrorDetect(RNG_TypeDef * RNGx)231 __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
232 {
233 CLEAR_BIT(RNGx->CR, RNG_CR_CED);
234 }
235
236 /**
237 * @brief Disable RNG Clock Error Detection
238 * @rmtoll CR CED LL_RNG_DisableClkErrorDetect
239 * @param RNGx RNG Instance
240 * @retval None
241 */
LL_RNG_DisableClkErrorDetect(RNG_TypeDef * RNGx)242 __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
243 {
244 SET_BIT(RNGx->CR, RNG_CR_CED);
245 }
246
247 /**
248 * @brief Check if RNG Clock Error Detection is enabled
249 * @rmtoll CR CED LL_RNG_IsEnabledClkErrorDetect
250 * @param RNGx RNG Instance
251 * @retval State of bit (1 or 0).
252 */
LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef * RNGx)253 __STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx)
254 {
255 return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
256 }
257
258 /**
259 * @brief Set RNG Conditioning Soft Reset bit
260 * @rmtoll CR CONDRST LL_RNG_EnableCondReset
261 * @param RNGx RNG Instance
262 * @retval None
263 */
LL_RNG_EnableCondReset(RNG_TypeDef * RNGx)264 __STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *RNGx)
265 {
266 SET_BIT(RNGx->CR, RNG_CR_CONDRST);
267 }
268
269 /**
270 * @brief Reset RNG Conditioning Soft Reset bit
271 * @rmtoll CR CONDRST LL_RNG_DisableCondReset
272 * @param RNGx RNG Instance
273 * @retval None
274 */
LL_RNG_DisableCondReset(RNG_TypeDef * RNGx)275 __STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx)
276 {
277 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
278 }
279
280 /**
281 * @brief Check if RNG Conditioning Soft Reset bit is set
282 * @rmtoll CR CONDRST LL_RNG_IsEnabledCondReset
283 * @param RNGx RNG Instance
284 * @retval State of bit (1 or 0).
285 */
LL_RNG_IsEnabledCondReset(RNG_TypeDef * RNGx)286 __STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(RNG_TypeDef *RNGx)
287 {
288 return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
289 }
290
291 /**
292 * @brief Enable RNG Config Lock
293 * @rmtoll CR CONFIGLOCK LL_RNG_ConfigLock
294 * @param RNGx RNG Instance
295 * @retval None
296 */
LL_RNG_ConfigLock(RNG_TypeDef * RNGx)297 __STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)
298 {
299 SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK);
300 }
301
302 /**
303 * @brief Check if RNG Config Lock is enabled
304 * @rmtoll CR CONFIGLOCK LL_RNG_IsConfigLocked
305 * @param RNGx RNG Instance
306 * @retval State of bit (1 or 0).
307 */
LL_RNG_IsConfigLocked(RNG_TypeDef * RNGx)308 __STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx)
309 {
310 return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
311 }
312
313 /**
314 * @brief Enable NIST Compliance
315 * @rmtoll CR NISTC LL_RNG_EnableNistCompliance
316 * @param RNGx RNG Instance
317 * @retval None
318 */
LL_RNG_EnableNistCompliance(RNG_TypeDef * RNGx)319 __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
320 {
321 MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_NIST_COMPLIANT | RNG_CR_CONDRST);
322 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
323 }
324
325 /**
326 * @brief Disable NIST Compliance
327 * @rmtoll CR NISTC LL_RNG_DisableNistCompliance
328 * @param RNGx RNG Instance
329 * @retval None
330 */
LL_RNG_DisableNistCompliance(RNG_TypeDef * RNGx)331 __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
332 {
333 MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST);
334 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);;
335 }
336
337 /**
338 * @brief Check if NIST Compliance is enabled
339 * @rmtoll CR NISTC LL_RNG_IsEnabledNistCompliance
340 * @param RNGx RNG Instance
341 * @retval State of bit (1 or 0).
342 */
LL_RNG_IsEnabledNistCompliance(RNG_TypeDef * RNGx)343 __STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(RNG_TypeDef *RNGx)
344 {
345 return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
346 }
347
348 /**
349 * @brief Set RNG Config1 Configuration field value
350 * @rmtoll CR RNG_CONFIG1 LL_RNG_SetConfig1
351 * @param RNGx RNG Instance
352 * @param Config1 Value between 0 and 0x3F
353 * @retval None
354 */
LL_RNG_SetConfig1(RNG_TypeDef * RNGx,uint32_t Config1)355 __STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
356 {
357 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1 | RNG_CR_CONDRST, (Config1 << RNG_CR_RNG_CONFIG1_Pos) | RNG_CR_CONDRST);
358 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
359 }
360
361 /**
362 * @brief Get RNG Config1 Configuration field value
363 * @rmtoll CR RNG_CONFIG1 LL_RNG_GetConfig1
364 * @param RNGx RNG Instance
365 * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F
366 */
LL_RNG_GetConfig1(RNG_TypeDef * RNGx)367 __STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx)
368 {
369 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
370 }
371
372 /**
373 * @brief Set RNG Config2 Configuration field value
374 * @rmtoll CR RNG_CONFIG2 LL_RNG_SetConfig2
375 * @param RNGx RNG Instance
376 * @param Config2 Value between 0 and 0x7
377 * @retval None
378 */
LL_RNG_SetConfig2(RNG_TypeDef * RNGx,uint32_t Config2)379 __STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
380 {
381 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2 | RNG_CR_CONDRST, (Config2 << RNG_CR_RNG_CONFIG2_Pos) | RNG_CR_CONDRST);
382 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
383 }
384
385 /**
386 * @brief Get RNG Config2 Configuration field value
387 * @rmtoll CR RNG_CONFIG2 LL_RNG_GetConfig2
388 * @param RNGx RNG Instance
389 * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7
390 */
LL_RNG_GetConfig2(RNG_TypeDef * RNGx)391 __STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx)
392 {
393 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
394 }
395
396 /**
397 * @brief Set RNG Config3 Configuration field value
398 * @rmtoll CR RNG_CONFIG3 LL_RNG_SetConfig3
399 * @param RNGx RNG Instance
400 * @param Config3 Value between 0 and 0xF
401 * @retval None
402 */
LL_RNG_SetConfig3(RNG_TypeDef * RNGx,uint32_t Config3)403 __STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
404 {
405 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3 | RNG_CR_CONDRST, (Config3 << RNG_CR_RNG_CONFIG3_Pos) | RNG_CR_CONDRST);
406 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
407 }
408
409 /**
410 * @brief Get RNG Config3 Configuration field value
411 * @rmtoll CR RNG_CONFIG3 LL_RNG_GetConfig3
412 * @param RNGx RNG Instance
413 * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF
414 */
LL_RNG_GetConfig3(RNG_TypeDef * RNGx)415 __STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx)
416 {
417 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
418 }
419
420 /**
421 * @brief Set RNG Clock divider factor
422 * @rmtoll CR CLKDIV LL_RNG_SetClockDivider
423 * @param RNGx RNG Instance
424 * @param Divider can be one of the following values:
425 * @arg @ref LL_RNG_CLKDIV_BY_1
426 * @arg @ref LL_RNG_CLKDIV_BY_2
427 * @arg @ref LL_RNG_CLKDIV_BY_4
428 * @arg @ref LL_RNG_CLKDIV_BY_8
429 * @arg @ref LL_RNG_CLKDIV_BY_16
430 * @arg @ref LL_RNG_CLKDIV_BY_32
431 * @arg @ref LL_RNG_CLKDIV_BY_64
432 * @arg @ref LL_RNG_CLKDIV_BY_128
433 * @arg @ref LL_RNG_CLKDIV_BY_256
434 * @arg @ref LL_RNG_CLKDIV_BY_512
435 * @arg @ref LL_RNG_CLKDIV_BY_1024
436 * @arg @ref LL_RNG_CLKDIV_BY_2048
437 * @arg @ref LL_RNG_CLKDIV_BY_4096
438 * @arg @ref LL_RNG_CLKDIV_BY_8192
439 * @arg @ref LL_RNG_CLKDIV_BY_16384
440 * @arg @ref LL_RNG_CLKDIV_BY_32768
441 * @retval None
442 */
LL_RNG_SetClockDivider(RNG_TypeDef * RNGx,uint32_t Divider)443 __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
444 {
445 MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, (Divider << RNG_CR_CLKDIV_Pos) | RNG_CR_CONDRST);
446 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
447 }
448
449 /**
450 * @brief Get RNG Clock divider factor
451 * @rmtoll CR CLKDIV LL_RNG_GetClockDivider
452 * @param RNGx RNG Instance
453 * @retval Returned value can be one of the following values:
454 * @arg @ref LL_RNG_CLKDIV_BY_1
455 * @arg @ref LL_RNG_CLKDIV_BY_2
456 * @arg @ref LL_RNG_CLKDIV_BY_4
457 * @arg @ref LL_RNG_CLKDIV_BY_8
458 * @arg @ref LL_RNG_CLKDIV_BY_16
459 * @arg @ref LL_RNG_CLKDIV_BY_32
460 * @arg @ref LL_RNG_CLKDIV_BY_64
461 * @arg @ref LL_RNG_CLKDIV_BY_128
462 * @arg @ref LL_RNG_CLKDIV_BY_256
463 * @arg @ref LL_RNG_CLKDIV_BY_512
464 * @arg @ref LL_RNG_CLKDIV_BY_1024
465 * @arg @ref LL_RNG_CLKDIV_BY_2048
466 * @arg @ref LL_RNG_CLKDIV_BY_4096
467 * @arg @ref LL_RNG_CLKDIV_BY_8192
468 * @arg @ref LL_RNG_CLKDIV_BY_16384
469 * @arg @ref LL_RNG_CLKDIV_BY_32768
470 */
LL_RNG_GetClockDivider(RNG_TypeDef * RNGx)471 __STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx)
472 {
473 return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);
474 }
475 /**
476 * @}
477 */
478
479 /** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
480 * @{
481 */
482
483 /**
484 * @brief Indicate if the RNG Data ready Flag is set or not
485 * @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY
486 * @param RNGx RNG Instance
487 * @retval State of bit (1 or 0).
488 */
LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef * RNGx)489 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
490 {
491 return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
492 }
493
494 /**
495 * @brief Indicate if the Clock Error Current Status Flag is set or not
496 * @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS
497 * @param RNGx RNG Instance
498 * @retval State of bit (1 or 0).
499 */
LL_RNG_IsActiveFlag_CECS(RNG_TypeDef * RNGx)500 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
501 {
502 return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
503 }
504
505 /**
506 * @brief Indicate if the Seed Error Current Status Flag is set or not
507 * @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS
508 * @param RNGx RNG Instance
509 * @retval State of bit (1 or 0).
510 */
LL_RNG_IsActiveFlag_SECS(RNG_TypeDef * RNGx)511 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
512 {
513 return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
514 }
515
516 /**
517 * @brief Indicate if the Clock Error Interrupt Status Flag is set or not
518 * @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS
519 * @param RNGx RNG Instance
520 * @retval State of bit (1 or 0).
521 */
LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef * RNGx)522 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
523 {
524 return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
525 }
526
527 /**
528 * @brief Indicate if the Seed Error Interrupt Status Flag is set or not
529 * @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS
530 * @param RNGx RNG Instance
531 * @retval State of bit (1 or 0).
532 */
LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef * RNGx)533 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
534 {
535 return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
536 }
537
538 /**
539 * @brief Clear Clock Error interrupt Status (CEIS) Flag
540 * @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS
541 * @param RNGx RNG Instance
542 * @retval None
543 */
LL_RNG_ClearFlag_CEIS(RNG_TypeDef * RNGx)544 __STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
545 {
546 WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
547 }
548
549 /**
550 * @brief Clear Seed Error interrupt Status (SEIS) Flag
551 * @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS
552 * @param RNGx RNG Instance
553 * @retval None
554 */
LL_RNG_ClearFlag_SEIS(RNG_TypeDef * RNGx)555 __STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
556 {
557 WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
558 }
559
560 /**
561 * @}
562 */
563
564 /** @defgroup RNG_LL_EF_IT_Management IT Management
565 * @{
566 */
567
568 /**
569 * @brief Enable Random Number Generator Interrupt
570 * (applies for either Seed error, Clock Error or Data ready interrupts)
571 * @rmtoll CR IE LL_RNG_EnableIT
572 * @param RNGx RNG Instance
573 * @retval None
574 */
LL_RNG_EnableIT(RNG_TypeDef * RNGx)575 __STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
576 {
577 SET_BIT(RNGx->CR, RNG_CR_IE);
578 }
579
580 /**
581 * @brief Disable Random Number Generator Interrupt
582 * (applies for either Seed error, Clock Error or Data ready interrupts)
583 * @rmtoll CR IE LL_RNG_DisableIT
584 * @param RNGx RNG Instance
585 * @retval None
586 */
LL_RNG_DisableIT(RNG_TypeDef * RNGx)587 __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
588 {
589 CLEAR_BIT(RNGx->CR, RNG_CR_IE);
590 }
591
592 /**
593 * @brief Check if Random Number Generator Interrupt is enabled
594 * (applies for either Seed error, Clock Error or Data ready interrupts)
595 * @rmtoll CR IE LL_RNG_IsEnabledIT
596 * @param RNGx RNG Instance
597 * @retval State of bit (1 or 0).
598 */
LL_RNG_IsEnabledIT(RNG_TypeDef * RNGx)599 __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
600 {
601 return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
602 }
603
604 /**
605 * @}
606 */
607
608 /** @defgroup RNG_LL_EF_Data_Management Data Management
609 * @{
610 */
611
612 /**
613 * @brief Return32-bit Random Number value
614 * @rmtoll DR RNDATA LL_RNG_ReadRandData32
615 * @param RNGx RNG Instance
616 * @retval Generated 32-bit random value
617 */
LL_RNG_ReadRandData32(RNG_TypeDef * RNGx)618 __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
619 {
620 return (uint32_t)(READ_REG(RNGx->DR));
621 }
622
623 /**
624 * @}
625 */
626
627 /**
628 * @brief Enable Auto reset
629 * @rmtoll CR ARDIS LL_RNG_EnableArdis
630 * @param RNGx RNG Instance
631 * @retval None
632 */
LL_RNG_EnableArdis(RNG_TypeDef * RNGx)633 __STATIC_INLINE void LL_RNG_EnableArdis(RNG_TypeDef *RNGx)
634 {
635 MODIFY_REG(RNGx->CR, RNG_CR_ARDIS | RNG_CR_CONDRST, LL_RNG_ARDIS_ENABLE | RNG_CR_CONDRST);
636 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
637 }
638
639 /**
640 * @brief Disable Auto reset
641 * @rmtoll CR ARDIS LL_RNG_DisableArdis
642 * @param RNGx RNG Instance
643 * @retval None
644 */
LL_RNG_DisableArdis(RNG_TypeDef * RNGx)645 __STATIC_INLINE void LL_RNG_DisableArdis(RNG_TypeDef *RNGx)
646 {
647 MODIFY_REG(RNGx->CR, RNG_CR_ARDIS | RNG_CR_CONDRST, LL_RNG_ARDIS_DISABLE | RNG_CR_CONDRST);
648 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
649 }
650
651 /**
652 * @brief Check if RNG Auto reset is enabled
653 * @rmtoll CR ARDIS LL_RNG_IsEnabledArdis
654 * @param RNGx RNG Instance
655 * @retval State of bit (1 or 0).
656 */
LL_RNG_IsEnabledArdis(RNG_TypeDef * RNGx)657 __STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(RNG_TypeDef *RNGx)
658 {
659 return ((READ_BIT(RNGx->CR, RNG_CR_ARDIS) != (RNG_CR_ARDIS)) ? 1UL : 0UL);
660 }
661
662 /** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control
663 * @{
664 */
665
666 /**
667 * @brief Set RNG Health Test Control
668 * @rmtoll HTCR HTCFG LL_RNG_SetHealthConfig
669 * @param RNGx RNG Instance
670 * @param HTCFG can be values of 32 bits
671 * @retval None
672 */
LL_RNG_SetHealthConfig(RNG_TypeDef * RNGx,uint32_t HTCFG)673 __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG)
674 {
675 WRITE_REG(RNGx->HTCR, HTCFG);
676 }
677
678 /**
679 * @brief Get RNG Health Test Control
680 * @rmtoll HTCR HTCFG LL_RNG_GetHealthConfig
681 * @param RNGx RNG Instance
682 * @retval Return 32-bit RNG Health Test configuration
683 */
LL_RNG_GetHealthConfig(RNG_TypeDef * RNGx)684 __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx)
685 {
686 return (uint32_t)READ_REG(RNGx->HTCR);
687 }
688
689 /**
690 * @}
691 */
692 #if defined(USE_FULL_LL_DRIVER)
693 /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
694 * @{
695 */
696 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
697 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
698 ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
699
700 /**
701 * @}
702 */
703 #endif /* USE_FULL_LL_DRIVER */
704
705 /**
706 * @}
707 */
708
709 /**
710 * @}
711 */
712
713 #endif /* RNG */
714
715 /**
716 * @}
717 */
718
719 #ifdef __cplusplus
720 }
721 #endif
722
723 #endif /* __STM32H5xx_LL_RNG_H */
724
