1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H5xx_LL_PWR_H
21 #define STM32H5xx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif /* __cplusplus */
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h5xx.h"
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
44 * @{
45 */
46
47 /** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines
48 * @brief Flags defines which can be used with LL_PWR_WriteReg function
49 * @{
50 */
51 /* Wake-Up Pins PWR register offsets */
52 #define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2UL
53 #define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK 0x7FU
54 /**
55 * @}
56 */
57 /**
58 * @}
59 */
60 /* Private macros ------------------------------------------------------------*/
61 /* Exported types ------------------------------------------------------------*/
62 /* Exported constants --------------------------------------------------------*/
63
64 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
65 * @{
66 */
67
68 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
69 * @brief Flags defines which can be used with LL_PWR_WriteReg function
70 * @{
71 */
72 #define LL_PWR_PMCR_CSSF PWR_PMCR_CSSF /*!< Clear STOP and STANDBY flags */
73 #define LL_PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1 /*!< Clear Wakeup flag 1 */
74 #define LL_PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2 /*!< Clear Wakeup flag 2 */
75 #define LL_PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3 /*!< Clear Wakeup flag 3 */
76 #define LL_PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4 /*!< Clear Wakeup flag 4 */
77 #define LL_PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5 /*!< Clear Wakeup flag 5 */
78 #define LL_PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6 /*!< Clear Wakeup flag 6 */
79 #define LL_PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7 /*!< Clear Wakeup flag 7 */
80 #define LL_PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8 /*!< Clear Wakeup flag 8 */
81 #define LL_PWR_WUSCR_CWUF_ALL PWR_WUSCR_CWUF /*!< Clear all Wakeup flags */
82 /**
83 * @}
84 */
85
86 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
87 * @brief Flags defines which can be used with LL_PWR_ReadReg function
88 * @{
89 */
90 #define LL_PWR_FLAG_VOSRDY PWR_VOSR_VOSRDY /*!< Voltage scaling ready flag */
91 #define LL_PWR_FLAG_ACTVOSRDY PWR_VOSR_ACTOVSRDY /*!< Currently applied VOS ready flag */
92 #define LL_PWR_FLAG_STOPF PWR_PMSR_STOPF /*!< STOP flag */
93 #define LL_PWR_FLAG_SBF PWR_PMSR_SBF /*!< STANDBY flag */
94 #define LL_PWR_FLAG_AVDO PWR_VMSR_AVDO /*!< Analog voltage detector output on VDDA flag */
95 #define LL_PWR_FLAG_VDDIO2RDY PWR_VMSR_VDDIO2RDY /*!< VDDIO2 ready flag */
96 #define LL_PWR_FLAG_PVDO PWR_VMSR_PVDO /*!< Programmable voltage detect output flag */
97 #define LL_PWR_FLAG_USB33RDY PWR_VMSR_USB33RDY /*!< VDDUSB ready flag */
98 #define LL_PWR_FLAG_TEMPH PWR_BDSR_TEMPH /*!< Temperature level flag (versus high threshold) */
99 #define LL_PWR_FLAG_TEMPL PWR_BDSR_TEMPL /*!< Temperature level flag (versus low threshold) */
100 #define LL_PWR_FLAG_VBATH PWR_BDSR_VBATH /*!< VBAT level flag (versus high threshold) */
101 #define LL_PWR_FLAG_VBATL PWR_BDSR_VBATL /*!< VBAT level flag (versus low threshold) */
102
103
104 #define LL_PWR_WAKEUP_FLAG1 PWR_WUSR_WUF1 /*!< Wakeup flag 1 */
105 #define LL_PWR_WAKEUP_FLAG2 PWR_WUSR_WUF2 /*!< Wakeup flag 2 */
106 #define LL_PWR_WAKEUP_FLAG3 PWR_WUSR_WUF3 /*!< Wakeup flag 3 */
107 #define LL_PWR_WAKEUP_FLAG4 PWR_WUSR_WUF4 /*!< Wakeup flag 4 */
108 #define LL_PWR_WAKEUP_FLAG5 PWR_WUSR_WUF5 /*!< Wakeup flag 5 */
109 #define LL_PWR_WAKEUP_FLAG6 PWR_WUSR_WUF6 /*!< Wakeup flag 6 */
110 #define LL_PWR_WAKEUP_FLAG7 PWR_WUSR_WUF7 /*!< Wakeup flag 7 */
111 #define LL_PWR_WAKEUP_FLAG8 PWR_WUSR_WUF8 /*!< Wakeup flag 8 */
112 /**
113 * @}
114 */
115
116 /** @defgroup PWR_LL_EC_LOW_POWER_MODE_SELCTION Low Power Mode Selection
117 * @{
118 */
119 #define LL_PWR_STOP_MODE (0U) /*!< STOP 0 mode */
120 #define LL_PWR_STANDBY_MODE PWR_PMCR_LPMS /*!< STANDBY mode */
121
122
123 /**
124 * @}
125 */
126
127 /** @defgroup PWR_LL_EC_VOLTAGE_SCALING_RANGE_SELECTION PWR Voltage scaling range selection
128 * @{
129 */
130 #define LL_PWR_REGU_VOLTAGE_SCALE0 PWR_VOSCR_VOS /*!< Voltage scaling range 0 */
131 #define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_VOSCR_VOS_1 /*!< Voltage scaling range 1 */
132 #define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_VOSCR_VOS_0 /*!< Voltage scaling range 2 */
133 #define LL_PWR_REGU_VOLTAGE_SCALE3 0x00000000U /*!< Voltage scaling range 3 */
134 /**
135 * @}
136 */
137
138 /** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling
139 * @{
140 */
141 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 PWR_PMCR_SVOS_0 /*!< Select voltage scale 5 when system enters STOP mode */
142 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 PWR_PMCR_SVOS_1 /*!< Select voltage scale 4 when system enters STOP mode */
143 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 (PWR_PMCR_SVOS_0 | PWR_PMCR_SVOS_1) /*!< Select voltage scale 3 when system enters STOP mode */
144 /**
145 * @}
146 */
147
148 /** @defgroup PWR_LL_EC_PVD_LEVEL_SELECTION PWR Power Voltage Detector Level Selection
149 * @{
150 */
151 #define LL_PWR_PVDLEVEL_0 0U /*!< Voltage threshold detected by PVD 1.95 V */
152 #define LL_PWR_PVDLEVEL_1 PWR_VMCR_PLS_0 /*!< Voltage threshold detected by PVD 2.10 V */
153 #define LL_PWR_PVDLEVEL_2 PWR_VMCR_PLS_1 /*!< Voltage threshold detected by PVD 2.25 V */
154 #define LL_PWR_PVDLEVEL_3 (PWR_VMCR_PLS_0 | PWR_VMCR_PLS_1) /*!< Voltage threshold detected by PVD 2.40 V */
155 #define LL_PWR_PVDLEVEL_4 PWR_VMCR_PLS_2 /*!< Voltage threshold detected by PVD 2.55 V */
156 #define LL_PWR_PVDLEVEL_5 (PWR_VMCR_PLS_0 | PWR_VMCR_PLS_2) /*!< Voltage threshold detected by PVD 2.70 V */
157 #define LL_PWR_PVDLEVEL_6 (PWR_VMCR_PLS_1 | PWR_VMCR_PLS_2) /*!< Voltage threshold detected by PVD 2.85 V */
158 #define LL_PWR_PVDLEVEL_7 PWR_VMCR_PLS /*!< External input analog voltage on PVD_IN
159 pin, compared to internal VREFINT level */
160 /**
161 * @}
162 */
163
164 /** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector
165 * @{
166 */
167 #define LL_PWR_AVDLEVEL_0 0U /*!< Analog Voltage threshold detected by AVD 1.7 V */
168 #define LL_PWR_AVDLEVEL_1 PWR_VMCR_ALS_0 /*!< Analog Voltage threshold detected by AVD 2.1 V */
169 #define LL_PWR_AVDLEVEL_2 PWR_VMCR_ALS_1 /*!< Analog Voltage threshold detected by AVD 2.5 V */
170 #define LL_PWR_AVDLEVEL_3 PWR_VMCR_ALS /*!< Analog Voltage threshold detected by AVD 2.8 V */
171
172 /**
173 * @}
174 */
175
176 /** @defgroup PWR_LL_EC_WAKEUP_PIN PWR Wake Up Pin
177 * @{
178 */
179 #define LL_PWR_WAKEUP_PIN1 PWR_WUCR_WUPEN1 /*!< Wakeup pin 1 enable */
180 #define LL_PWR_WAKEUP_PIN2 PWR_WUCR_WUPEN2 /*!< Wakeup pin 2 enable */
181 #define LL_PWR_WAKEUP_PIN3 PWR_WUCR_WUPEN3 /*!< Wakeup pin 3 enable */
182 #define LL_PWR_WAKEUP_PIN4 PWR_WUCR_WUPEN4 /*!< Wakeup pin 4 enable */
183 #define LL_PWR_WAKEUP_PIN5 PWR_WUCR_WUPEN5 /*!< Wakeup pin 5 enable */
184 #define LL_PWR_WAKEUP_PIN6 PWR_WUCR_WUPEN6 /*!< Wakeup pin 6 enable */
185 #define LL_PWR_WAKEUP_PIN7 PWR_WUCR_WUPEN7 /*!< Wakeup pin 7 enable */
186 #define LL_PWR_WAKEUP_PIN8 PWR_WUCR_WUPEN8 /*!< Wakeup pin 8 enable */
187 /**
188 * @}
189 */
190
191 /** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL Wakeup Pins pull configuration
192 * @{
193 */
194 #define LL_PWR_WAKEUP_PIN_NOPULL 0x00000000UL /*!< Configure Wake-Up pin in no pull */
195 #define LL_PWR_WAKEUP_PIN_PULLUP 0x00000001UL /*!< Configure Wake-Up pin in pull Up */
196 #define LL_PWR_WAKEUP_PIN_PULLDOWN 0x00000002UL /*!< Configure Wake-Up pin in pull Down */
197 /**
198 * @}
199 */
200
201 /** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
202 * @{
203 */
204 #define LL_PWR_EXTERNAL_SOURCE_SUPPLY PWR_SCCR_BYPASS /*!< The SMPS and the LDO are Bypassed.
205 The Core domains are supplied from an external source */
206 /**
207 * @}
208 */
209
210 /** @defgroup PWR_LL_EC_CHARGING_RESISTOR_SELECTION PWR VBAT Charging Resistor Selection
211 * @{
212 */
213 #define LL_PWR_BATT_CHARG_RESISTOR_5K 0U /*!< Charge the battery through a 5 kO resistor */
214 #define LL_PWR_BATT_CHARG_RESISTOR_1_5K PWR_BDCR_VBRS /*!< Charge the battery through a 1.5 kO resistor */
215 /**
216 * @}
217 */
218
219 /** @defgroup PWR_LL_EC_ITEMS_SECURE_ATTRIBUTE PWR Items Secure Attribute
220 * @{
221 */
222 #define LL_PWR_WAKEUP_PIN1_NSEC 0U /* Wake up pin 1 nsecure mode */
223 #define LL_PWR_WAKEUP_PIN1_SEC PWR_SECCFGR_WUP1SEC /* Wake up pin 1 secure mode */
224 #define LL_PWR_WAKEUP_PIN2_NSEC 0U /* Wake up pin 2 nsecure mode */
225 #define LL_PWR_WAKEUP_PIN2_SEC PWR_SECCFGR_WUP2SEC /* Wake up pin 2 secure mode */
226 #define LL_PWR_WAKEUP_PIN3_NSEC 0U /* Wake up pin 3 nsecure mode */
227 #define LL_PWR_WAKEUP_PIN3_SEC PWR_SECCFGR_WUP3SEC /* Wake up pin 3 secure mode */
228 #define LL_PWR_WAKEUP_PIN4_NSEC 0U /* Wake up pin 4 nsecure mode */
229 #define LL_PWR_WAKEUP_PIN4_SEC PWR_SECCFGR_WUP4SEC /* Wake up pin 4 secure mode */
230 #define LL_PWR_WAKEUP_PIN5_NSEC 0U /* Wake up pin 5 nsecure mode */
231 #define LL_PWR_WAKEUP_PIN5_SEC PWR_SECCFGR_WUP5SEC /* Wake up pin 5 secure mode */
232 #define LL_PWR_WAKEUP_PIN6_NSEC 0U /* Wake up pin 6 nsecure mode */
233 #define LL_PWR_WAKEUP_PIN6_SEC PWR_SECCFGR_WUP6SEC /* Wake up pin 6 secure mode */
234 #define LL_PWR_WAKEUP_PIN7_NSEC 0U /* Wake up pin 7 nsecure mode */
235 #define LL_PWR_WAKEUP_PIN7_SEC PWR_SECCFGR_WUP7SEC /* Wake up pin 7 secure mode */
236 #define LL_PWR_WAKEUP_PIN8_NSEC 0U /* Wake up pin 8 nsecure mode */
237 #define LL_PWR_WAKEUP_PIN8_SEC PWR_SECCFGR_WUP8SEC /* Wake up pin 8 secure mode */
238
239 #define LL_PWR_RET_NSEC 0U /* Retention nsecure mode */
240 #define LL_PWR_RET_SEC PWR_SECCFGR_RETSEC /* Retention secure mode */
241 #define LL_PWR_LPM_NSEC 0U /* Low-power modes nsecure mode */
242 #define LL_PWR_LPM_SEC PWR_SECCFGR_LPMSEC /* Low-power modes secure mode */
243 #define LL_PWR_VDM_NSEC 0U /* Voltage detection and monitoring nsecure mode */
244 #define LL_PWR_VDM_SEC PWR_SECCFGR_SCMSEC /* Voltage detection and monitoring secure mode */
245 #define LL_PWR_VB_NSEC 0U /* Backup domain nsecure mode */
246 #define LL_PWR_VB_SEC PWR_SECCFGR_VBSEC /* Backup domain secure mode */
247 #define LL_PWR_APC_NSEC 0U /* Pull-up/pull-down nsecure mode */
248 #define LL_PWR_APC_SEC PWR_SECCFGR_VUSBSEC /* Pull-up/pull-down secure mode */
249 /**
250 * @}
251 */
252
253 /**
254 * @}
255 */
256
257 /* Exported macro ------------------------------------------------------------*/
258
259 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
260 * @{
261 */
262
263 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and Read Registers Macros
264 * @{
265 */
266
267 /**
268 * @brief Write a value in PWR register.
269 * @param __REG__ Register to be written.
270 * @param __VALUE__ Value to be written in the register.
271 * @retval None.
272 */
273 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
274
275 /**
276 * @brief Read a value in PWR register.
277 * @param __REG__ Register to be read.
278 * @retval Register value.
279 */
280 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
281 /**
282 * @}
283 */
284
285 /**
286 * @}
287 */
288
289 /* Exported functions --------------------------------------------------------*/
290
291 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
292 * @{
293 */
294
295 /** @defgroup PWR_LL_EF_CONFIGURATION PWR Configuration
296 * @{
297 */
298
299 /**
300 * @brief Set system power mode.
301 * @rmtoll PMCR LPMS LL_PWR_SetPowerMode
302 * @param Mode : This parameter can be one of the following values:
303 * @arg @ref LL_PWR_STOP_MODE
304 * @arg @ref LL_PWR_STANDBY_MODE
305 * @retval None
306 */
LL_PWR_SetPowerMode(uint32_t Mode)307 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t Mode)
308 {
309 MODIFY_REG(PWR->PMCR, PWR_PMCR_LPMS, Mode);
310 }
311
312 /**
313 * @brief Get system power mode.
314 * @rmtoll PMCR LPMS LL_PWR_GetPowerMode
315 * @retval Returned value can be one of the following values:
316 * @arg @ref LL_PWR_STOP_MODE
317 * @arg @ref LL_PWR_STANDBY_MODE
318 */
LL_PWR_GetPowerMode(void)319 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
320 {
321 return (READ_BIT(PWR->PMCR, PWR_PMCR_LPMS));
322 }
323
324 /**
325 * @brief Set the internal Regulator output voltage in STOP mode
326 * @rmtoll PMCR SVOS LL_PWR_SetStopModeRegulVoltageScaling
327 * @param VoltageScaling This parameter can be one of the following values:
328 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
329 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
330 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
331 * @retval None
332 */
LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)333 __STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)
334 {
335 MODIFY_REG(PWR->PMCR, PWR_PMCR_SVOS, VoltageScaling);
336 }
337
338 /**
339 * @brief Get the internal Regulator output voltage in STOP mode
340 * @rmtoll PMCR SVOS LL_PWR_GetStopModeRegulVoltageScaling
341 * @retval Returned value can be one of the following values:
342 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
343 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
344 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
345 */
LL_PWR_GetStopModeRegulVoltageScaling(void)346 __STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void)
347 {
348 return (uint32_t)(READ_BIT(PWR->PMCR, PWR_PMCR_SVOS));
349 }
350
351 /**
352 * @brief Enable the Flash Power Down in Stop Mode
353 * @rmtoll PMCR FLPS LL_PWR_EnableFlashPowerDown
354 * @retval None
355 */
LL_PWR_EnableFlashPowerDown(void)356 __STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
357 {
358 SET_BIT(PWR->PMCR, PWR_PMCR_FLPS);
359 }
360
361 /**
362 * @brief Disable the Flash Power Down in Stop Mode
363 * @rmtoll PMCR FLPS LL_PWR_DisableFlashPowerDown
364 * @retval None
365 */
LL_PWR_DisableFlashPowerDown(void)366 __STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
367 {
368 CLEAR_BIT(PWR->PMCR, PWR_PMCR_FLPS);
369 }
370
371 /**
372 * @brief Check if the Flash Power Down in Stop Mode is enabled
373 * @rmtoll PMCR FLPS LL_PWR_IsEnabledFlashPowerDown
374 * @retval State of bit (1 or 0).
375 */
LL_PWR_IsEnabledFlashPowerDown(void)376 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
377 {
378 return ((READ_BIT(PWR->PMCR, PWR_PMCR_FLPS) == (PWR_PMCR_FLPS)) ? 1UL : 0UL);
379 }
380
381 /**
382 * @brief Enable the Analog Voltage Booster (VDDA)
383 * @rmtoll PMCR BOOSTE LL_PWR_EnableAnalogBooster
384 * @retval None
385 */
LL_PWR_EnableAnalogBooster(void)386 __STATIC_INLINE void LL_PWR_EnableAnalogBooster(void)
387 {
388 SET_BIT(PWR->PMCR, PWR_PMCR_BOOSTE);
389 }
390
391 /**
392 * @brief Disable the Analog Voltage Booster (VDDA)
393 * @rmtoll PMCR BOOSTE LL_PWR_DisableAnalogBooster
394 * @retval None
395 */
LL_PWR_DisableAnalogBooster(void)396 __STATIC_INLINE void LL_PWR_DisableAnalogBooster(void)
397 {
398 CLEAR_BIT(PWR->PMCR, PWR_PMCR_BOOSTE);
399 }
400
401 /**
402 * @brief Check if the Analog Voltage Booster (VDDA) is enabled
403 * @rmtoll PMCR BOOSTE LL_PWR_IsEnabledAnalogBooster
404 * @retval State of bit (1 or 0).
405 */
LL_PWR_IsEnabledAnalogBooster(void)406 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void)
407 {
408 return ((READ_BIT(PWR->PMCR, PWR_PMCR_BOOSTE) == (PWR_PMCR_BOOSTE)) ? 1UL : 0UL);
409 }
410
411 /**
412 * @brief Enable the Analog Voltage Ready to isolate the BOOST IP until VDDA will be ready
413 * @rmtoll PMCR AVD_READY LL_PWR_EnableAnalogVoltageReady
414 * @retval None
415 */
LL_PWR_EnableAnalogVoltageReady(void)416 __STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void)
417 {
418 SET_BIT(PWR->PMCR, PWR_PMCR_AVD_READY);
419 }
420
421 /**
422 * @brief Disable the Analog Voltage Ready (VDDA)
423 * @rmtoll PMCR AVD_READY LL_PWR_DisableAnalogVoltageReady
424 * @retval None
425 */
LL_PWR_DisableAnalogVoltageReady(void)426 __STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void)
427 {
428 CLEAR_BIT(PWR->PMCR, PWR_PMCR_AVD_READY);
429 }
430
431 /**
432 * @brief Check if the Analog Voltage Booster (VDDA) is enabled
433 * @rmtoll PMCR AVD_READY LL_PWR_IsEnabledAnalogVoltageReady
434 * @retval State of bit (1 or 0).
435 */
LL_PWR_IsEnabledAnalogVoltageReady(void)436 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void)
437 {
438 return ((READ_BIT(PWR->PMCR, PWR_PMCR_AVD_READY) == (PWR_PMCR_AVD_READY)) ? 1UL : 0UL);
439 }
440
441 /**
442 * @brief Enable the AHB RAM1 shut-off in Stop mode
443 * @rmtoll PMCR SRAM1SO LL_PWR_EnableAHBRAM1ShutOff
444 * @retval None
445 */
LL_PWR_EnableAHBRAM1ShutOff(void)446 __STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff(void)
447 {
448 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM1SO);
449 }
450
451 /**
452 * @brief Disable the AHB RAM1 shut-off in Stop mode
453 * @rmtoll PMCR SRAM1SO LL_PWR_DisableAHBRAM1ShutOff
454 * @retval None
455 */
LL_PWR_DisableAHBRAM1ShutOff(void)456 __STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff(void)
457 {
458 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM1SO);
459 }
460
461 /**
462 * @brief Check if the AHB RAM1 shut-off in Stop mode is enabled
463 * @rmtoll CR1 SRAM1SO LL_PWR_IsEnabledAHBRAM1ShutOff
464 * @retval State of bit (1 or 0).
465 */
LL_PWR_IsEnabledAHBRAM1ShutOff(void)466 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff(void)
467 {
468 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM1SO) == (PWR_PMCR_SRAM1SO)) ? 1UL : 0UL);
469 }
470 #if defined (PWR_PMCR_SRAM2_48SO)
471 /**
472 * @brief Enable the AHB RAM2 48K Bytes shut-off in Stop mode
473 * @rmtoll PMCR SRAM2_48SO LL_PWR_EnableAHBRAM2_48K_ShutOff
474 * @retval None
475 */
LL_PWR_EnableAHBRAM2_48K_ShutOff(void)476 __STATIC_INLINE void LL_PWR_EnableAHBRAM2_48K_ShutOff(void)
477 {
478 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48SO);
479 }
480
481 /**
482 * @brief Disable the AHB RAM2 48K Bytes shut-off in Stop mode
483 * @rmtoll PMCR SRAM2_48SO LL_PWR_DisableAHBRAM2_48K_ShutOff
484 * @retval None
485 */
LL_PWR_DisableAHBRAM2_48K_ShutOff(void)486 __STATIC_INLINE void LL_PWR_DisableAHBRAM2_48K_ShutOff(void)
487 {
488 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48SO);
489 }
490
491 /**
492 * @brief Check if the AHB RAM2 shut-off in Stop mode is enabled
493 * @rmtoll PMCR SRAM2_48SO LL_PWR_IsEnabledAHBRAM2_48K_ShutOff
494 * @retval State of bit (1 or 0).
495 */
LL_PWR_IsEnabledAHBRAM2_48K_ShutOff(void)496 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2_48K_ShutOff(void)
497 {
498 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48SO) == (PWR_PMCR_SRAM2_48SO)) ? 1UL : 0UL);
499 }
500 #endif /* PWR_PMCR_SRAM2_48SO */
501
502 #if defined (PWR_PMCR_SRAM2_16SO)
503 /**
504 * @brief Enable the AHB RAM2 16K Bytes shut-off in Stop mode
505 * @rmtoll PMCR SRAM2_16SO LL_PWR_EnableAHBRAM2_16K_ShutOff
506 * @retval None
507 */
LL_PWR_EnableAHBRAM2_16K_ShutOff(void)508 __STATIC_INLINE void LL_PWR_EnableAHBRAM2_16K_ShutOff(void)
509 {
510 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16SO);
511 }
512
513 /**
514 * @brief Disable the AHB RAM2 16K Bytes shut-off in Stop mode
515 * @rmtoll PMCR SRAM2_16SO LL_PWR_DisableAHBRAM2_16K_ShutOff
516 * @retval None
517 */
LL_PWR_DisableAHBRAM2_16K_ShutOff(void)518 __STATIC_INLINE void LL_PWR_DisableAHBRAM2_16K_ShutOff(void)
519 {
520 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16SO);
521 }
522
523 /**
524 * @brief Check if the AHB RAM2 shut-off in Stop mode is enabled
525 * @rmtoll PMCR SRAM2_16SO LL_PWR_IsEnabledAHBRAM2_16K_ShutOff
526 * @retval State of bit (1 or 0).
527 */
LL_PWR_IsEnabledAHBRAM2_16K_ShutOff(void)528 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2_16K_ShutOff(void)
529 {
530 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16SO) == (PWR_PMCR_SRAM2_16SO)) ? 1UL : 0UL);
531 }
532 #else
533 /**
534 * @brief Enable the AHB RAM2 shut-off in Stop mode
535 * @rmtoll PMCR SRAM2SO LL_PWR_EnableAHBRAM2ShutOff
536 * @retval None
537 */
LL_PWR_EnableAHBRAM2ShutOff(void)538 __STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff(void)
539 {
540 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2SO);
541 }
542
543 /**
544 * @brief Disable the AHB RAM2 shut-off in Stop mode
545 * @rmtoll PMCR SRAM2SO LL_PWR_DisableAHBRAM2ShutOff
546 * @retval None
547 */
LL_PWR_DisableAHBRAM2ShutOff(void)548 __STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff(void)
549 {
550 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2SO);
551 }
552
553 /**
554 * @brief Check if the AHB RAM2 shut-off in Stop mode is enabled
555 * @rmtoll PMCR SRAM2SO LL_PWR_IsEnabledAHBRAM2ShutOff
556 * @retval State of bit (1 or 0).
557 */
LL_PWR_IsEnabledAHBRAM2ShutOff(void)558 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void)
559 {
560 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2SO) == (PWR_PMCR_SRAM2SO)) ? 1UL : 0UL);
561 }
562 #endif /* PWR_PMCR_SRAM2_16SO */
563
564 #if defined (PWR_PMCR_SRAM3SO)
565 /**
566 * @brief Enable the AHB RAM3 shut-off in Stop mode
567 * @rmtoll PMCR SRAM3SO LL_PWR_EnableAHBRAM3ShutOff
568 * @retval None
569 */
LL_PWR_EnableAHBRAM3ShutOff(void)570 __STATIC_INLINE void LL_PWR_EnableAHBRAM3ShutOff(void)
571 {
572 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM3SO);
573 }
574
575 /**
576 * @brief Disable the AHB RAM3 shut-off in Stop mode
577 * @rmtoll PMCR SRAM3SO LL_PWR_DisableAHBRAM3ShutOff
578 * @retval None
579 */
LL_PWR_DisableAHBRAM3ShutOff(void)580 __STATIC_INLINE void LL_PWR_DisableAHBRAM3ShutOff(void)
581 {
582 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM3SO);
583 }
584
585 /**
586 * @brief Check if the AHB RAM3 shut-off in Stop mode is enabled
587 * @rmtoll PMCR SRAM3SO LL_PWR_IsEnabledAHBRAM3ShutOff
588 * @retval State of bit (1 or 0).
589 */
LL_PWR_IsEnabledAHBRAM3ShutOff(void)590 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM3ShutOff(void)
591 {
592 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM3SO) == (PWR_PMCR_SRAM3SO)) ? 1UL : 0UL);
593 }
594 #endif /* PWR_PMCR_SRAM3SO */
595
596 #if defined (PWR_PMCR_ETHERNETSO)
597 /**
598 * @brief Enable the ETHERNET RAM shut-off in Stop mode
599 * @rmtoll PMCR ETHERNETSO LL_PWR_EnableETHERNETRAMShutOff
600 * @retval None
601 */
LL_PWR_EnableETHERNETRAMShutOff(void)602 __STATIC_INLINE void LL_PWR_EnableETHERNETRAMShutOff(void)
603 {
604 SET_BIT(PWR->PMCR, PWR_PMCR_ETHERNETSO);
605 }
606
607 /**
608 * @brief Disable the ETHERNET RAM shut-off in Stop mode
609 * @rmtoll PMCR ETHERNETSO LL_PWR_DisableETHERNETRAMShutOff
610 * @retval None
611 */
LL_PWR_DisableETHERNETRAMShutOff(void)612 __STATIC_INLINE void LL_PWR_DisableETHERNETRAMShutOff(void)
613 {
614 CLEAR_BIT(PWR->PMCR, PWR_PMCR_ETHERNETSO);
615 }
616
617 /**
618 * @brief Check if the ETHERNET RAM shut-off in Stop mode is enabled
619 * @rmtoll PMCR ETHERNETSO LL_PWR_IsEnabledETHERNETRAMShutOff
620 * @retval State of bit (1 or 0).
621 */
LL_PWR_IsEnabledETHERNETRAMShutOff(void)622 __STATIC_INLINE uint32_t LL_PWR_IsEnabledETHERNETRAMShutOff(void)
623 {
624 return ((READ_BIT(PWR->PMCR, PWR_PMCR_ETHERNETSO) == (PWR_PMCR_ETHERNETSO)) ? 1UL : 0UL);
625 }
626 #endif /* PWR_PMCR_ETHERNETSO */
627
628 /**
629 * @brief Set the regulator supply output voltage.
630 * @rmtoll VOSCR VOS LL_PWR_SetRegulVoltageScaling
631 * @param VoltageScaling This parameter can be one of the following values:
632 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
633 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
634 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
635 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4
636 * @retval None
637 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)638 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
639 {
640 MODIFY_REG(PWR->VOSCR, PWR_VOSCR_VOS, VoltageScaling);
641 }
642
643 /**
644 * @brief Get the regulator supply output voltage.
645 * @rmtoll VOSCR VOS LL_PWR_GetRegulVoltageScaling
646 * @retval Returned value can be one of the following values:
647 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
648 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
649 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
650 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4
651 */
LL_PWR_GetRegulVoltageScaling(void)652 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
653 {
654 return (uint32_t)(READ_BIT(PWR->VOSCR, PWR_VOSCR_VOS));
655 }
656
657 /**
658 * @brief Get currently voltage scaling applied to VCORE.
659 * @rmtoll VOSSR ACTVOS[1:0] LL_PWR_GetCurrentVOS
660 * @retval Returned value can be one of the following values:
661 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
662 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
663 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
664 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4
665 */
LL_PWR_GetCurrentVOS(void)666 __STATIC_INLINE uint32_t LL_PWR_GetCurrentVOS(void)
667 {
668 return (READ_BIT(PWR->VOSSR, PWR_VOSSR_ACTVOS));
669 }
670
671 /**
672 * @brief Enable Backup Regulator
673 * @rmtoll BDCR BREN LL_PWR_EnableBkUpRegulator
674 * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and
675 * VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup
676 * SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,
677 * the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
678 * the data written into the RAM will be maintained in the Standby and VBAT modes.
679 * @retval None
680 */
LL_PWR_EnableBkUpRegulator(void)681 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
682 {
683 SET_BIT(PWR->BDCR, PWR_BDCR_BREN);
684 }
685
686 /**
687 * @brief Disable Backup Regulator
688 * @rmtoll BDCR BREN LL_PWR_DisableBkUpRegulator
689 * @retval None
690 */
LL_PWR_DisableBkUpRegulator(void)691 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
692 {
693 CLEAR_BIT(PWR->BDCR, PWR_BDCR_BREN);
694 }
695
696 /**
697 * @brief Check if the backup Regulator is enabled
698 * @rmtoll BDCR BREN LL_PWR_IsEnabledBkUpRegulator
699 * @retval State of bit (1 or 0).
700 */
LL_PWR_IsEnabledBkUpRegulator(void)701 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
702 {
703 return ((READ_BIT(PWR->BDCR, PWR_BDCR_BREN) == (PWR_BDCR_BREN)) ? 1UL : 0UL);
704 }
705
706 /**
707 * @brief Enable VBAT and Temperature monitoring
708 * @rmtoll BDCR MONEN LL_PWR_EnableMonitoring
709 * @retval None
710 */
LL_PWR_EnableMonitoring(void)711 __STATIC_INLINE void LL_PWR_EnableMonitoring(void)
712 {
713 SET_BIT(PWR->BDCR, PWR_BDCR_MONEN);
714 }
715
716 /**
717 * @brief Disable VBAT and Temperature monitoring
718 * @rmtoll BDCR MONEN LL_PWR_DisableMonitoring
719 * @retval None
720 */
LL_PWR_DisableMonitoring(void)721 __STATIC_INLINE void LL_PWR_DisableMonitoring(void)
722 {
723 CLEAR_BIT(PWR->BDCR, PWR_BDCR_MONEN);
724 }
725
726 /**
727 * @brief Check if the VBAT and Temperature monitoring is enabled
728 * @rmtoll BDCR MONEN LL_PWR_IsEnabledMonitoring
729 * @retval State of bit (1 or 0).
730 */
LL_PWR_IsEnabledMonitoring(void)731 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
732 {
733 return ((READ_BIT(PWR->BDCR, PWR_BDCR_MONEN) == (PWR_BDCR_MONEN)) ? 1UL : 0UL);
734 }
735
736 /**
737 * @brief Enable battery charging
738 * @rmtoll BDCR VBE LL_PWR_EnableBatteryCharging
739 * @retval None
740 */
LL_PWR_EnableBatteryCharging(void)741 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
742 {
743 SET_BIT(PWR->BDCR, PWR_BDCR_VBE);
744 }
745
746 /**
747 * @brief Disable battery charging
748 * @rmtoll BDCR VBE LL_PWR_DisableBatteryCharging
749 * @retval None
750 */
LL_PWR_DisableBatteryCharging(void)751 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
752 {
753 CLEAR_BIT(PWR->BDCR, PWR_BDCR_VBE);
754 }
755
756 /**
757 * @brief Check if battery charging is enabled
758 * @rmtoll BDCR VBE LL_PWR_IsEnabledBatteryCharging
759 * @retval State of bit (1 or 0).
760 */
LL_PWR_IsEnabledBatteryCharging(void)761 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
762 {
763 return ((READ_BIT(PWR->BDCR, PWR_BDCR_VBE) == (PWR_BDCR_VBE)) ? 1UL : 0UL);
764 }
765
766 /**
767 * @brief Set the Battery charge resistor impedance
768 * @rmtoll BDCR VBRS LL_PWR_SetBattChargResistor
769 * @param Resistor This parameter can be one of the following values:
770 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
771 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
772 * @retval None
773 */
LL_PWR_SetBattChargResistor(uint32_t Resistor)774 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
775 {
776 MODIFY_REG(PWR->BDCR, PWR_BDCR_VBRS, Resistor);
777 }
778
779 /**
780 * @brief Get the Battery charge resistor impedance
781 * @rmtoll BDCR VBRS LL_PWR_GetBattChargResistor
782 * @retval Returned value can be one of the following values:
783 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
784 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
785 */
LL_PWR_GetBattChargResistor(void)786 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
787 {
788 return (uint32_t)(READ_BIT(PWR->BDCR, PWR_BDCR_VBRS));
789 }
790
791 /**
792 * @brief Enable access to the backup domain
793 * @rmtoll DBPCR DBP LL_PWR_EnableBkUpAccess
794 * @retval None
795 */
LL_PWR_EnableBkUpAccess(void)796 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
797 {
798 SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP);
799 }
800
801 /**
802 * @brief Disable access to the backup domain
803 * @rmtoll DBPCR DBP LL_PWR_DisableBkUpAccess
804 * @retval None
805 */
LL_PWR_DisableBkUpAccess(void)806 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
807 {
808 CLEAR_BIT(PWR->DBPCR, PWR_DBPCR_DBP);
809 }
810
811 /**
812 * @brief Check if the backup domain is enabled
813 * @rmtoll DBPCR DBP LL_PWR_IsEnabledBkUpAccess
814 * @retval State of bit (1 or 0).
815 */
LL_PWR_IsEnabledBkUpAccess(void)816 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
817 {
818 return ((READ_BIT(PWR->DBPCR, PWR_DBPCR_DBP) == (PWR_DBPCR_DBP)) ? 1UL : 0UL);
819 }
820
821 #if defined (PWR_UCPDR_UCPD_STBY)
822 /**
823 * @brief Enable the USB type-C and power delivery memorization in Standby
824 * mode.
825 * @note This function must be called just before entering Standby mode.
826 * @rmtoll UCPDR UCPD_STDBY LL_PWR_EnableUCPDStandbyMode
827 * @retval None
828 */
LL_PWR_EnableUCPDStandbyMode(void)829 __STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void)
830 {
831 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY);
832 }
833
834 /**
835 * @brief Disable the USB type-C and power delivery memorization in Standby
836 * mode.
837 * @note This function must be called after exiting Standby mode and before
838 * any UCPD configuration update.
839 * @rmtoll UCPDR UCPD_STDBY LL_PWR_DisableUCPDStandbyMode
840 * @retval None
841 */
LL_PWR_DisableUCPDStandbyMode(void)842 __STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void)
843 {
844 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY);
845 }
846
847 /**
848 * @brief Check if the USB Type-C and Power Delivery Standby mode memorization
849 * is enabled.
850 * @rmtoll UCPDR UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode
851 * @retval State of bit (1 or 0).
852 */
LL_PWR_IsEnabledUCPDStandbyMode(void)853 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void)
854 {
855 return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY) == (PWR_UCPDR_UCPD_STBY)) ? 1UL : 0UL);
856 }
857 #endif /* PWR_UCPDR_UCPD_STBY */
858
859 #if defined (PWR_UCPDR_UCPD_DBDIS)
860 /**
861 * @brief Enable the USB Type-C and power delivery dead battery pull-down behavior
862 * on UCPD CC1 and CC2 pins.
863 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
864 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
865 * to disable it in all cases, either to stop this pull-down or to hand over
866 * control to the UCPD (which should therefore be initialized before doing the disable).
867 * @rmtoll UCPDR UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery
868 * @retval None
869 */
LL_PWR_EnableUCPDDeadBattery(void)870 __STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void)
871 {
872 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
873 }
874
875 /**
876 * @brief Disable the USB Type-C and power delivery dead battery pull-down behavior
877 * on UCPD CC1 and CC2 pins.
878 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
879 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
880 * to disable it in all cases, either to stop this pull-down or to hand over
881 * control to the UCPD (which should therefore be initialized before doing the disable).
882 * @rmtoll UCPDR UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery
883 * @retval None
884 */
LL_PWR_DisableUCPDDeadBattery(void)885 __STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void)
886 {
887 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
888 }
889
890 /**
891 * @brief Check the USB Type-C and power delivery dead battery pull-down behavior
892 * on UCPD CC1 and CC2 pins.
893 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
894 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
895 * to disable it in all cases, either to stop this pull-down or to hand over
896 * control to the UCPD (which should therefore be initialized before doing the disable).
897 * @rmtoll UCPDR UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
898 * @retval State of feature (1 : enabled; 0 : disabled).
899 */
LL_PWR_IsEnabledUCPDDeadBattery(void)900 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
901 {
902 return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS) == (PWR_UCPDR_UCPD_DBDIS)) ? 0UL : 1UL);
903 }
904 #endif /* PWR_UCPDR_UCPD_DBDIS */
905
906 /**
907 * @brief Configure the PWR supply
908 * @rmtoll SCCR BYPASS LL_PWR_ConfigSupply
909 * @param SupplySource This parameter can be one of the following values:
910 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
911 * @retval None
912 */
LL_PWR_ConfigSupply(uint32_t SupplySource)913 __STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
914 {
915 /* Set the power supply configuration */
916 MODIFY_REG(PWR->SCCR, (PWR_SCCR_BYPASS), SupplySource);
917 }
918
919 /**
920 * @brief Get the PWR supply
921 * @rmtoll SCCR BYPASS LL_PWR_GetSupply
922 * @retval The supply configuration.
923 */
LL_PWR_GetSupply(void)924 __STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
925 {
926 #if defined (PWR_SCCR_SMPSEN)
927 /* Get the power supply configuration */
928 return (uint32_t)(READ_BIT(PWR->SCCR, (PWR_SCCR_SMPSEN | PWR_SCCR_LDOEN | PWR_SCCR_BYPASS)));
929 #else
930 /* Get the power supply configuration */
931 return (uint32_t)(READ_BIT(PWR->SCCR, (PWR_SCCR_LDOEN | PWR_SCCR_BYPASS)));
932 #endif /* PWR_SCCR_SMPSEN */
933 }
934
935 /**
936 * @brief Enable Power Voltage Detector
937 * @rmtoll VMCR PVDEN LL_PWR_EnablePVD
938 * @retval None
939 */
LL_PWR_EnablePVD(void)940 __STATIC_INLINE void LL_PWR_EnablePVD(void)
941 {
942 SET_BIT(PWR->VMCR, PWR_VMCR_PVDEN);
943 }
944
945 /**
946 * @brief Disable Power Voltage Detector
947 * @rmtoll VMCR PVDEN LL_PWR_DisablePVD
948 * @retval None
949 */
LL_PWR_DisablePVD(void)950 __STATIC_INLINE void LL_PWR_DisablePVD(void)
951 {
952 CLEAR_BIT(PWR->VMCR, PWR_VMCR_PVDEN);
953 }
954
955 /**
956 * @brief Check if Power Voltage Detector is enabled
957 * @rmtoll VMCR PVDEN LL_PWR_IsEnabledPVD
958 * @retval State of bit (1 or 0).
959 */
LL_PWR_IsEnabledPVD(void)960 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
961 {
962 return ((READ_BIT(PWR->VMCR, PWR_VMCR_PVDEN) == (PWR_VMCR_PVDEN)) ? 1UL : 0UL);
963 }
964
965 /**
966 * @brief Configure the voltage threshold detected by the Power Voltage Detector
967 * @rmtoll VMCR PLS LL_PWR_SetPVDLevel
968 * @param PVDLevel This parameter can be one of the following values:
969 * @arg @ref LL_PWR_PVDLEVEL_0
970 * @arg @ref LL_PWR_PVDLEVEL_1
971 * @arg @ref LL_PWR_PVDLEVEL_2
972 * @arg @ref LL_PWR_PVDLEVEL_3
973 * @arg @ref LL_PWR_PVDLEVEL_4
974 * @arg @ref LL_PWR_PVDLEVEL_5
975 * @arg @ref LL_PWR_PVDLEVEL_6
976 * @arg @ref LL_PWR_PVDLEVEL_7
977 * @retval None
978 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)979 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
980 {
981 MODIFY_REG(PWR->VMCR, PWR_VMCR_PLS, PVDLevel);
982 }
983
984 /**
985 * @brief Get the voltage threshold detection
986 * @rmtoll VMCR PLS LL_PWR_GetPVDLevel
987 * @retval Returned value can be one of the following values:
988 * @arg @ref LL_PWR_PVDLEVEL_0
989 * @arg @ref LL_PWR_PVDLEVEL_1
990 * @arg @ref LL_PWR_PVDLEVEL_2
991 * @arg @ref LL_PWR_PVDLEVEL_3
992 * @arg @ref LL_PWR_PVDLEVEL_4
993 * @arg @ref LL_PWR_PVDLEVEL_5
994 * @arg @ref LL_PWR_PVDLEVEL_6
995 * @arg @ref LL_PWR_PVDLEVEL_7
996 */
LL_PWR_GetPVDLevel(void)997 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
998 {
999 return (uint32_t)(READ_BIT(PWR->VMCR, PWR_VMCR_PLS));
1000 }
1001
1002
1003 /**
1004 * @brief Enable Analog Power Voltage Detector
1005 * @rmtoll VMCR AVDEN LL_PWR_EnableAVD
1006 * @retval None
1007 */
LL_PWR_EnableAVD(void)1008 __STATIC_INLINE void LL_PWR_EnableAVD(void)
1009 {
1010 SET_BIT(PWR->VMCR, PWR_VMCR_AVDEN);
1011 }
1012
1013 /**
1014 * @brief Disable Analog Power Voltage Detector
1015 * @rmtoll VMCR AVDEN LL_PWR_DisableAVD
1016 * @retval None
1017 */
LL_PWR_DisableAVD(void)1018 __STATIC_INLINE void LL_PWR_DisableAVD(void)
1019 {
1020 CLEAR_BIT(PWR->VMCR, PWR_VMCR_AVDEN);
1021 }
1022
1023 /**
1024 * @brief Check if Analog Power Voltage Detector is enabled
1025 * @rmtoll VMCR AVDEN LL_PWR_IsEnabledAVD
1026 * @retval State of bit (1 or 0).
1027 */
LL_PWR_IsEnabledAVD(void)1028 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void)
1029 {
1030 return ((READ_BIT(PWR->VMCR, PWR_VMCR_AVDEN) == (PWR_VMCR_AVDEN)) ? 1UL : 0UL);
1031 }
1032
1033 /**
1034 * @brief Configure the voltage threshold to be detected by the Analog Power Voltage Detector
1035 * @rmtoll VMCR ALS LL_PWR_SetAVDLevel
1036 * @param AVDLevel This parameter can be one of the following values:
1037 * @arg @ref LL_PWR_AVDLEVEL_0
1038 * @arg @ref LL_PWR_AVDLEVEL_1
1039 * @arg @ref LL_PWR_AVDLEVEL_2
1040 * @arg @ref LL_PWR_AVDLEVEL_3
1041 * @retval None
1042 */
LL_PWR_SetAVDLevel(uint32_t AVDLevel)1043 __STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel)
1044 {
1045 MODIFY_REG(PWR->VMCR, PWR_VMCR_ALS, AVDLevel);
1046 }
1047
1048 /**
1049 * @brief Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector
1050 * @rmtoll CR1 ALS LL_PWR_GetAVDLevel
1051 * @retval Returned value can be one of the following values:
1052 * @arg @ref LL_PWR_AVDLEVEL_0
1053 * @arg @ref LL_PWR_AVDLEVEL_1
1054 * @arg @ref LL_PWR_AVDLEVEL_2
1055 * @arg @ref LL_PWR_AVDLEVEL_3
1056 */
LL_PWR_GetAVDLevel(void)1057 __STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void)
1058 {
1059 return (uint32_t)(READ_BIT(PWR->VMCR, PWR_VMCR_ALS));
1060 }
1061
1062 #if defined (PWR_USBSCR_USB33DEN)
1063 /**
1064 * @brief Enable the USB voltage detector
1065 * @rmtoll USBSCR USB33DEN LL_PWR_EnableUSBVoltageDetector
1066 * @retval None
1067 */
LL_PWR_EnableUSBVoltageDetector(void)1068 __STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void)
1069 {
1070 SET_BIT(PWR->USBSCR, PWR_USBSCR_USB33DEN);
1071 }
1072
1073 /**
1074 * @brief Disable the USB voltage detector
1075 * @rmtoll USBSCR USB33DEN LL_PWR_DisableUSBVoltageDetector
1076 * @retval None
1077 */
LL_PWR_DisableUSBVoltageDetector(void)1078 __STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void)
1079 {
1080 CLEAR_BIT(PWR->USBSCR, PWR_USBSCR_USB33DEN);
1081 }
1082
1083 /**
1084 * @brief Check if the USB voltage detector is enabled
1085 * @rmtoll USBSCR USB33DEN LL_PWR_IsEnabledUSBVoltageDetector
1086 * @retval State of bit (1 or 0).
1087 */
LL_PWR_IsEnabledUSBVoltageDetector(void)1088 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void)
1089 {
1090 return ((READ_BIT(PWR->USBSCR, PWR_USBSCR_USB33DEN) == (PWR_USBSCR_USB33DEN)) ? 1UL : 0UL);
1091 }
1092
1093 /**
1094 * @brief Enable the independent USB supply.
1095 * @rmtoll USBSCR USB33SV LL_PWR_EnableVDDUSB
1096 * @retval None
1097 */
LL_PWR_EnableVDDUSB(void)1098 __STATIC_INLINE void LL_PWR_EnableVDDUSB(void)
1099 {
1100 SET_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV);
1101 }
1102
1103 /**
1104 * @brief Disable the independent USB supply.
1105 * @rmtoll USBSCR USB33SV LL_PWR_DisableVDDUSB
1106 * @retval None
1107 */
LL_PWR_DisableVDDUSB(void)1108 __STATIC_INLINE void LL_PWR_DisableVDDUSB(void)
1109 {
1110 CLEAR_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV);
1111 }
1112
1113 /**
1114 * @brief Check if the independent USB supply is enabled.
1115 * @rmtoll USBSCR USB33SV LL_PWR_IsEnabledVDDUSB
1116 * @retval State of bit (1 or 0).
1117 */
LL_PWR_IsEnabledVDDUSB(void)1118 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDUSB(void)
1119 {
1120 return ((READ_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV) == (PWR_USBSCR_USB33SV)) ? 1UL : 0UL);
1121 }
1122 #endif /* PWR_USBSCR_USB33DEN */
1123
1124 /**
1125 * @brief Enable the wake up pin_x.
1126 * @rmtoll WUCR WUPENx LL_PWR_EnableWakeUpPin
1127 * @param WakeUpPin This parameter can be a combination of the following values:
1128 * @arg @ref LL_PWR_WAKEUP_PIN1
1129 * @arg @ref LL_PWR_WAKEUP_PIN2
1130 * @arg @ref LL_PWR_WAKEUP_PIN3
1131 * @arg @ref LL_PWR_WAKEUP_PIN4
1132 * @arg @ref LL_PWR_WAKEUP_PIN5
1133 * @arg @ref LL_PWR_WAKEUP_PIN6
1134 * @arg @ref LL_PWR_WAKEUP_PIN7
1135 * @arg @ref LL_PWR_WAKEUP_PIN8
1136 * @retval None
1137 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)1138 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
1139 {
1140 SET_BIT(PWR->WUCR, WakeUpPin);
1141 }
1142
1143 /**
1144 * @brief Disable the wake up pin_x.
1145 * @rmtoll WUCR WUPENx LL_PWR_DisableWakeUpPin
1146 * @param WakeUpPin This parameter can be a combination of the following values:
1147 * @arg @ref LL_PWR_WAKEUP_PIN1
1148 * @arg @ref LL_PWR_WAKEUP_PIN2
1149 * @arg @ref LL_PWR_WAKEUP_PIN3
1150 * @arg @ref LL_PWR_WAKEUP_PIN4
1151 * @arg @ref LL_PWR_WAKEUP_PIN5
1152 * @arg @ref LL_PWR_WAKEUP_PIN6
1153 * @arg @ref LL_PWR_WAKEUP_PIN7
1154 * @arg @ref LL_PWR_WAKEUP_PIN8
1155 * @retval None
1156 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)1157 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
1158 {
1159 CLEAR_BIT(PWR->WUCR, WakeUpPin);
1160 }
1161
1162 /**
1163 * @brief Check if the wake up pin_x is enabled.
1164 * @rmtoll WUCR WUPPx LL_PWR_IsEnabledWakeUpPin
1165 * @param WakeUpPin This parameter can be one of the following values:
1166 * @arg @ref LL_PWR_WAKEUP_PIN1
1167 * @arg @ref LL_PWR_WAKEUP_PIN2
1168 * @arg @ref LL_PWR_WAKEUP_PIN3
1169 * @arg @ref LL_PWR_WAKEUP_PIN4
1170 * @arg @ref LL_PWR_WAKEUP_PIN5
1171 * @arg @ref LL_PWR_WAKEUP_PIN6
1172 * @arg @ref LL_PWR_WAKEUP_PIN7
1173 * @arg @ref LL_PWR_WAKEUP_PIN8
1174 * @retval State of bit (1 or 0).
1175 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)1176 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
1177 {
1178 return ((READ_BIT(PWR->WUCR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1179 }
1180
1181 /**
1182 * @brief Set the Wake-Up pin polarity low for the event detection
1183 * @rmtoll WUCR WKUPP1 LL_PWR_SetWakeUpPinPolarityLow\n
1184 * WUCR WKUPP2 LL_PWR_SetWakeUpPinPolarityLow\n
1185 * WUCR WKUPP3 LL_PWR_SetWakeUpPinPolarityLow\n
1186 * WUCR WKUPP4 LL_PWR_SetWakeUpPinPolarityLow\n
1187 * WUCR WKUPP5 LL_PWR_SetWakeUpPinPolarityLow\n
1188 * WUCR WKUPP6 LL_PWR_SetWakeUpPinPolarityLow\n
1189 * WUCR WKUPP7 LL_PWR_SetWakeUpPinPolarityLow\n
1190 * WUCR WKUPP8 LL_PWR_SetWakeUpPinPolarityLow
1191 * @param WakeUpPin This parameter can be one of the following values:
1192 * @arg @ref LL_PWR_WAKEUP_PIN1
1193 * @arg @ref LL_PWR_WAKEUP_PIN2
1194 * @arg @ref LL_PWR_WAKEUP_PIN3
1195 * @arg @ref LL_PWR_WAKEUP_PIN4
1196 * @arg @ref LL_PWR_WAKEUP_PIN5
1197 * @arg @ref LL_PWR_WAKEUP_PIN6
1198 * @arg @ref LL_PWR_WAKEUP_PIN7
1199 * @arg @ref LL_PWR_WAKEUP_PIN8
1200 * @retval None
1201 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)1202 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
1203 {
1204 SET_BIT(PWR->WUCR, (WakeUpPin << PWR_WUCR_WUPP1_Pos));
1205 }
1206
1207 /**
1208 * @brief Set the Wake-Up pin polarity high for the event detection
1209 * @rmtoll WUCR WKUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n
1210 * WUCR WKUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n
1211 * WUCR WKUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n
1212 * WUCR WKUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n
1213 * WUCR WKUPP5 LL_PWR_SetWakeUpPinPolarityHigh\n
1214 * WUCR WKUPP6 LL_PWR_SetWakeUpPinPolarityHigh\n
1215 * WUCR WKUPP7 LL_PWR_SetWakeUpPinPolarityHigh\n
1216 * WUCR WKUPP8 LL_PWR_SetWakeUpPinPolarityHigh
1217 * @param WakeUpPin This parameter can be one of the following values:
1218 * @arg @ref LL_PWR_WAKEUP_PIN1
1219 * @arg @ref LL_PWR_WAKEUP_PIN2
1220 * @arg @ref LL_PWR_WAKEUP_PIN3
1221 * @arg @ref LL_PWR_WAKEUP_PIN4
1222 * @arg @ref LL_PWR_WAKEUP_PIN5
1223 * @arg @ref LL_PWR_WAKEUP_PIN6
1224 * @arg @ref LL_PWR_WAKEUP_PIN7
1225 * @arg @ref LL_PWR_WAKEUP_PIN8
1226 * @retval None
1227 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)1228 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
1229 {
1230 CLEAR_BIT(PWR->WUCR, (WakeUpPin << PWR_WUCR_WUPP1_Pos));
1231 }
1232
1233 /**
1234 * @brief Get the Wake-Up pin polarity for the event detection
1235 * @rmtoll WUCR WUPP1 LL_PWR_SetWakeUpPinPolarityLow\n
1236 * WUCR WUPP2 LL_PWR_SetWakeUpPinPolarityLow\n
1237 * WUCR WUPP3 LL_PWR_SetWakeUpPinPolarityLow\n
1238 * WUCR WUPP4 LL_PWR_SetWakeUpPinPolarityLow\n
1239 * WUCR WUPP5 LL_PWR_SetWakeUpPinPolarityLow\n
1240 * WUCR WUPP6 LL_PWR_SetWakeUpPinPolarityLow\n
1241 * WUCR WUPP7 LL_PWR_SetWakeUpPinPolarityLow\n
1242 * WUCR WUPP8 LL_PWR_SetWakeUpPinPolarityLow
1243 * @param WakeUpPin This parameter can be one of the following values:
1244 * @arg @ref LL_PWR_WAKEUP_PIN1
1245 * @arg @ref LL_PWR_WAKEUP_PIN2
1246 * @arg @ref LL_PWR_WAKEUP_PIN3
1247 * @arg @ref LL_PWR_WAKEUP_PIN4
1248 * @arg @ref LL_PWR_WAKEUP_PIN5
1249 * @arg @ref LL_PWR_WAKEUP_PIN6
1250 * @arg @ref LL_PWR_WAKEUP_PIN7
1251 * @arg @ref LL_PWR_WAKEUP_PIN8
1252 * @retval State of bit (1 or 0).
1253 */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)1254 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
1255 {
1256 return ((READ_BIT(PWR->WUCR, (WakeUpPin << PWR_WUCR_WUPP1_Pos)) == (WakeUpPin << PWR_WUCR_WUPP1_Pos)) ? 1UL : 0UL);
1257 }
1258
1259 /**
1260 * @brief Set the Wake-Up pin Pull None
1261 * @rmtoll WUCR WUPPUPD1 LL_PWR_SetWakeUpPinPullNone\n
1262 * WUCR WUPPUPD2 LL_PWR_SetWakeUpPinPullNone\n
1263 * WUCR WUPPUPD3 LL_PWR_SetWakeUpPinPullNone\n
1264 * WUCR WUPPUPD4 LL_PWR_SetWakeUpPinPullNone\n
1265 * WUCR WUPPUPD5 LL_PWR_SetWakeUpPinPullNone\n
1266 * WUCR WUPPUPD6 LL_PWR_SetWakeUpPinPullNone\n
1267 * WUCR WUPPUPD7 LL_PWR_SetWakeUpPinPullNone\n
1268 * WUCR WUPPUPD8 LL_PWR_SetWakeUpPinPullNone
1269 * @param WakeUpPin This parameter can be one of the following values:
1270 * @arg @ref LL_PWR_WAKEUP_PIN1
1271 * @arg @ref LL_PWR_WAKEUP_PIN2
1272 * @arg @ref LL_PWR_WAKEUP_PIN3
1273 * @arg @ref LL_PWR_WAKEUP_PIN4
1274 * @arg @ref LL_PWR_WAKEUP_PIN5
1275 * @arg @ref LL_PWR_WAKEUP_PIN6
1276 * @arg @ref LL_PWR_WAKEUP_PIN7
1277 * @arg @ref LL_PWR_WAKEUP_PIN8
1278 *
1279 * @retval None
1280 */
LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)1281 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
1282 {
1283 MODIFY_REG(PWR->WUCR,
1284 (PWR_WUCR_WUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * (POSITION_VAL(WakeUpPin) & 0xFU)) & \
1285 LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)),
1286 (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WUCR_WUPPUPD1_Pos + ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \
1287 POSITION_VAL(WakeUpPin)) & 0xFU)) & \
1288 LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1289 }
1290
1291 /**
1292 * @brief Set the Wake-Up pin Pull Up
1293 * @rmtoll WUCR WUPPUPD1 LL_PWR_SetWakeUpPinPullUp\n
1294 * WUCR WUPPUPD2 LL_PWR_SetWakeUpPinPullUp\n
1295 * WUCR WUPPUPD3 LL_PWR_SetWakeUpPinPullUp\n
1296 * WUCR WUPPUPD4 LL_PWR_SetWakeUpPinPullUp\n
1297 * WUCR WUPPUPD5 LL_PWR_SetWakeUpPinPullUp\n
1298 * WUCR WUPPUPD6 LL_PWR_SetWakeUpPinPullUp\n
1299 * WUCR WUPPUPD7 LL_PWR_SetWakeUpPinPullUp\n
1300 * WUCR WUPPUPD8 LL_PWR_SetWakeUpPinPullUp
1301 * @param WakeUpPin This parameter can be one of the following values:
1302 * @arg @ref LL_PWR_WAKEUP_PIN1
1303 * @arg @ref LL_PWR_WAKEUP_PIN2
1304 * @arg @ref LL_PWR_WAKEUP_PIN3
1305 * @arg @ref LL_PWR_WAKEUP_PIN4
1306 * @arg @ref LL_PWR_WAKEUP_PIN5
1307 * @arg @ref LL_PWR_WAKEUP_PIN6
1308 * @arg @ref LL_PWR_WAKEUP_PIN7
1309 * @arg @ref LL_PWR_WAKEUP_PIN8
1310 *
1311 *
1312 * @retval None
1313 */
LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)1314 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
1315 {
1316 MODIFY_REG(PWR->WUCR,
1317 (PWR_WUCR_WUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * (POSITION_VAL(WakeUpPin) & 0xFU)) & \
1318 LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)),
1319 (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WUCR_WUPPUPD1_Pos + ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \
1320 POSITION_VAL(WakeUpPin)) & 0xFU)) & \
1321 LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1322 }
1323
1324 /**
1325 * @brief Set the Wake-Up pin Pull Down
1326 * @rmtoll WUCR WUPPUPD1 LL_PWR_SetWakeUpPinPullDown\n
1327 * WUCR WUPPUPD2 LL_PWR_SetWakeUpPinPullDown\n
1328 * WUCR WUPPUPD3 LL_PWR_SetWakeUpPinPullDown\n
1329 * WUCR WUPPUPD4 LL_PWR_SetWakeUpPinPullDown\n
1330 * WUCR WUPPUPD5 LL_PWR_SetWakeUpPinPullDown\n
1331 * WUCR WUPPUPD6 LL_PWR_SetWakeUpPinPullDown\n
1332 * WUCR WUPPUPD7 LL_PWR_SetWakeUpPinPullDown\n
1333 * WUCR WUPPUPD8 LL_PWR_SetWakeUpPinPullDown
1334 * @param WakeUpPin This parameter can be one of the following values:
1335 * @arg @ref LL_PWR_WAKEUP_PIN1
1336 * @arg @ref LL_PWR_WAKEUP_PIN2
1337 * @arg @ref LL_PWR_WAKEUP_PIN3
1338 * @arg @ref LL_PWR_WAKEUP_PIN4
1339 * @arg @ref LL_PWR_WAKEUP_PIN5
1340 * @arg @ref LL_PWR_WAKEUP_PIN6
1341 * @arg @ref LL_PWR_WAKEUP_PIN7
1342 * @arg @ref LL_PWR_WAKEUP_PIN8
1343 *
1344 * @retval None
1345 */
LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)1346 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
1347 {
1348 MODIFY_REG(PWR->WUCR,
1349 (PWR_WUCR_WUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * (POSITION_VAL(WakeUpPin) & 0xFU)) & \
1350 LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)),
1351 (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WUCR_WUPPUPD1_Pos + ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \
1352 POSITION_VAL(WakeUpPin)) & 0xFU)) & \
1353 LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1354 }
1355
1356 /**
1357 * @brief Get the Wake-Up pin pull
1358 * @rmtoll WUCR WUPPUPD1 LL_PWR_GetWakeUpPinPull\n
1359 * WUCR WUPPUPD2 LL_PWR_GetWakeUpPinPull\n
1360 * WUCR WUPPUPD3 LL_PWR_GetWakeUpPinPull\n
1361 * WUCR WUPPUPD4 LL_PWR_GetWakeUpPinPull\n
1362 * WUCR WUPPUPD5 LL_PWR_GetWakeUpPinPull\n
1363 * WUCR WUPPUPD7 LL_PWR_GetWakeUpPinPull\n
1364 * WUCR WUPPUPD7 LL_PWR_GetWakeUpPinPull\n
1365 * WUCR WUPPUPD8 LL_PWR_GetWakeUpPinPull
1366 * @param WakeUpPin This parameter can be one of the following values:
1367 * @arg @ref LL_PWR_WAKEUP_PIN1
1368 * @arg @ref LL_PWR_WAKEUP_PIN2
1369 * @arg @ref LL_PWR_WAKEUP_PIN3
1370 * @arg @ref LL_PWR_WAKEUP_PIN4
1371 * @arg @ref LL_PWR_WAKEUP_PIN5
1372 * @arg @ref LL_PWR_WAKEUP_PIN6
1373 * @arg @ref LL_PWR_WAKEUP_PIN7
1374 * @arg @ref LL_PWR_WAKEUP_PIN8
1375 *
1376 * @retval Returned value can be one of the following values:
1377 * @arg @ref LL_PWR_WAKEUP_PIN_NOPULL
1378 * @arg @ref LL_PWR_WAKEUP_PIN_PULLUP
1379 * @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN
1380 */
LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)1381 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
1382 {
1383 uint32_t regValue = READ_BIT(PWR->WUCR, (PWR_WUCR_WUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \
1384 (POSITION_VAL(WakeUpPin) & 0xFU)) & \
1385 LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1386
1387 return (uint32_t)(regValue >> ((PWR_WUCR_WUPPUPD1_Pos + ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * \
1388 POSITION_VAL(WakeUpPin)) & 0xFU)) & \
1389 LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
1390 }
1391
1392 /**
1393 * @brief Enable IO Retention
1394 * @rmtoll IORETR IORETEN LL_PWR_EnableIORetention
1395 * @retval None
1396 */
LL_PWR_EnableIORetention(void)1397 __STATIC_INLINE void LL_PWR_EnableIORetention(void)
1398 {
1399 SET_BIT(PWR->IORETR, PWR_IORETR_IORETEN);
1400 }
1401
1402 /**
1403 * @brief Disable IO Retention
1404 * @rmtoll IORETR IORETEN LL_PWR_DisableIORetention
1405 * @retval None
1406 */
LL_PWR_DisableIORetention(void)1407 __STATIC_INLINE void LL_PWR_DisableIORetention(void)
1408 {
1409 CLEAR_BIT(PWR->IORETR, PWR_IORETR_IORETEN);
1410 }
1411
1412 /**
1413 * @brief Check if IO Retention is enabled
1414 * @rmtoll IORETR IORETEN LL_PWR_IsEnabledIORetention
1415 * @retval State of bit (1 or 0).
1416 */
LL_PWR_IsEnabledIORetention(void)1417 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIORetention(void)
1418 {
1419 return ((READ_BIT(PWR->IORETR, PWR_IORETR_IORETEN) == (PWR_IORETR_IORETEN)) ? 1UL : 0UL);
1420 }
1421
1422 /**
1423 * @brief Enable JTAGIO Retention
1424 * @rmtoll JTAGIORETR JTAGIORETEN LL_PWR_EnableJTAGIORetention
1425 * @retval None
1426 */
LL_PWR_EnableJTAGIORetention(void)1427 __STATIC_INLINE void LL_PWR_EnableJTAGIORetention(void)
1428 {
1429 SET_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN);
1430 }
1431
1432 /**
1433 * @brief Disable JTAGIO Retention
1434 * @rmtoll JTAGIORETR JTAGIORETEN LL_PWR_DisableJTAGIORetention
1435 * @retval None
1436 */
LL_PWR_DisableJTAGIORetention(void)1437 __STATIC_INLINE void LL_PWR_DisableJTAGIORetention(void)
1438 {
1439 CLEAR_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN);
1440 }
1441
1442 /**
1443 * @brief Check if JTAGIO Retention is enabled
1444 * @rmtoll IORETR JTAGIORETEN LL_PWR_IsEnabledJTAGIORetention
1445 * @retval State of bit (1 or 0).
1446 */
LL_PWR_IsEnabledJTAGIORetention(void)1447 __STATIC_INLINE uint32_t LL_PWR_IsEnabledJTAGIORetention(void)
1448 {
1449 return ((READ_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN) == (PWR_IORETR_JTAGIORETEN)) ? 1UL : 0UL);
1450 }
1451 /**
1452 * @}
1453 */
1454
1455 /** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management
1456 * @{
1457 */
1458
1459 /**
1460 * @brief Indicate whether the regulator voltage output is above voltage
1461 * scaling range or not.
1462 * @rmtoll VOSSR VOSRDY LL_PWR_IsActiveFlag_VOS
1463 * @retval State of bit (1 or 0).
1464 */
LL_PWR_IsActiveFlag_VOS(void)1465 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
1466 {
1467 return ((READ_BIT(PWR->VOSSR, PWR_VOSSR_VOSRDY) == (PWR_VOSSR_VOSRDY)) ? 1UL : 0UL);
1468 }
1469
1470 /**
1471 * @brief Indicate whether the system was in standby mode or not.
1472 * @rmtoll PMSR SBF LL_PWR_IsActiveFlag_SB
1473 * @retval State of bit (1 or 0).
1474 */
LL_PWR_IsActiveFlag_SB(void)1475 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
1476 {
1477 return ((READ_BIT(PWR->PMSR, PWR_PMSR_SBF) == (PWR_PMSR_SBF)) ? 1UL : 0UL);
1478 }
1479
1480 /**
1481 * @brief Indicate whether the system was in stop mode or not.
1482 * @rmtoll PMSR STOPF LL_PWR_IsActiveFlag_STOP
1483 * @retval State of bit (1 or 0).
1484 */
LL_PWR_IsActiveFlag_STOP(void)1485 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void)
1486 {
1487 return ((READ_BIT(PWR->PMSR, PWR_PMSR_STOPF) == (PWR_PMSR_STOPF)) ? 1UL : 0UL);
1488 }
1489
1490 /**
1491 * @brief Indicate whether the VDD voltage is below the threshold or not.
1492 * @rmtoll VMSR PVDO LL_PWR_IsActiveFlag_PVDO
1493 * @retval State of bit (1 or 0).
1494 */
LL_PWR_IsActiveFlag_PVDO(void)1495 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1496 {
1497 return ((READ_BIT(PWR->VMSR, PWR_VMSR_PVDO) == (PWR_VMSR_PVDO)) ? 1UL : 0UL);
1498 }
1499
1500 /**
1501 * @brief Indicate whether the VDD voltage is below the threshold or not.
1502 * @rmtoll VMSR AVDO LL_PWR_IsActiveFlag_AVDO
1503 * @retval State of bit (1 or 0).
1504 */
LL_PWR_IsActiveFlag_AVDO(void)1505 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void)
1506 {
1507 return ((READ_BIT(PWR->VMSR, PWR_VMSR_PVDO) == (PWR_VMSR_AVDO)) ? 1UL : 0UL);
1508 }
1509
1510 /**
1511 * @brief Indicate whether the regulator voltage output is equal to current
1512 * used voltage scaling range or not.
1513 * @rmtoll VOSSR ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS
1514 * @retval State of bit (1 or 0).
1515 */
LL_PWR_IsActiveFlag_ACTVOS(void)1516 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
1517 {
1518 return ((READ_BIT(PWR->VOSSR, PWR_VOSSR_ACTVOSRDY) == (PWR_VOSSR_ACTVOSRDY)) ? 1UL : 0UL);
1519 }
1520
1521 #if defined (PWR_VMSR_USB33RDY)
1522 /**
1523 * @brief Indicate whether the VDDUSB is below the threshold of monitor or not.
1524 * @rmtoll VMSR USB33RDY LL_PWR_IsActiveFlag_VDDUSB
1525 * @retval State of bit (1 or 0).
1526 */
LL_PWR_IsActiveFlag_VDDUSB(void)1527 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDUSB(void)
1528 {
1529 return ((READ_BIT(PWR->VMSR, PWR_VMSR_USB33RDY) == (PWR_VMSR_USB33RDY)) ? 1UL : 0UL);
1530 }
1531 #endif /* PWR_VMSR_USB33RDY */
1532
1533 /**
1534 * @brief Indicate whether VDDMMC voltage is below 1V2
1535 * @rmtoll VMSR VDDIO2RDY LL_PWR_IsActiveFlag_VDDIO2
1536 * @retval State of bit (1 or 0).
1537 */
LL_PWR_IsActiveFlag_VDDIO2(void)1538 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO2(void)
1539 {
1540 return ((READ_BIT(PWR->VMCR, PWR_VMSR_VDDIO2RDY) == (PWR_VMSR_VDDIO2RDY)) ? 1UL : 0UL);
1541 }
1542
1543 /**
1544 * @brief Get Backup Regulator ready Flag
1545 * @rmtoll BDSR BRRDY LL_PWR_IsActiveFlag_BRR
1546 * @retval State of bit (1 or 0).
1547 */
LL_PWR_IsActiveFlag_BRR(void)1548 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
1549 {
1550 return ((READ_BIT(PWR->BDSR, PWR_BDSR_BRRDY) == (PWR_BDSR_BRRDY)) ? 1UL : 0UL);
1551 }
1552
1553 /**
1554 * @brief Indicate whether the VBAT level is below high threshold or not.
1555 * @rmtoll BDSR VBATL LL_PWR_IsActiveFlag_VBATL
1556 * @retval State of bit (1 or 0).
1557 */
LL_PWR_IsActiveFlag_VBATL(void)1558 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void)
1559 {
1560 return ((READ_BIT(PWR->BDSR, PWR_BDSR_VBATL) == (PWR_BDSR_VBATL)) ? 1UL : 0UL);
1561 }
1562
1563 /**
1564 * @brief Indicate whether the VBAT level is below high threshold or not.
1565 * @rmtoll BDSR VBATH LL_PWR_IsActiveFlag_VBATH
1566 * @retval State of bit (1 or 0).
1567 */
LL_PWR_IsActiveFlag_VBATH(void)1568 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
1569 {
1570 return ((READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == (PWR_BDSR_VBATH)) ? 1UL : 0UL);
1571 }
1572
1573 /**
1574 * @brief Indicate whether the CPU temperature level is above low threshold or
1575 * not.
1576 * @rmtoll BDSR TEMPL LL_PWR_IsActiveFlag_TEMPL
1577 * @retval State of bit (1 or 0).
1578 */
LL_PWR_IsActiveFlag_TEMPL(void)1579 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
1580 {
1581 return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == (PWR_BDSR_TEMPL)) ? 1UL : 0UL);
1582 }
1583
1584 /**
1585 * @brief Indicate whether the CPU temperature level is below high threshold
1586 * or not.
1587 * @rmtoll BDSR TEMPH LL_PWR_IsActiveFlag_TEMPH
1588 * @retval State of bit (1 or 0).
1589 */
LL_PWR_IsActiveFlag_TEMPH(void)1590 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
1591 {
1592 return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == (PWR_BDSR_TEMPH)) ? 1UL : 0UL);
1593 }
1594
1595 /**
1596 * @brief Indicate whether a wakeup event is detected on wake up pin 1.
1597 * @rmtoll WUSR WUF1 LL_PWR_IsActiveFlag_WU1
1598 * @retval State of bit (1 or 0).
1599 */
LL_PWR_IsActiveFlag_WU1(void)1600 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1601 {
1602 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == (PWR_WUSR_WUF1)) ? 1UL : 0UL);
1603 }
1604
1605 /**
1606 * @brief Indicate whether a wakeup event is detected on wake up pin 2.
1607 * @rmtoll WUSR WUF2 LL_PWR_IsActiveFlag_WU2
1608 * @retval State of bit (1 or 0).
1609 */
LL_PWR_IsActiveFlag_WU2(void)1610 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1611 {
1612 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == (PWR_WUSR_WUF2)) ? 1UL : 0UL);
1613 }
1614
1615 /**
1616 * @brief Indicate whether a wakeup event is detected on wake up pin 3.
1617 * @rmtoll WUSR WUF3 LL_PWR_IsActiveFlag_WU3
1618 * @retval State of bit (1 or 0).
1619 */
LL_PWR_IsActiveFlag_WU3(void)1620 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1621 {
1622 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == (PWR_WUSR_WUF3)) ? 1UL : 0UL);
1623 }
1624
1625 /**
1626 * @brief Indicate whether a wakeup event is detected on wake up pin 4.
1627 * @rmtoll WUSR WUF4 LL_PWR_IsActiveFlag_WU4
1628 * @retval State of bit (1 or 0).
1629 */
LL_PWR_IsActiveFlag_WU4(void)1630 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1631 {
1632 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == (PWR_WUSR_WUF4)) ? 1UL : 0UL);
1633 }
1634
1635 /**
1636 * @brief Indicate whether a wakeup event is detected on wake up pin 5.
1637 * @rmtoll WUSR WUF5 LL_PWR_IsActiveFlag_WU5
1638 * @retval State of bit (1 or 0).
1639 */
LL_PWR_IsActiveFlag_WU5(void)1640 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
1641 {
1642 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == (PWR_WUSR_WUF5)) ? 1UL : 0UL);
1643 }
1644
1645 #if defined (PWR_WUSR_WUF6)
1646 /**
1647 * @brief Indicate whether a wakeup event is detected on wake up pin 6.
1648 * @rmtoll WUSR WUF6 LL_PWR_IsActiveFlag_WU6
1649 * @retval State of bit (1 or 0).
1650 */
LL_PWR_IsActiveFlag_WU6(void)1651 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
1652 {
1653 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == (PWR_WUSR_WUF6)) ? 1UL : 0UL);
1654 }
1655 #endif /* PWR_WUSR_WUF6 */
1656
1657 #if defined (PWR_WUSR_WUF7)
1658 /**
1659 * @brief Indicate whether a wakeup event is detected on wake up pin 7.
1660 * @rmtoll WUSR WUF7 LL_PWR_IsActiveFlag_WU7
1661 * @retval State of bit (1 or 0).
1662 */
LL_PWR_IsActiveFlag_WU7(void)1663 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU7(void)
1664 {
1665 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == (PWR_WUSR_WUF7)) ? 1UL : 0UL);
1666 }
1667 #endif /* PWR_WUSR_WUF7 */
1668
1669 #if defined (PWR_WUSR_WUF8)
1670 /**
1671 * @brief Indicate whether a wakeup event is detected on wake up pin 8.
1672 * @rmtoll WUSR WUF8 LL_PWR_IsActiveFlag_WU8
1673 * @retval State of bit (1 or 0).
1674 */
LL_PWR_IsActiveFlag_WU8(void)1675 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU8(void)
1676 {
1677 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == (PWR_WUSR_WUF8)) ? 1UL : 0UL);
1678 }
1679 #endif /* PWR_WUSR_WUF8 */
1680
1681 /**
1682 * @brief Clear stop flag.
1683 * @rmtoll PMCR CSSF LL_PWR_ClearFlag_STOP
1684 * @retval None
1685 */
LL_PWR_ClearFlag_STOP(void)1686 __STATIC_INLINE void LL_PWR_ClearFlag_STOP(void)
1687 {
1688 WRITE_REG(PWR->PMCR, PWR_PMCR_CSSF);
1689 }
1690
1691 /**
1692 * @brief Clear standby flag.
1693 * @rmtoll PMCR CSSF LL_PWR_ClearFlag_SB
1694 * @retval None
1695 */
LL_PWR_ClearFlag_SB(void)1696 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
1697 {
1698 WRITE_REG(PWR->PMCR, PWR_PMCR_CSSF);
1699 }
1700
1701 /**
1702 * @brief Clear wake up flag 1.
1703 * @rmtoll WUSCR CWUF1 LL_PWR_ClearFlag_WU1
1704 * @retval None
1705 */
LL_PWR_ClearFlag_WU1(void)1706 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1707 {
1708 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF1);
1709 }
1710
1711 /**
1712 * @brief Clear wake up flag 2.
1713 * @rmtoll WUSCR CWUF2 LL_PWR_ClearFlag_WU2
1714 * @retval None
1715 */
LL_PWR_ClearFlag_WU2(void)1716 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1717 {
1718 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF2);
1719 }
1720
1721 /**
1722 * @brief Clear wake up flag 3.
1723 * @rmtoll WUSCR CWUF3 LL_PWR_ClearFlag_WU3
1724 * @retval None
1725 */
LL_PWR_ClearFlag_WU3(void)1726 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1727 {
1728 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF3);
1729 }
1730
1731 /**
1732 * @brief Clear wake up flag 4.
1733 * @rmtoll WUSCR CWUF4 LL_PWR_ClearFlag_WU4
1734 * @retval None
1735 */
LL_PWR_ClearFlag_WU4(void)1736 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
1737 {
1738 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF4);
1739 }
1740
1741 /**
1742 * @brief Clear wake up flag 5.
1743 * @rmtoll WUSCR CWUF5 LL_PWR_ClearFlag_WU5
1744 * @retval None
1745 */
LL_PWR_ClearFlag_WU5(void)1746 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
1747 {
1748 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF5);
1749 }
1750
1751 #if defined (PWR_WUSCR_CWUF6)
1752 /**
1753 * @brief Clear wake up flag 6.
1754 * @rmtoll WUSCR CWUF6 LL_PWR_ClearFlag_WU6
1755 * @retval None
1756 */
LL_PWR_ClearFlag_WU6(void)1757 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
1758 {
1759 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF6);
1760 }
1761 #endif /* PWR_WUSCR_CWUF6 */
1762
1763 #if defined (PWR_WUSCR_CWUF7)
1764 /**
1765 * @brief Clear wake up flag 7.
1766 * @rmtoll WUSCR CWUF7 LL_PWR_ClearFlag_WU7
1767 * @retval None
1768 */
LL_PWR_ClearFlag_WU7(void)1769 __STATIC_INLINE void LL_PWR_ClearFlag_WU7(void)
1770 {
1771 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF7);
1772 }
1773 #endif /* PWR_WUSCR_CWUF7 */
1774
1775 #if defined (PWR_WUSCR_CWUF8)
1776 /**
1777 * @brief Clear wake up flag 8.
1778 * @rmtoll WUSCR CWUF8 LL_PWR_ClearFlag_WU8
1779 * @retval None
1780 */
LL_PWR_ClearFlag_WU8(void)1781 __STATIC_INLINE void LL_PWR_ClearFlag_WU8(void)
1782 {
1783 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF8);
1784 }
1785 #endif /* PWR_WUSCR_CWUF8 */
1786
1787 /**
1788 * @brief Clear all wake up flags.
1789 * @rmtoll WUSCR CWUF LL_PWR_ClearFlag_WU
1790 * @retval None
1791 */
LL_PWR_ClearFlag_WU(void)1792 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
1793 {
1794 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF);
1795 }
1796 /**
1797 * @}
1798 */
1799
1800 /** @defgroup PWR_LL_EF_ATTRIBUTE_MANAGEMENT PWR Attribute Management
1801 * @{
1802 */
1803
1804 #if defined(PWR_PRIVCFGR_NSPRIV)
1805 /**
1806 * @brief Enable privileged mode for nsecure items.
1807 * @rmtoll PRIVCFGR NSPRIV LL_PWR_EnableNSecurePrivilege
1808 * @retval None
1809 */
LL_PWR_EnableNSecurePrivilege(void)1810 __STATIC_INLINE void LL_PWR_EnableNSecurePrivilege(void)
1811 {
1812 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
1813 }
1814
1815 /**
1816 * @brief Disable privileged mode for nsecure items.
1817 * @rmtoll PRIVCFGR NSPRIV LL_PWR_DisableNSecurePrivilege
1818 * @retval None
1819 */
LL_PWR_DisableNSecurePrivilege(void)1820 __STATIC_INLINE void LL_PWR_DisableNSecurePrivilege(void)
1821 {
1822 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
1823 }
1824
1825 /**
1826 * @brief Check if privileged mode for nsecure items is enabled.
1827 * @rmtoll PRIVCFGR NSPRIV LL_PWR_IsEnabledNSecurePrivilege
1828 * @retval State of bit (1 or 0).
1829 */
LL_PWR_IsEnabledNSecurePrivilege(void)1830 __STATIC_INLINE uint32_t LL_PWR_IsEnabledNSecurePrivilege(void)
1831 {
1832 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV) == PWR_PRIVCFGR_NSPRIV) ? 1UL : 0UL);
1833 }
1834 #else
1835 /**
1836 * @brief Enable privileged mode for nsecure items.
1837 * @rmtoll PRIVCFGR NSPRIV LL_PWR_EnableNSecurePrivilege
1838 * @retval None
1839 */
LL_PWR_EnableNSecurePrivilege(void)1840 __STATIC_INLINE void LL_PWR_EnableNSecurePrivilege(void)
1841 {
1842 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV);
1843 }
1844
1845 /**
1846 * @brief Disable privileged mode for nsecure items.
1847 * @rmtoll PRIVCFGR NSPRIV LL_PWR_DisableNSecurePrivilege
1848 * @retval None
1849 */
LL_PWR_DisableNSecurePrivilege(void)1850 __STATIC_INLINE void LL_PWR_DisableNSecurePrivilege(void)
1851 {
1852 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV);
1853 }
1854
1855 /**
1856 * @brief Check if privileged mode for nsecure items is enabled.
1857 * @rmtoll PRIVCFGR NSPRIV LL_PWR_IsEnabledNSecurePrivilege
1858 * @retval State of bit (1 or 0).
1859 */
LL_PWR_IsEnabledNSecurePrivilege(void)1860 __STATIC_INLINE uint32_t LL_PWR_IsEnabledNSecurePrivilege(void)
1861 {
1862 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV) == PWR_PRIVCFGR_PRIV) ? 1UL : 0UL);
1863 }
1864 #endif /* RCC_PRIVCFGR_NSPRIV */
1865
1866 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1867 /**
1868 * @brief Enable privileged mode for secure items.
1869 * @rmtoll PRIVCFGR SPRIV LL_PWR_EnableSecurePrivilege
1870 * @retval None
1871 */
LL_PWR_EnableSecurePrivilege(void)1872 __STATIC_INLINE void LL_PWR_EnableSecurePrivilege(void)
1873 {
1874 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
1875 }
1876
1877 /**
1878 * @brief Disable privileged mode for secure items.
1879 * @rmtoll PRIVCFGR SPRIV LL_PWR_DisableSecurePrivilege
1880 * @retval None
1881 */
LL_PWR_DisableSecurePrivilege(void)1882 __STATIC_INLINE void LL_PWR_DisableSecurePrivilege(void)
1883 {
1884 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
1885 }
1886 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1887
1888 #if defined (PWR_PRIVCFGR_SPRIV)
1889 /**
1890 * @brief Check if privileged mode for secure items is enabled.
1891 * @rmtoll PRIVCFGR SPRIV LL_PWR_IsEnabledSecurePrivilege
1892 * @retval State of bit (1 or 0).
1893 */
LL_PWR_IsEnabledSecurePrivilege(void)1894 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSecurePrivilege(void)
1895 {
1896 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV) == PWR_PRIVCFGR_SPRIV) ? 1UL : 0UL);
1897 }
1898 #endif /* PWR_PRIVCFGR_SPRIV */
1899
1900 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1901 /**
1902 * @brief Configure secure attribute mode.
1903 * @note This API can be executed only by CPU in secure mode.
1904 * @rmtoll SECCFGR WUP1SEC LL_PWR_ConfigSecure\n
1905 * SECCFGR WUP2SEC LL_PWR_ConfigSecure\n
1906 * SECCFGR WUP3SEC LL_PWR_ConfigSecure\n
1907 * SECCFGR WUP4SEC LL_PWR_ConfigSecure\n
1908 * SECCFGR WUP5SEC LL_PWR_ConfigSecure\n
1909 * SECCFGR WUP6SEC LL_PWR_ConfigSecure\n
1910 * SECCFGR WUP7SEC LL_PWR_ConfigSecure\n
1911 * SECCFGR WUP8SEC LL_PWR_ConfigSecure\n
1912 * SECCFGR RETSEC LL_PWR_ConfigSecure\n
1913 * SECCFGR LPMSEC LL_PWR_ConfigSecure\n
1914 * SECCFGR VDMSEC LL_PWR_ConfigSecure\n
1915 * SECCFGR VBSEC LL_PWR_ConfigSecure\n
1916 * SECCFGR APCSEC LL_PWR_ConfigSecure
1917 * @param SecureConfig This parameter can be the full combination
1918 * of the following values:
1919 * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
1920 * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
1921 * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
1922 * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
1923 * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC
1924 * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC
1925 * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC
1926 * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC
1927 * @arg @ref LL_PWR_RET_NSEC or LL_PWR_RET_SEC
1928 * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC
1929 * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC
1930 * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC
1931 * @arg @ref LL_PWR_APC_NSEC or LL_PWR_APC_SEC
1932 * @retval None.
1933 */
LL_PWR_ConfigSecure(uint32_t SecureConfig)1934 __STATIC_INLINE void LL_PWR_ConfigSecure(uint32_t SecureConfig)
1935 {
1936 WRITE_REG(PWR->SECCFGR, SecureConfig);
1937 }
1938
1939 /**
1940 * @brief Get secure attribute configuration.
1941 * @note This API can be executed only by CPU in secure mode.
1942 * @rmtoll SECCFGR WUP1SEC LL_PWR_GetConfigSecure\n
1943 * SECCFGR WUP2SEC LL_PWR_GetConfigSecure\n
1944 * SECCFGR WUP3SEC LL_PWR_GetConfigSecure\n
1945 * SECCFGR WUP4SEC LL_PWR_GetConfigSecure\n
1946 * SECCFGR WUP5SEC LL_PWR_GetConfigSecure\n
1947 * SECCFGR WUP6SEC LL_PWR_GetConfigSecure\n
1948 * SECCFGR WUP7SEC LL_PWR_GetConfigSecure\n
1949 * SECCFGR WUP8SEC LL_PWR_GetConfigSecure\n
1950 * SECCFGR RETSEC LL_PWR_ConfigSecure\n
1951 * SECCFGR LPMSEC LL_PWR_GetConfigSecure\n
1952 * SECCFGR VDMSEC LL_PWR_GetConfigSecure\n
1953 * SECCFGR VBSEC LL_PWR_GetConfigSecure\n
1954 * SECCFGR APCSEC LL_PWR_GetConfigSecure
1955 * @retval Returned value is the combination of the following values:
1956 * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
1957 * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
1958 * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
1959 * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
1960 * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC
1961 * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC
1962 * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC
1963 * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC
1964 * @arg @ref LL_PWR_RET_NSEC or LL_PWR_RET_SEC
1965 * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC
1966 * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC
1967 * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC
1968 * @arg @ref LL_PWR_APC_NSEC or LL_PWR_APC_SEC
1969 */
LL_PWR_GetConfigSecure(void)1970 __STATIC_INLINE uint32_t LL_PWR_GetConfigSecure(void)
1971 {
1972 return (READ_REG(PWR->SECCFGR));
1973 }
1974 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1975 /**
1976 * @}
1977 */
1978
1979 #if defined (USE_FULL_LL_DRIVER)
1980 /** @defgroup PWR_LL_EF_Init De-initialization function
1981 * @{
1982 */
1983 ErrorStatus LL_PWR_DeInit(void);
1984 /**
1985 * @}
1986 */
1987 #endif /* defined (USE_FULL_LL_DRIVER) */
1988
1989
1990 /**
1991 * @}
1992 */
1993
1994 /**
1995 * @}
1996 */
1997
1998 #endif /* defined (PWR) */
1999
2000 /**
2001 * @}
2002 */
2003
2004 #ifdef __cplusplus
2005 }
2006 #endif /* __cplusplus */
2007
2008 #endif /* STM32H5xx_LL_PWR_H */
2009
