1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H5xx_LL_LPTIM_H
21 #define STM32H5xx_LL_LPTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h5xx.h"
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5) || defined (LPTIM6)
35
36 /** @defgroup LPTIM_LL LPTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup LPTIM_LL_Private_variables LPTIM Private variables
43 * @{
44 */
45
46 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxP[] =
47 {
48 0U, /* CC1P */
49 16U /* CC2P */
50 };
51
52 static const uint8_t LL_LPTIM_SHIFT_TAB_ICxF[] =
53 {
54 0U, /* IC1F */
55 16U /* IC2F */
56 };
57
58 static const uint8_t LL_LPTIM_SHIFT_TAB_ICxPSC[] =
59 {
60 0U, /* IC1PSC */
61 16U /* IC2PSC */
62 };
63
64 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] =
65 {
66 0U, /* CC1SEL */
67 16U /* CC2SEL */
68 };
69
70 static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] =
71 {
72 LPTIM_CCMR1_CC1E_Pos, /* CC1E */
73 LPTIM_CCMR1_CC2E_Pos /* CC2E */
74 };
75
76 static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] =
77 {
78 {2, 7, 9, 13},
79 {3, 5, 6, 8},
80 {2, 3, 4, 5},
81 {2, 2, 3, 3},
82 {2, 2, 2, 2},
83 {2, 2, 2, 2},
84 {2, 2, 2, 2},
85 {2, 2, 2, 2}
86
87 };
88
89 /**
90 * @}
91 */
92
93 /* Private constants ---------------------------------------------------------*/
94 /** Legacy definitions for compatibility purpose
95 @cond 0
96 */
97 #define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1
98 #define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2
99 #define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1
100 #define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2
101 /**
102 @endcond
103 */
104
105 /* Private macros ------------------------------------------------------------*/
106 #if defined(USE_FULL_LL_DRIVER)
107 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
108 * @{
109 */
110 /**
111 * @}
112 */
113 #endif /*USE_FULL_LL_DRIVER*/
114
115 /* Exported types ------------------------------------------------------------*/
116 #if defined(USE_FULL_LL_DRIVER)
117 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
118 * @{
119 */
120
121 /**
122 * @brief LPTIM Init structure definition
123 */
124 typedef struct
125 {
126 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
127 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
128
129 This feature can be modified afterwards using unitary
130 function @ref LL_LPTIM_SetClockSource().*/
131
132 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
133 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
134
135 This feature can be modified afterwards using using unitary
136 function @ref LL_LPTIM_SetPrescaler().*/
137
138 uint32_t Waveform; /*!< Specifies the waveform shape.
139 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
140
141 This feature can be modified afterwards using unitary
142 function @ref LL_LPTIM_SetWaveform().*/
143 } LL_LPTIM_InitTypeDef;
144
145 /**
146 * @}
147 */
148 #endif /* USE_FULL_LL_DRIVER */
149
150 /* Exported constants --------------------------------------------------------*/
151 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
152 * @{
153 */
154
155 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
156 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
157 * @{
158 */
159 #define LL_LPTIM_ISR_CMP1OK LPTIM_ISR_CMP1OK /*!< Compare register 1 update OK */
160 #define LL_LPTIM_ISR_CMP2OK LPTIM_ISR_CMP2OK /*!< Compare register 2 update OK */
161 #define LL_LPTIM_ISR_CC1IF LPTIM_ISR_CC1IF /*!< Capture/Compare 1 interrupt flag */
162 #define LL_LPTIM_ISR_CC2IF LPTIM_ISR_CC2IF /*!< Capture/Compare 2 interrupt flag */
163 #define LL_LPTIM_ISR_CC1OF LPTIM_ISR_CC1OF /*!< Capture/Compare 1 over-capture flag */
164 #define LL_LPTIM_ISR_CC2OF LPTIM_ISR_CC2OF /*!< Capture/Compare 2 over-capture flag */
165 #define LL_LPTIM_ISR_DIEROK LPTIM_ISR_DIEROK /*!< Interrupt enable register update OK */
166 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
167 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
168 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
169 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
170 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
171 #define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */
172 #define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */
173 /**
174 * @}
175 */
176
177 /** @defgroup LPTIM_LL_EC_IT IT Defines
178 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
179 * @{
180 */
181 #define LL_LPTIM_DIER_CMP1OKIE LPTIM_DIER_CMP1OKIE /*!< Compare register 1 update OK */
182 #define LL_LPTIM_DIER_CMP2OKIE LPTIM_DIER_CMP2OKIE /*!< Compare register 2 update OK */
183 #define LL_LPTIM_DIER_CC1IFIE LPTIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt flag */
184 #define LL_LPTIM_DIER_CC2IFIE LPTIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt flag */
185 #define LL_LPTIM_DIER_CC1OFIE LPTIM_DIER_CC1OIE /*!< Capture/Compare 1 over-capture flag */
186 #define LL_LPTIM_DIER_CC2OFIE LPTIM_DIER_CC2OIE /*!< Capture/Compare 2 over-capture flag */
187 #define LL_LPTIM_DIER_ARRMIE LPTIM_DIER_ARRMIE /*!< Autoreload match */
188 #define LL_LPTIM_DIER_EXTTRIGIE LPTIM_DIER_EXTTRIGIE /*!< External trigger edge event */
189 #define LL_LPTIM_DIER_ARROKIE LPTIM_DIER_ARROKIE /*!< Autoreload register update OK */
190 #define LL_LPTIM_DIER_UPIE LPTIM_DIER_UPIE /*!< Counter direction change down to up */
191 #define LL_LPTIM_DIER_DOWNIE LPTIM_DIER_DOWNIE /*!< Counter direction change up to down */
192 #define LL_LPTIM_DIER_UEIE LPTIM_DIER_UEIE /*!< Update event */
193 #define LL_LPTIM_DIER_REPOKIE LPTIM_DIER_REPOKIE /*!< Repetition register update OK */
194 /**
195 * @}
196 */
197
198 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
199 * @{
200 */
201 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
202 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
203 /**
204 * @}
205 */
206
207 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
208 * @{
209 */
210 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
211 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
212 /**
213 * @}
214 */
215
216 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
217 * @{
218 */
219 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
220 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
221 /**
222 * @}
223 */
224
225 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
226 * @{
227 */
228 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
229 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
230 /**
231 * @}
232 */
233
234 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
235 * @{
236 */
237 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CCRx registers*/
238 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CCMR1_CC1P_0 /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CCx registers*/
239 /**
240 * @}
241 */
242
243 /** @defgroup TIM_LL_EC_CHANNEL Channel
244 * @{
245 */
246 #define LL_LPTIM_CHANNEL_CH1 0x00000000U /*!< LPTIM input/output channel 1 */
247 #define LL_LPTIM_CHANNEL_CH2 0x00000001U /*!< LPTIM input/output channel 2 */
248 /**
249 * @}
250 */
251
252 /** @defgroup LPTIM_LL_EC_LPTIM_IC_PRESCALER Input Capture Prescaler
253 * @{
254 */
255 #define LL_LPTIM_ICPSC_DIV1 0x00000000UL /*!< Capture performed each time an edge is detected on the capture input */
256 #define LL_LPTIM_ICPSC_DIV2 LPTIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
257 #define LL_LPTIM_ICPSC_DIV4 LPTIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
258 #define LL_LPTIM_ICPSC_DIV8 (LPTIM_CCMR1_IC1PSC_0|LPTIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 8 events */
259 /**
260 * @}
261 */
262
263 /** @defgroup LPTIM_LL_EC_LPTIM_IC_FILTER Input Capture Filter
264 * @{
265 */
266 #define LL_LPTIM_ICFLT_CLOCK_DIV1 0x00000000UL /*!< any external input capture signal level change is considered as a valid transition */
267 #define LL_LPTIM_ICFLT_CLOCK_DIV2 LPTIM_CCMR1_IC1F_0 /*!< external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition */
268 #define LL_LPTIM_ICFLT_CLOCK_DIV4 LPTIM_CCMR1_IC1F_1 /*!< external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition */
269 #define LL_LPTIM_ICFLT_CLOCK_DIV8 (LPTIM_CCMR1_IC1F_0|LPTIM_CCMR1_IC1F_1) /*!< external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition */
270 /**
271 * @}
272 */
273
274 /** @defgroup LPTIM_LL_EC_LPTIM_IC_POLARITY Input Capture Polarity
275 * @{
276 */
277 #define LL_LPTIM_ICPOLARITY_RISING 0x00000000UL /*!< Capture/Compare input rising polarity */
278 #define LL_LPTIM_ICPOLARITY_FALLING LPTIM_CCMR1_CC1P_0 /*!< Capture/Compare input falling polarity */
279 #define LL_LPTIM_ICPOLARITY_RISING_FALLING (LPTIM_CCMR1_CC1P_0|LPTIM_CCMR1_CC1P_1) /*!< Capture/Compare input rising and falling polarities */
280 /**
281 * @}
282 */
283 /** @defgroup LPTIM_LL_EC_LPTIM_IC_Selection Input Capture selection
284 * @{
285 */
286 #define LL_LPTIM_CCMODE_OUTPUT_PWM 0x00000000UL /*!< Select PWM mode */
287 #define LL_LPTIM_CCMODE_INPUTCAPTURE LPTIM_CCMR1_CC1SEL /*!< Select Input Capture mode*/
288 /**
289 * @}
290 */
291
292 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
293 * @{
294 */
295 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
296 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
297 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
298 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
299 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
300 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
301 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
302 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
303 /**
304 * @}
305 */
306
307 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
308 * @{
309 */
310 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
311 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
312 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
313 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
314 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
315 #if defined(COMP1)
316 #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
317 #endif /* COMP1 */
318 #define LL_LPTIM_TRIG_SOURCE_GPDMA_CH0_TCF LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to GPDMA CH0 transfer complete */
319 #define LL_LPTIM_TRIG_SOURCE_GPDMA_CH1_TCF (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to GPDMA CH1 transfer complete */
320 #define LL_LPTIM_TRIG_SOURCE_GPDMA_CH4_TCF (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to GPDMA CH4 transfer complete */
321 #define LL_LPTIM_TRIG_SOURCE_EVENTOUT (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to EVENTOUT */
322 /**
323 * @}
324 */
325
326 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
327 * @{
328 */
329 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
330 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
331 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
332 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
333 /**
334 * @}
335 */
336
337 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
338 * @{
339 */
340 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
341 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
342 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
343 /**
344 * @}
345 */
346
347 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
348 * @{
349 */
350 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
351 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
352 /**
353 * @}
354 */
355
356 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
357 * @{
358 */
359 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
360 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
361 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
362 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
363 /**
364 * @}
365 */
366
367 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
368 * @{
369 */
370 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
371 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
372 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
373 /**
374 * @}
375 */
376
377 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
378 * @{
379 */
380 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
381 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
382 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
383 /**
384 * @}
385 */
386
387 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
388 * @{
389 */
390 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5 and LPTIM6 */
391 #if defined(STM32H503xx)
392 #define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM1 and LPTIM2 */
393 #define LL_LPTIM_INPUT1_SRC_LPTIM2_CH1 LPTIM_CFGR2_IN1SEL_1 /*!< For LPTIM1 */
394 #define LL_LPTIM_INPUT1_SRC_LPTIM1_CH2 LPTIM_CFGR2_IN1SEL_1 /*!< For LPTIM2 */
395 #endif /* STM32H503xx */
396 /**
397 * @}
398 */
399
400 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
401 * @{
402 */
403 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2, LPTIM3, LPTIM4 , LPTIM5 and LPTIM6 */
404 /**
405 * @}
406 */
407
408 /** @defgroup LPTIM_EC_LPTIM1_IC1_RMP LPTIM1 Input Ch1 Remap
409 * @{
410 */
411 #define LL_LPTIM_LPTIM1_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
412 #if defined(STM32H503xx)
413 #define LL_LPTIM_LPTIM1_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
414 #define LL_LPTIM_LPTIM1_IC1_RMP_EVENTOUT LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to EVENTOUT */
415 #define LL_LPTIM_LPTIM1_IC1_RMP_MCO1 (LPTIM_CFGR2_IC1SEL_0 | LPTIM_CFGR2_IC1SEL_1) /*!< IC1 connected to MCO1 */
416 #endif /* STM32H503xx */
417 /**
418 * @}
419 */
420
421 /** @defgroup LPTIM_EC_LPTIM1_IC2_RMP LPTIM1 Input Ch2 Remap
422 * @{
423 */
424 #define LL_LPTIM_LPTIM1_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
425 #define LL_LPTIM_LPTIM1_IC2_RMP_LSI LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to LSI */
426 #define LL_LPTIM_LPTIM1_IC2_RMP_LSE LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to LSE */
427 #if defined(STM32H503xx)
428 #define LL_LPTIM_LPTIM1_IC2_RMP_HSE_1M (LPTIM_CFGR2_IC2SEL_0 | LPTIM_CFGR2_IC2SEL_1) /*!< IC2 connected to HSE_1M */
429 #endif /* STM32H503xx */
430 /**
431 * @}
432 */
433
434 /** @defgroup LPTIM_EC_LPTIM2_IC1_RMP LPTIM2 Input Ch1 Remap
435 * @{
436 */
437 #define LL_LPTIM_LPTIM2_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
438 #if defined(STM32H503xx)
439 #define LL_LPTIM_LPTIM2_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
440 #define LL_LPTIM_LPTIM2_IC1_RMP_EVENTOUT LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to EVENTOUT */
441 #define LL_LPTIM_LPTIM2_IC1_RMP_MCO2 (LPTIM_CFGR2_IC1SEL_0 | LPTIM_CFGR2_IC1SEL_1) /*!< IC1 connected to MCO2 */
442 #endif /* STM32H503xx */
443 /**
444 * @}
445 */
446
447 /** @defgroup LPTIM_EC_LPTIM2_IC2_RMP LPTIM2 Input Ch2 Remap
448 * @{
449 */
450 #define LL_LPTIM_LPTIM2_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
451 #define LL_LPTIM_LPTIM2_IC2_RMP_HSI_1024 LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to HSI/1024 */
452 #define LL_LPTIM_LPTIM2_IC2_RMP_CSI_128 LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to CSI/128 */
453 #define LL_LPTIM_LPTIM2_IC2_RMP_CSI_HSI_8 (LPTIM_CFGR2_IC2SEL_0 | LPTIM_CFGR2_IC2SEL_1) /*!< IC2 connected to HSI/8 */
454 /**
455 * @}
456 */
457
458 /** @defgroup LPTIM_EC_LPTIM3_IC1_RMP LPTIM3 Input Ch1 Remap
459 * @{
460 */
461 #define LL_LPTIM_LPTIM3_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
462 /**
463 * @}
464 */
465
466 /** @defgroup LPTIM_EC_LPTIM3_IC2_RMP LPTIM3 Input Ch2 Remap
467 * @{
468 */
469 #define LL_LPTIM_LPTIM3_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
470 /**
471 * @}
472 */
473
474 #if defined(LPTIM5) && defined(LPTIM6)
475 /** @defgroup LPTIM_EC_LPTIM5_IC1_RMP LPTIM5 Input Ch1 Remap
476 * @{
477 */
478 #define LL_LPTIM_LPTIM5_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
479 /**
480 * @}
481 */
482
483 /** @defgroup LPTIM_EC_LPTIM5_IC2_RMP LPTIM5 Input Ch2 Remap
484 * @{
485 */
486 #define LL_LPTIM_LPTIM5_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
487 /**
488 * @}
489 */
490
491 /** @defgroup LPTIM_EC_LPTIM6_IC1_RMP LPTIM6 Input Ch1 Remap
492 * @{
493 */
494 #define LL_LPTIM_LPTIM6_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
495 /**
496 * @}
497 */
498
499 /** @defgroup LPTIM_EC_LPTIM6_IC2_RMP LPTIM6 Input Ch2 Remap
500 * @{
501 */
502 #define LL_LPTIM_LPTIM6_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
503 /**
504 * @}
505 */
506
507 #endif /* LPTIM5 && LPTIM6 */
508
509 /**
510 * @}
511 */
512
513 /* Exported macro ------------------------------------------------------------*/
514 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
515 * @{
516 */
517
518 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
519 * @{
520 */
521
522 /**
523 * @brief Write a value in LPTIM register
524 * @param __INSTANCE__ LPTIM Instance
525 * @param __REG__ Register to be written
526 * @param __VALUE__ Value to be written in the register
527 * @retval None
528 */
529 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
530
531 /**
532 * @brief Read a value in LPTIM register
533 * @param __INSTANCE__ LPTIM Instance
534 * @param __REG__ Register to be read
535 * @retval Register value
536 */
537 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
538
539 /**
540 * @brief LPTimer Input Capture Get Offset(in counter step unit)
541 * @note The real capture value corresponding to the input capture trigger can be calculated using
542 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
543 * The Offset value is depending on the glitch filter value for the channel
544 * and the value of the prescaler for the kernel clock.
545 * Please check Errata Sheet V1_8 for more details under "variable latency
546 * on input capture channel" section.
547 * @param __PSC__ This parameter can be one of the following values:
548 * @arg @ref LL_LPTIM_PRESCALER_DIV1
549 * @arg @ref LL_LPTIM_PRESCALER_DIV2
550 * @arg @ref LL_LPTIM_PRESCALER_DIV4
551 * @arg @ref LL_LPTIM_PRESCALER_DIV8
552 * @arg @ref LL_LPTIM_PRESCALER_DIV16
553 * @arg @ref LL_LPTIM_PRESCALER_DIV32
554 * @arg @ref LL_LPTIM_PRESCALER_DIV64
555 * @arg @ref LL_LPTIM_PRESCALER_DIV128
556 * @param __FLT__ This parameter can be one of the following values:
557 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
558 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
559 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
560 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
561 * @retval offset value
562 */
563 #define LL_LPTIM_IC_GET_OFFSET(__PSC__, __FLT__) LL_LPTIM_OFFSET_TAB_ICx\
564 [((__PSC__) & LPTIM_CFGR_PRESC_Msk) >> LPTIM_CFGR_PRESC_Pos]\
565 [((__FLT__) & LPTIM_CCMR1_IC1F_Msk) >> LPTIM_CCMR1_IC1F_Pos]
566 /**
567 * @}
568 */
569
570 /**
571 * @}
572 */
573
574 /* Exported functions --------------------------------------------------------*/
575 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
576 * @{
577 */
578
579 /** Legacy definitions for compatibility purpose
580 @cond 0
581 */
582 #define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM
583 #define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1
584 #define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2
585 #define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O
586 #define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O
587 #define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM
588 /**
589 @endcond
590 */
591
592 #if defined(USE_FULL_LL_DRIVER)
593 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
594 * @{
595 */
596
597 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
598 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
599 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
600 /**
601 * @}
602 */
603 #endif /* USE_FULL_LL_DRIVER */
604
605 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
606 * @{
607 */
608
609 /**
610 * @brief Enable the LPTIM instance
611 * @note After setting the ENABLE bit, a delay of two counter clock is needed
612 * before the LPTIM instance is actually enabled.
613 * @rmtoll CR ENABLE LL_LPTIM_Enable
614 * @param LPTIMx Low-Power Timer instance
615 * @retval None
616 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)617 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
618 {
619 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
620 }
621
622 /**
623 * @brief Disable the LPTIM instance
624 * @rmtoll CR ENABLE LL_LPTIM_Disable
625 * @param LPTIMx Low-Power Timer instance
626 * @retval None
627 */
LL_LPTIM_Disable(LPTIM_TypeDef * LPTIMx)628 __STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
629 {
630 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
631 }
632
633 /**
634 * @brief Indicates whether the LPTIM instance is enabled.
635 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
636 * @param LPTIMx Low-Power Timer instance
637 * @retval State of bit (1 or 0).
638 */
LL_LPTIM_IsEnabled(const LPTIM_TypeDef * LPTIMx)639 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
640 {
641 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
642 }
643
644 /**
645 * @brief Starts the LPTIM counter in the desired mode.
646 * @note LPTIM instance must be enabled before starting the counter.
647 * @note It is possible to change on the fly from One Shot mode to
648 * Continuous mode.
649 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
650 * CR SNGSTRT LL_LPTIM_StartCounter
651 * @param LPTIMx Low-Power Timer instance
652 * @param OperatingMode This parameter can be one of the following values:
653 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
654 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
655 * @retval None
656 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)657 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
658 {
659 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
660 }
661
662 /**
663 * @brief Enable reset after read.
664 * @note After calling this function any read access to LPTIM_CNT
665 * register will asynchronously reset the LPTIM_CNT register content.
666 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
667 * @param LPTIMx Low-Power Timer instance
668 * @retval None
669 */
LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef * LPTIMx)670 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
671 {
672 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
673 }
674
675 /**
676 * @brief Disable reset after read.
677 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
678 * @param LPTIMx Low-Power Timer instance
679 * @retval None
680 */
LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef * LPTIMx)681 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
682 {
683 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
684 }
685
686 /**
687 * @brief Indicate whether the reset after read feature is enabled.
688 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
689 * @param LPTIMx Low-Power Timer instance
690 * @retval State of bit (1 or 0).
691 */
LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef * LPTIMx)692 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
693 {
694 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
695 }
696
697 /**
698 * @brief Reset of the LPTIM_CNT counter register (synchronous).
699 * @note Due to the synchronous nature of this reset, it only takes
700 * place after a synchronization delay of 3 LPTIM core clock cycles
701 * (LPTIM core clock may be different from APB clock).
702 * @note COUNTRST is automatically cleared by hardware
703 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
704 * @param LPTIMx Low-Power Timer instance
705 * @retval None
706 */
LL_LPTIM_ResetCounter(LPTIM_TypeDef * LPTIMx)707 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
708 {
709 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
710 }
711
712 /**
713 * @brief Set the LPTIM registers update mode (enable/disable register preload)
714 * @note This function must be called when the LPTIM instance is disabled.
715 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
716 * @param LPTIMx Low-Power Timer instance
717 * @param UpdateMode This parameter can be one of the following values:
718 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
719 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
720 * @retval None
721 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)722 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
723 {
724 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
725 }
726
727 /**
728 * @brief Get the LPTIM registers update mode
729 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
730 * @param LPTIMx Low-Power Timer instance
731 * @retval Returned value can be one of the following values:
732 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
733 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
734 */
LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef * LPTIMx)735 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
736 {
737 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
738 }
739
740 /**
741 * @brief Set the auto reload value
742 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
743 * @note After a write to the LPTIMx_ARR register a new write operation to the
744 * same register can only be performed when the previous write operation
745 * is completed. Any successive write before the ARROK flag is set, will
746 * lead to unpredictable results.
747 * @note autoreload value be strictly greater than the compare value.
748 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
749 * @param LPTIMx Low-Power Timer instance
750 * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
751 * @retval None
752 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)753 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
754 {
755 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
756 }
757
758 /**
759 * @brief Get actual auto reload value
760 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
761 * @param LPTIMx Low-Power Timer instance
762 * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
763 */
LL_LPTIM_GetAutoReload(const LPTIM_TypeDef * LPTIMx)764 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
765 {
766 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
767 }
768
769 /**
770 * @brief Set the repetition value
771 * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled
772 * @rmtoll RCR REP LL_LPTIM_SetRepetition
773 * @param LPTIMx Low-Power Timer instance
774 * @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF
775 * @retval None
776 */
LL_LPTIM_SetRepetition(LPTIM_TypeDef * LPTIMx,uint32_t Repetition)777 __STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition)
778 {
779 MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition);
780 }
781
782 /**
783 * @brief Get the repetition value
784 * @rmtoll RCR REP LL_LPTIM_GetRepetition
785 * @param LPTIMx Low-Power Timer instance
786 * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF
787 */
LL_LPTIM_GetRepetition(const LPTIM_TypeDef * LPTIMx)788 __STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *LPTIMx)
789 {
790 return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP));
791 }
792
793 /**
794 * @brief Enable capture/compare channel.
795 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_EnableChannel\n
796 * CCMR1 CC2E LL_LPTIM_CC_EnableChannel
797 * @param LPTIMx LPTimer instance
798 * @param Channel This parameter can be one of the following values:
799 * @arg @ref LL_LPTIM_CHANNEL_CH1
800 * @arg @ref LL_LPTIM_CHANNEL_CH2
801 * @retval None
802 */
LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef * LPTIMx,uint32_t Channel)803 __STATIC_INLINE void LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
804 {
805 SET_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
806 }
807
808 /**
809 * @brief Disable capture/compare channel.
810 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_DisableChannel\n
811 * CCMR1 CC2E LL_LPTIM_CC_DisableChannel
812 * @param LPTIMx LPTimer instance
813 * @param Channel This parameter can be one of the following values:
814 * @arg @ref LL_LPTIM_CHANNEL_CH1
815 * @arg @ref LL_LPTIM_CHANNEL_CH2
816 * @retval None
817 */
LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef * LPTIMx,uint32_t Channel)818 __STATIC_INLINE void LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
819 {
820 CLEAR_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
821 }
822
823 /**
824 * @brief Indicate whether channel is enabled.
825 * @rmtoll CCMR1 CC1E LL_LPTIM_CC_IsEnabledChannel\n
826 * CCMR1 CC2E LL_LPTIM_CC_IsEnabledChannel
827 * @param LPTIMx LPTimer instance
828 * @param Channel This parameter can be one of the following values:
829 * @arg @ref LL_LPTIM_CHANNEL_CH1
830 * @arg @ref LL_LPTIM_CHANNEL_CH2
831 * @retval State of bit (1 or 0).
832 */
LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)833 __STATIC_INLINE uint32_t LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
834 {
835 return ((READ_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]) == \
836 (0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel])) ? 1UL : 0UL);
837
838 }
839
840 /**
841 * @brief Set the compare value
842 * @note After a write to the LPTIMx_CCR1 register a new write operation to the
843 * same register can only be performed when the previous write operation
844 * is completed. Any successive write before the CMP1OK flag is set, will
845 * lead to unpredictable results.
846 * @rmtoll CCR1 CCR1 LL_LPTIM_OC_SetCompareCH1
847 * @param LPTIMx Low-Power Timer instance
848 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
849 * @retval None
850 */
LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)851 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
852 {
853 MODIFY_REG(LPTIMx->CCR1, LPTIM_CCR1_CCR1, CompareValue);
854 }
855
856 /**
857 * @brief Get actual compare value
858 * @rmtoll CCR1 CCR1 LL_LPTIM_OC_GetCompareCH1
859 * @param LPTIMx Low-Power Timer instance
860 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
861 */
LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef * LPTIMx)862 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef *LPTIMx)
863 {
864 return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
865 }
866
867 /**
868 * @brief Set the compare value
869 * @note After a write to the LPTIMx_CCR2 register a new write operation to the
870 * same register can only be performed when the previous write operation
871 * is completed. Any successive write before the CMP2OK flag is set, will
872 * lead to unpredictable results.
873 * @rmtoll CCR2 CCR2 LL_LPTIM_OC_SetCompareCH2
874 * @param LPTIMx Low-Power Timer instance
875 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
876 * @retval None
877 */
LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)878 __STATIC_INLINE void LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
879 {
880 MODIFY_REG(LPTIMx->CCR2, LPTIM_CCR2_CCR2, CompareValue);
881 }
882
883 /**
884 * @brief Get actual compare value
885 * @rmtoll CCR2 CCR2 LL_LPTIM_OC_GetCompareCH2
886 * @param LPTIMx Low-Power Timer instance
887 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
888 */
LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef * LPTIMx)889 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef *LPTIMx)
890 {
891 return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
892 }
893
894 /**
895 * @brief Get actual counter value
896 * @note When the LPTIM instance is running with an asynchronous clock, reading
897 * the LPTIMx_CNT register may return unreliable values. So in this case
898 * it is necessary to perform two consecutive read accesses and verify
899 * that the two returned values are identical.
900 * @rmtoll CNT CNT LL_LPTIM_GetCounter
901 * @param LPTIMx Low-Power Timer instance
902 * @retval Counter value
903 */
LL_LPTIM_GetCounter(const LPTIM_TypeDef * LPTIMx)904 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
905 {
906 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
907 }
908
909 /**
910 * @brief Set the counter mode (selection of the LPTIM counter clock source).
911 * @note The counter mode can be set only when the LPTIM instance is disabled.
912 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
913 * @param LPTIMx Low-Power Timer instance
914 * @param CounterMode This parameter can be one of the following values:
915 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
916 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
917 * @retval None
918 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)919 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
920 {
921 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
922 }
923
924 /**
925 * @brief Get the counter mode
926 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
927 * @param LPTIMx Low-Power Timer instance
928 * @retval Returned value can be one of the following values:
929 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
930 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
931 */
LL_LPTIM_GetCounterMode(const LPTIM_TypeDef * LPTIMx)932 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
933 {
934 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
935 }
936
937 /**
938 * @brief Set waveform shape
939 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
940 * @param LPTIMx Low-Power Timer instance
941 * @param Waveform This parameter can be one of the following values:
942 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
943 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
944 * @retval None
945 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)946 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
947 {
948 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
949 }
950
951 /**
952 * @brief Get actual waveform shape
953 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
954 * @param LPTIMx Low-Power Timer instance
955 * @retval Returned value can be one of the following values:
956 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
957 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
958 */
LL_LPTIM_GetWaveform(const LPTIM_TypeDef * LPTIMx)959 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
960 {
961 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
962 }
963
964 /**
965 * @brief Set the polarity of an output channel.
966 * @rmtoll CCMR1 CC1P LL_LPTIM_OC_SetPolarity\n
967 * @rmtoll CCMR1 CC2P LL_LPTIM_OC_SetPolarity\n
968 * @param LPTIMx Low-Power Timer instance
969 * @param Channel This parameter can be one of the following values:
970 * @arg @ref LL_LPTIM_CHANNEL_CH1
971 * @arg @ref LL_LPTIM_CHANNEL_CH2
972 * @param Polarity This parameter can be one of the following values:
973 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
974 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
975 * @retval None
976 */
LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Polarity)977 __STATIC_INLINE void LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
978 {
979 #if defined(LPTIM4)
980 if (LPTIMx == LPTIM4)
981 {
982 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, ((Polarity >> LPTIM_CCMR1_CC1P_Pos) << LPTIM_CFGR_WAVPOL_Pos));
983 }
984 else
985 #endif /* LPTIM4 */
986 {
987 MODIFY_REG(LPTIMx->CCMR1, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]),
988 (Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]));
989 }
990 }
991
992 /**
993 * @brief Get the polarity of an output channel.
994 * @rmtoll CCMR1 CC1P LL_LPTIM_OC_GetPolarity\n
995 * @rmtoll CCMR1 CC2P LL_LPTIM_OC_GetPolarity\n
996 * @param LPTIMx Low-Power Timer instance
997 * @param Channel This parameter can be one of the following values:
998 * @arg @ref LL_LPTIM_CHANNEL_CH1
999 * @arg @ref LL_LPTIM_CHANNEL_CH2
1000 * @retval Returned value can be one of the following values:
1001 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
1002 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
1003 */
LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1004 __STATIC_INLINE uint32_t LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1005 {
1006 #if defined(LPTIM4)
1007 if (LPTIMx == LPTIM4)
1008 {
1009 return (uint32_t)((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL) >> LPTIM_CFGR_WAVPOL_Pos) << LPTIM_CCMR1_CC1P_Pos);
1010 }
1011 else
1012 #endif /* LPTIM4 */
1013 {
1014 return (uint32_t)(READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]) >> \
1015 LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1016 }
1017 }
1018
1019 /**
1020 * @brief Set actual prescaler division ratio.
1021 * @note This function must be called when the LPTIM instance is disabled.
1022 * @note When the LPTIM is configured to be clocked by an internal clock source
1023 * and the LPTIM counter is configured to be updated by active edges
1024 * detected on the LPTIM external Input1, the internal clock provided to
1025 * the LPTIM must be not be prescaled.
1026 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
1027 * @param LPTIMx Low-Power Timer instance
1028 * @param Prescaler This parameter can be one of the following values:
1029 * @arg @ref LL_LPTIM_PRESCALER_DIV1
1030 * @arg @ref LL_LPTIM_PRESCALER_DIV2
1031 * @arg @ref LL_LPTIM_PRESCALER_DIV4
1032 * @arg @ref LL_LPTIM_PRESCALER_DIV8
1033 * @arg @ref LL_LPTIM_PRESCALER_DIV16
1034 * @arg @ref LL_LPTIM_PRESCALER_DIV32
1035 * @arg @ref LL_LPTIM_PRESCALER_DIV64
1036 * @arg @ref LL_LPTIM_PRESCALER_DIV128
1037 * @retval None
1038 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)1039 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
1040 {
1041 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
1042 }
1043
1044 /**
1045 * @brief Get actual prescaler division ratio.
1046 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
1047 * @param LPTIMx Low-Power Timer instance
1048 * @retval Returned value can be one of the following values:
1049 * @arg @ref LL_LPTIM_PRESCALER_DIV1
1050 * @arg @ref LL_LPTIM_PRESCALER_DIV2
1051 * @arg @ref LL_LPTIM_PRESCALER_DIV4
1052 * @arg @ref LL_LPTIM_PRESCALER_DIV8
1053 * @arg @ref LL_LPTIM_PRESCALER_DIV16
1054 * @arg @ref LL_LPTIM_PRESCALER_DIV32
1055 * @arg @ref LL_LPTIM_PRESCALER_DIV64
1056 * @arg @ref LL_LPTIM_PRESCALER_DIV128
1057 */
LL_LPTIM_GetPrescaler(const LPTIM_TypeDef * LPTIMx)1058 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
1059 {
1060 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
1061 }
1062
1063 /**
1064 * @brief Set LPTIM input 1 source (default GPIO).
1065 * @rmtoll CFGR2 IN1SEL LL_LPTIM_SetInput1Src
1066 * @param LPTIMx Low-Power Timer instance
1067 * @param Src This parameter can be one of the following values:
1068 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
1069 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
1070 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
1071 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1 (*)
1072 * @arg @ref LL_LPTIM_INPUT1SOURCE_LPTIM2_CH1 (*)
1073 * @arg @ref LL_LPTIM_INPUT1SOURCE_LPTIM1_CH2 (*)
1074 * (*) Value not defined for all devices
1075 * @retval None
1076 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)1077 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1078 {
1079 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src);
1080 }
1081
1082 /**
1083 * @brief Set LPTIM input 2 source (default GPIO).
1084 * @rmtoll CFGR2 IN2SEL LL_LPTIM_SetInput2Src
1085 * @param LPTIMx Low-Power Timer instance
1086 * @param Src This parameter can be one of the following values:
1087 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
1088 * @retval None
1089 */
LL_LPTIM_SetInput2Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)1090 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1091 {
1092 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src);
1093 }
1094
1095 /**
1096 * @brief Set LPTIM input source (default GPIO).
1097 * @rmtoll CFGR2 IC1SEL LL_LPTIM_SetRemap
1098 * @rmtoll CFGR2 IC2SEL LL_LPTIM_SetRemap
1099 * @param LPTIMx Low-Power Timer instance
1100 * @param Src This parameter can be one of the following values:
1101 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_GPIO
1102 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP1 (*)
1103 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_EVENTOUT (*)
1104 * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_MCO1 (*)
1105 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_GPIO
1106 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSI (*)
1107 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSE (*)
1108 * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_HSE_1M (*)
1109 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_GPIO
1110 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP1 (*)
1111 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMPE_VENTOUT (*)
1112 * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_MCO2 (*)
1113 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_GPIO
1114 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI
1115 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_MSI_1024
1116 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_MSI_4
1117 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI_1024
1118 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_CSI_128
1119 * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI_8
1120 * @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_GPIO (*)
1121 * @arg @ref LL_LPTIM_LPTIM3_IC2_RMP_GPIO (*)
1122 * @arg @ref LL_LPTIM_LPTIM5_IC1_RMP_GPIO (*)
1123 * @arg @ref LL_LPTIM_LPTIM5_IC2_RMP_GPIO (*)
1124 * @arg @ref LL_LPTIM_LPTIM6_IC1_RMP_GPIO (*)
1125 * @arg @ref LL_LPTIM_LPTIM6_IC2_RMP_GPIO (*)
1126 *
1127 * (*) Value not defined in all devices. \n
1128 *
1129 * @retval None
1130 */
LL_LPTIM_SetRemap(LPTIM_TypeDef * LPTIMx,uint32_t Src)1131 __STATIC_INLINE void LL_LPTIM_SetRemap(LPTIM_TypeDef *LPTIMx, uint32_t Src)
1132 {
1133 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IC1SEL | LPTIM_CFGR2_IC2SEL, Src);
1134 }
1135
1136 /**
1137 * @brief Set the polarity of IC channel 1.
1138 * @rmtoll CCMR1 CC1P LL_LPTIM_IC_SetPolarity\n
1139 * @rmtoll CCMR1 CC2P LL_LPTIM_IC_SetPolarity\n
1140 * @param LPTIMx Low-Power Timer instance
1141 * @param Channel This parameter can be one of the following values:
1142 * @arg @ref LL_LPTIM_CHANNEL_CH1
1143 * @arg @ref LL_LPTIM_CHANNEL_CH2
1144 * @param Polarity This parameter can be one of the following values:
1145 * @arg @ref LL_LPTIM_ICPOLARITY_RISING
1146 * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
1147 * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
1148 * @retval None
1149 */
LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Polarity)1150 __STATIC_INLINE void LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
1151 {
1152 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel],
1153 Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1154 }
1155
1156 /**
1157 * @brief Get the polarity of IC channels.
1158 * @rmtoll CCMR1 CC1P LL_LPTIM_IC_GetPolarity\n
1159 * @rmtoll CCMR1 CC2P LL_LPTIM_IC_GetPolarity\n
1160 * @param LPTIMx Low-Power Timer instance
1161 * @param Channel This parameter can be one of the following values:
1162 * @arg @ref LL_LPTIM_CHANNEL_CH1
1163 * @arg @ref LL_LPTIM_CHANNEL_CH2
1164 * @retval Returned value can be one of the following values:
1165 * @arg @ref LL_LPTIM_ICPOLARITY_RISING
1166 * @arg @ref LL_LPTIM_ICPOLARITY_FALLING
1167 * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
1168 */
LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1169 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1170 {
1171 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel])) >> \
1172 LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
1173
1174 }
1175
1176 /**
1177 * @brief Set the filter of IC channels.
1178 * @rmtoll CCMR1 IC1F LL_LPTIM_IC_SetFilter\n
1179 * @rmtoll CCMR1 IC2F LL_LPTIM_IC_SetFilter\n
1180 * @param LPTIMx Low-Power Timer instance
1181 * @param Channel This parameter can be one of the following values:
1182 * @arg @ref LL_LPTIM_CHANNEL_CH1
1183 * @arg @ref LL_LPTIM_CHANNEL_CH2
1184 * @param Filter This parameter can be one of the following values:
1185 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
1186 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
1187 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
1188 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
1189 * @retval None
1190 */
LL_LPTIM_IC_SetFilter(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Filter)1191 __STATIC_INLINE void LL_LPTIM_IC_SetFilter(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Filter)
1192 {
1193 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel],
1194 Filter << LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
1195 }
1196
1197 /**
1198 * @brief Get the filter of IC channels.
1199 * @rmtoll CCMR1 IC1F LL_LPTIM_IC_GetFilter\n
1200 * @rmtoll CCMR1 IC2F LL_LPTIM_IC_GetFilter\n
1201 * @param LPTIMx Low-Power Timer instance
1202 * @param Channel This parameter can be one of the following values:
1203 * @arg @ref LL_LPTIM_CHANNEL_CH1
1204 * @arg @ref LL_LPTIM_CHANNEL_CH2
1205 * @retval Returned value can be one of the following values:
1206 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
1207 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
1208 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
1209 * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
1210 */
LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1211 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1212 {
1213 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel])) >> \
1214 LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
1215 }
1216
1217 /**
1218 * @brief Set the prescaler of IC channels.
1219 * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_SetPrescaler\n
1220 * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_SetPrescaler\n
1221 * @param LPTIMx Low-Power Timer instance
1222 * @param Channel This parameter can be one of the following values:
1223 * @arg @ref LL_LPTIM_CHANNEL_CH1
1224 * @arg @ref LL_LPTIM_CHANNEL_CH2
1225 * @param Prescaler This parameter can be one of the following values:
1226 * @arg @ref LL_LPTIM_ICPSC_DIV1
1227 * @arg @ref LL_LPTIM_ICPSC_DIV2
1228 * @arg @ref LL_LPTIM_ICPSC_DIV4
1229 * @arg @ref LL_LPTIM_ICPSC_DIV8
1230 * @retval None
1231 */
LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t Prescaler)1232 __STATIC_INLINE void LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Prescaler)
1233 {
1234 MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel],
1235 Prescaler << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
1236 }
1237
1238 /**
1239 * @brief Get the prescaler of IC channels.
1240 * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_GetPrescaler\n
1241 * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_GetPrescaler\n
1242 * @param LPTIMx Low-Power Timer instance
1243 * @param Channel This parameter can be one of the following values:
1244 * @arg @ref LL_LPTIM_CHANNEL_CH1
1245 * @arg @ref LL_LPTIM_CHANNEL_CH2
1246 * @retval Returned value can be one of the following values:
1247 * @arg @ref LL_LPTIM_ICPSC_DIV1
1248 * @arg @ref LL_LPTIM_ICPSC_DIV2
1249 * @arg @ref LL_LPTIM_ICPSC_DIV4
1250 * @arg @ref LL_LPTIM_ICPSC_DIV8
1251 */
LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1252 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1253 {
1254 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel])) >> \
1255 LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
1256 }
1257
1258 /**
1259 * @brief Set the Channel Mode.
1260 * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_SetChannelMode\n
1261 * CCMR1 CC2SEL LL_LPTIM_CC_SetChannelMode
1262 * @param LPTIMx Low-Power Timer instance
1263 * @param Channel This parameter can be one of the following values:
1264 * @arg @ref LL_LPTIM_CHANNEL_CH1
1265 * @arg @ref LL_LPTIM_CHANNEL_CH2
1266 * @param CCMode This parameter can be one of the following values:
1267 * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
1268 * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
1269 * @retval None
1270 */
LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef * LPTIMx,uint32_t Channel,uint32_t CCMode)1271 __STATIC_INLINE void LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t CCMode)
1272 {
1273 SET_BIT(LPTIMx->CCMR1, CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
1274 }
1275
1276 /**
1277 * @brief Get the Channel Mode.
1278 * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_GetChannelMode\n
1279 * CCMR1 CC2SEL LL_LPTIM_CC_GetChannelMode
1280 * @param LPTIMx Low-Power Timer instance
1281 * @param Channel This parameter can be one of the following values:
1282 * @arg @ref LL_LPTIM_CHANNEL_CH1
1283 * @arg @ref LL_LPTIM_CHANNEL_CH2
1284 * @retval Returned value can be one of the following values:
1285 * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
1286 * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
1287 */
LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef * LPTIMx,uint32_t Channel)1288 __STATIC_INLINE uint32_t LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef *LPTIMx, uint32_t Channel)
1289 {
1290 return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel])) >> \
1291 LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
1292 }
1293
1294 /**
1295 * @brief Get captured value for input channel 1.
1296 * @rmtoll CCR1 CCR1 LL_LPTIM_IC_GetCaptureCH1
1297 * @note The real capture value corresponding to the input capture trigger can be calculated using
1298 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1299 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1300 * @param LPTIMx Low-Power Timer instance
1301 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1302 */
LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef * LPTIMx)1303 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef *LPTIMx)
1304 {
1305 return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
1306 }
1307
1308 /**
1309 * @brief Get captured value for input channel 2.
1310 * @rmtoll CCR2 CCR2 LL_LPTIM_IC_GetCaptureCH2
1311 * @note The real capture value corresponding to the input capture trigger can be calculated using
1312 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
1313 * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
1314 * @param LPTIMx Low-Power Timer instance
1315 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
1316 */
LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef * LPTIMx)1317 __STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef *LPTIMx)
1318 {
1319 return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
1320 }
1321
1322 /**
1323 * @}
1324 */
1325
1326 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
1327 * @{
1328 */
1329
1330 /**
1331 * @brief Enable the timeout function
1332 * @note This function must be called when the LPTIM instance is disabled.
1333 * @note The first trigger event will start the timer, any successive trigger
1334 * event will reset the counter and the timer will restart.
1335 * @note The timeout value corresponds to the compare value; if no trigger
1336 * occurs within the expected time frame, the MCU is waked-up by the
1337 * compare match event.
1338 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
1339 * @param LPTIMx Low-Power Timer instance
1340 * @retval None
1341 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)1342 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
1343 {
1344 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
1345 }
1346
1347 /**
1348 * @brief Disable the timeout function
1349 * @note This function must be called when the LPTIM instance is disabled.
1350 * @note A trigger event arriving when the timer is already started will be
1351 * ignored.
1352 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
1353 * @param LPTIMx Low-Power Timer instance
1354 * @retval None
1355 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)1356 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
1357 {
1358 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
1359 }
1360
1361 /**
1362 * @brief Indicate whether the timeout function is enabled.
1363 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
1364 * @param LPTIMx Low-Power Timer instance
1365 * @retval State of bit (1 or 0).
1366 */
LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef * LPTIMx)1367 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
1368 {
1369 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
1370 }
1371
1372 /**
1373 * @brief Start the LPTIM counter
1374 * @note This function must be called when the LPTIM instance is disabled.
1375 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
1376 * @param LPTIMx Low-Power Timer instance
1377 * @retval None
1378 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)1379 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
1380 {
1381 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
1382 }
1383
1384 /**
1385 * @brief Configure the external trigger used as a trigger event for the LPTIM.
1386 * @note This function must be called when the LPTIM instance is disabled.
1387 * @note An internal clock source must be present when a digital filter is
1388 * required for the trigger.
1389 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
1390 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
1391 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
1392 * @param LPTIMx Low-Power Timer instance
1393 * @param Source This parameter can be one of the following values:
1394 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
1395 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
1396 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
1397 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
1398 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
1399 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 (*)
1400 *
1401 * (*) Value not defined in all devices. \n
1402 *
1403 * @param Filter This parameter can be one of the following values:
1404 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
1405 * @arg @ref LL_LPTIM_TRIG_FILTER_2
1406 * @arg @ref LL_LPTIM_TRIG_FILTER_4
1407 * @arg @ref LL_LPTIM_TRIG_FILTER_8
1408 * @param Polarity This parameter can be one of the following values:
1409 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
1410 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
1411 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
1412 * @retval None
1413 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)1414 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
1415 {
1416 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
1417 }
1418
1419 /**
1420 * @brief Get actual external trigger source.
1421 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
1422 * @param LPTIMx Low-Power Timer instance
1423 * @retval Returned value can be one of the following values:
1424 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
1425 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
1426 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
1427 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
1428 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
1429 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 (*)
1430 *
1431 * (*) Value not defined in all devices. \n
1432 *
1433 */
LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef * LPTIMx)1434 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
1435 {
1436 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
1437 }
1438
1439 /**
1440 * @brief Get actual external trigger filter.
1441 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
1442 * @param LPTIMx Low-Power Timer instance
1443 * @retval Returned value can be one of the following values:
1444 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
1445 * @arg @ref LL_LPTIM_TRIG_FILTER_2
1446 * @arg @ref LL_LPTIM_TRIG_FILTER_4
1447 * @arg @ref LL_LPTIM_TRIG_FILTER_8
1448 */
LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef * LPTIMx)1449 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
1450 {
1451 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
1452 }
1453
1454 /**
1455 * @brief Get actual external trigger polarity.
1456 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
1457 * @param LPTIMx Low-Power Timer instance
1458 * @retval Returned value can be one of the following values:
1459 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
1460 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
1461 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
1462 */
LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef * LPTIMx)1463 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
1464 {
1465 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
1466 }
1467
1468 /**
1469 * @}
1470 */
1471
1472 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
1473 * @{
1474 */
1475
1476 /**
1477 * @brief Set the source of the clock used by the LPTIM instance.
1478 * @note This function must be called when the LPTIM instance is disabled.
1479 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
1480 * @param LPTIMx Low-Power Timer instance
1481 * @param ClockSource This parameter can be one of the following values:
1482 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
1483 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
1484 * @retval None
1485 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)1486 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
1487 {
1488 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
1489 }
1490
1491 /**
1492 * @brief Get actual LPTIM instance clock source.
1493 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
1494 * @param LPTIMx Low-Power Timer instance
1495 * @retval Returned value can be one of the following values:
1496 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
1497 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
1498 */
LL_LPTIM_GetClockSource(const LPTIM_TypeDef * LPTIMx)1499 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
1500 {
1501 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
1502 }
1503
1504 /**
1505 * @brief Configure the active edge or edges used by the counter when
1506 the LPTIM is clocked by an external clock source.
1507 * @note This function must be called when the LPTIM instance is disabled.
1508 * @note When both external clock signal edges are considered active ones,
1509 * the LPTIM must also be clocked by an internal clock source with a
1510 * frequency equal to at least four times the external clock frequency.
1511 * @note An internal clock source must be present when a digital filter is
1512 * required for external clock.
1513 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
1514 * CFGR CKPOL LL_LPTIM_ConfigClock
1515 * @param LPTIMx Low-Power Timer instance
1516 * @param ClockFilter This parameter can be one of the following values:
1517 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1518 * @arg @ref LL_LPTIM_CLK_FILTER_2
1519 * @arg @ref LL_LPTIM_CLK_FILTER_4
1520 * @arg @ref LL_LPTIM_CLK_FILTER_8
1521 * @param ClockPolarity This parameter can be one of the following values:
1522 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
1523 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
1524 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
1525 * @retval None
1526 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)1527 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
1528 {
1529 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
1530 }
1531
1532 /**
1533 * @brief Get actual clock polarity
1534 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
1535 * @param LPTIMx Low-Power Timer instance
1536 * @retval Returned value can be one of the following values:
1537 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
1538 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
1539 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
1540 */
LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef * LPTIMx)1541 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
1542 {
1543 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1544 }
1545
1546 /**
1547 * @brief Get actual clock digital filter
1548 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
1549 * @param LPTIMx Low-Power Timer instance
1550 * @retval Returned value can be one of the following values:
1551 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
1552 * @arg @ref LL_LPTIM_CLK_FILTER_2
1553 * @arg @ref LL_LPTIM_CLK_FILTER_4
1554 * @arg @ref LL_LPTIM_CLK_FILTER_8
1555 */
LL_LPTIM_GetClockFilter(const LPTIM_TypeDef * LPTIMx)1556 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
1557 {
1558 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
1559 }
1560
1561 /**
1562 * @}
1563 */
1564
1565 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
1566 * @{
1567 */
1568
1569 /**
1570 * @brief Configure the encoder mode.
1571 * @note This function must be called when the LPTIM instance is disabled.
1572 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
1573 * @param LPTIMx Low-Power Timer instance
1574 * @param EncoderMode This parameter can be one of the following values:
1575 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1576 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1577 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1578 * @retval None
1579 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)1580 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
1581 {
1582 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
1583 }
1584
1585 /**
1586 * @brief Get actual encoder mode.
1587 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1588 * @param LPTIMx Low-Power Timer instance
1589 * @retval Returned value can be one of the following values:
1590 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1591 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1592 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1593 */
LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef * LPTIMx)1594 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
1595 {
1596 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1597 }
1598
1599 /**
1600 * @brief Enable the encoder mode
1601 * @note This function must be called when the LPTIM instance is disabled.
1602 * @note In this mode the LPTIM instance must be clocked by an internal clock
1603 * source. Also, the prescaler division ratio must be equal to 1.
1604 * @note LPTIM instance must be configured in continuous mode prior enabling
1605 * the encoder mode.
1606 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1607 * @param LPTIMx Low-Power Timer instance
1608 * @retval None
1609 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)1610 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1611 {
1612 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1613 }
1614
1615 /**
1616 * @brief Disable the encoder mode
1617 * @note This function must be called when the LPTIM instance is disabled.
1618 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1619 * @param LPTIMx Low-Power Timer instance
1620 * @retval None
1621 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)1622 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1623 {
1624 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1625 }
1626
1627 /**
1628 * @brief Indicates whether the LPTIM operates in encoder mode.
1629 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1630 * @param LPTIMx Low-Power Timer instance
1631 * @retval State of bit (1 or 0).
1632 */
LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef * LPTIMx)1633 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
1634 {
1635 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
1636 }
1637
1638 /**
1639 * @}
1640 */
1641
1642 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1643 * @{
1644 */
1645
1646 /**
1647 * @brief Clear the compare match flag for channel 1 (CC1CF)
1648 * @rmtoll ICR CC1CF LL_LPTIM_ClearFlag_CC1
1649 * @param LPTIMx Low-Power Timer instance
1650 * @retval None
1651 */
LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef * LPTIMx)1652 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef *LPTIMx)
1653 {
1654 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1CF);
1655 }
1656
1657 /**
1658 * @brief Inform application whether a capture/compare interrupt has occurred for channel 1.
1659 * @rmtoll ISR CC1IF LL_LPTIM_IsActiveFlag_CC1
1660 * @param LPTIMx Low-Power Timer instance
1661 * @retval State of bit (1 or 0).
1662 */
LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef * LPTIMx)1663 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef *LPTIMx)
1664 {
1665 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1IF) == LPTIM_ISR_CC1IF) ? 1UL : 0UL));
1666 }
1667
1668 /**
1669 * @brief Clear the compare match flag for channel 2 (CC2CF)
1670 * @rmtoll ICR CC2CF LL_LPTIM_ClearFlag_CC2
1671 * @param LPTIMx Low-Power Timer instance
1672 * @retval None
1673 */
LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef * LPTIMx)1674 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef *LPTIMx)
1675 {
1676 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2CF);
1677 }
1678
1679 /**
1680 * @brief Inform application whether a capture/compare interrupt has occurred for channel 2.
1681 * @rmtoll ISR CC2IF LL_LPTIM_IsActiveFlag_CC2
1682 * @param LPTIMx Low-Power Timer instance
1683 * @retval State of bit (1 or 0).
1684 */
LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef * LPTIMx)1685 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef *LPTIMx)
1686 {
1687 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2IF) == LPTIM_ISR_CC2IF) ? 1UL : 0UL));
1688 }
1689
1690 /**
1691 * @brief Clear the Capture/Compare 1 over-capture flag for channel 1 (CC1OCF)
1692 * @rmtoll ICR CC1OCF LL_LPTIM_ClearFlag_CC1O
1693 * @param LPTIMx Low-Power Timer instance
1694 * @retval None
1695 */
LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef * LPTIMx)1696 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef *LPTIMx)
1697 {
1698 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1OCF);
1699 }
1700
1701 /**
1702 * @brief Inform application whether a Capture/Compare 1 over-capture has occurred for channel 1.
1703 * @rmtoll ISR CC1OF LL_LPTIM_IsActiveFlag_CC1O
1704 * @param LPTIMx Low-Power Timer instance
1705 * @retval State of bit (1 or 0).
1706 */
LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef * LPTIMx)1707 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef *LPTIMx)
1708 {
1709 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1OF) == LPTIM_ISR_CC1OF) ? 1UL : 0UL));
1710 }
1711
1712 /**
1713 * @brief Clear the Capture/Compare 2 over-capture flag for channel 2 (CC2OCF)
1714 * @rmtoll ICR CC2OCF LL_LPTIM_ClearFlag_CC2O
1715 * @param LPTIMx Low-Power Timer instance
1716 * @retval None
1717 */
LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef * LPTIMx)1718 __STATIC_INLINE void LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef *LPTIMx)
1719 {
1720 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2OCF);
1721 }
1722
1723 /**
1724 * @brief Inform application whether a Capture/Compare 2 over-capture has occurred for channel 2.
1725 * @rmtoll ISR CC2OF LL_LPTIM_IsActiveFlag_CC2O
1726 * @param LPTIMx Low-Power Timer instance
1727 * @retval State of bit (1 or 0).
1728 */
LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef * LPTIMx)1729 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *LPTIMx)
1730 {
1731 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL));
1732 }
1733 /**
1734 * @brief Clear the autoreload match flag (ARRMCF)
1735 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM
1736 * @param LPTIMx Low-Power Timer instance
1737 * @retval None
1738 */
LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef * LPTIMx)1739 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1740 {
1741 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1742 }
1743
1744 /**
1745 * @brief Inform application whether a autoreload match interrupt has occurred.
1746 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1747 * @param LPTIMx Low-Power Timer instance
1748 * @retval State of bit (1 or 0).
1749 */
LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef * LPTIMx)1750 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
1751 {
1752 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
1753 }
1754
1755 /**
1756 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1757 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1758 * @param LPTIMx Low-Power Timer instance
1759 * @retval None
1760 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1761 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1762 {
1763 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1764 }
1765
1766 /**
1767 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1768 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1769 * @param LPTIMx Low-Power Timer instance
1770 * @retval State of bit (1 or 0).
1771 */
LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef * LPTIMx)1772 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
1773 {
1774 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
1775 }
1776
1777 /**
1778 * @brief Clear the compare register update interrupt flag (CMP1OKCF).
1779 * @rmtoll ICR CMP1OKCF LL_LPTIM_ClearFlag_CMP1OK
1780 * @param LPTIMx Low-Power Timer instance
1781 * @retval None
1782 */
LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef * LPTIMx)1783 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef *LPTIMx)
1784 {
1785 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP1OKCF);
1786 }
1787
1788 /**
1789 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR1 register has been successfully
1790 completed. If so, a new one can be initiated.
1791 * @rmtoll ISR CMP1OK LL_LPTIM_IsActiveFlag_CMP1OK
1792 * @param LPTIMx Low-Power Timer instance
1793 * @retval State of bit (1 or 0).
1794 */
LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef * LPTIMx)1795 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef *LPTIMx)
1796 {
1797 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP1OK) == LPTIM_ISR_CMP1OK) ? 1UL : 0UL));
1798 }
1799
1800 /**
1801 * @brief Clear the compare register update interrupt flag (CMP2OKCF).
1802 * @rmtoll ICR CMP2OKCF LL_LPTIM_ClearFlag_CMP2OK
1803 * @param LPTIMx Low-Power Timer instance
1804 * @retval None
1805 */
LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef * LPTIMx)1806 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef *LPTIMx)
1807 {
1808 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP2OKCF);
1809 }
1810
1811 /**
1812 * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR2 register has been successfully
1813 completed. If so, a new one can be initiated.
1814 * @rmtoll ISR CMP2OK LL_LPTIM_IsActiveFlag_CMP2OK
1815 * @param LPTIMx Low-Power Timer instance
1816 * @retval State of bit (1 or 0).
1817 */
LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef * LPTIMx)1818 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef *LPTIMx)
1819 {
1820 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP2OK) == LPTIM_ISR_CMP2OK) ? 1UL : 0UL));
1821 }
1822
1823 /**
1824 * @brief Clear the interrupt register update interrupt flag (DIEROKCF).
1825 * @rmtoll ICR DIEROKCF LL_LPTIM_ClearFlag_DIEROK
1826 * @param LPTIMx Low-Power Timer instance
1827 * @retval None
1828 */
LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef * LPTIMx)1829 __STATIC_INLINE void LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef *LPTIMx)
1830 {
1831 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DIEROKCF);
1832 }
1833
1834 /**
1835 * @brief Informs application whether the APB bus write operation to the LPTIMx_DIER register has been successfully
1836 completed. If so, a new one can be initiated.
1837 * @rmtoll ISR DIEROK LL_LPTIM_IsActiveFlag_DIEROK
1838 * @param LPTIMx Low-Power Timer instance
1839 * @retval State of bit (1 or 0).
1840 */
LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef * LPTIMx)1841 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef *LPTIMx)
1842 {
1843 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DIEROK) == (LPTIM_ISR_DIEROK)) ? 1UL : 0UL);
1844 }
1845
1846 /**
1847 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1848 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1849 * @param LPTIMx Low-Power Timer instance
1850 * @retval None
1851 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)1852 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1853 {
1854 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1855 }
1856
1857 /**
1858 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
1859 completed. If so, a new one can be initiated.
1860 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1861 * @param LPTIMx Low-Power Timer instance
1862 * @retval State of bit (1 or 0).
1863 */
LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef * LPTIMx)1864 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
1865 {
1866 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
1867 }
1868
1869 /**
1870 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1871 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1872 * @param LPTIMx Low-Power Timer instance
1873 * @retval None
1874 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)1875 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1876 {
1877 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1878 }
1879
1880 /**
1881 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
1882 operates in encoder mode).
1883 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1884 * @param LPTIMx Low-Power Timer instance
1885 * @retval State of bit (1 or 0).
1886 */
LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef * LPTIMx)1887 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
1888 {
1889 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
1890 }
1891
1892 /**
1893 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1894 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1895 * @param LPTIMx Low-Power Timer instance
1896 * @retval None
1897 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)1898 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1899 {
1900 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1901 }
1902
1903 /**
1904 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
1905 operates in encoder mode).
1906 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1907 * @param LPTIMx Low-Power Timer instance
1908 * @retval State of bit (1 or 0).
1909 */
LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef * LPTIMx)1910 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
1911 {
1912 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
1913 }
1914
1915 /**
1916 * @brief Clear the repetition register update interrupt flag (REPOKCF).
1917 * @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK
1918 * @param LPTIMx Low-Power Timer instance
1919 * @retval None
1920 */
LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef * LPTIMx)1921 __STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx)
1922 {
1923 SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF);
1924 }
1925
1926 /**
1927 * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully
1928 completed; If so, a new one can be initiated.
1929 * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK
1930 * @param LPTIMx Low-Power Timer instance
1931 * @retval State of bit (1 or 0).
1932 */
LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef * LPTIMx)1933 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *LPTIMx)
1934 {
1935 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL);
1936 }
1937
1938 /**
1939 * @brief Clear the update event flag (UECF).
1940 * @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE
1941 * @param LPTIMx Low-Power Timer instance
1942 * @retval None
1943 */
LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef * LPTIMx)1944 __STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx)
1945 {
1946 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF);
1947 }
1948
1949 /**
1950 * @brief Informs application whether the LPTIMx update event has occurred.
1951 * @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE
1952 * @param LPTIMx Low-Power Timer instance
1953 * @retval State of bit (1 or 0).
1954 */
LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef * LPTIMx)1955 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *LPTIMx)
1956 {
1957 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL);
1958 }
1959
1960 /**
1961 * @}
1962 */
1963
1964 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1965 * @{
1966 */
1967 /**
1968 * @brief Enable capture/compare 1 interrupt (CC1IE).
1969 * @rmtoll DIER CC1IE LL_LPTIM_EnableIT_CC1
1970 * @param LPTIMx Low-Power Timer instance
1971 * @retval None
1972 */
LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef * LPTIMx)1973 __STATIC_INLINE void LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef *LPTIMx)
1974 {
1975 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
1976 }
1977
1978 /**
1979 * @brief Disable capture/compare 1 interrupt (CC1IE).
1980 * @rmtoll DIER CC1IE LL_LPTIM_DisableIT_CC1
1981 * @param LPTIMx Low-Power Timer instance
1982 * @retval None
1983 */
LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef * LPTIMx)1984 __STATIC_INLINE void LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef *LPTIMx)
1985 {
1986 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
1987 }
1988
1989 /**
1990 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
1991 * @rmtoll DIER CC1IE LL_LPTIM_IsEnabledIT_CC1
1992 * @param LPTIMx Low-Power Timer instance
1993 * @retval State of bit (1 or 0).
1994 */
LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef * LPTIMx)1995 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef *LPTIMx)
1996 {
1997 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE) == LPTIM_DIER_CC1IE) ? 1UL : 0UL));
1998 }
1999
2000 /**
2001 * @brief Enable capture/compare 1 interrupt (CC2IE).
2002 * @rmtoll DIER CC2IE LL_LPTIM_EnableIT_CC2
2003 * @param LPTIMx Low-Power Timer instance
2004 * @retval None
2005 */
LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef * LPTIMx)2006 __STATIC_INLINE void LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef *LPTIMx)
2007 {
2008 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
2009 }
2010
2011 /**
2012 * @brief Disable capture/compare 2 interrupt (CC2IE).
2013 * @rmtoll DIER CC2IE LL_LPTIM_DisableIT_CC2
2014 * @param LPTIMx Low-Power Timer instance
2015 * @retval None
2016 */
LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef * LPTIMx)2017 __STATIC_INLINE void LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef *LPTIMx)
2018 {
2019 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
2020 }
2021
2022 /**
2023 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
2024 * @rmtoll DIER CC2IE LL_LPTIM_IsEnabledIT_CC2
2025 * @param LPTIMx Low-Power Timer instance
2026 * @retval State of bit (1 or 0).
2027 */
LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef * LPTIMx)2028 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef *LPTIMx)
2029 {
2030 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE) == LPTIM_DIER_CC2IE) ? 1UL : 0UL));
2031 }
2032
2033 /**
2034 * @brief Enable capture/compare 1 over-capture interrupt (CC1OIE).
2035 * @rmtoll DIER CC1OIE LL_LPTIM_EnableIT_CC1O
2036 * @param LPTIMx Low-Power Timer instance
2037 * @retval None
2038 */
LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef * LPTIMx)2039 __STATIC_INLINE void LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef *LPTIMx)
2040 {
2041 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
2042 }
2043
2044 /**
2045 * @brief Disable capture/compare 1 over-capture interrupt (CC1OIE).
2046 * @rmtoll DIER CC1OIE LL_LPTIM_DisableIT_CC1O
2047 * @param LPTIMx Low-Power Timer instance
2048 * @retval None
2049 */
LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef * LPTIMx)2050 __STATIC_INLINE void LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef *LPTIMx)
2051 {
2052 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
2053 }
2054
2055 /**
2056 * @brief Indicates whether the capture/compare 1 over-capture interrupt (CC1OIE) is enabled.
2057 * @rmtoll DIER CC1OIE LL_LPTIM_IsEnabledIT_CC1O
2058 * @param LPTIMx Low-Power Timer instance
2059 * @retval State of bit (1 or 0).
2060 */
LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef * LPTIMx)2061 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef *LPTIMx)
2062 {
2063 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE) == LPTIM_DIER_CC1OIE) ? 1UL : 0UL));
2064 }
2065
2066 /**
2067 * @brief Enable capture/compare 1 over-capture interrupt (CC2OIE).
2068 * @rmtoll DIER CC2OIE LL_LPTIM_EnableIT_CC2O
2069 * @param LPTIMx Low-Power Timer instance
2070 * @retval None
2071 */
LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef * LPTIMx)2072 __STATIC_INLINE void LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef *LPTIMx)
2073 {
2074 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
2075 }
2076
2077 /**
2078 * @brief Disable capture/compare 1 over-capture interrupt (CC2OIE).
2079 * @rmtoll DIER CC2OIE LL_LPTIM_DisableIT_CC2O
2080 * @param LPTIMx Low-Power Timer instance
2081 * @retval None
2082 */
LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef * LPTIMx)2083 __STATIC_INLINE void LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef *LPTIMx)
2084 {
2085 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
2086 }
2087
2088 /**
2089 * @brief Indicates whether the capture/compare 2 over-capture interrupt (CC2OIE) is enabled.
2090 * @rmtoll DIER CC2OIE LL_LPTIM_IsEnabledIT_CC2O
2091 * @param LPTIMx Low-Power Timer instance
2092 * @retval State of bit (1 or 0).
2093 */
LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef * LPTIMx)2094 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef *LPTIMx)
2095 {
2096 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE) == LPTIM_DIER_CC2OIE) ? 1UL : 0UL));
2097 }
2098
2099 /**
2100 * @brief Enable autoreload match interrupt (ARRMIE).
2101 * @rmtoll DIER ARRMIE LL_LPTIM_EnableIT_ARRM
2102 * @param LPTIMx Low-Power Timer instance
2103 * @retval None
2104 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)2105 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
2106 {
2107 SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
2108 }
2109
2110 /**
2111 * @brief Disable autoreload match interrupt (ARRMIE).
2112 * @rmtoll DIER ARRMIE LL_LPTIM_DisableIT_ARRM
2113 * @param LPTIMx Low-Power Timer instance
2114 * @retval None
2115 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)2116 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
2117 {
2118 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
2119 }
2120
2121 /**
2122 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
2123 * @rmtoll DIER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
2124 * @param LPTIMx Low-Power Timer instance
2125 * @retval State of bit (1 or 0).
2126 */
LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef * LPTIMx)2127 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
2128 {
2129 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE) == LPTIM_DIER_ARRMIE) ? 1UL : 0UL));
2130 }
2131
2132 /**
2133 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
2134 * @rmtoll DIER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
2135 * @param LPTIMx Low-Power Timer instance
2136 * @retval None
2137 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)2138 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2139 {
2140 SET_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
2141 }
2142
2143 /**
2144 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
2145 * @rmtoll DIER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
2146 * @param LPTIMx Low-Power Timer instance
2147 * @retval None
2148 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)2149 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
2150 {
2151 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
2152 }
2153
2154 /**
2155 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
2156 * @rmtoll DIER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
2157 * @param LPTIMx Low-Power Timer instance
2158 * @retval State of bit (1 or 0).
2159 */
LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef * LPTIMx)2160 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
2161 {
2162 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE) == LPTIM_DIER_EXTTRIGIE) ? 1UL : 0UL));
2163 }
2164
2165 /**
2166 * @brief Enable compare register write completed interrupt (CMP1OKIE).
2167 * @rmtoll IER CMP1OKIE LL_LPTIM_EnableIT_CMP1OK
2168 * @param LPTIMx Low-Power Timer instance
2169 * @retval None
2170 */
LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef * LPTIMx)2171 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
2172 {
2173 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
2174 }
2175
2176 /**
2177 * @brief Disable compare register write completed interrupt (CMP1OKIE).
2178 * @rmtoll IER CMPO1KIE LL_LPTIM_DisableIT_CMP1OK
2179 * @param LPTIMx Low-Power Timer instance
2180 * @retval None
2181 */
LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef * LPTIMx)2182 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
2183 {
2184 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
2185 }
2186
2187 /**
2188 * @brief Indicates whether the compare register write completed interrupt (CMP1OKIE) is enabled.
2189 * @rmtoll IER CMP1OKIE LL_LPTIM_IsEnabledIT_CMP1OK
2190 * @param LPTIMx Low-Power Timer instance
2191 * @retval State of bit (1 or 0).
2192 */
LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef * LPTIMx)2193 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef *LPTIMx)
2194 {
2195 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE) == LPTIM_DIER_CMP1OKIE) ? 1UL : 0UL));
2196 }
2197
2198 /**
2199 * @brief Enable compare register write completed interrupt (CMP2OKIE).
2200 * @rmtoll IER CMP2OKIE LL_LPTIM_EnableIT_CMP2OK
2201 * @param LPTIMx Low-Power Timer instance
2202 * @retval None
2203 */
LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef * LPTIMx)2204 __STATIC_INLINE void LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
2205 {
2206 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
2207 }
2208
2209 /**
2210 * @brief Disable compare register write completed interrupt (CMP2OKIE).
2211 * @rmtoll IER CMP2OKIE LL_LPTIM_DisableIT_CMP2OK
2212 * @param LPTIMx Low-Power Timer instance
2213 * @retval None
2214 */
LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef * LPTIMx)2215 __STATIC_INLINE void LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
2216 {
2217 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
2218 }
2219
2220 /**
2221 * @brief Indicates whether the compare register write completed interrupt (CMP2OKIE) is enabled.
2222 * @rmtoll IER CMP2OKIE LL_LPTIM_IsEnabledIT_CMP2OK
2223 * @param LPTIMx Low-Power Timer instance
2224 * @retval State of bit (1 or 0).
2225 */
LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef * LPTIMx)2226 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef *LPTIMx)
2227 {
2228 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE) == LPTIM_DIER_CMP2OKIE) ? 1UL : 0UL));
2229 }
2230
2231 /**
2232 * @brief Enable autoreload register write completed interrupt (ARROKIE).
2233 * @rmtoll DIER ARROKIE LL_LPTIM_EnableIT_ARROK
2234 * @param LPTIMx Low-Power Timer instance
2235 * @retval None
2236 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)2237 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
2238 {
2239 SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
2240 }
2241
2242 /**
2243 * @brief Disable autoreload register write completed interrupt (ARROKIE).
2244 * @rmtoll DIER ARROKIE LL_LPTIM_DisableIT_ARROK
2245 * @param LPTIMx Low-Power Timer instance
2246 * @retval None
2247 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)2248 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
2249 {
2250 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
2251 }
2252
2253 /**
2254 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
2255 * @rmtoll DIER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
2256 * @param LPTIMx Low-Power Timer instance
2257 * @retval State of bit(1 or 0).
2258 */
LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef * LPTIMx)2259 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
2260 {
2261 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE) == LPTIM_DIER_ARROKIE) ? 1UL : 0UL));
2262 }
2263
2264 /**
2265 * @brief Enable direction change to up interrupt (UPIE).
2266 * @rmtoll DIER UPIE LL_LPTIM_EnableIT_UP
2267 * @param LPTIMx Low-Power Timer instance
2268 * @retval None
2269 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)2270 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
2271 {
2272 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
2273 }
2274
2275 /**
2276 * @brief Disable direction change to up interrupt (UPIE).
2277 * @rmtoll DIER UPIE LL_LPTIM_DisableIT_UP
2278 * @param LPTIMx Low-Power Timer instance
2279 * @retval None
2280 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)2281 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
2282 {
2283 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
2284 }
2285
2286 /**
2287 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
2288 * @rmtoll DIER UPIE LL_LPTIM_IsEnabledIT_UP
2289 * @param LPTIMx Low-Power Timer instance
2290 * @retval State of bit(1 or 0).
2291 */
LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef * LPTIMx)2292 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
2293 {
2294 return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE) == LPTIM_DIER_UPIE) ? 1UL : 0UL));
2295 }
2296
2297 /**
2298 * @brief Enable direction change to down interrupt (DOWNIE).
2299 * @rmtoll DIER DOWNIE LL_LPTIM_EnableIT_DOWN
2300 * @param LPTIMx Low-Power Timer instance
2301 * @retval None
2302 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)2303 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
2304 {
2305 SET_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
2306 }
2307
2308 /**
2309 * @brief Disable direction change to down interrupt (DOWNIE).
2310 * @rmtoll DIER DOWNIE LL_LPTIM_DisableIT_DOWN
2311 * @param LPTIMx Low-Power Timer instance
2312 * @retval None
2313 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)2314 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
2315 {
2316 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
2317 }
2318
2319 /**
2320 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
2321 * @rmtoll DIER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
2322 * @param LPTIMx Low-Power Timer instance
2323 * @retval State of bit(1 or 0).
2324 */
LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef * LPTIMx)2325 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
2326 {
2327 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE) == LPTIM_DIER_DOWNIE) ? 1UL : 0UL);
2328 }
2329
2330 /**
2331 * @brief Enable repetition register update successfully completed interrupt (REPOKIE).
2332 * @rmtoll DIER REPOKIE LL_LPTIM_EnableIT_REPOK
2333 * @param LPTIMx Low-Power Timer instance
2334 * @retval None
2335 */
LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef * LPTIMx)2336 __STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx)
2337 {
2338 SET_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
2339 }
2340
2341 /**
2342 * @brief Disable repetition register update successfully completed interrupt (REPOKIE).
2343 * @rmtoll DIER REPOKIE LL_LPTIM_DisableIT_REPOK
2344 * @param LPTIMx Low-Power Timer instance
2345 * @retval None
2346 */
LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef * LPTIMx)2347 __STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx)
2348 {
2349 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
2350 }
2351
2352 /**
2353 * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled.
2354 * @rmtoll DIER REPOKIE LL_LPTIM_IsEnabledIT_REPOK
2355 * @param LPTIMx Low-Power Timer instance
2356 * @retval State of bit(1 or 0).
2357 */
LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef * LPTIMx)2358 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *LPTIMx)
2359 {
2360 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE) == (LPTIM_DIER_REPOKIE)) ? 1UL : 0UL);
2361 }
2362
2363 /**
2364 * @brief Enable update event interrupt (UEIE).
2365 * @rmtoll DIER UEIE LL_LPTIM_EnableIT_UE
2366 * @param LPTIMx Low-Power Timer instance
2367 * @retval None
2368 */
LL_LPTIM_EnableIT_UE(LPTIM_TypeDef * LPTIMx)2369 __STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx)
2370 {
2371 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
2372 }
2373
2374 /**
2375 * @brief Disable update event interrupt (UEIE).
2376 * @rmtoll DIER UEIE LL_LPTIM_DisableIT_UE
2377 * @param LPTIMx Low-Power Timer instance
2378 * @retval None
2379 */
LL_LPTIM_DisableIT_UE(LPTIM_TypeDef * LPTIMx)2380 __STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx)
2381 {
2382 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
2383 }
2384
2385 /**
2386 * @brief Indicates whether the update event interrupt (UEIE) is enabled.
2387 * @rmtoll DIER UEIE LL_LPTIM_IsEnabledIT_UE
2388 * @param LPTIMx Low-Power Timer instance
2389 *@ retval State of bit(1 or 0).
2390 */
LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef * LPTIMx)2391 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *LPTIMx)
2392 {
2393 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE) == (LPTIM_DIER_UEIE)) ? 1UL : 0UL);
2394 }
2395 /**
2396 * @}
2397 */
2398
2399
2400 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
2401 * @{
2402 */
2403 /**
2404 * @brief Enable update DMA request.
2405 * @rmtoll DIER UEDE LL_LPTIM_EnableDMAReq_UPDATE
2406 * @param LPTIMx Low-Power Timer instance
2407 * @retval None
2408 */
LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef * LPTIMx)2409 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
2410 {
2411 SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
2412 }
2413
2414 /**
2415 * @brief Disable update DMA request.
2416 * @rmtoll DIER UEDE LL_LPTIM_DisableDMAReq_UPDATE
2417 * @param LPTIMx Low-Power Timer instance
2418 * @retval None
2419 */
LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef * LPTIMx)2420 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
2421 {
2422 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
2423 }
2424
2425 /**
2426 * @brief Indicates whether the update DMA request is enabled.
2427 * @rmtoll DIER UEDE LL_LPTIM_IsEnabledDMAReq_UPDATE
2428 * @param LPTIMx Low-Power Timer instance
2429 * @retval State of bit (1 or 0).
2430 */
LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef * LPTIMx)2431 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef *LPTIMx)
2432 {
2433 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE) == (LPTIM_DIER_UEDE)) ? 1UL : 0UL);
2434 }
2435
2436 /**
2437 * @brief Enable capture/compare 1 DMA request (CC1DE).
2438 * @rmtoll DIER CC1DE LL_LPTIM_EnableDMAReq_CC1
2439 * @param LPTIMx Low-Power Timer instance
2440 * @retval None
2441 */
LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef * LPTIMx)2442 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
2443 {
2444 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
2445 }
2446
2447 /**
2448 * @brief Disable capture/compare 1 DMA request (CC1DE).
2449 * @rmtoll DIER CC1DE LL_LPTIM_DisableDMAReq_CC1
2450 * @param LPTIMx Low-Power Timer instance
2451 * @retval None
2452 */
LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef * LPTIMx)2453 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
2454 {
2455 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
2456 }
2457
2458 /**
2459 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
2460 * @rmtoll DIER CC1DE LL_LPTIM_IsEnabledDMAReq_CC1
2461 * @param LPTIMx Low-Power Timer instance
2462 * @retval State of bit (1 or 0).
2463 */
LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef * LPTIMx)2464 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef *LPTIMx)
2465 {
2466 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE) == (LPTIM_DIER_CC1DE)) ? 1UL : 0UL);
2467 }
2468
2469 /**
2470 * @brief Enable capture/compare 2 DMA request (CC2DE).
2471 * @rmtoll DIER CC2DE LL_LPTIM_EnableDMAReq_CC2
2472 * @param LPTIMx Low-Power Timer instance
2473 * @retval None
2474 */
LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef * LPTIMx)2475 __STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
2476 {
2477 SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
2478 }
2479
2480 /**
2481 * @brief Disable capture/compare 2 DMA request (CC2DE).
2482 * @rmtoll DIER CC2DE LL_LPTIM_DisableDMAReq_CC2
2483 * @param LPTIMx Low-Power Timer instance
2484 * @retval None
2485 */
LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef * LPTIMx)2486 __STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
2487 {
2488 CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
2489 }
2490
2491 /**
2492 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
2493 * @rmtoll DIER CC2DE LL_LPTIM_IsEnabledDMAReq_CC2
2494 * @param LPTIMx Low-Power Timer instance
2495 * @retval State of bit (1 or 0).
2496 */
LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef * LPTIMx)2497 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef *LPTIMx)
2498 {
2499 return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE) == (LPTIM_DIER_CC2DE)) ? 1UL : 0UL);
2500 }
2501
2502 /**
2503 * @}
2504 */
2505 /**
2506 * @}
2507 */
2508
2509 /**
2510 * @}
2511 */
2512
2513 #endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 || LPTIM6 */
2514
2515 /**
2516 * @}
2517 */
2518
2519 #ifdef __cplusplus
2520 }
2521 #endif
2522
2523 #endif /* STM32H5xx_LL_LPTIM_H */
2524
