1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_i2c.h
4 * @author MCD Application Team
5 * @brief Header file of I2C LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H5xx_LL_I2C_H
21 #define STM32H5xx_LL_I2C_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h5xx.h"
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
35
36 /** @defgroup I2C_LL I2C
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
45 * @{
46 */
47 /**
48 * @}
49 */
50
51 /* Private macros ------------------------------------------------------------*/
52 #if defined(USE_FULL_LL_DRIVER)
53 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
54 * @{
55 */
56 /**
57 * @}
58 */
59 #endif /*USE_FULL_LL_DRIVER*/
60
61 /* Exported types ------------------------------------------------------------*/
62 #if defined(USE_FULL_LL_DRIVER)
63 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
64 * @{
65 */
66 typedef struct
67 {
68 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
69 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
70
71 This feature can be modified afterwards using unitary function
72 @ref LL_I2C_SetMode(). */
73
74 uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
75 This parameter must be set by referring to the STM32CubeMX Tool and
76 the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
77
78 This feature can be modified afterwards using unitary function
79 @ref LL_I2C_SetTiming(). */
80
81 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
82 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
83
84 This feature can be modified afterwards using unitary functions
85 @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
86
87 uint32_t DigitalFilter; /*!< Configures the digital noise filter.
88 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
89
90 This feature can be modified afterwards using unitary function
91 @ref LL_I2C_SetDigitalFilter(). */
92
93 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
94 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
95
96 This feature can be modified afterwards using unitary function
97 @ref LL_I2C_SetOwnAddress1(). */
98
99 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
100 match code or next received byte.
101 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
102
103 This feature can be modified afterwards using unitary function
104 @ref LL_I2C_AcknowledgeNextData(). */
105
106 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
107 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
108
109 This feature can be modified afterwards using unitary function
110 @ref LL_I2C_SetOwnAddress1(). */
111 } LL_I2C_InitTypeDef;
112 /**
113 * @}
114 */
115 #endif /*USE_FULL_LL_DRIVER*/
116
117 /* Exported constants --------------------------------------------------------*/
118 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
119 * @{
120 */
121
122 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
123 * @brief Flags defines which can be used with LL_I2C_WriteReg function
124 * @{
125 */
126 #define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */
127 #define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */
128 #define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */
129 #define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */
130 #define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */
131 #define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */
132 #define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */
133 #define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */
134 #define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */
135 /**
136 * @}
137 */
138
139 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
140 * @brief Flags defines which can be used with LL_I2C_ReadReg function
141 * @{
142 */
143 #define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */
144 #define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */
145 #define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */
146 #define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */
147 #define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */
148 #define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */
149 #define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */
150 #define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */
151 #define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */
152 #define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */
153 #define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
154 #define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
155 #define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
156 #define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
157 #define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */
158 /**
159 * @}
160 */
161
162 /** @defgroup I2C_LL_EC_IT IT Defines
163 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
164 * @{
165 */
166 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */
167 #define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */
168 #define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
169 #define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
170 #define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
171 #define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
172 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */
173 /**
174 * @}
175 */
176
177 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
178 * @{
179 */
180 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
181 #define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
182 #define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode
183 (Default address not acknowledge) */
184 #define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
185 /**
186 * @}
187 */
188
189 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
190 * @{
191 */
192 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
193 #define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
194 /**
195 * @}
196 */
197
198 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
199 * @{
200 */
201 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
202 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
203 /**
204 * @}
205 */
206
207 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
208 * @{
209 */
210 #define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
211 #define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
212 /**
213 * @}
214 */
215
216 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
217 * @{
218 */
219 #define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
220 #define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
221 #define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
222 #define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
223 #define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
224 #define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
225 #define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
226 #define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done.
227 All Address2 are acknowledged. */
228 /**
229 * @}
230 */
231
232 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
233 * @{
234 */
235 #define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
236 #define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
237 /**
238 * @}
239 */
240
241 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
242 * @{
243 */
244 #define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
245 #define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
246 /**
247 * @}
248 */
249
250 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
251 * @{
252 */
253 #define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
254 #define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
255 /**
256 * @}
257 */
258
259 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
260 * @{
261 */
262 #define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
263 #define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode
264 with no HW PEC comparison. */
265 #define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode
266 with no HW PEC comparison. */
267 #define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode
268 with HW PEC comparison. */
269 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode
270 with HW PEC comparison. */
271 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode
272 with HW PEC comparison. */
273 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
274 /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
275 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
276 /*!< Enable SMBUS Software end mode with HW PEC comparison. */
277 /**
278 * @}
279 */
280
281 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
282 * @{
283 */
284 #define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
285 /*!< Don't Generate Stop and Start condition. */
286 #define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
287 /*!< Generate Stop condition (Size should be set to 0). */
288 #define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
289 /*!< Generate Start for read request. */
290 #define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
291 /*!< Generate Start for write request. */
292 #define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
293 /*!< Generate Restart for read request, slave 7Bit address. */
294 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
295 /*!< Generate Restart for write request, slave 7Bit address. */
296 #define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \
297 I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
298 /*!< Generate Restart for read request, slave 10Bit address. */
299 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
300 /*!< Generate Restart for write request, slave 10Bit address.*/
301 /**
302 * @}
303 */
304
305 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
306 * @{
307 */
308 #define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master,
309 slave enters receiver mode. */
310 #define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master,
311 slave enters transmitter mode.*/
312 /**
313 * @}
314 */
315
316 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
317 * @{
318 */
319 #define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for
320 transmission */
321 #define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for
322 reception */
323 /**
324 * @}
325 */
326
327 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
328 * @{
329 */
330 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect
331 SCL low level timeout. */
332 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect
333 both SCL and SDA high level timeout.*/
334 /**
335 * @}
336 */
337
338 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
339 * @{
340 */
341 #define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
342 #define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock)
343 enable bit */
344 #define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
345 I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB
346 (extended clock) enable bits */
347 /**
348 * @}
349 */
350
351 /**
352 * @}
353 */
354
355 /* Exported macro ------------------------------------------------------------*/
356 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
357 * @{
358 */
359
360 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
361 * @{
362 */
363
364 /**
365 * @brief Write a value in I2C register
366 * @param __INSTANCE__ I2C Instance
367 * @param __REG__ Register to be written
368 * @param __VALUE__ Value to be written in the register
369 * @retval None
370 */
371 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
372
373 /**
374 * @brief Read a value in I2C register
375 * @param __INSTANCE__ I2C Instance
376 * @param __REG__ Register to be read
377 * @retval Register value
378 */
379 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
380 /**
381 * @}
382 */
383
384 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
385 * @{
386 */
387 /**
388 * @brief Configure the SDA setup, hold time and the SCL high, low period.
389 * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
390 * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
391 (tscldel = (SCLDEL+1)xtpresc)
392 * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
393 (tsdadel = SDADELxtpresc)
394 * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
395 (tsclh = (SCLH+1)xtpresc)
396 * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
397 (tscll = (SCLL+1)xtpresc)
398 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
399 */
400 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
401 ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
402 (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
403 (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
404 (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
405 (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
406 /**
407 * @}
408 */
409
410 /**
411 * @}
412 */
413
414 /* Exported functions --------------------------------------------------------*/
415 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
416 * @{
417 */
418
419 /** @defgroup I2C_LL_EF_Configuration Configuration
420 * @{
421 */
422
423 /**
424 * @brief Enable I2C peripheral (PE = 1).
425 * @rmtoll CR1 PE LL_I2C_Enable
426 * @param I2Cx I2C Instance.
427 * @retval None
428 */
LL_I2C_Enable(I2C_TypeDef * I2Cx)429 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
430 {
431 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
432 }
433
434 /**
435 * @brief Disable I2C peripheral (PE = 0).
436 * @note When PE = 0, the I2C SCL and SDA lines are released.
437 * Internal state machines and status bits are put back to their reset value.
438 * When cleared, PE must be kept low for at least 3 APB clock cycles.
439 * @rmtoll CR1 PE LL_I2C_Disable
440 * @param I2Cx I2C Instance.
441 * @retval None
442 */
LL_I2C_Disable(I2C_TypeDef * I2Cx)443 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
444 {
445 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
446 }
447
448 /**
449 * @brief Check if the I2C peripheral is enabled or disabled.
450 * @rmtoll CR1 PE LL_I2C_IsEnabled
451 * @param I2Cx I2C Instance.
452 * @retval State of bit (1 or 0).
453 */
LL_I2C_IsEnabled(I2C_TypeDef * I2Cx)454 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
455 {
456 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
457 }
458
459 /**
460 * @brief Configure Noise Filters (Analog and Digital).
461 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
462 * The filters can only be programmed when the I2C is disabled (PE = 0).
463 * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
464 * CR1 DNF LL_I2C_ConfigFilters
465 * @param I2Cx I2C Instance.
466 * @param AnalogFilter This parameter can be one of the following values:
467 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
468 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
469 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
470 and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
471 * This parameter is used to configure the digital noise filter on SDA and SCL input.
472 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
473 * @retval None
474 */
LL_I2C_ConfigFilters(I2C_TypeDef * I2Cx,uint32_t AnalogFilter,uint32_t DigitalFilter)475 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
476 {
477 MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
478 }
479
480 /**
481 * @brief Configure Digital Noise Filter.
482 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
483 * This filter can only be programmed when the I2C is disabled (PE = 0).
484 * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
485 * @param I2Cx I2C Instance.
486 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
487 and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
488 * This parameter is used to configure the digital noise filter on SDA and SCL input.
489 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
490 * @retval None
491 */
LL_I2C_SetDigitalFilter(I2C_TypeDef * I2Cx,uint32_t DigitalFilter)492 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
493 {
494 MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
495 }
496
497 /**
498 * @brief Get the current Digital Noise Filter configuration.
499 * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
500 * @param I2Cx I2C Instance.
501 * @retval Value between Min_Data=0x0 and Max_Data=0xF
502 */
LL_I2C_GetDigitalFilter(I2C_TypeDef * I2Cx)503 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
504 {
505 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
506 }
507
508 /**
509 * @brief Enable Analog Noise Filter.
510 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
511 * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
512 * @param I2Cx I2C Instance.
513 * @retval None
514 */
LL_I2C_EnableAnalogFilter(I2C_TypeDef * I2Cx)515 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
516 {
517 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
518 }
519
520 /**
521 * @brief Disable Analog Noise Filter.
522 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
523 * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
524 * @param I2Cx I2C Instance.
525 * @retval None
526 */
LL_I2C_DisableAnalogFilter(I2C_TypeDef * I2Cx)527 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
528 {
529 SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
530 }
531
532 /**
533 * @brief Check if Analog Noise Filter is enabled or disabled.
534 * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
535 * @param I2Cx I2C Instance.
536 * @retval State of bit (1 or 0).
537 */
LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef * I2Cx)538 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
539 {
540 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
541 }
542
543 /**
544 * @brief Enable DMA transmission requests.
545 * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
546 * @param I2Cx I2C Instance.
547 * @retval None
548 */
LL_I2C_EnableDMAReq_TX(I2C_TypeDef * I2Cx)549 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
550 {
551 SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
552 }
553
554 /**
555 * @brief Disable DMA transmission requests.
556 * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
557 * @param I2Cx I2C Instance.
558 * @retval None
559 */
LL_I2C_DisableDMAReq_TX(I2C_TypeDef * I2Cx)560 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
561 {
562 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
563 }
564
565 /**
566 * @brief Check if DMA transmission requests are enabled or disabled.
567 * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
568 * @param I2Cx I2C Instance.
569 * @retval State of bit (1 or 0).
570 */
LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef * I2Cx)571 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
572 {
573 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
574 }
575
576 /**
577 * @brief Enable DMA reception requests.
578 * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
579 * @param I2Cx I2C Instance.
580 * @retval None
581 */
LL_I2C_EnableDMAReq_RX(I2C_TypeDef * I2Cx)582 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
583 {
584 SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
585 }
586
587 /**
588 * @brief Disable DMA reception requests.
589 * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
590 * @param I2Cx I2C Instance.
591 * @retval None
592 */
LL_I2C_DisableDMAReq_RX(I2C_TypeDef * I2Cx)593 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
594 {
595 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
596 }
597
598 /**
599 * @brief Check if DMA reception requests are enabled or disabled.
600 * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
601 * @param I2Cx I2C Instance.
602 * @retval State of bit (1 or 0).
603 */
LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef * I2Cx)604 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
605 {
606 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
607 }
608
609 /**
610 * @brief Get the data register address used for DMA transfer
611 * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
612 * RXDR RXDATA LL_I2C_DMA_GetRegAddr
613 * @param I2Cx I2C Instance
614 * @param Direction This parameter can be one of the following values:
615 * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
616 * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
617 * @retval Address of data register
618 */
LL_I2C_DMA_GetRegAddr(I2C_TypeDef * I2Cx,uint32_t Direction)619 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
620 {
621 uint32_t data_reg_addr;
622
623 if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
624 {
625 /* return address of TXDR register */
626 data_reg_addr = (uint32_t) &(I2Cx->TXDR);
627 }
628 else
629 {
630 /* return address of RXDR register */
631 data_reg_addr = (uint32_t) &(I2Cx->RXDR);
632 }
633
634 return data_reg_addr;
635 }
636
637 /**
638 * @brief Enable Clock stretching.
639 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
640 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
641 * @param I2Cx I2C Instance.
642 * @retval None
643 */
LL_I2C_EnableClockStretching(I2C_TypeDef * I2Cx)644 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
645 {
646 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
647 }
648
649 /**
650 * @brief Disable Clock stretching.
651 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
652 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
653 * @param I2Cx I2C Instance.
654 * @retval None
655 */
LL_I2C_DisableClockStretching(I2C_TypeDef * I2Cx)656 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
657 {
658 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
659 }
660
661 /**
662 * @brief Check if Clock stretching is enabled or disabled.
663 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
664 * @param I2Cx I2C Instance.
665 * @retval State of bit (1 or 0).
666 */
LL_I2C_IsEnabledClockStretching(I2C_TypeDef * I2Cx)667 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
668 {
669 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
670 }
671
672 /**
673 * @brief Enable hardware byte control in slave mode.
674 * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
675 * @param I2Cx I2C Instance.
676 * @retval None
677 */
LL_I2C_EnableSlaveByteControl(I2C_TypeDef * I2Cx)678 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
679 {
680 SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
681 }
682
683 /**
684 * @brief Disable hardware byte control in slave mode.
685 * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
686 * @param I2Cx I2C Instance.
687 * @retval None
688 */
LL_I2C_DisableSlaveByteControl(I2C_TypeDef * I2Cx)689 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
690 {
691 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
692 }
693
694 /**
695 * @brief Check if hardware byte control in slave mode is enabled or disabled.
696 * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
697 * @param I2Cx I2C Instance.
698 * @retval State of bit (1 or 0).
699 */
LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef * I2Cx)700 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
701 {
702 return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
703 }
704
705 /**
706 * @brief Enable Wakeup from STOP.
707 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
708 * WakeUpFromStop feature is supported by the I2Cx Instance.
709 * @note This bit can only be programmed when Digital Filter is disabled.
710 * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
711 * @param I2Cx I2C Instance.
712 * @retval None
713 */
LL_I2C_EnableWakeUpFromStop(I2C_TypeDef * I2Cx)714 __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
715 {
716 SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
717 }
718
719 /**
720 * @brief Disable Wakeup from STOP.
721 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
722 * WakeUpFromStop feature is supported by the I2Cx Instance.
723 * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
724 * @param I2Cx I2C Instance.
725 * @retval None
726 */
LL_I2C_DisableWakeUpFromStop(I2C_TypeDef * I2Cx)727 __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
728 {
729 CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
730 }
731
732 /**
733 * @brief Check if Wakeup from STOP is enabled or disabled.
734 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
735 * WakeUpFromStop feature is supported by the I2Cx Instance.
736 * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
737 * @param I2Cx I2C Instance.
738 * @retval State of bit (1 or 0).
739 */
LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef * I2Cx)740 __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
741 {
742 return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
743 }
744
745 /**
746 * @brief Enable General Call.
747 * @note When enabled the Address 0x00 is ACKed.
748 * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
749 * @param I2Cx I2C Instance.
750 * @retval None
751 */
LL_I2C_EnableGeneralCall(I2C_TypeDef * I2Cx)752 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
753 {
754 SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
755 }
756
757 /**
758 * @brief Disable General Call.
759 * @note When disabled the Address 0x00 is NACKed.
760 * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
761 * @param I2Cx I2C Instance.
762 * @retval None
763 */
LL_I2C_DisableGeneralCall(I2C_TypeDef * I2Cx)764 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
765 {
766 CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
767 }
768
769 /**
770 * @brief Check if General Call is enabled or disabled.
771 * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
772 * @param I2Cx I2C Instance.
773 * @retval State of bit (1 or 0).
774 */
LL_I2C_IsEnabledGeneralCall(I2C_TypeDef * I2Cx)775 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
776 {
777 return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
778 }
779
780 /**
781 * @brief Enable I2C Fast Mode Plus (FMP = 1).
782 * @note 20mA I/O drive enable
783 * @rmtoll CR1 FMP LL_I2C_EnableFastModePlus
784 * @param I2Cx I2C Instance.
785 * @retval None
786 */
LL_I2C_EnableFastModePlus(I2C_TypeDef * I2Cx)787 __STATIC_INLINE void LL_I2C_EnableFastModePlus(I2C_TypeDef *I2Cx)
788 {
789 SET_BIT(I2Cx->CR1, I2C_CR1_FMP);
790 }
791
792 /**
793 * @brief Disable I2C Fast Mode Plus (FMP = 0).
794 * @note 20mA I/O drive disable
795 * @rmtoll CR1 FMP LL_I2C_DisableFastModePlus
796 * @param I2Cx I2C Instance.
797 * @retval None
798 */
LL_I2C_DisableFastModePlus(I2C_TypeDef * I2Cx)799 __STATIC_INLINE void LL_I2C_DisableFastModePlus(I2C_TypeDef *I2Cx)
800 {
801 CLEAR_BIT(I2Cx->CR1, I2C_CR1_FMP);
802 }
803
804 /**
805 * @brief Check if the I2C Fast Mode Plus is enabled or disabled.
806 * @rmtoll CR1 FMP LL_I2C_IsEnabledFastModePlus
807 * @param I2Cx I2C Instance.
808 * @retval State of bit (1 or 0).
809 */
LL_I2C_IsEnabledFastModePlus(I2C_TypeDef * I2Cx)810 __STATIC_INLINE uint32_t LL_I2C_IsEnabledFastModePlus(I2C_TypeDef *I2Cx)
811 {
812 return ((READ_BIT(I2Cx->CR1, I2C_CR1_FMP) == (I2C_CR1_FMP)) ? 1UL : 0UL);
813 }
814
815 /**
816 * @brief Enable automatic clear of ADDR flag.
817 * @rmtoll CR1 ADDRACLR LL_I2C_EnableAutoClearFlag_ADDR
818 * @param I2Cx I2C Instance.
819 * @retval None
820 */
LL_I2C_EnableAutoClearFlag_ADDR(I2C_TypeDef * I2Cx)821 __STATIC_INLINE void LL_I2C_EnableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx)
822 {
823 SET_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR);
824 }
825
826 /**
827 * @brief Disable automatic clear of ADDR flag.
828 * @rmtoll CR1 ADDRACLR LL_I2C_DisableAutoClearFlag_ADDR
829 * @param I2Cx I2C Instance.
830 * @retval None
831 */
LL_I2C_DisableAutoClearFlag_ADDR(I2C_TypeDef * I2Cx)832 __STATIC_INLINE void LL_I2C_DisableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx)
833 {
834 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR);
835 }
836
837 /**
838 * @brief Check if the automatic clear of ADDR flag is enabled or disabled.
839 * @rmtoll CR1 ADDRACLR LL_I2C_IsEnabledAutoClearFlag_ADDR
840 * @param I2Cx I2C Instance.
841 * @retval State of bit (1 or 0).
842 */
LL_I2C_IsEnabledAutoClearFlag_ADDR(I2C_TypeDef * I2Cx)843 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_ADDR(I2C_TypeDef *I2Cx)
844 {
845 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR) == (I2C_CR1_ADDRACLR)) ? 1UL : 0UL);
846 }
847
848 /**
849 * @brief Enable automatic clear of STOP flag.
850 * @rmtoll CR1 STOPFACLR LL_I2C_EnableAutoClearFlag_STOP
851 * @param I2Cx I2C Instance.
852 * @retval None
853 */
LL_I2C_EnableAutoClearFlag_STOP(I2C_TypeDef * I2Cx)854 __STATIC_INLINE void LL_I2C_EnableAutoClearFlag_STOP(I2C_TypeDef *I2Cx)
855 {
856 SET_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR);
857 }
858
859 /**
860 * @brief Disable automatic clear of STOP flag.
861 * @rmtoll CR1 STOPFACLR LL_I2C_DisableAutoClearFlag_STOP
862 * @param I2Cx I2C Instance.
863 * @retval None
864 */
LL_I2C_DisableAutoClearFlag_STOP(I2C_TypeDef * I2Cx)865 __STATIC_INLINE void LL_I2C_DisableAutoClearFlag_STOP(I2C_TypeDef *I2Cx)
866 {
867 CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR);
868 }
869
870 /**
871 * @brief Check if the automatic clear of STOP flag is enabled or disabled.
872 * @rmtoll CR1 STOPFACLR LL_I2C_IsEnabledAutoClearFlag_STOP
873 * @param I2Cx I2C Instance.
874 * @retval State of bit (1 or 0).
875 */
LL_I2C_IsEnabledAutoClearFlag_STOP(I2C_TypeDef * I2Cx)876 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_STOP(I2C_TypeDef *I2Cx)
877 {
878 return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR) == (I2C_CR1_STOPFACLR)) ? 1UL : 0UL);
879 }
880
881 /**
882 * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
883 * @note Changing this bit is not allowed, when the START bit is set.
884 * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
885 * @param I2Cx I2C Instance.
886 * @param AddressingMode This parameter can be one of the following values:
887 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
888 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
889 * @retval None
890 */
LL_I2C_SetMasterAddressingMode(I2C_TypeDef * I2Cx,uint32_t AddressingMode)891 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
892 {
893 MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
894 }
895
896 /**
897 * @brief Get the Master addressing mode.
898 * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
899 * @param I2Cx I2C Instance.
900 * @retval Returned value can be one of the following values:
901 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
902 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
903 */
LL_I2C_GetMasterAddressingMode(I2C_TypeDef * I2Cx)904 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
905 {
906 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
907 }
908
909 /**
910 * @brief Set the Own Address1.
911 * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
912 * OAR1 OA1MODE LL_I2C_SetOwnAddress1
913 * @param I2Cx I2C Instance.
914 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
915 * @param OwnAddrSize This parameter can be one of the following values:
916 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
917 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
918 * @retval None
919 */
LL_I2C_SetOwnAddress1(I2C_TypeDef * I2Cx,uint32_t OwnAddress1,uint32_t OwnAddrSize)920 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
921 {
922 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
923 }
924
925 /**
926 * @brief Enable acknowledge on Own Address1 match address.
927 * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
928 * @param I2Cx I2C Instance.
929 * @retval None
930 */
LL_I2C_EnableOwnAddress1(I2C_TypeDef * I2Cx)931 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
932 {
933 SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
934 }
935
936 /**
937 * @brief Disable acknowledge on Own Address1 match address.
938 * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
939 * @param I2Cx I2C Instance.
940 * @retval None
941 */
LL_I2C_DisableOwnAddress1(I2C_TypeDef * I2Cx)942 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
943 {
944 CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
945 }
946
947 /**
948 * @brief Check if Own Address1 acknowledge is enabled or disabled.
949 * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
950 * @param I2Cx I2C Instance.
951 * @retval State of bit (1 or 0).
952 */
LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef * I2Cx)953 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
954 {
955 return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
956 }
957
958 /**
959 * @brief Set the 7bits Own Address2.
960 * @note This action has no effect if own address2 is enabled.
961 * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
962 * OAR2 OA2MSK LL_I2C_SetOwnAddress2
963 * @param I2Cx I2C Instance.
964 * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
965 * @param OwnAddrMask This parameter can be one of the following values:
966 * @arg @ref LL_I2C_OWNADDRESS2_NOMASK
967 * @arg @ref LL_I2C_OWNADDRESS2_MASK01
968 * @arg @ref LL_I2C_OWNADDRESS2_MASK02
969 * @arg @ref LL_I2C_OWNADDRESS2_MASK03
970 * @arg @ref LL_I2C_OWNADDRESS2_MASK04
971 * @arg @ref LL_I2C_OWNADDRESS2_MASK05
972 * @arg @ref LL_I2C_OWNADDRESS2_MASK06
973 * @arg @ref LL_I2C_OWNADDRESS2_MASK07
974 * @retval None
975 */
LL_I2C_SetOwnAddress2(I2C_TypeDef * I2Cx,uint32_t OwnAddress2,uint32_t OwnAddrMask)976 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
977 {
978 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
979 }
980
981 /**
982 * @brief Enable acknowledge on Own Address2 match address.
983 * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
984 * @param I2Cx I2C Instance.
985 * @retval None
986 */
LL_I2C_EnableOwnAddress2(I2C_TypeDef * I2Cx)987 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
988 {
989 SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
990 }
991
992 /**
993 * @brief Disable acknowledge on Own Address2 match address.
994 * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
995 * @param I2Cx I2C Instance.
996 * @retval None
997 */
LL_I2C_DisableOwnAddress2(I2C_TypeDef * I2Cx)998 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
999 {
1000 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
1001 }
1002
1003 /**
1004 * @brief Check if Own Address1 acknowledge is enabled or disabled.
1005 * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
1006 * @param I2Cx I2C Instance.
1007 * @retval State of bit (1 or 0).
1008 */
LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef * I2Cx)1009 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
1010 {
1011 return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
1012 }
1013
1014 /**
1015 * @brief Configure the SDA setup, hold time and the SCL high, low period.
1016 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
1017 * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
1018 * @param I2Cx I2C Instance.
1019 * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
1020 * @note This parameter is computed with the STM32CubeMX Tool.
1021 * @retval None
1022 */
LL_I2C_SetTiming(I2C_TypeDef * I2Cx,uint32_t Timing)1023 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
1024 {
1025 WRITE_REG(I2Cx->TIMINGR, Timing);
1026 }
1027
1028 /**
1029 * @brief Get the Timing Prescaler setting.
1030 * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
1031 * @param I2Cx I2C Instance.
1032 * @retval Value between Min_Data=0x0 and Max_Data=0xF
1033 */
LL_I2C_GetTimingPrescaler(I2C_TypeDef * I2Cx)1034 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
1035 {
1036 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
1037 }
1038
1039 /**
1040 * @brief Get the SCL low period setting.
1041 * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
1042 * @param I2Cx I2C Instance.
1043 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1044 */
LL_I2C_GetClockLowPeriod(I2C_TypeDef * I2Cx)1045 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
1046 {
1047 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
1048 }
1049
1050 /**
1051 * @brief Get the SCL high period setting.
1052 * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
1053 * @param I2Cx I2C Instance.
1054 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1055 */
LL_I2C_GetClockHighPeriod(I2C_TypeDef * I2Cx)1056 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
1057 {
1058 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
1059 }
1060
1061 /**
1062 * @brief Get the SDA hold time.
1063 * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
1064 * @param I2Cx I2C Instance.
1065 * @retval Value between Min_Data=0x0 and Max_Data=0xF
1066 */
LL_I2C_GetDataHoldTime(I2C_TypeDef * I2Cx)1067 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
1068 {
1069 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
1070 }
1071
1072 /**
1073 * @brief Get the SDA setup time.
1074 * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
1075 * @param I2Cx I2C Instance.
1076 * @retval Value between Min_Data=0x0 and Max_Data=0xF
1077 */
LL_I2C_GetDataSetupTime(I2C_TypeDef * I2Cx)1078 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
1079 {
1080 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
1081 }
1082
1083 /**
1084 * @brief Configure peripheral mode.
1085 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1086 * SMBus feature is supported by the I2Cx Instance.
1087 * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
1088 * CR1 SMBDEN LL_I2C_SetMode
1089 * @param I2Cx I2C Instance.
1090 * @param PeripheralMode This parameter can be one of the following values:
1091 * @arg @ref LL_I2C_MODE_I2C
1092 * @arg @ref LL_I2C_MODE_SMBUS_HOST
1093 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
1094 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
1095 * @retval None
1096 */
LL_I2C_SetMode(I2C_TypeDef * I2Cx,uint32_t PeripheralMode)1097 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
1098 {
1099 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
1100 }
1101
1102 /**
1103 * @brief Get peripheral mode.
1104 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1105 * SMBus feature is supported by the I2Cx Instance.
1106 * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
1107 * CR1 SMBDEN LL_I2C_GetMode
1108 * @param I2Cx I2C Instance.
1109 * @retval Returned value can be one of the following values:
1110 * @arg @ref LL_I2C_MODE_I2C
1111 * @arg @ref LL_I2C_MODE_SMBUS_HOST
1112 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
1113 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
1114 */
LL_I2C_GetMode(I2C_TypeDef * I2Cx)1115 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
1116 {
1117 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
1118 }
1119
1120 /**
1121 * @brief Enable SMBus alert (Host or Device mode)
1122 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1123 * SMBus feature is supported by the I2Cx Instance.
1124 * @note SMBus Device mode:
1125 * - SMBus Alert pin is drived low and
1126 * Alert Response Address Header acknowledge is enabled.
1127 * SMBus Host mode:
1128 * - SMBus Alert pin management is supported.
1129 * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
1130 * @param I2Cx I2C Instance.
1131 * @retval None
1132 */
LL_I2C_EnableSMBusAlert(I2C_TypeDef * I2Cx)1133 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
1134 {
1135 SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
1136 }
1137
1138 /**
1139 * @brief Disable SMBus alert (Host or Device mode)
1140 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1141 * SMBus feature is supported by the I2Cx Instance.
1142 * @note SMBus Device mode:
1143 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
1144 * Alert Response Address Header acknowledge is disabled.
1145 * SMBus Host mode:
1146 * - SMBus Alert pin management is not supported.
1147 * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
1148 * @param I2Cx I2C Instance.
1149 * @retval None
1150 */
LL_I2C_DisableSMBusAlert(I2C_TypeDef * I2Cx)1151 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
1152 {
1153 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
1154 }
1155
1156 /**
1157 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
1158 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1159 * SMBus feature is supported by the I2Cx Instance.
1160 * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
1161 * @param I2Cx I2C Instance.
1162 * @retval State of bit (1 or 0).
1163 */
LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef * I2Cx)1164 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
1165 {
1166 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
1167 }
1168
1169 /**
1170 * @brief Enable SMBus Packet Error Calculation (PEC).
1171 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1172 * SMBus feature is supported by the I2Cx Instance.
1173 * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
1174 * @param I2Cx I2C Instance.
1175 * @retval None
1176 */
LL_I2C_EnableSMBusPEC(I2C_TypeDef * I2Cx)1177 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
1178 {
1179 SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1180 }
1181
1182 /**
1183 * @brief Disable SMBus Packet Error Calculation (PEC).
1184 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1185 * SMBus feature is supported by the I2Cx Instance.
1186 * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
1187 * @param I2Cx I2C Instance.
1188 * @retval None
1189 */
LL_I2C_DisableSMBusPEC(I2C_TypeDef * I2Cx)1190 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
1191 {
1192 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1193 }
1194
1195 /**
1196 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
1197 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1198 * SMBus feature is supported by the I2Cx Instance.
1199 * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
1200 * @param I2Cx I2C Instance.
1201 * @retval State of bit (1 or 0).
1202 */
LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef * I2Cx)1203 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
1204 {
1205 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
1206 }
1207
1208 /**
1209 * @brief Configure the SMBus Clock Timeout.
1210 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1211 * SMBus feature is supported by the I2Cx Instance.
1212 * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
1213 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
1214 * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
1215 * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
1216 * @param I2Cx I2C Instance.
1217 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1218 * @param TimeoutAMode This parameter can be one of the following values:
1219 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1220 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1221 * @param TimeoutB
1222 * @retval None
1223 */
LL_I2C_ConfigSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t TimeoutA,uint32_t TimeoutAMode,uint32_t TimeoutB)1224 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
1225 uint32_t TimeoutB)
1226 {
1227 MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
1228 TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
1229 }
1230
1231 /**
1232 * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
1233 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1234 * SMBus feature is supported by the I2Cx Instance.
1235 * @note These bits can only be programmed when TimeoutA is disabled.
1236 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
1237 * @param I2Cx I2C Instance.
1238 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1239 * @retval None
1240 */
LL_I2C_SetSMBusTimeoutA(I2C_TypeDef * I2Cx,uint32_t TimeoutA)1241 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
1242 {
1243 WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
1244 }
1245
1246 /**
1247 * @brief Get the SMBus Clock TimeoutA setting.
1248 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1249 * SMBus feature is supported by the I2Cx Instance.
1250 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
1251 * @param I2Cx I2C Instance.
1252 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1253 */
LL_I2C_GetSMBusTimeoutA(I2C_TypeDef * I2Cx)1254 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
1255 {
1256 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
1257 }
1258
1259 /**
1260 * @brief Set the SMBus Clock TimeoutA mode.
1261 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1262 * SMBus feature is supported by the I2Cx Instance.
1263 * @note This bit can only be programmed when TimeoutA is disabled.
1264 * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
1265 * @param I2Cx I2C Instance.
1266 * @param TimeoutAMode This parameter can be one of the following values:
1267 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1268 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1269 * @retval None
1270 */
LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef * I2Cx,uint32_t TimeoutAMode)1271 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
1272 {
1273 WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
1274 }
1275
1276 /**
1277 * @brief Get the SMBus Clock TimeoutA mode.
1278 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1279 * SMBus feature is supported by the I2Cx Instance.
1280 * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
1281 * @param I2Cx I2C Instance.
1282 * @retval Returned value can be one of the following values:
1283 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1284 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1285 */
LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef * I2Cx)1286 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
1287 {
1288 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
1289 }
1290
1291 /**
1292 * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
1293 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1294 * SMBus feature is supported by the I2Cx Instance.
1295 * @note These bits can only be programmed when TimeoutB is disabled.
1296 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
1297 * @param I2Cx I2C Instance.
1298 * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1299 * @retval None
1300 */
LL_I2C_SetSMBusTimeoutB(I2C_TypeDef * I2Cx,uint32_t TimeoutB)1301 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
1302 {
1303 WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
1304 }
1305
1306 /**
1307 * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
1308 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1309 * SMBus feature is supported by the I2Cx Instance.
1310 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
1311 * @param I2Cx I2C Instance.
1312 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1313 */
LL_I2C_GetSMBusTimeoutB(I2C_TypeDef * I2Cx)1314 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
1315 {
1316 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
1317 }
1318
1319 /**
1320 * @brief Enable the SMBus Clock Timeout.
1321 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1322 * SMBus feature is supported by the I2Cx Instance.
1323 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
1324 * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
1325 * @param I2Cx I2C Instance.
1326 * @param ClockTimeout This parameter can be one of the following values:
1327 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1328 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1329 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1330 * @retval None
1331 */
LL_I2C_EnableSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1332 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1333 {
1334 SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1335 }
1336
1337 /**
1338 * @brief Disable the SMBus Clock Timeout.
1339 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1340 * SMBus feature is supported by the I2Cx Instance.
1341 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
1342 * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
1343 * @param I2Cx I2C Instance.
1344 * @param ClockTimeout This parameter can be one of the following values:
1345 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1346 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1347 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1348 * @retval None
1349 */
LL_I2C_DisableSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1350 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1351 {
1352 CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1353 }
1354
1355 /**
1356 * @brief Check if the SMBus Clock Timeout is enabled or disabled.
1357 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1358 * SMBus feature is supported by the I2Cx Instance.
1359 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
1360 * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
1361 * @param I2Cx I2C Instance.
1362 * @param ClockTimeout This parameter can be one of the following values:
1363 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1364 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1365 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1366 * @retval State of bit (1 or 0).
1367 */
LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef * I2Cx,uint32_t ClockTimeout)1368 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1369 {
1370 return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
1371 (ClockTimeout)) ? 1UL : 0UL);
1372 }
1373
1374 /**
1375 * @}
1376 */
1377
1378 /** @defgroup I2C_LL_EF_IT_Management IT_Management
1379 * @{
1380 */
1381
1382 /**
1383 * @brief Enable TXIS interrupt.
1384 * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
1385 * @param I2Cx I2C Instance.
1386 * @retval None
1387 */
LL_I2C_EnableIT_TX(I2C_TypeDef * I2Cx)1388 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
1389 {
1390 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1391 }
1392
1393 /**
1394 * @brief Disable TXIS interrupt.
1395 * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
1396 * @param I2Cx I2C Instance.
1397 * @retval None
1398 */
LL_I2C_DisableIT_TX(I2C_TypeDef * I2Cx)1399 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
1400 {
1401 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1402 }
1403
1404 /**
1405 * @brief Check if the TXIS Interrupt is enabled or disabled.
1406 * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
1407 * @param I2Cx I2C Instance.
1408 * @retval State of bit (1 or 0).
1409 */
LL_I2C_IsEnabledIT_TX(I2C_TypeDef * I2Cx)1410 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
1411 {
1412 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
1413 }
1414
1415 /**
1416 * @brief Enable RXNE interrupt.
1417 * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
1418 * @param I2Cx I2C Instance.
1419 * @retval None
1420 */
LL_I2C_EnableIT_RX(I2C_TypeDef * I2Cx)1421 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
1422 {
1423 SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1424 }
1425
1426 /**
1427 * @brief Disable RXNE interrupt.
1428 * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
1429 * @param I2Cx I2C Instance.
1430 * @retval None
1431 */
LL_I2C_DisableIT_RX(I2C_TypeDef * I2Cx)1432 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
1433 {
1434 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1435 }
1436
1437 /**
1438 * @brief Check if the RXNE Interrupt is enabled or disabled.
1439 * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
1440 * @param I2Cx I2C Instance.
1441 * @retval State of bit (1 or 0).
1442 */
LL_I2C_IsEnabledIT_RX(I2C_TypeDef * I2Cx)1443 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
1444 {
1445 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
1446 }
1447
1448 /**
1449 * @brief Enable Address match interrupt (slave mode only).
1450 * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
1451 * @param I2Cx I2C Instance.
1452 * @retval None
1453 */
LL_I2C_EnableIT_ADDR(I2C_TypeDef * I2Cx)1454 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
1455 {
1456 SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1457 }
1458
1459 /**
1460 * @brief Disable Address match interrupt (slave mode only).
1461 * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
1462 * @param I2Cx I2C Instance.
1463 * @retval None
1464 */
LL_I2C_DisableIT_ADDR(I2C_TypeDef * I2Cx)1465 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
1466 {
1467 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1468 }
1469
1470 /**
1471 * @brief Check if Address match interrupt is enabled or disabled.
1472 * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
1473 * @param I2Cx I2C Instance.
1474 * @retval State of bit (1 or 0).
1475 */
LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef * I2Cx)1476 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
1477 {
1478 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
1479 }
1480
1481 /**
1482 * @brief Enable Not acknowledge received interrupt.
1483 * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
1484 * @param I2Cx I2C Instance.
1485 * @retval None
1486 */
LL_I2C_EnableIT_NACK(I2C_TypeDef * I2Cx)1487 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
1488 {
1489 SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1490 }
1491
1492 /**
1493 * @brief Disable Not acknowledge received interrupt.
1494 * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
1495 * @param I2Cx I2C Instance.
1496 * @retval None
1497 */
LL_I2C_DisableIT_NACK(I2C_TypeDef * I2Cx)1498 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
1499 {
1500 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1501 }
1502
1503 /**
1504 * @brief Check if Not acknowledge received interrupt is enabled or disabled.
1505 * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
1506 * @param I2Cx I2C Instance.
1507 * @retval State of bit (1 or 0).
1508 */
LL_I2C_IsEnabledIT_NACK(I2C_TypeDef * I2Cx)1509 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
1510 {
1511 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
1512 }
1513
1514 /**
1515 * @brief Enable STOP detection interrupt.
1516 * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
1517 * @param I2Cx I2C Instance.
1518 * @retval None
1519 */
LL_I2C_EnableIT_STOP(I2C_TypeDef * I2Cx)1520 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
1521 {
1522 SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1523 }
1524
1525 /**
1526 * @brief Disable STOP detection interrupt.
1527 * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
1528 * @param I2Cx I2C Instance.
1529 * @retval None
1530 */
LL_I2C_DisableIT_STOP(I2C_TypeDef * I2Cx)1531 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
1532 {
1533 CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1534 }
1535
1536 /**
1537 * @brief Check if STOP detection interrupt is enabled or disabled.
1538 * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
1539 * @param I2Cx I2C Instance.
1540 * @retval State of bit (1 or 0).
1541 */
LL_I2C_IsEnabledIT_STOP(I2C_TypeDef * I2Cx)1542 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
1543 {
1544 return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
1545 }
1546
1547 /**
1548 * @brief Enable Transfer Complete interrupt.
1549 * @note Any of these events will generate interrupt :
1550 * Transfer Complete (TC)
1551 * Transfer Complete Reload (TCR)
1552 * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
1553 * @param I2Cx I2C Instance.
1554 * @retval None
1555 */
LL_I2C_EnableIT_TC(I2C_TypeDef * I2Cx)1556 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
1557 {
1558 SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1559 }
1560
1561 /**
1562 * @brief Disable Transfer Complete interrupt.
1563 * @note Any of these events will generate interrupt :
1564 * Transfer Complete (TC)
1565 * Transfer Complete Reload (TCR)
1566 * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
1567 * @param I2Cx I2C Instance.
1568 * @retval None
1569 */
LL_I2C_DisableIT_TC(I2C_TypeDef * I2Cx)1570 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
1571 {
1572 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1573 }
1574
1575 /**
1576 * @brief Check if Transfer Complete interrupt is enabled or disabled.
1577 * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
1578 * @param I2Cx I2C Instance.
1579 * @retval State of bit (1 or 0).
1580 */
LL_I2C_IsEnabledIT_TC(I2C_TypeDef * I2Cx)1581 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
1582 {
1583 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
1584 }
1585
1586 /**
1587 * @brief Enable Error interrupts.
1588 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1589 * SMBus feature is supported by the I2Cx Instance.
1590 * @note Any of these errors will generate interrupt :
1591 * Arbitration Loss (ARLO)
1592 * Bus Error detection (BERR)
1593 * Overrun/Underrun (OVR)
1594 * SMBus Timeout detection (TIMEOUT)
1595 * SMBus PEC error detection (PECERR)
1596 * SMBus Alert pin event detection (ALERT)
1597 * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
1598 * @param I2Cx I2C Instance.
1599 * @retval None
1600 */
LL_I2C_EnableIT_ERR(I2C_TypeDef * I2Cx)1601 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
1602 {
1603 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1604 }
1605
1606 /**
1607 * @brief Disable Error interrupts.
1608 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1609 * SMBus feature is supported by the I2Cx Instance.
1610 * @note Any of these errors will generate interrupt :
1611 * Arbitration Loss (ARLO)
1612 * Bus Error detection (BERR)
1613 * Overrun/Underrun (OVR)
1614 * SMBus Timeout detection (TIMEOUT)
1615 * SMBus PEC error detection (PECERR)
1616 * SMBus Alert pin event detection (ALERT)
1617 * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
1618 * @param I2Cx I2C Instance.
1619 * @retval None
1620 */
LL_I2C_DisableIT_ERR(I2C_TypeDef * I2Cx)1621 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
1622 {
1623 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1624 }
1625
1626 /**
1627 * @brief Check if Error interrupts are enabled or disabled.
1628 * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
1629 * @param I2Cx I2C Instance.
1630 * @retval State of bit (1 or 0).
1631 */
LL_I2C_IsEnabledIT_ERR(I2C_TypeDef * I2Cx)1632 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
1633 {
1634 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
1635 }
1636
1637 /**
1638 * @}
1639 */
1640
1641 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
1642 * @{
1643 */
1644
1645 /**
1646 * @brief Indicate the status of Transmit data register empty flag.
1647 * @note RESET: When next data is written in Transmit data register.
1648 * SET: When Transmit data register is empty.
1649 * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
1650 * @param I2Cx I2C Instance.
1651 * @retval State of bit (1 or 0).
1652 */
LL_I2C_IsActiveFlag_TXE(I2C_TypeDef * I2Cx)1653 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
1654 {
1655 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
1656 }
1657
1658 /**
1659 * @brief Indicate the status of Transmit interrupt flag.
1660 * @note RESET: When next data is written in Transmit data register.
1661 * SET: When Transmit data register is empty.
1662 * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
1663 * @param I2Cx I2C Instance.
1664 * @retval State of bit (1 or 0).
1665 */
LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef * I2Cx)1666 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
1667 {
1668 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
1669 }
1670
1671 /**
1672 * @brief Indicate the status of Receive data register not empty flag.
1673 * @note RESET: When Receive data register is read.
1674 * SET: When the received data is copied in Receive data register.
1675 * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
1676 * @param I2Cx I2C Instance.
1677 * @retval State of bit (1 or 0).
1678 */
LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef * I2Cx)1679 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
1680 {
1681 return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
1682 }
1683
1684 /**
1685 * @brief Indicate the status of Address matched flag (slave mode).
1686 * @note RESET: Clear default value.
1687 * SET: When the received slave address matched with one of the enabled slave address.
1688 * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
1689 * @param I2Cx I2C Instance.
1690 * @retval State of bit (1 or 0).
1691 */
LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef * I2Cx)1692 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
1693 {
1694 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
1695 }
1696
1697 /**
1698 * @brief Indicate the status of Not Acknowledge received flag.
1699 * @note RESET: Clear default value.
1700 * SET: When a NACK is received after a byte transmission.
1701 * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
1702 * @param I2Cx I2C Instance.
1703 * @retval State of bit (1 or 0).
1704 */
LL_I2C_IsActiveFlag_NACK(I2C_TypeDef * I2Cx)1705 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
1706 {
1707 return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
1708 }
1709
1710 /**
1711 * @brief Indicate the status of Stop detection flag.
1712 * @note RESET: Clear default value.
1713 * SET: When a Stop condition is detected.
1714 * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
1715 * @param I2Cx I2C Instance.
1716 * @retval State of bit (1 or 0).
1717 */
LL_I2C_IsActiveFlag_STOP(I2C_TypeDef * I2Cx)1718 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
1719 {
1720 return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
1721 }
1722
1723 /**
1724 * @brief Indicate the status of Transfer complete flag (master mode).
1725 * @note RESET: Clear default value.
1726 * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
1727 * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
1728 * @param I2Cx I2C Instance.
1729 * @retval State of bit (1 or 0).
1730 */
LL_I2C_IsActiveFlag_TC(I2C_TypeDef * I2Cx)1731 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
1732 {
1733 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
1734 }
1735
1736 /**
1737 * @brief Indicate the status of Transfer complete flag (master mode).
1738 * @note RESET: Clear default value.
1739 * SET: When RELOAD=1 and NBYTES date have been transferred.
1740 * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
1741 * @param I2Cx I2C Instance.
1742 * @retval State of bit (1 or 0).
1743 */
LL_I2C_IsActiveFlag_TCR(I2C_TypeDef * I2Cx)1744 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
1745 {
1746 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
1747 }
1748
1749 /**
1750 * @brief Indicate the status of Bus error flag.
1751 * @note RESET: Clear default value.
1752 * SET: When a misplaced Start or Stop condition is detected.
1753 * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
1754 * @param I2Cx I2C Instance.
1755 * @retval State of bit (1 or 0).
1756 */
LL_I2C_IsActiveFlag_BERR(I2C_TypeDef * I2Cx)1757 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
1758 {
1759 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
1760 }
1761
1762 /**
1763 * @brief Indicate the status of Arbitration lost flag.
1764 * @note RESET: Clear default value.
1765 * SET: When arbitration lost.
1766 * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
1767 * @param I2Cx I2C Instance.
1768 * @retval State of bit (1 or 0).
1769 */
LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef * I2Cx)1770 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
1771 {
1772 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
1773 }
1774
1775 /**
1776 * @brief Indicate the status of Overrun/Underrun flag (slave mode).
1777 * @note RESET: Clear default value.
1778 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1779 * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
1780 * @param I2Cx I2C Instance.
1781 * @retval State of bit (1 or 0).
1782 */
LL_I2C_IsActiveFlag_OVR(I2C_TypeDef * I2Cx)1783 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
1784 {
1785 return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
1786 }
1787
1788 /**
1789 * @brief Indicate the status of SMBus PEC error flag in reception.
1790 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1791 * SMBus feature is supported by the I2Cx Instance.
1792 * @note RESET: Clear default value.
1793 * SET: When the received PEC does not match with the PEC register content.
1794 * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
1795 * @param I2Cx I2C Instance.
1796 * @retval State of bit (1 or 0).
1797 */
LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef * I2Cx)1798 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1799 {
1800 return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
1801 }
1802
1803 /**
1804 * @brief Indicate the status of SMBus Timeout detection flag.
1805 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1806 * SMBus feature is supported by the I2Cx Instance.
1807 * @note RESET: Clear default value.
1808 * SET: When a timeout or extended clock timeout occurs.
1809 * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
1810 * @param I2Cx I2C Instance.
1811 * @retval State of bit (1 or 0).
1812 */
LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef * I2Cx)1813 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1814 {
1815 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
1816 }
1817
1818 /**
1819 * @brief Indicate the status of SMBus alert flag.
1820 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1821 * SMBus feature is supported by the I2Cx Instance.
1822 * @note RESET: Clear default value.
1823 * SET: When SMBus host configuration, SMBus alert enabled and
1824 * a falling edge event occurs on SMBA pin.
1825 * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
1826 * @param I2Cx I2C Instance.
1827 * @retval State of bit (1 or 0).
1828 */
LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef * I2Cx)1829 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1830 {
1831 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
1832 }
1833
1834 /**
1835 * @brief Indicate the status of Bus Busy flag.
1836 * @note RESET: Clear default value.
1837 * SET: When a Start condition is detected.
1838 * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
1839 * @param I2Cx I2C Instance.
1840 * @retval State of bit (1 or 0).
1841 */
LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef * I2Cx)1842 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
1843 {
1844 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
1845 }
1846
1847 /**
1848 * @brief Clear Address Matched flag.
1849 * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
1850 * @param I2Cx I2C Instance.
1851 * @retval None
1852 */
LL_I2C_ClearFlag_ADDR(I2C_TypeDef * I2Cx)1853 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
1854 {
1855 SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
1856 }
1857
1858 /**
1859 * @brief Clear Not Acknowledge flag.
1860 * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
1861 * @param I2Cx I2C Instance.
1862 * @retval None
1863 */
LL_I2C_ClearFlag_NACK(I2C_TypeDef * I2Cx)1864 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
1865 {
1866 SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
1867 }
1868
1869 /**
1870 * @brief Clear Stop detection flag.
1871 * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
1872 * @param I2Cx I2C Instance.
1873 * @retval None
1874 */
LL_I2C_ClearFlag_STOP(I2C_TypeDef * I2Cx)1875 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
1876 {
1877 SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
1878 }
1879
1880 /**
1881 * @brief Clear Transmit data register empty flag (TXE).
1882 * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
1883 * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
1884 * @param I2Cx I2C Instance.
1885 * @retval None
1886 */
LL_I2C_ClearFlag_TXE(I2C_TypeDef * I2Cx)1887 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
1888 {
1889 WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
1890 }
1891
1892 /**
1893 * @brief Clear Bus error flag.
1894 * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
1895 * @param I2Cx I2C Instance.
1896 * @retval None
1897 */
LL_I2C_ClearFlag_BERR(I2C_TypeDef * I2Cx)1898 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
1899 {
1900 SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
1901 }
1902
1903 /**
1904 * @brief Clear Arbitration lost flag.
1905 * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
1906 * @param I2Cx I2C Instance.
1907 * @retval None
1908 */
LL_I2C_ClearFlag_ARLO(I2C_TypeDef * I2Cx)1909 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
1910 {
1911 SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
1912 }
1913
1914 /**
1915 * @brief Clear Overrun/Underrun flag.
1916 * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
1917 * @param I2Cx I2C Instance.
1918 * @retval None
1919 */
LL_I2C_ClearFlag_OVR(I2C_TypeDef * I2Cx)1920 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
1921 {
1922 SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
1923 }
1924
1925 /**
1926 * @brief Clear SMBus PEC error flag.
1927 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1928 * SMBus feature is supported by the I2Cx Instance.
1929 * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
1930 * @param I2Cx I2C Instance.
1931 * @retval None
1932 */
LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef * I2Cx)1933 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1934 {
1935 SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
1936 }
1937
1938 /**
1939 * @brief Clear SMBus Timeout detection flag.
1940 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1941 * SMBus feature is supported by the I2Cx Instance.
1942 * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
1943 * @param I2Cx I2C Instance.
1944 * @retval None
1945 */
LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef * I2Cx)1946 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1947 {
1948 SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
1949 }
1950
1951 /**
1952 * @brief Clear SMBus Alert flag.
1953 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1954 * SMBus feature is supported by the I2Cx Instance.
1955 * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
1956 * @param I2Cx I2C Instance.
1957 * @retval None
1958 */
LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef * I2Cx)1959 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1960 {
1961 SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
1962 }
1963
1964 /**
1965 * @}
1966 */
1967
1968 /** @defgroup I2C_LL_EF_Data_Management Data_Management
1969 * @{
1970 */
1971
1972 /**
1973 * @brief Enable automatic STOP condition generation (master mode).
1974 * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
1975 * This bit has no effect in slave mode or when RELOAD bit is set.
1976 * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
1977 * @param I2Cx I2C Instance.
1978 * @retval None
1979 */
LL_I2C_EnableAutoEndMode(I2C_TypeDef * I2Cx)1980 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
1981 {
1982 SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1983 }
1984
1985 /**
1986 * @brief Disable automatic STOP condition generation (master mode).
1987 * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
1988 * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
1989 * @param I2Cx I2C Instance.
1990 * @retval None
1991 */
LL_I2C_DisableAutoEndMode(I2C_TypeDef * I2Cx)1992 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
1993 {
1994 CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1995 }
1996
1997 /**
1998 * @brief Check if automatic STOP condition is enabled or disabled.
1999 * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
2000 * @param I2Cx I2C Instance.
2001 * @retval State of bit (1 or 0).
2002 */
LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef * I2Cx)2003 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
2004 {
2005 return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
2006 }
2007
2008 /**
2009 * @brief Enable reload mode (master mode).
2010 * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
2011 * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
2012 * @param I2Cx I2C Instance.
2013 * @retval None
2014 */
LL_I2C_EnableReloadMode(I2C_TypeDef * I2Cx)2015 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
2016 {
2017 SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
2018 }
2019
2020 /**
2021 * @brief Disable reload mode (master mode).
2022 * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
2023 * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
2024 * @param I2Cx I2C Instance.
2025 * @retval None
2026 */
LL_I2C_DisableReloadMode(I2C_TypeDef * I2Cx)2027 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
2028 {
2029 CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
2030 }
2031
2032 /**
2033 * @brief Check if reload mode is enabled or disabled.
2034 * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
2035 * @param I2Cx I2C Instance.
2036 * @retval State of bit (1 or 0).
2037 */
LL_I2C_IsEnabledReloadMode(I2C_TypeDef * I2Cx)2038 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
2039 {
2040 return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
2041 }
2042
2043 /**
2044 * @brief Configure the number of bytes for transfer.
2045 * @note Changing these bits when START bit is set is not allowed.
2046 * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
2047 * @param I2Cx I2C Instance.
2048 * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
2049 * @retval None
2050 */
LL_I2C_SetTransferSize(I2C_TypeDef * I2Cx,uint32_t TransferSize)2051 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
2052 {
2053 MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
2054 }
2055
2056 /**
2057 * @brief Get the number of bytes configured for transfer.
2058 * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
2059 * @param I2Cx I2C Instance.
2060 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
2061 */
LL_I2C_GetTransferSize(I2C_TypeDef * I2Cx)2062 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
2063 {
2064 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
2065 }
2066
2067 /**
2068 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
2069 or next received byte.
2070 * @note Usage in Slave mode only.
2071 * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
2072 * @param I2Cx I2C Instance.
2073 * @param TypeAcknowledge This parameter can be one of the following values:
2074 * @arg @ref LL_I2C_ACK
2075 * @arg @ref LL_I2C_NACK
2076 * @retval None
2077 */
LL_I2C_AcknowledgeNextData(I2C_TypeDef * I2Cx,uint32_t TypeAcknowledge)2078 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
2079 {
2080 MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
2081 }
2082
2083 /**
2084 * @brief Generate a START or RESTART condition
2085 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
2086 * This action has no effect when RELOAD is set.
2087 * @rmtoll CR2 START LL_I2C_GenerateStartCondition
2088 * @param I2Cx I2C Instance.
2089 * @retval None
2090 */
LL_I2C_GenerateStartCondition(I2C_TypeDef * I2Cx)2091 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
2092 {
2093 SET_BIT(I2Cx->CR2, I2C_CR2_START);
2094 }
2095
2096 /**
2097 * @brief Generate a STOP condition after the current byte transfer (master mode).
2098 * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
2099 * @param I2Cx I2C Instance.
2100 * @retval None
2101 */
LL_I2C_GenerateStopCondition(I2C_TypeDef * I2Cx)2102 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
2103 {
2104 SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
2105 }
2106
2107 /**
2108 * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
2109 * @note The master sends the complete 10bit slave address read sequence :
2110 * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
2111 in Read direction.
2112 * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
2113 * @param I2Cx I2C Instance.
2114 * @retval None
2115 */
LL_I2C_EnableAuto10BitRead(I2C_TypeDef * I2Cx)2116 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
2117 {
2118 CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
2119 }
2120
2121 /**
2122 * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
2123 * @note The master only sends the first 7 bits of 10bit address in Read direction.
2124 * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
2125 * @param I2Cx I2C Instance.
2126 * @retval None
2127 */
LL_I2C_DisableAuto10BitRead(I2C_TypeDef * I2Cx)2128 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
2129 {
2130 SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
2131 }
2132
2133 /**
2134 * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
2135 * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
2136 * @param I2Cx I2C Instance.
2137 * @retval State of bit (1 or 0).
2138 */
LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef * I2Cx)2139 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
2140 {
2141 return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
2142 }
2143
2144 /**
2145 * @brief Configure the transfer direction (master mode).
2146 * @note Changing these bits when START bit is set is not allowed.
2147 * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
2148 * @param I2Cx I2C Instance.
2149 * @param TransferRequest This parameter can be one of the following values:
2150 * @arg @ref LL_I2C_REQUEST_WRITE
2151 * @arg @ref LL_I2C_REQUEST_READ
2152 * @retval None
2153 */
LL_I2C_SetTransferRequest(I2C_TypeDef * I2Cx,uint32_t TransferRequest)2154 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
2155 {
2156 MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
2157 }
2158
2159 /**
2160 * @brief Get the transfer direction requested (master mode).
2161 * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
2162 * @param I2Cx I2C Instance.
2163 * @retval Returned value can be one of the following values:
2164 * @arg @ref LL_I2C_REQUEST_WRITE
2165 * @arg @ref LL_I2C_REQUEST_READ
2166 */
LL_I2C_GetTransferRequest(I2C_TypeDef * I2Cx)2167 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
2168 {
2169 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
2170 }
2171
2172 /**
2173 * @brief Configure the slave address for transfer (master mode).
2174 * @note Changing these bits when START bit is set is not allowed.
2175 * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
2176 * @param I2Cx I2C Instance.
2177 * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
2178 * @retval None
2179 */
LL_I2C_SetSlaveAddr(I2C_TypeDef * I2Cx,uint32_t SlaveAddr)2180 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
2181 {
2182 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
2183 }
2184
2185 /**
2186 * @brief Get the slave address programmed for transfer.
2187 * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
2188 * @param I2Cx I2C Instance.
2189 * @retval Value between Min_Data=0x0 and Max_Data=0x3F
2190 */
LL_I2C_GetSlaveAddr(I2C_TypeDef * I2Cx)2191 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
2192 {
2193 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
2194 }
2195
2196 /**
2197 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
2198 * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
2199 * CR2 ADD10 LL_I2C_HandleTransfer\n
2200 * CR2 RD_WRN LL_I2C_HandleTransfer\n
2201 * CR2 START LL_I2C_HandleTransfer\n
2202 * CR2 STOP LL_I2C_HandleTransfer\n
2203 * CR2 RELOAD LL_I2C_HandleTransfer\n
2204 * CR2 NBYTES LL_I2C_HandleTransfer\n
2205 * CR2 AUTOEND LL_I2C_HandleTransfer\n
2206 * CR2 HEAD10R LL_I2C_HandleTransfer
2207 * @param I2Cx I2C Instance.
2208 * @param SlaveAddr Specifies the slave address to be programmed.
2209 * @param SlaveAddrSize This parameter can be one of the following values:
2210 * @arg @ref LL_I2C_ADDRSLAVE_7BIT
2211 * @arg @ref LL_I2C_ADDRSLAVE_10BIT
2212 * @param TransferSize Specifies the number of bytes to be programmed.
2213 * This parameter must be a value between Min_Data=0 and Max_Data=255.
2214 * @param EndMode This parameter can be one of the following values:
2215 * @arg @ref LL_I2C_MODE_RELOAD
2216 * @arg @ref LL_I2C_MODE_AUTOEND
2217 * @arg @ref LL_I2C_MODE_SOFTEND
2218 * @arg @ref LL_I2C_MODE_SMBUS_RELOAD
2219 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
2220 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
2221 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
2222 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
2223 * @param Request This parameter can be one of the following values:
2224 * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
2225 * @arg @ref LL_I2C_GENERATE_STOP
2226 * @arg @ref LL_I2C_GENERATE_START_READ
2227 * @arg @ref LL_I2C_GENERATE_START_WRITE
2228 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
2229 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
2230 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
2231 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
2232 * @retval None
2233 */
LL_I2C_HandleTransfer(I2C_TypeDef * I2Cx,uint32_t SlaveAddr,uint32_t SlaveAddrSize,uint32_t TransferSize,uint32_t EndMode,uint32_t Request)2234 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
2235 uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
2236 {
2237 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
2238 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
2239 I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
2240 I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
2241 SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
2242 }
2243
2244 /**
2245 * @brief Indicate the value of transfer direction (slave mode).
2246 * @note RESET: Write transfer, Slave enters in receiver mode.
2247 * SET: Read transfer, Slave enters in transmitter mode.
2248 * @rmtoll ISR DIR LL_I2C_GetTransferDirection
2249 * @param I2Cx I2C Instance.
2250 * @retval Returned value can be one of the following values:
2251 * @arg @ref LL_I2C_DIRECTION_WRITE
2252 * @arg @ref LL_I2C_DIRECTION_READ
2253 */
LL_I2C_GetTransferDirection(I2C_TypeDef * I2Cx)2254 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
2255 {
2256 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
2257 }
2258
2259 /**
2260 * @brief Return the slave matched address.
2261 * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
2262 * @param I2Cx I2C Instance.
2263 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
2264 */
LL_I2C_GetAddressMatchCode(I2C_TypeDef * I2Cx)2265 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
2266 {
2267 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
2268 }
2269
2270 /**
2271 * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
2272 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2273 * SMBus feature is supported by the I2Cx Instance.
2274 * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
2275 or an Address Matched is received.
2276 * This bit has no effect when RELOAD bit is set.
2277 * This bit has no effect in device mode when SBC bit is not set.
2278 * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
2279 * @param I2Cx I2C Instance.
2280 * @retval None
2281 */
LL_I2C_EnableSMBusPECCompare(I2C_TypeDef * I2Cx)2282 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
2283 {
2284 SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
2285 }
2286
2287 /**
2288 * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
2289 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2290 * SMBus feature is supported by the I2Cx Instance.
2291 * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
2292 * @param I2Cx I2C Instance.
2293 * @retval State of bit (1 or 0).
2294 */
LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef * I2Cx)2295 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
2296 {
2297 return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
2298 }
2299
2300 /**
2301 * @brief Get the SMBus Packet Error byte calculated.
2302 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2303 * SMBus feature is supported by the I2Cx Instance.
2304 * @rmtoll PECR PEC LL_I2C_GetSMBusPEC
2305 * @param I2Cx I2C Instance.
2306 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2307 */
LL_I2C_GetSMBusPEC(I2C_TypeDef * I2Cx)2308 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
2309 {
2310 return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
2311 }
2312
2313 /**
2314 * @brief Read Receive Data register.
2315 * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
2316 * @param I2Cx I2C Instance.
2317 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2318 */
LL_I2C_ReceiveData8(I2C_TypeDef * I2Cx)2319 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
2320 {
2321 return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
2322 }
2323
2324 /**
2325 * @brief Write in Transmit Data Register .
2326 * @rmtoll TXDR TXDATA LL_I2C_TransmitData8
2327 * @param I2Cx I2C Instance.
2328 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
2329 * @retval None
2330 */
LL_I2C_TransmitData8(I2C_TypeDef * I2Cx,uint8_t Data)2331 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
2332 {
2333 WRITE_REG(I2Cx->TXDR, Data);
2334 }
2335
2336 /**
2337 * @}
2338 */
2339
2340 #if defined(USE_FULL_LL_DRIVER)
2341 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
2342 * @{
2343 */
2344
2345 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
2346 ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
2347 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
2348
2349
2350 /**
2351 * @}
2352 */
2353 #endif /* USE_FULL_LL_DRIVER */
2354
2355 /**
2356 * @}
2357 */
2358
2359 /**
2360 * @}
2361 */
2362
2363 #endif /* I2C1 || I2C2 || I2C3 || I2C4 */
2364
2365 /**
2366 * @}
2367 */
2368
2369 #ifdef __cplusplus
2370 }
2371 #endif
2372
2373 #endif /* STM32H5xx_LL_I2C_H */
2374
