1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_dcache.h
4 * @author MCD Application Team
5 * @brief Header file of DCACHE LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion ------------------------------------*/
20 #ifndef STM32H5xx_LL_DCACHE_H
21 #define STM32H5xx_LL_DCACHE_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes -----------------------------------------------------------------*/
28 #include "stm32h5xx.h"
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DCACHE1)
35
36 /** @defgroup DCACHE_LL DCACHE
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup DCACHE_Private_Constants DCACHE Private Constants
44 * @{
45 */
46 #define LL_DCACHE_COMMAND_NO_OPERATION (0x00000000)
47 #define LL_DCACHE_COMMAND_CLEAN_BY_ADDR DCACHE_CR_CACHECMD_0
48 #define LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR DCACHE_CR_CACHECMD_1
49 #define LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR (DCACHE_CR_CACHECMD_0|DCACHE_CR_CACHECMD_1)
50 /**
51 * @}
52 */
53
54 /** @defgroup DCACHE_Read_Burst_Type Remapped Output burst type
55 * @{
56 */
57 #define LL_DCACHE_READ_BURST_WRAP 0U /*!< WRAP */
58 #define LL_DCACHE_READ_BURST_INCR DCACHE_CR_HBURST /*!< INCR */
59 /**
60 * @}
61 */
62
63 /** @defgroup DCACHE_LL_EC_GET_FLAG Get Flags Defines
64 * @brief Flags defines which can be used with LL_DCACHE_ReadReg function
65 * @{
66 */
67 #define LL_DCACHE_SR_ERRF DCACHE_SR_ERRF /*!< Cache error flag */
68 #define LL_DCACHE_SR_BUSYF DCACHE_SR_BUSYF /*!< Busy flag */
69 #define LL_DCACHE_SR_CMDENDF DCACHE_SR_CMDENDF /*!< Command end flag */
70 #define LL_DCACHE_SR_BSYENDF DCACHE_SR_BSYENDF /*!< Full invalidate busy end flag */
71 #define LL_DCACHE_SR_BUSYCMDF DCACHE_SR_BUSYCMDF /*!< Command busy flag */
72 /**
73 * @}
74 */
75
76 /** @defgroup DCACHE_LL_EC_CLEAR_FLAG Clear Flags Defines
77 * @brief Flags defines which can be used with LL_DCACHE_WriteReg function
78 * @{
79 */
80 #define LL_DCACHE_FCR_CERRF DCACHE_FCR_CERRF /*!< Cache error flag */
81 #define LL_DCACHE_FCR_CBSYENDF DCACHE_FCR_CBSYENDF /*!< Full invalidate busy end flag */
82 #define LL_DCACHE_FCR_CCMDENDF DCACHE_FCR_CCMDENDF /*!< Command end flag*/
83 /**
84 * @}
85 */
86
87 /** @defgroup DCACHE_LL_EC_IT IT Defines
88 * @brief IT defines which can be used with LL_DCACHE_ReadReg and LL_DCACHE_WriteReg functions
89 * @{
90 */
91 #define LL_DCACHE_IER_BSYENDIE DCACHE_IER_BSYENDIE /*!< Busy end interrupt */
92 #define LL_DCACHE_IER_ERRIE DCACHE_IER_ERRIE /*!< Cache error interrupt */
93 #define LL_DCACHE_IER_CMDENDIE DCACHE_IER_CMDENDIE /*!< Command end interrupt */
94 /**
95 * @}
96 */
97
98 /** @defgroup DCACHE_Monitor_Type Monitor type
99 * @{
100 */
101 #define LL_DCACHE_MONITOR_READ_HIT DCACHE_CR_RHITMEN /*!< Read Hit monitoring */
102 #define LL_DCACHE_MONITOR_READ_MISS DCACHE_CR_RMISSMEN /*!< Read Miss monitoring */
103 #define LL_DCACHE_MONITOR_WRITE_HIT DCACHE_CR_WHITMEN /*!< Write Hit monitoring */
104 #define LL_DCACHE_MONITOR_WRITE_MISS DCACHE_CR_WMISSMEN /*!< Write Miss monitoring */
105 #define LL_DCACHE_MONITOR_ALL (DCACHE_CR_RHITMEN | DCACHE_CR_RMISSMEN \
106 | DCACHE_CR_WHITMEN | DCACHE_CR_WMISSMEN)
107 /**
108 * @}
109 */
110
111 /* Exported macros --------------------------------------------------------*/
112 /** @defgroup DCACHE_LL_Exported_Macros DCACHE Exported Macros
113 * @{
114 */
115
116 /** @defgroup DCACHE_LL_EM_WRITE_READ Common write and read registers Macros
117 * @{
118 */
119
120 /**
121 * @brief Write a value in DCACHE register
122 * @param __INSTANCE__ DCACHE Instance
123 * @param __REG__ Register to be written
124 * @param __VALUE__ Value to be written in the register
125 * @retval None
126 */
127 #define LL_DCACHE_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
128
129 /**
130 * @brief Read a value in DCACHE register
131 * @param __INSTANCE__ DCACHE Instance
132 * @param __REG__ Register to be read
133 * @retval Register value
134 */
135 #define LL_DCACHE_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
136 /**
137 * @}
138 */
139
140 /**
141 * @}
142 */
143
144 /* Exported functions --------------------------------------------------------*/
145 /** @defgroup DCACHE_LL_Exported_Functions DCACHE Exported Functions
146 * @{
147 */
148
149 /** @defgroup DCACHE_LL_EF_Configuration Configuration
150 * @{
151 */
152
153 /**
154 * @brief Enable the selected DCACHE instance.
155 * @rmtoll CR EN LL_DCACHE_Enable
156 * @param DCACHEx DCACHE instance
157 * @retval None
158 */
LL_DCACHE_Enable(DCACHE_TypeDef * DCACHEx)159 __STATIC_INLINE void LL_DCACHE_Enable(DCACHE_TypeDef *DCACHEx)
160 {
161 SET_BIT(DCACHEx->CR, DCACHE_CR_EN);
162 }
163
164 /**
165 * @brief Disable the selected DCACHE instance.
166 * @rmtoll CR EN LL_DCACHE_Disable
167 * @param DCACHEx DCACHE instance
168 * @retval None
169 */
LL_DCACHE_Disable(DCACHE_TypeDef * DCACHEx)170 __STATIC_INLINE void LL_DCACHE_Disable(DCACHE_TypeDef *DCACHEx)
171 {
172 CLEAR_BIT(DCACHEx->CR, DCACHE_CR_EN);
173 }
174
175 /**
176 * @brief Get the selected DCACHE instance enable state.
177 * @rmtoll CR EN LL_DCACHE_IsEnabled
178 * @param DCACHEx DCACHE instance
179 * @retval 0: DCACHE is disabled, 1: DCACHE is enabled.
180 */
LL_DCACHE_IsEnabled(DCACHE_TypeDef * DCACHEx)181 __STATIC_INLINE uint32_t LL_DCACHE_IsEnabled(DCACHE_TypeDef *DCACHEx)
182 {
183 return ((READ_BIT(DCACHEx->CR, DCACHE_CR_EN) == (DCACHE_CR_EN)) ? 1UL : 0UL);
184 }
185
186 /**
187 * @brief Set the dcache instance start command address.
188 * @rmtoll CR CMDRSADDRR LL_DCACHE_SetStartAddress
189 * @param addr dcache command start address(Clean, Invalidate or Clean and Invalidate).
190 * @param DCACHEx DCACHE instance
191 * @retval None
192 */
LL_DCACHE_SetStartAddress(DCACHE_TypeDef * DCACHEx,uint32_t addr)193 __STATIC_INLINE void LL_DCACHE_SetStartAddress(DCACHE_TypeDef *DCACHEx, uint32_t addr)
194 {
195 WRITE_REG(DCACHEx->CMDRSADDRR, addr);
196 }
197
198 /**
199 * @brief Get the dcache command start address.
200 * @rmtoll CR CMDRSADDRR LL_DCACHE_GetStartAddress
201 * @param DCACHEx DCACHE instance
202 * @retval Start address of dcache command
203 */
LL_DCACHE_GetStartAddress(DCACHE_TypeDef * DCACHEx)204 __STATIC_INLINE uint32_t LL_DCACHE_GetStartAddress(DCACHE_TypeDef *DCACHEx)
205 {
206 return (uint32_t)(READ_REG(DCACHEx->CMDRSADDRR));
207 }
208
209 /**
210 * @brief Set the dcache instance End command address.
211 * @rmtoll CR CMDREADDRR LL_DCACHE_SetEndAddress
212 * @param DCACHEx DCACHE instance
213 * @param addr dcache command end address(Clean, Invalidate or Clean and Invalidate).
214 * @retval None
215 */
LL_DCACHE_SetEndAddress(DCACHE_TypeDef * DCACHEx,uint32_t addr)216 __STATIC_INLINE void LL_DCACHE_SetEndAddress(DCACHE_TypeDef *DCACHEx, uint32_t addr)
217 {
218 WRITE_REG(DCACHEx->CMDREADDRR, addr);
219 }
220
221 /**
222 * @brief Get the dcache command End address.
223 * @rmtoll CR CMDREADDRR LL_DCACHE_GetEndAddress
224 * @param DCACHEx DCACHE instance
225 * @retval End address of dcache command
226 */
LL_DCACHE_GetEndAddress(DCACHE_TypeDef * DCACHEx)227 __STATIC_INLINE uint32_t LL_DCACHE_GetEndAddress(DCACHE_TypeDef *DCACHEx)
228 {
229 return (uint32_t)(READ_REG(DCACHEx->CMDREADDRR));
230 }
231
232 /**
233 * @brief Set Dcache command.
234 * @rmtoll CR CACHECMD LL_DCACHE_SetCommand
235 * @param DCACHEx DCACHE instance
236 * @param Command command to be applied for the dcache
237 * LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR, LL_DCACHE_COMMAND_CLEAN_BY_ADDR,
238 * LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR,LL_DCACHE_COMMAND_NO_OPERATION
239 * @retval None
240 */
LL_DCACHE_SetCommand(DCACHE_TypeDef * DCACHEx,uint32_t Command)241 __STATIC_INLINE void LL_DCACHE_SetCommand(DCACHE_TypeDef *DCACHEx, uint32_t Command)
242 {
243 /* Set dcache command */
244 MODIFY_REG(DCACHEx->CR, DCACHE_CR_CACHECMD, Command);
245 }
246
247 /**
248 * @brief Set Dcache command.
249 * @rmtoll CR CACHECMD LL_DCACHE_GetCommand
250 * @param DCACHEx DCACHE instance
251 * @retval Returned value can be one of the following values:
252 * @arg @ref LL_DCACHE_COMMAND_NO_OPERATION
253 * @arg @ref LL_DCACHE_COMMAND_CLEAN_BY_ADDR
254 * @arg @ref LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR
255 * @arg @ref LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR
256 */
LL_DCACHE_GetCommand(DCACHE_TypeDef * DCACHEx)257 __STATIC_INLINE uint32_t LL_DCACHE_GetCommand(DCACHE_TypeDef *DCACHEx)
258 {
259 /*Get Dcache Command */
260 return (uint32_t)(READ_BIT(DCACHEx->CR, DCACHE_CR_CACHECMD));
261 }
262
263 /**
264 * @brief Launch Dcache Command.
265 * @rmtoll CR CACHECMD LL_DCACHE_StartCommand
266 * @param DCACHEx DCACHE instance
267 * @retval None
268 */
LL_DCACHE_StartCommand(DCACHE_TypeDef * DCACHEx)269 __STATIC_INLINE void LL_DCACHE_StartCommand(DCACHE_TypeDef *DCACHEx)
270 {
271 SET_BIT(DCACHEx->CR, DCACHE_CR_STARTCMD);
272 }
273
274 /**
275 * @brief Set requested read burst type.
276 * @rmtoll CR HBURST LL_DCACHE_SetReadBurstType
277 * @param DCACHEx DCACHE instance
278 * @param ReadBurstType Burst type to be applied for Data Cache
279 * LL_DCACHE_READ_BURST_WRAP, LL_DCACHE_READ_BURST_INCR.
280 * @retval None
281 */
LL_DCACHE_SetReadBurstType(DCACHE_TypeDef * DCACHEx,uint32_t ReadBurstType)282 __STATIC_INLINE void LL_DCACHE_SetReadBurstType(DCACHE_TypeDef *DCACHEx, uint32_t ReadBurstType)
283 {
284 MODIFY_REG(DCACHEx->CR, DCACHE_CR_HBURST, ReadBurstType);
285 }
286
287 /**
288 * @brief Get requested read burst type.
289 * @rmtoll CR HBURST LL_DCACHE_GetReadBurstType
290 * @param DCACHEx DCACHE instance
291 * @retval Returned value can be one of the following values:
292 * @arg @ref LL_DCACHE_READ_BURST_WRAP
293 * @arg @ref LL_DCACHE_READ_BURST_INCR
294 */
LL_DCACHE_GetReadBurstType(DCACHE_TypeDef * DCACHEx)295 __STATIC_INLINE uint32_t LL_DCACHE_GetReadBurstType(DCACHE_TypeDef *DCACHEx)
296 {
297 return (uint32_t)(READ_BIT(DCACHEx->CR, DCACHE_CR_HBURST));
298 }
299
300 /**
301 * @brief Invalidate the Data cache.
302 * @rmtoll CR CACHEINV LL_DCACHE_Invalidate
303 * @param DCACHEx DCACHE instance
304 * @retval None
305 */
LL_DCACHE_Invalidate(DCACHE_TypeDef * DCACHEx)306 __STATIC_INLINE void LL_DCACHE_Invalidate(DCACHE_TypeDef *DCACHEx)
307 {
308 SET_BIT(DCACHEx->CR, DCACHE_CR_CACHEINV);
309 }
310
311 /**
312 * @}
313 */
314
315
316 /** @defgroup DCACHE_LL_EF_Monitor Monitor
317 * @{
318 */
319
320 /**
321 * @brief Enable the hit/miss monitor(s).
322 * @rmtoll CR (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN) LL_DCACHE_EnableMonitors
323 * @param DCACHEx DCACHE instance
324 * @param Monitors This parameter can be one or a combination of the following values:
325 * @arg LL_DCACHE_MONITOR_READ_HIT
326 * @arg LL_DCACHE_MONITOR_READ_MISS
327 * @arg LL_DCACHE_MONITOR_WRITE_HIT
328 * @arg LL_DCACHE_MONITOR_WRITE_MISS
329 * @arg LL_DCACHE_MONITOR_ALL
330 * @retval None
331 */
LL_DCACHE_EnableMonitors(DCACHE_TypeDef * DCACHEx,uint32_t Monitors)332 __STATIC_INLINE void LL_DCACHE_EnableMonitors(DCACHE_TypeDef *DCACHEx, uint32_t Monitors)
333 {
334 SET_BIT(DCACHEx->CR, Monitors);
335 }
336
337 /**
338 * @brief Disable the hit/miss monitor(s).
339 * @rmtoll CR (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN) LL_DCACHE_DisableMonitors
340 * @param DCACHEx DCACHE instance
341 * @param Monitors This parameter can be one or a combination of the following values:
342 * @arg LL_DCACHE_MONITOR_READ_HIT
343 * @arg LL_DCACHE_MONITOR_READ_MISS
344 * @arg LL_DCACHE_MONITOR_WRITE_HIT
345 * @arg LL_DCACHE_MONITOR_WRITE_MISS
346 * @arg LL_DCACHE_MONITOR_ALL
347 * @retval None
348 */
LL_DCACHE_DisableMonitors(DCACHE_TypeDef * DCACHEx,uint32_t Monitors)349 __STATIC_INLINE void LL_DCACHE_DisableMonitors(DCACHE_TypeDef *DCACHEx, uint32_t Monitors)
350 {
351 CLEAR_BIT(DCACHEx->CR, Monitors);
352 }
353
354 /**
355 * @brief Return the hit/miss monitor(s) enable state.
356 * @rmtoll CR (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN) LL_DCACHE_IsEnabledMonitors
357 * @param DCACHEx DCACHE instance
358 * @param Monitors This parameter can be one or a combination of the following values:
359 * @arg LL_DCACHE_MONITOR_READ_HIT
360 * @arg LL_DCACHE_MONITOR_READ_MISS
361 * @arg LL_DCACHE_MONITOR_WRITE_HIT
362 * @arg LL_DCACHE_MONITOR_WRITE_MISS
363 * @arg LL_DCACHE_MONITOR_ALL
364 * @retval State of parameter value (1 or 0).
365 */
LL_DCACHE_IsEnabledMonitors(DCACHE_TypeDef * DCACHEx,uint32_t Monitors)366 __STATIC_INLINE uint32_t LL_DCACHE_IsEnabledMonitors(DCACHE_TypeDef *DCACHEx, uint32_t Monitors)
367 {
368 return (((READ_BIT(DCACHEx->CR, (DCACHE_CR_WMISSMEN | DCACHE_CR_WHITMEN | DCACHE_CR_RMISSMEN | DCACHE_CR_RHITMEN))\
369 & Monitors) == (Monitors)) ? 1UL : 0UL);
370 }
371
372 /**
373 * @brief Reset the Data Cache performance monitoring.
374 * @rmtoll CR (RHITMRST/RMISSMRST/WHITMRST/WMISSMRST) LL_DCACHE_ResetMonitors
375 * @param DCACHEx DCACHE instance
376 * @param Monitors Monitoring type
377 * This parameter can be a combination of the following values:
378 * @arg LL_DCACHE_MONITOR_READ_HIT
379 * @arg LL_DCACHE_MONITOR_READ_MISS
380 * @arg LL_DCACHE_MONITOR_WRITE_HIT
381 * @arg LL_DCACHE_MONITOR_WRITE_MISS
382 * @arg LL_DCACHE_MONITOR_ALL
383 * @retval None
384 */
LL_DCACHE_ResetMonitors(DCACHE_TypeDef * DCACHEx,uint32_t Monitors)385 __STATIC_INLINE void LL_DCACHE_ResetMonitors(DCACHE_TypeDef *DCACHEx, uint32_t Monitors)
386 {
387 /* Reset */
388 SET_BIT(DCACHEx->CR, (Monitors << 2U));
389
390 /* Release reset */
391 CLEAR_BIT(DCACHEx->CR, (Monitors << 2U));
392 }
393
394 /**
395 * @brief Get the Read Hit monitor Value
396 * @rmtoll RHMONR LL_DCACHE_Monitor_GetReadHitValue
397 * @param DCACHEx DCACHE instance
398 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
399 */
LL_DCACHE_Monitor_GetReadHitValue(DCACHE_TypeDef * DCACHEx)400 __STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadHitValue(DCACHE_TypeDef *DCACHEx)
401 {
402 return DCACHEx->RHMONR;
403 }
404
405 /**
406 * @brief Get the Read Miss monitor Value
407 * @rmtoll RMMONR LL_DCACHE_Monitor_GetReadMissValue
408 * @param DCACHEx DCACHE instance
409 * @retval Value between Min_Data=0 and Max_Data=0xFFFF
410 */
LL_DCACHE_Monitor_GetReadMissValue(DCACHE_TypeDef * DCACHEx)411 __STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadMissValue(DCACHE_TypeDef *DCACHEx)
412 {
413 return DCACHEx->RMMONR;
414 }
415
416 /**
417 * @brief Get the Write Hit monitor Value
418 * @rmtoll WHMONR LL_DCACHE_Monitor_GetWriteHitValue
419 * @param DCACHEx DCACHE instance
420 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
421 */
LL_DCACHE_Monitor_GetWriteHitValue(DCACHE_TypeDef * DCACHEx)422 __STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteHitValue(DCACHE_TypeDef *DCACHEx)
423 {
424 return DCACHEx->WHMONR;
425 }
426
427 /**
428 * @brief Get the Write Miss monitor Value
429 * @rmtoll WMMONR LL_DCACHE_Monitor_GetWriteMissValue
430 * @param DCACHEx DCACHE instance
431 * @retval Value between Min_Data=0 and Max_Data=0xFFFF
432 */
LL_DCACHE_Monitor_GetWriteMissValue(DCACHE_TypeDef * DCACHEx)433 __STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteMissValue(DCACHE_TypeDef *DCACHEx)
434 {
435 return DCACHEx->WMMONR;
436 }
437
438 /**
439 * @}
440 */
441
442 /** @defgroup DCACHE_LL_EF_IT_Management IT-Management
443 * @{
444 */
445
446 /**
447 * @brief Enable BusyEnd interrupt.
448 * @rmtoll IER BSYENDIE LL_DCACHE_EnableIT_BSYEND
449 * @param DCACHEx DCACHE instance
450 * @retval None
451 */
LL_DCACHE_EnableIT_BSYEND(DCACHE_TypeDef * DCACHEx)452 __STATIC_INLINE void LL_DCACHE_EnableIT_BSYEND(DCACHE_TypeDef *DCACHEx)
453 {
454 SET_BIT(DCACHEx->IER, DCACHE_IER_BSYENDIE);
455 }
456
457 /**
458 * @brief Disable BusyEnd interrupt.
459 * @rmtoll IER BSYENDIE LL_DCACHE_DisableIT_BSYEND
460 * @param DCACHEx DCACHE instance
461 * @retval None
462 */
LL_DCACHE_DisableIT_BSYEND(DCACHE_TypeDef * DCACHEx)463 __STATIC_INLINE void LL_DCACHE_DisableIT_BSYEND(DCACHE_TypeDef *DCACHEx)
464 {
465 CLEAR_BIT(DCACHEx->IER, DCACHE_IER_BSYENDIE);
466 }
467
468 /**
469 * @brief Indicates whether the Busyend interrupt is enabled.
470 * @rmtoll IER BSYENDIE LL_DCACHE_IsEnabledIT_BSYEND
471 * @param DCACHEx DCACHE instance
472 * @retval State of bit (1 or 0).
473 */
LL_DCACHE_IsEnabledIT_BSYEND(DCACHE_TypeDef * DCACHEx)474 __STATIC_INLINE uint32_t LL_DCACHE_IsEnabledIT_BSYEND(DCACHE_TypeDef *DCACHEx)
475 {
476 return ((READ_BIT(DCACHEx->IER, DCACHE_IER_BSYENDIE) == (DCACHE_IER_BSYENDIE)) ? 1UL : 0UL);
477 }
478
479 /**
480 * @brief Enable Error interrupt.
481 * @rmtoll IER ERRIE LL_DCACHE_EnableIT_ERR
482 * @param DCACHEx DCACHE instance
483 * @retval None
484 */
LL_DCACHE_EnableIT_ERR(DCACHE_TypeDef * DCACHEx)485 __STATIC_INLINE void LL_DCACHE_EnableIT_ERR(DCACHE_TypeDef *DCACHEx)
486 {
487 SET_BIT(DCACHEx->IER, DCACHE_IER_ERRIE);
488 }
489
490 /**
491 * @brief Disable Error interrupt.
492 * @rmtoll IER ERRIE LL_DCACHE_DisableIT_ERR
493 * @param DCACHEx DCACHE instance
494 * @retval None
495 */
LL_DCACHE_DisableIT_ERR(DCACHE_TypeDef * DCACHEx)496 __STATIC_INLINE void LL_DCACHE_DisableIT_ERR(DCACHE_TypeDef *DCACHEx)
497 {
498 CLEAR_BIT(DCACHEx->IER, DCACHE_IER_ERRIE);
499 }
500
501 /**
502 * @brief Indicates whether the Error interrupt is enabled.
503 * @rmtoll IER ERRIE LL_DCACHE_IsEnabledIT_ERR
504 * @param DCACHEx DCACHE instance
505 * @retval State of bit (1 or 0).
506 */
LL_DCACHE_IsEnabledIT_ERR(DCACHE_TypeDef * DCACHEx)507 __STATIC_INLINE uint32_t LL_DCACHE_IsEnabledIT_ERR(DCACHE_TypeDef *DCACHEx)
508 {
509 return ((READ_BIT(DCACHEx->IER, DCACHE_IER_ERRIE) == (DCACHE_IER_ERRIE)) ? 1UL : 0UL);
510 }
511
512 /**
513 * @brief Enable command end interrupt.
514 * @rmtoll IER CMDENDIE LL_DCACHE_EnableIT_CMDEND
515 * @param DCACHEx DCACHE instance
516 * @retval None
517 */
LL_DCACHE_EnableIT_CMDEND(DCACHE_TypeDef * DCACHEx)518 __STATIC_INLINE void LL_DCACHE_EnableIT_CMDEND(DCACHE_TypeDef *DCACHEx)
519 {
520 SET_BIT(DCACHEx->IER, DCACHE_IER_CMDENDIE);
521 }
522
523 /**
524 * @brief Disable command end interrupt.
525 * @rmtoll IER CMDENDIE LL_DCACHE_DisableIT_CMDEND
526 * @param DCACHEx DCACHE instance
527 * @retval None
528 */
LL_DCACHE_DisableIT_CMDEND(DCACHE_TypeDef * DCACHEx)529 __STATIC_INLINE void LL_DCACHE_DisableIT_CMDEND(DCACHE_TypeDef *DCACHEx)
530 {
531 CLEAR_BIT(DCACHEx->IER, DCACHE_IER_CMDENDIE);
532 }
533
534 /**
535 * @brief Indicates whether the command end interrupt is enabled.
536 * @rmtoll IER CMDENDIE LL_DCACHE_IsEnabledIT_CMDEND
537 * @param DCACHEx DCACHE instance
538 * @retval State of bit (1 or 0).
539 */
LL_DCACHE_IsEnabledIT_CMDEND(DCACHE_TypeDef * DCACHEx)540 __STATIC_INLINE uint32_t LL_DCACHE_IsEnabledIT_CMDEND(DCACHE_TypeDef *DCACHEx)
541 {
542 return ((READ_BIT(DCACHEx->IER, DCACHE_IER_CMDENDIE) == (DCACHE_IER_CMDENDIE)) ? 1UL : 0UL);
543 }
544
545 /**
546 * @brief Clear full invalidate busy end flag.
547 * @rmtoll FCR CBSYENDF LL_DCACHE_ClearFlag_BSYEND
548 * @param DCACHEx DCACHE instance
549 * @retval None
550 */
LL_DCACHE_ClearFlag_BSYEND(DCACHE_TypeDef * DCACHEx)551 __STATIC_INLINE void LL_DCACHE_ClearFlag_BSYEND(DCACHE_TypeDef *DCACHEx)
552 {
553 WRITE_REG(DCACHEx->FCR, DCACHE_FCR_CBSYENDF);
554 }
555
556 /**
557 * @brief Clear cache error flag.
558 * @rmtoll FCR CERRF LL_DCACHE_ClearFlag_ERR
559 * @param DCACHEx DCACHE instance
560 * @retval None
561 */
LL_DCACHE_ClearFlag_ERR(DCACHE_TypeDef * DCACHEx)562 __STATIC_INLINE void LL_DCACHE_ClearFlag_ERR(DCACHE_TypeDef *DCACHEx)
563 {
564 WRITE_REG(DCACHEx->FCR, DCACHE_FCR_CERRF);
565 }
566
567 /**
568 * @brief Clear command end flag.
569 * @rmtoll FCR CCMDENDF LL_DCACHE_ClearFlag_CMDEND
570 * @param DCACHEx DCACHE instance
571 * @retval None
572 */
LL_DCACHE_ClearFlag_CMDEND(DCACHE_TypeDef * DCACHEx)573 __STATIC_INLINE void LL_DCACHE_ClearFlag_CMDEND(DCACHE_TypeDef *DCACHEx)
574 {
575 WRITE_REG(DCACHEx->FCR, DCACHE_FCR_CCMDENDF);
576 }
577
578 /**
579 * @brief Get flag Dcache BUSY.
580 * @rmtoll SR BUSYF LL_DCACHE_IsActiveFlag_BUSY
581 * @param DCACHEx DCACHE instance
582 * @retval State of bit (1 or 0).
583 */
LL_DCACHE_IsActiveFlag_BUSY(DCACHE_TypeDef * DCACHEx)584 __STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BUSY(DCACHE_TypeDef *DCACHEx)
585 {
586 return ((READ_BIT(DCACHEx->SR, DCACHE_SR_BUSYF) == (DCACHE_SR_BUSYF)) ? 1UL : 0UL);
587 }
588
589 /**
590 * @brief Get flag Dcache Busyend.
591 * @rmtoll SR BSYENDF LL_DCACHE_IsActiveFlag_BSYEND
592 * @param DCACHEx DCACHE instance
593 * @retval State of bit (1 or 0).
594 */
LL_DCACHE_IsActiveFlag_BSYEND(DCACHE_TypeDef * DCACHEx)595 __STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BSYEND(DCACHE_TypeDef *DCACHEx)
596 {
597 return ((READ_BIT(DCACHEx->SR, DCACHE_SR_BSYENDF) == (DCACHE_SR_BSYENDF)) ? 1UL : 0UL);
598 }
599
600 /**
601 * @brief Get flag Dcache Error.
602 * @rmtoll SR ERRF LL_DCACHE_IsActiveFlag_ERR
603 * @param DCACHEx DCACHE instance
604 * @retval State of bit (1 or 0).
605 */
LL_DCACHE_IsActiveFlag_ERR(DCACHE_TypeDef * DCACHEx)606 __STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_ERR(DCACHE_TypeDef *DCACHEx)
607 {
608 return ((READ_BIT(DCACHEx->SR, DCACHE_SR_ERRF) == (DCACHE_SR_ERRF)) ? 1UL : 0UL);
609 }
610
611 /**
612 * @brief Get flag Dcache Busy command.
613 * @rmtoll SR BUSYCMDF LL_DCACHE_IsActiveFlag_BUSYCMD
614 * @param DCACHEx DCACHE instance
615 * @retval State of bit (1 or 0).
616 */
LL_DCACHE_IsActiveFlag_BUSYCMD(DCACHE_TypeDef * DCACHEx)617 __STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BUSYCMD(DCACHE_TypeDef *DCACHEx)
618 {
619 return ((READ_BIT(DCACHEx->SR, DCACHE_SR_BUSYCMDF) == (DCACHE_SR_BUSYCMDF)) ? 1UL : 0UL);
620 }
621
622 /**
623 * @brief Get flag Dcache command end.
624 * @rmtoll SR CMDENDF LL_DCACHE_IsActiveFlag_CMDEND
625 * @param DCACHEx DCACHE instance
626 * @retval State of bit (1 or 0).
627 */
LL_DCACHE_IsActiveFlag_CMDEND(DCACHE_TypeDef * DCACHEx)628 __STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_CMDEND(DCACHE_TypeDef *DCACHEx)
629 {
630 return ((READ_BIT(DCACHEx->SR, DCACHE_SR_CMDENDF) == (DCACHE_SR_CMDENDF)) ? 1UL : 0UL);
631 }
632
633 /**
634 * @}
635 */
636
637 /**
638 * @}
639 */
640
641 /**
642 * @}
643 */
644
645 #endif /* defined(DCACHE1) */
646
647 /**
648 * @}
649 */
650
651 #ifdef __cplusplus
652 }
653 #endif
654
655 #endif /* STM32H5xx_LL_DCACHE_H */
656
