1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_crs.h
4 * @author MCD Application Team
5 * @brief Header file of CRS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H5xx_LL_CRS_H
21 #define STM32H5xx_LL_CRS_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h5xx.h"
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined(CRS)
35
36 /** @defgroup CRS_LL CRS
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @defgroup CRS_LL_Private_Constants CRS Private Constants
44 * @{
45 */
46
47 /* Defines used for the bit position in the register and perform offsets*/
48 #define CRS_POSITION_TRIM (CRS_CR_TRIM_Pos) /* bit position in CR reg */
49 #define CRS_POSITION_FECAP (CRS_ISR_FECAP_Pos) /* bit position in ISR reg */
50 #define CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */
51
52
53 /**
54 * @}
55 */
56
57 /* Private macros ------------------------------------------------------------*/
58
59 /* Exported types ------------------------------------------------------------*/
60 /* Exported constants --------------------------------------------------------*/
61 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
62 * @{
63 */
64
65 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
66 * @brief Flags defines which can be used with LL_CRS_ReadReg function
67 * @{
68 */
69 #define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
70 #define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
71 #define LL_CRS_ISR_ERRF CRS_ISR_ERRF
72 #define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
73 #define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
74 #define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
75 #define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
76 /**
77 * @}
78 */
79
80 /** @defgroup CRS_LL_EC_IT IT Defines
81 * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
82 * @{
83 */
84 #define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
85 #define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
86 #define LL_CRS_CR_ERRIE CRS_CR_ERRIE
87 #define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
88 /**
89 * @}
90 */
91
92 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
93 * @{
94 */
95 #define LL_CRS_SYNC_DIV_1 0x00000000U /*!< Synchro Signal not divided (default) */
96 #define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
97 #define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
98 #define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
99 #define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
100 #define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
101 #define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
102 #define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
103 /**
104 * @}
105 */
106
107 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
108 * @{
109 */
110 #define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */
111 #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
112 #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
113 /**
114 * @}
115 */
116
117 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
118 * @{
119 */
120 #define LL_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */
121 #define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
122 /**
123 * @}
124 */
125
126 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
127 * @{
128 */
129 #define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */
130 #define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */
131 /**
132 * @}
133 */
134
135 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
136 * @{
137 */
138 /**
139 * @brief Reset value of the RELOAD field
140 * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
141 * and a synchronization signal frequency of 1 kHz (SOF signal from USB)
142 */
143 #define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
144
145 /**
146 * @brief Reset value of Frequency error limit.
147 */
148 #define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U
149
150 /**
151 * @brief Reset value of the HSI48 Calibration field
152 * @note The default value is 32, which corresponds to the middle of the trimming interval.
153 * The trimming step is specified in the product datasheet.
154 * A higher TRIM value corresponds to a higher output frequency.
155 */
156 #define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U
157 /**
158 * @}
159 */
160
161 /**
162 * @}
163 */
164
165 /* Exported macro ------------------------------------------------------------*/
166 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
167 * @{
168 */
169
170 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
171 * @{
172 */
173
174 /**
175 * @brief Write a value in CRS register
176 * @param __INSTANCE__ CRS Instance
177 * @param __REG__ Register to be written
178 * @param __VALUE__ Value to be written in the register
179 * @retval None
180 */
181 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
182
183 /**
184 * @brief Read a value in CRS register
185 * @param __INSTANCE__ CRS Instance
186 * @param __REG__ Register to be read
187 * @retval Register value
188 */
189 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
190 /**
191 * @}
192 */
193
194 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
195 * @{
196 */
197
198 /**
199 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
200 * @note The RELOAD value should be selected according to the ratio between
201 * the target frequency and the frequency of the synchronization source after
202 * prescaling. It is then decreased by one in order to reach the expected
203 * synchronization on the zero value. The formula is the following:
204 * RELOAD = (fTARGET / fSYNC) -1
205 * @param __FTARGET__ Target frequency (value in Hz)
206 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
207 * @retval Reload value (in Hz)
208 */
209 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
210
211 /**
212 * @}
213 */
214
215 /**
216 * @}
217 */
218
219 /* Exported functions --------------------------------------------------------*/
220 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
221 * @{
222 */
223
224 /** @defgroup CRS_LL_EF_Configuration Configuration
225 * @{
226 */
227
228 /**
229 * @brief Enable Frequency error counter
230 * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
231 * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
232 * @retval None
233 */
LL_CRS_EnableFreqErrorCounter(void)234 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
235 {
236 SET_BIT(CRS->CR, CRS_CR_CEN);
237 }
238
239 /**
240 * @brief Disable Frequency error counter
241 * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
242 * @retval None
243 */
LL_CRS_DisableFreqErrorCounter(void)244 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
245 {
246 CLEAR_BIT(CRS->CR, CRS_CR_CEN);
247 }
248
249 /**
250 * @brief Check if Frequency error counter is enabled or not
251 * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
252 * @retval State of bit (1 or 0).
253 */
LL_CRS_IsEnabledFreqErrorCounter(void)254 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
255 {
256 return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
257 }
258
259 /**
260 * @brief Enable Automatic trimming counter
261 * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
262 * @retval None
263 */
LL_CRS_EnableAutoTrimming(void)264 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
265 {
266 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
267 }
268
269 /**
270 * @brief Disable Automatic trimming counter
271 * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
272 * @retval None
273 */
LL_CRS_DisableAutoTrimming(void)274 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
275 {
276 CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
277 }
278
279 /**
280 * @brief Check if Automatic trimming is enabled or not
281 * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
282 * @retval State of bit (1 or 0).
283 */
LL_CRS_IsEnabledAutoTrimming(void)284 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
285 {
286 return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
287 }
288
289 /**
290 * @brief Set HSI48 oscillator smooth trimming
291 * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
292 * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
293 * @param Value a number between Min_Data = 0 and Max_Data = 63
294 * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
295 * @retval None
296 */
LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)297 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
298 {
299 MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM);
300 }
301
302 /**
303 * @brief Get HSI48 oscillator smooth trimming
304 * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
305 * @retval a number between Min_Data = 0 and Max_Data = 63
306 */
LL_CRS_GetHSI48SmoothTrimming(void)307 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
308 {
309 return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM);
310 }
311
312 /**
313 * @brief Set counter reload value
314 * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
315 * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
316 * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
317 * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
318 * @retval None
319 */
LL_CRS_SetReloadCounter(uint32_t Value)320 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
321 {
322 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
323 }
324
325 /**
326 * @brief Get counter reload value
327 * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
328 * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
329 */
LL_CRS_GetReloadCounter(void)330 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
331 {
332 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
333 }
334
335 /**
336 * @brief Set frequency error limit
337 * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
338 * @param Value a number between Min_Data = 0 and Max_Data = 255
339 * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
340 * @retval None
341 */
LL_CRS_SetFreqErrorLimit(uint32_t Value)342 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
343 {
344 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM);
345 }
346
347 /**
348 * @brief Get frequency error limit
349 * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
350 * @retval A number between Min_Data = 0 and Max_Data = 255
351 */
LL_CRS_GetFreqErrorLimit(void)352 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
353 {
354 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM);
355 }
356
357 /**
358 * @brief Set division factor for SYNC signal
359 * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
360 * @param Divider This parameter can be one of the following values:
361 * @arg @ref LL_CRS_SYNC_DIV_1
362 * @arg @ref LL_CRS_SYNC_DIV_2
363 * @arg @ref LL_CRS_SYNC_DIV_4
364 * @arg @ref LL_CRS_SYNC_DIV_8
365 * @arg @ref LL_CRS_SYNC_DIV_16
366 * @arg @ref LL_CRS_SYNC_DIV_32
367 * @arg @ref LL_CRS_SYNC_DIV_64
368 * @arg @ref LL_CRS_SYNC_DIV_128
369 * @retval None
370 */
LL_CRS_SetSyncDivider(uint32_t Divider)371 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
372 {
373 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
374 }
375
376 /**
377 * @brief Get division factor for SYNC signal
378 * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
379 * @retval Returned value can be one of the following values:
380 * @arg @ref LL_CRS_SYNC_DIV_1
381 * @arg @ref LL_CRS_SYNC_DIV_2
382 * @arg @ref LL_CRS_SYNC_DIV_4
383 * @arg @ref LL_CRS_SYNC_DIV_8
384 * @arg @ref LL_CRS_SYNC_DIV_16
385 * @arg @ref LL_CRS_SYNC_DIV_32
386 * @arg @ref LL_CRS_SYNC_DIV_64
387 * @arg @ref LL_CRS_SYNC_DIV_128
388 */
LL_CRS_GetSyncDivider(void)389 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
390 {
391 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
392 }
393
394 /**
395 * @brief Set SYNC signal source
396 * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
397 * @param Source This parameter can be one of the following values:
398 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
399 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
400 * @arg @ref LL_CRS_SYNC_SOURCE_USB
401 * @retval None
402 */
LL_CRS_SetSyncSignalSource(uint32_t Source)403 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
404 {
405 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
406 }
407
408 /**
409 * @brief Get SYNC signal source
410 * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
411 * @retval Returned value can be one of the following values:
412 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
413 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
414 * @arg @ref LL_CRS_SYNC_SOURCE_USB
415 */
LL_CRS_GetSyncSignalSource(void)416 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
417 {
418 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
419 }
420
421 /**
422 * @brief Set input polarity for the SYNC signal source
423 * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
424 * @param Polarity This parameter can be one of the following values:
425 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
426 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
427 * @retval None
428 */
LL_CRS_SetSyncPolarity(uint32_t Polarity)429 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
430 {
431 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
432 }
433
434 /**
435 * @brief Get input polarity for the SYNC signal source
436 * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
437 * @retval Returned value can be one of the following values:
438 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
439 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
440 */
LL_CRS_GetSyncPolarity(void)441 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
442 {
443 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
444 }
445
446 /**
447 * @brief Configure CRS for the synchronization
448 * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
449 * CFGR RELOAD LL_CRS_ConfigSynchronization\n
450 * CFGR FELIM LL_CRS_ConfigSynchronization\n
451 * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
452 * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
453 * CFGR SYNCPOL LL_CRS_ConfigSynchronization
454 * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
455 * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
456 * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
457 * @param Settings This parameter can be a combination of the following values:
458 * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
459 * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64
460 * or @ref LL_CRS_SYNC_DIV_128
461 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
462 * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
463 * @retval None
464 */
LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue,uint32_t ErrorLimitValue,uint32_t ReloadValue,uint32_t Settings)465 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue,
466 uint32_t ReloadValue, uint32_t Settings)
467 {
468 MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
469 MODIFY_REG(CRS->CFGR,
470 CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
471 ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings);
472 }
473
474 /**
475 * @}
476 */
477
478 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
479 * @{
480 */
481
482 /**
483 * @brief Generate software SYNC event
484 * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
485 * @retval None
486 */
LL_CRS_GenerateEvent_SWSYNC(void)487 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
488 {
489 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
490 }
491
492 /**
493 * @brief Get the frequency error direction latched in the time of the last
494 * SYNC event
495 * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
496 * @retval Returned value can be one of the following values:
497 * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
498 * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
499 */
LL_CRS_GetFreqErrorDirection(void)500 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
501 {
502 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
503 }
504
505 /**
506 * @brief Get the frequency error counter value latched in the time of the last SYNC event
507 * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
508 * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
509 */
LL_CRS_GetFreqErrorCapture(void)510 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
511 {
512 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP);
513 }
514
515 /**
516 * @}
517 */
518
519 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
520 * @{
521 */
522
523 /**
524 * @brief Check if SYNC event OK signal occurred or not
525 * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
526 * @retval State of bit (1 or 0).
527 */
LL_CRS_IsActiveFlag_SYNCOK(void)528 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
529 {
530 return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
531 }
532
533 /**
534 * @brief Check if SYNC warning signal occurred or not
535 * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
536 * @retval State of bit (1 or 0).
537 */
LL_CRS_IsActiveFlag_SYNCWARN(void)538 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
539 {
540 return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
541 }
542
543 /**
544 * @brief Check if Synchronization or trimming error signal occurred or not
545 * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
546 * @retval State of bit (1 or 0).
547 */
LL_CRS_IsActiveFlag_ERR(void)548 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
549 {
550 return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
551 }
552
553 /**
554 * @brief Check if Expected SYNC signal occurred or not
555 * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
556 * @retval State of bit (1 or 0).
557 */
LL_CRS_IsActiveFlag_ESYNC(void)558 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
559 {
560 return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
561 }
562
563 /**
564 * @brief Check if SYNC error signal occurred or not
565 * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
566 * @retval State of bit (1 or 0).
567 */
LL_CRS_IsActiveFlag_SYNCERR(void)568 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
569 {
570 return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
571 }
572
573 /**
574 * @brief Check if SYNC missed error signal occurred or not
575 * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
576 * @retval State of bit (1 or 0).
577 */
LL_CRS_IsActiveFlag_SYNCMISS(void)578 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
579 {
580 return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
581 }
582
583 /**
584 * @brief Check if Trimming overflow or underflow occurred or not
585 * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
586 * @retval State of bit (1 or 0).
587 */
LL_CRS_IsActiveFlag_TRIMOVF(void)588 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
589 {
590 return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
591 }
592
593 /**
594 * @brief Clear the SYNC event OK flag
595 * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
596 * @retval None
597 */
LL_CRS_ClearFlag_SYNCOK(void)598 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
599 {
600 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
601 }
602
603 /**
604 * @brief Clear the SYNC warning flag
605 * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
606 * @retval None
607 */
LL_CRS_ClearFlag_SYNCWARN(void)608 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
609 {
610 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
611 }
612
613 /**
614 * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
615 * the ERR flag
616 * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
617 * @retval None
618 */
LL_CRS_ClearFlag_ERR(void)619 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
620 {
621 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
622 }
623
624 /**
625 * @brief Clear Expected SYNC flag
626 * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
627 * @retval None
628 */
LL_CRS_ClearFlag_ESYNC(void)629 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
630 {
631 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
632 }
633
634 /**
635 * @}
636 */
637
638 /** @defgroup CRS_LL_EF_IT_Management IT_Management
639 * @{
640 */
641
642 /**
643 * @brief Enable SYNC event OK interrupt
644 * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
645 * @retval None
646 */
LL_CRS_EnableIT_SYNCOK(void)647 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
648 {
649 SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
650 }
651
652 /**
653 * @brief Disable SYNC event OK interrupt
654 * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
655 * @retval None
656 */
LL_CRS_DisableIT_SYNCOK(void)657 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
658 {
659 CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
660 }
661
662 /**
663 * @brief Check if SYNC event OK interrupt is enabled or not
664 * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
665 * @retval State of bit (1 or 0).
666 */
LL_CRS_IsEnabledIT_SYNCOK(void)667 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
668 {
669 return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
670 }
671
672 /**
673 * @brief Enable SYNC warning interrupt
674 * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
675 * @retval None
676 */
LL_CRS_EnableIT_SYNCWARN(void)677 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
678 {
679 SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
680 }
681
682 /**
683 * @brief Disable SYNC warning interrupt
684 * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
685 * @retval None
686 */
LL_CRS_DisableIT_SYNCWARN(void)687 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
688 {
689 CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
690 }
691
692 /**
693 * @brief Check if SYNC warning interrupt is enabled or not
694 * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
695 * @retval State of bit (1 or 0).
696 */
LL_CRS_IsEnabledIT_SYNCWARN(void)697 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
698 {
699 return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
700 }
701
702 /**
703 * @brief Enable Synchronization or trimming error interrupt
704 * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
705 * @retval None
706 */
LL_CRS_EnableIT_ERR(void)707 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
708 {
709 SET_BIT(CRS->CR, CRS_CR_ERRIE);
710 }
711
712 /**
713 * @brief Disable Synchronization or trimming error interrupt
714 * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
715 * @retval None
716 */
LL_CRS_DisableIT_ERR(void)717 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
718 {
719 CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
720 }
721
722 /**
723 * @brief Check if Synchronization or trimming error interrupt is enabled or not
724 * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
725 * @retval State of bit (1 or 0).
726 */
LL_CRS_IsEnabledIT_ERR(void)727 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
728 {
729 return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
730 }
731
732 /**
733 * @brief Enable Expected SYNC interrupt
734 * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
735 * @retval None
736 */
LL_CRS_EnableIT_ESYNC(void)737 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
738 {
739 SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
740 }
741
742 /**
743 * @brief Disable Expected SYNC interrupt
744 * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
745 * @retval None
746 */
LL_CRS_DisableIT_ESYNC(void)747 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
748 {
749 CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
750 }
751
752 /**
753 * @brief Check if Expected SYNC interrupt is enabled or not
754 * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
755 * @retval State of bit (1 or 0).
756 */
LL_CRS_IsEnabledIT_ESYNC(void)757 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
758 {
759 return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
760 }
761
762 /**
763 * @}
764 */
765
766 #if defined(USE_FULL_LL_DRIVER)
767 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
768 * @{
769 */
770
771 ErrorStatus LL_CRS_DeInit(void);
772
773 /**
774 * @}
775 */
776 #endif /* USE_FULL_LL_DRIVER */
777
778 /**
779 * @}
780 */
781
782 /**
783 * @}
784 */
785
786 #endif /* defined(CRS) */
787
788 /**
789 * @}
790 */
791
792 #ifdef __cplusplus
793 }
794 #endif
795
796 #endif /* STM32H5xx_LL_CRS_H */
797
