1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_tim.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H5xx_HAL_TIM_H 21 #define STM32H5xx_HAL_TIM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /** @addtogroup STM32H5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup TIM 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup TIM_Exported_Types TIM Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief TIM Time base Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 49 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF 50 Macro __HAL_TIM_CALC_PSC() can be used to calculate prescaler value */ 51 52 uint32_t CounterMode; /*!< Specifies the counter mode. 53 This parameter can be a value of @ref TIM_Counter_Mode */ 54 55 uint32_t Period; /*!< Specifies the period value to be loaded into the active 56 Auto-Reload Register at the next update event. 57 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF 58 (or 0xFFEF if dithering is activated)Macros __HAL_TIM_CALC_PERIOD(), 59 __HAL_TIM_CALC_PERIOD_DITHER(),__HAL_TIM_CALC_PERIOD_BY_DELAY(), 60 __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY()can be used to calculate Period value */ 61 62 uint32_t ClockDivision; /*!< Specifies the clock division. 63 This parameter can be a value of @ref TIM_ClockDivision */ 64 65 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 66 reaches zero, an update event is generated and counting restarts 67 from the RCR value (N). 68 This means in PWM mode that (N+1) corresponds to: 69 - the number of PWM periods in edge-aligned mode 70 - the number of half PWM period in center-aligned mode 71 GP timers: this parameter must be a number between Min_Data = 0x00 and 72 Max_Data = 0xFF. 73 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and 74 Max_Data = 0xFFFF. */ 75 76 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 77 This parameter can be a value of @ref TIM_AutoReloadPreload */ 78 } TIM_Base_InitTypeDef; 79 80 /** 81 * @brief TIM Output Compare Configuration Structure definition 82 */ 83 typedef struct 84 { 85 uint32_t OCMode; /*!< Specifies the TIM mode. 86 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 87 88 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 89 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF 90 (or 0xFFEF if dithering is activated) 91 Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate 92 Pulse value */ 93 94 uint32_t OCPolarity; /*!< Specifies the output polarity. 95 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 96 97 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 98 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 99 @note This parameter is valid only for timer instances supporting break feature. */ 100 101 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 102 This parameter can be a value of @ref TIM_Output_Fast_State 103 @note This parameter is valid only in PWM1 and PWM2 mode. */ 104 105 106 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 107 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 108 @note This parameter is valid only for timer instances supporting break feature. */ 109 110 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 111 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 112 @note This parameter is valid only for timer instances supporting break feature. */ 113 } TIM_OC_InitTypeDef; 114 115 /** 116 * @brief TIM One Pulse Mode Configuration Structure definition 117 */ 118 typedef struct 119 { 120 uint32_t OCMode; /*!< Specifies the TIM mode. 121 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 122 123 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 124 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF 125 (or 0xFFEF if dithering is activated) 126 Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate 127 Pulse value */ 128 129 uint32_t OCPolarity; /*!< Specifies the output polarity. 130 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 131 132 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 133 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 134 @note This parameter is valid only for timer instances supporting break feature. */ 135 136 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 137 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 138 @note This parameter is valid only for timer instances supporting break feature. */ 139 140 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 141 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 142 @note This parameter is valid only for timer instances supporting break feature. */ 143 144 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 145 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 146 147 uint32_t ICSelection; /*!< Specifies the input. 148 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 149 150 uint32_t ICFilter; /*!< Specifies the input capture filter. 151 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 152 } TIM_OnePulse_InitTypeDef; 153 154 /** 155 * @brief TIM Input Capture Configuration Structure definition 156 */ 157 typedef struct 158 { 159 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 160 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 161 162 uint32_t ICSelection; /*!< Specifies the input. 163 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 164 165 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 166 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 167 168 uint32_t ICFilter; /*!< Specifies the input capture filter. 169 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 170 } TIM_IC_InitTypeDef; 171 172 /** 173 * @brief TIM Encoder Configuration Structure definition 174 */ 175 typedef struct 176 { 177 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 178 This parameter can be a value of @ref TIM_Encoder_Mode */ 179 180 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 181 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 182 183 uint32_t IC1Selection; /*!< Specifies the input. 184 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 185 186 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 187 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 188 189 uint32_t IC1Filter; /*!< Specifies the input capture filter. 190 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 191 192 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 193 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 194 195 uint32_t IC2Selection; /*!< Specifies the input. 196 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 197 198 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 199 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 200 201 uint32_t IC2Filter; /*!< Specifies the input capture filter. 202 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 203 } TIM_Encoder_InitTypeDef; 204 205 /** 206 * @brief Clock Configuration Handle Structure definition 207 */ 208 typedef struct 209 { 210 uint32_t ClockSource; /*!< TIM clock sources 211 This parameter can be a value of @ref TIM_Clock_Source */ 212 uint32_t ClockPolarity; /*!< TIM clock polarity 213 This parameter can be a value of @ref TIM_Clock_Polarity */ 214 uint32_t ClockPrescaler; /*!< TIM clock prescaler 215 This parameter can be a value of @ref TIM_Clock_Prescaler */ 216 uint32_t ClockFilter; /*!< TIM clock filter 217 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 218 } TIM_ClockConfigTypeDef; 219 220 /** 221 * @brief TIM Clear Input Configuration Handle Structure definition 222 */ 223 typedef struct 224 { 225 uint32_t ClearInputState; /*!< TIM clear Input state 226 This parameter can be ENABLE or DISABLE */ 227 uint32_t ClearInputSource; /*!< TIM clear Input sources 228 This parameter can be a value of @ref TIM_ClearInput_Source */ 229 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 230 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 231 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 232 This parameter must be 0: When OCRef clear feature is used with ETR source, 233 ETR prescaler must be off */ 234 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 235 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 236 } TIM_ClearInputConfigTypeDef; 237 238 /** 239 * @brief TIM Master configuration Structure definition 240 * @note Advanced timers provide TRGO2 internal line which is redirected 241 * to the ADC 242 */ 243 typedef struct 244 { 245 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 246 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 247 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection 248 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ 249 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 250 This parameter can be a value of @ref TIM_Master_Slave_Mode 251 @note When the Master/slave mode is enabled, the effect of 252 an event on the trigger input (TRGI) is delayed to allow a 253 perfect synchronization between the current timer and its 254 slaves (through TRGO). It is not mandatory in case of timer 255 synchronization mode. */ 256 } TIM_MasterConfigTypeDef; 257 258 /** 259 * @brief TIM Slave configuration Structure definition 260 */ 261 typedef struct 262 { 263 uint32_t SlaveMode; /*!< Slave mode selection 264 This parameter can be a value of @ref TIM_Slave_Mode */ 265 uint32_t InputTrigger; /*!< Input Trigger source 266 This parameter can be a value of @ref TIM_Trigger_Selection */ 267 uint32_t TriggerPolarity; /*!< Input Trigger polarity 268 This parameter can be a value of @ref TIM_Trigger_Polarity */ 269 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 270 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 271 uint32_t TriggerFilter; /*!< Input trigger filter 272 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 273 274 } TIM_SlaveConfigTypeDef; 275 276 /** 277 * @brief TIM Break input(s) and Dead time configuration Structure definition 278 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable 279 * filter and polarity. 280 */ 281 typedef struct 282 { 283 uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 284 285 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 286 287 uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ 288 289 uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 290 291 uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 292 293 uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ 294 295 uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 296 297 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ 298 299 uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ 300 301 uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ 302 303 uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 304 305 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ 306 307 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 308 309 } TIM_BreakDeadTimeConfigTypeDef; 310 311 /** 312 * @brief HAL State structures definition 313 */ 314 typedef enum 315 { 316 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 317 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 318 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 319 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 320 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 321 } HAL_TIM_StateTypeDef; 322 323 /** 324 * @brief TIM Channel States definition 325 */ 326 typedef enum 327 { 328 HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ 329 HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ 330 HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ 331 } HAL_TIM_ChannelStateTypeDef; 332 333 /** 334 * @brief DMA Burst States definition 335 */ 336 typedef enum 337 { 338 HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ 339 HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ 340 HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ 341 } HAL_TIM_DMABurstStateTypeDef; 342 343 /** 344 * @brief HAL Active channel structures definition 345 */ 346 typedef enum 347 { 348 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 349 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 350 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 351 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 352 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ 353 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ 354 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 355 } HAL_TIM_ActiveChannel; 356 357 /** 358 * @brief TIM Time Base Handle Structure definition 359 */ 360 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 361 typedef struct __TIM_HandleTypeDef 362 #else 363 typedef struct 364 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 365 { 366 TIM_TypeDef *Instance; /*!< Register base address */ 367 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 368 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 369 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 370 This array is accessed by a @ref DMA_Handle_index */ 371 HAL_LockTypeDef Lock; /*!< Locking object */ 372 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 373 __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ 374 __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ 375 __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ 376 377 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 378 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 379 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 380 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 381 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 382 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 383 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 384 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 385 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 386 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 387 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 388 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 389 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 390 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ 391 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ 392 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 393 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ 394 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 395 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ 396 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 397 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ 398 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 399 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 400 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ 401 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 402 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ 403 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ 404 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ 405 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ 406 void (* EncoderIndexCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Index Callback */ 407 void (* DirectionChangeCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Direction Change Callback */ 408 void (* IndexErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Index Error Callback */ 409 void (* TransitionErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Transition Error Callback */ 410 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 411 } TIM_HandleTypeDef; 412 413 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 414 /** 415 * @brief HAL TIM Callback ID enumeration definition 416 */ 417 typedef enum 418 { 419 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ 420 , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ 421 , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ 422 , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ 423 , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ 424 , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ 425 , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ 426 , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ 427 , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ 428 , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ 429 , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ 430 , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ 431 , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ 432 , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ 433 , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ 434 , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ 435 , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ 436 , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ 437 438 , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ 439 , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ 440 , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ 441 , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ 442 , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ 443 , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ 444 , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ 445 , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ 446 , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ 447 , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ 448 , HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */ 449 , HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU /*!< TIM Direction Change Callback ID */ 450 , HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */ 451 , HAL_TIM_TRANSITION_ERROR_CB_ID = 0x1FU /*!< TIM Transition Error Callback ID */ 452 } HAL_TIM_CallbackIDTypeDef; 453 454 /** 455 * @brief HAL TIM Callback pointer definition 456 */ 457 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 458 459 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 460 461 /** 462 * @} 463 */ 464 /* End of exported types -----------------------------------------------------*/ 465 466 /* Exported constants --------------------------------------------------------*/ 467 /** @defgroup TIM_Exported_Constants TIM Exported Constants 468 * @{ 469 */ 470 471 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 472 * @{ 473 */ 474 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ 475 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ 476 #define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */ 477 /** 478 * @} 479 */ 480 481 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 482 * @{ 483 */ 484 #define TIM_DMABASE_CR1 0x00000000U 485 #define TIM_DMABASE_CR2 0x00000001U 486 #define TIM_DMABASE_SMCR 0x00000002U 487 #define TIM_DMABASE_DIER 0x00000003U 488 #define TIM_DMABASE_SR 0x00000004U 489 #define TIM_DMABASE_EGR 0x00000005U 490 #define TIM_DMABASE_CCMR1 0x00000006U 491 #define TIM_DMABASE_CCMR2 0x00000007U 492 #define TIM_DMABASE_CCER 0x00000008U 493 #define TIM_DMABASE_CNT 0x00000009U 494 #define TIM_DMABASE_PSC 0x0000000AU 495 #define TIM_DMABASE_ARR 0x0000000BU 496 #define TIM_DMABASE_RCR 0x0000000CU 497 #define TIM_DMABASE_CCR1 0x0000000DU 498 #define TIM_DMABASE_CCR2 0x0000000EU 499 #define TIM_DMABASE_CCR3 0x0000000FU 500 #define TIM_DMABASE_CCR4 0x00000010U 501 #define TIM_DMABASE_BDTR 0x00000011U 502 #define TIM_DMABASE_CCR5 0x00000012U 503 #define TIM_DMABASE_CCR6 0x00000013U 504 #define TIM_DMABASE_CCMR3 0x00000014U 505 #define TIM_DMABASE_DTR2 0x00000015U 506 #define TIM_DMABASE_ECR 0x00000016U 507 #define TIM_DMABASE_TISEL 0x00000017U 508 #define TIM_DMABASE_AF1 0x00000018U 509 #define TIM_DMABASE_AF2 0x00000019U 510 /** 511 * @} 512 */ 513 514 /** @defgroup TIM_Event_Source TIM Event Source 515 * @{ 516 */ 517 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 518 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 519 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 520 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 521 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 522 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ 523 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 524 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ 525 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ 526 /** 527 * @} 528 */ 529 530 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 531 * @{ 532 */ 533 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 534 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 535 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 536 /** 537 * @} 538 */ 539 540 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 541 * @{ 542 */ 543 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 544 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 545 /** 546 * @} 547 */ 548 549 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 550 * @{ 551 */ 552 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 553 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 554 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 555 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 556 /** 557 * @} 558 */ 559 560 /** @defgroup TIM_Counter_Mode TIM Counter Mode 561 * @{ 562 */ 563 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 564 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 565 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 566 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 567 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 568 /** 569 * @} 570 */ 571 572 /** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap 573 * @{ 574 */ 575 #define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ 576 #define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ 577 /** 578 * @} 579 */ 580 581 /** @defgroup TIM_ClockDivision TIM Clock Division 582 * @{ 583 */ 584 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 585 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 586 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 587 /** 588 * @} 589 */ 590 591 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 592 * @{ 593 */ 594 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 595 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 596 /** 597 * @} 598 */ 599 600 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 601 * @{ 602 */ 603 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 604 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 605 606 /** 607 * @} 608 */ 609 610 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 611 * @{ 612 */ 613 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 614 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 615 /** 616 * @} 617 */ 618 619 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 620 * @{ 621 */ 622 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 623 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 624 /** 625 * @} 626 */ 627 628 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 629 * @{ 630 */ 631 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 632 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 633 /** 634 * @} 635 */ 636 637 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 638 * @{ 639 */ 640 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ 641 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ 642 /** 643 * @} 644 */ 645 646 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 647 * @{ 648 */ 649 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ 650 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ 651 /** 652 * @} 653 */ 654 655 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 656 * @{ 657 */ 658 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ 659 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ 660 /** 661 * @} 662 */ 663 664 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 665 * @{ 666 */ 667 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 668 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 669 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 670 /** 671 * @} 672 */ 673 674 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity 675 * @{ 676 */ 677 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ 678 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ 679 /** 680 * @} 681 */ 682 683 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 684 * @{ 685 */ 686 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ 687 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ 688 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 689 /** 690 * @} 691 */ 692 693 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 694 * @{ 695 */ 696 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 697 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 698 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 699 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 700 /** 701 * @} 702 */ 703 704 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 705 * @{ 706 */ 707 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 708 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 709 /** 710 * @} 711 */ 712 713 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 714 * @{ 715 */ 716 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 717 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 718 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 719 #define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction, x2 mode */ 720 #define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */ 721 #define TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */ 722 #define TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */ 723 #define TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */ 724 #define TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */ 725 /** 726 * @} 727 */ 728 729 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 730 * @{ 731 */ 732 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 733 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 734 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 735 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 736 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 737 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ 738 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 739 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ 740 #define TIM_IT_IDX TIM_DIER_IDXIE /*!< Index interrupt */ 741 #define TIM_IT_DIR TIM_DIER_DIRIE /*!< Direction change interrupt */ 742 #define TIM_IT_IERR TIM_DIER_IERRIE /*!< Index error interrupt */ 743 #define TIM_IT_TERR TIM_DIER_TERRIE /*!< Transition error interrupt */ 744 /** 745 * @} 746 */ 747 748 /** @defgroup TIM_Commutation_Source TIM Commutation Source 749 * @{ 750 */ 751 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ 752 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ 753 /** 754 * @} 755 */ 756 757 /** @defgroup TIM_DMA_sources TIM DMA Sources 758 * @{ 759 */ 760 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 761 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 762 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 763 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 764 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 765 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ 766 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ 767 /** 768 * @} 769 */ 770 771 /** @defgroup TIM_CC_DMA_Request CCx DMA request selection 772 * @{ 773 */ 774 #define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ 775 #define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ 776 /** 777 * @} 778 */ 779 780 /** @defgroup TIM_Flag_definition TIM Flag Definition 781 * @{ 782 */ 783 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 784 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 785 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 786 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 787 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 788 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ 789 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ 790 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ 791 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 792 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ 793 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ 794 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ 795 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 796 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 797 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 798 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 799 #define TIM_FLAG_IDX TIM_SR_IDXF /*!< Encoder index flag */ 800 #define TIM_FLAG_DIR TIM_SR_DIRF /*!< Direction change flag */ 801 #define TIM_FLAG_IERR TIM_SR_IERRF /*!< Index error flag */ 802 #define TIM_FLAG_TERR TIM_SR_TERRF /*!< Transition error flag */ 803 /** 804 * @} 805 */ 806 807 /** @defgroup TIM_Channel TIM Channel 808 * @{ 809 */ 810 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 811 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 812 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 813 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 814 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ 815 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ 816 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 817 /** 818 * @} 819 */ 820 821 /** @defgroup TIM_Clock_Source TIM Clock Source 822 * @{ 823 */ 824 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 825 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 826 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 827 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 828 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 829 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 830 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ 831 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ 832 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ 833 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ 834 #define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */ 835 #define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */ 836 #define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */ 837 #define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */ 838 #define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */ 839 #define TIM_CLOCKSOURCE_ITR9 TIM_TS_ITR9 /*!< External clock source mode 1 (ITR9) */ 840 #define TIM_CLOCKSOURCE_ITR10 TIM_TS_ITR10 /*!< External clock source mode 1 (ITR10) */ 841 #define TIM_CLOCKSOURCE_ITR11 TIM_TS_ITR11 /*!< External clock source mode 1 (ITR11) */ 842 #define TIM_CLOCKSOURCE_ITR12 TIM_TS_ITR12 /*!< External clock source mode 1 (ITR12) */ 843 /** 844 * @} 845 */ 846 847 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 848 * @{ 849 */ 850 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 851 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 852 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 853 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 854 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 855 /** 856 * @} 857 */ 858 859 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 860 * @{ 861 */ 862 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 863 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 864 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 865 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 866 /** 867 * @} 868 */ 869 870 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 871 * @{ 872 */ 873 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 874 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 875 /** 876 * @} 877 */ 878 879 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 880 * @{ 881 */ 882 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 883 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 884 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 885 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 886 /** 887 * @} 888 */ 889 890 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 891 * @{ 892 */ 893 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 894 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 895 /** 896 * @} 897 */ 898 899 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 900 * @{ 901 */ 902 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 903 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 904 /** 905 * @} 906 */ 907 /** @defgroup TIM_Lock_level TIM Lock level 908 * @{ 909 */ 910 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ 911 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 912 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 913 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 914 /** 915 * @} 916 */ 917 918 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable 919 * @{ 920 */ 921 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ 922 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ 923 /** 924 * @} 925 */ 926 927 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 928 * @{ 929 */ 930 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 931 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 932 /** 933 * @} 934 */ 935 936 /** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode 937 * @{ 938 */ 939 #define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ 940 #define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ 941 /** 942 * @} 943 */ 944 945 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable 946 * @{ 947 */ 948 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ 949 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ 950 /** 951 * @} 952 */ 953 954 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity 955 * @{ 956 */ 957 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 958 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 959 /** 960 * @} 961 */ 962 963 /** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode 964 * @{ 965 */ 966 #define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ 967 #define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ 968 /** 969 * @} 970 */ 971 972 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 973 * @{ 974 */ 975 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 976 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ 977 /** 978 * @} 979 */ 980 981 /** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 982 * @{ 983 */ 984 #define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 985 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ 986 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ 987 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ 988 /** 989 * @} 990 */ 991 992 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 993 * @{ 994 */ 995 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ 996 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ 997 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ 998 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ 999 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ 1000 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ 1001 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ 1002 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ 1003 #define TIM_TRGO_ENCODER_CLK TIM_CR2_MMS_3 /*!< Encoder clock is used as trigger output(TRGO) */ 1004 /** 1005 * @} 1006 */ 1007 1008 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) 1009 * @{ 1010 */ 1011 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ 1012 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ 1013 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ 1014 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ 1015 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ 1016 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ 1017 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ 1018 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ 1019 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ 1020 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ 1021 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ 1022 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ 1023 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ 1024 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ 1025 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 1026 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 1027 /** 1028 * @} 1029 */ 1030 1031 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode 1032 * @{ 1033 */ 1034 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ 1035 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ 1036 /** 1037 * @} 1038 */ 1039 1040 /** @defgroup TIM_Slave_Mode TIM Slave mode 1041 * @{ 1042 */ 1043 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 1044 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 1045 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 1046 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 1047 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 1048 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ 1049 #define TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode */ 1050 /** 1051 * @} 1052 */ 1053 1054 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 1055 * @{ 1056 */ 1057 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 1058 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 1059 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 1060 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 1061 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 1062 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 1063 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 1064 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 1065 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ 1066 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ 1067 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ 1068 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ 1069 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ 1070 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ 1071 #define TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */ 1072 #define TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */ 1073 /** 1074 * @} 1075 */ 1076 1077 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 1078 * @{ 1079 */ 1080 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ 1081 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ 1082 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ 1083 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ 1084 #define TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) */ 1085 #define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */ 1086 #define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */ 1087 #define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ 1088 #define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */ 1089 #define TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) */ 1090 #define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) */ 1091 #define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */ 1092 #define TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) */ 1093 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 1094 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 1095 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 1096 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 1097 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ 1098 /** 1099 * @} 1100 */ 1101 1102 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 1103 * @{ 1104 */ 1105 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 1106 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 1107 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1108 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1109 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1110 /** 1111 * @} 1112 */ 1113 1114 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 1115 * @{ 1116 */ 1117 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 1118 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 1119 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 1120 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 1121 /** 1122 * @} 1123 */ 1124 1125 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 1126 * @{ 1127 */ 1128 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 1129 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 1130 /** 1131 * @} 1132 */ 1133 1134 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 1135 * @{ 1136 */ 1137 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ 1138 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1139 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1140 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1141 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1142 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1143 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1144 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1145 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1146 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1147 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1148 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1149 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1150 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1151 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1152 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1153 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1154 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1155 #define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U /*!< The transfer is done to 19 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1156 #define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U /*!< The transfer is done to 20 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1157 #define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U /*!< The transfer is done to 21 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1158 #define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U /*!< The transfer is done to 22 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1159 #define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U /*!< The transfer is done to 23 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1160 #define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U /*!< The transfer is done to 24 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1161 #define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U /*!< The transfer is done to 25 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1162 #define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U /*!< The transfer is done to 26 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1163 /** 1164 * @} 1165 */ 1166 1167 /** @defgroup DMA_Handle_index TIM DMA Handle Index 1168 * @{ 1169 */ 1170 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 1171 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 1172 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 1173 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 1174 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 1175 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 1176 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 1177 /** 1178 * @} 1179 */ 1180 1181 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 1182 * @{ 1183 */ 1184 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 1185 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 1186 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ 1187 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ 1188 /** 1189 * @} 1190 */ 1191 1192 /** @defgroup TIM_Break_System TIM Break System 1193 * @{ 1194 */ 1195 #define TIM_BREAK_SYSTEM_ECC SBS_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17/20 */ 1196 #define TIM_BREAK_SYSTEM_PVD SBS_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17/20 Break Input and also the PVDE and PLS bits of the Power Control Interface */ 1197 #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SBS_CFGR2_SEL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17/20 */ 1198 #define TIM_BREAK_SYSTEM_LOCKUP SBS_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17/20 */ 1199 /** 1200 * @} 1201 */ 1202 1203 /** 1204 * @} 1205 */ 1206 /* End of exported constants -------------------------------------------------*/ 1207 1208 /* Exported macros -----------------------------------------------------------*/ 1209 /** @defgroup TIM_Exported_Macros TIM Exported Macros 1210 * @{ 1211 */ 1212 1213 /** @brief Reset TIM handle state. 1214 * @param __HANDLE__ TIM handle. 1215 * @retval None 1216 */ 1217 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 1218 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1219 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1220 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1221 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1222 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1223 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1224 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ 1225 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ 1226 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1227 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1228 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1229 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1230 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 1231 (__HANDLE__)->Base_MspInitCallback = NULL; \ 1232 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 1233 (__HANDLE__)->IC_MspInitCallback = NULL; \ 1234 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 1235 (__HANDLE__)->OC_MspInitCallback = NULL; \ 1236 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 1237 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 1238 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 1239 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 1240 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 1241 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 1242 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 1243 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ 1244 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ 1245 } while(0) 1246 #else 1247 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1248 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1249 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1250 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1251 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1252 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1253 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ 1254 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ 1255 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1256 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1257 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1258 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1259 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 1260 } while(0) 1261 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1262 1263 /** 1264 * @brief Enable the TIM peripheral. 1265 * @param __HANDLE__ TIM handle 1266 * @retval None 1267 */ 1268 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 1269 1270 /** 1271 * @brief Enable the TIM main Output. 1272 * @param __HANDLE__ TIM handle 1273 * @retval None 1274 */ 1275 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 1276 1277 /** 1278 * @brief Disable the TIM peripheral. 1279 * @param __HANDLE__ TIM handle 1280 * @retval None 1281 */ 1282 #define __HAL_TIM_DISABLE(__HANDLE__) \ 1283 do { \ 1284 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1285 { \ 1286 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1287 { \ 1288 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 1289 } \ 1290 } \ 1291 } while(0) 1292 1293 /** 1294 * @brief Disable the TIM main Output. 1295 * @param __HANDLE__ TIM handle 1296 * @retval None 1297 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been 1298 * disabled 1299 */ 1300 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 1301 do { \ 1302 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1303 { \ 1304 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1305 { \ 1306 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 1307 } \ 1308 } \ 1309 } while(0) 1310 1311 /** 1312 * @brief Disable the TIM main Output. 1313 * @param __HANDLE__ TIM handle 1314 * @retval None 1315 * @note The Main Output Enable of a timer instance is disabled unconditionally 1316 */ 1317 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 1318 1319 /** @brief Enable the specified TIM interrupt. 1320 * @param __HANDLE__ specifies the TIM Handle. 1321 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 1322 * This parameter can be one of the following values: 1323 * @arg TIM_IT_UPDATE: Update interrupt 1324 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1325 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1326 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1327 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1328 * @arg TIM_IT_COM: Commutation interrupt 1329 * @arg TIM_IT_TRIGGER: Trigger interrupt 1330 * @arg TIM_IT_BREAK: Break interrupt 1331 * @arg TIM_IT_IDX: Index interrupt 1332 * @arg TIM_IT_DIR: Direction change interrupt 1333 * @arg TIM_IT_IERR: Index error interrupt 1334 * @arg TIM_IT_TERR: Transition error interrupt 1335 * @retval None 1336 */ 1337 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 1338 1339 /** @brief Disable the specified TIM interrupt. 1340 * @param __HANDLE__ specifies the TIM Handle. 1341 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 1342 * This parameter can be one of the following values: 1343 * @arg TIM_IT_UPDATE: Update interrupt 1344 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1345 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1346 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1347 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1348 * @arg TIM_IT_COM: Commutation interrupt 1349 * @arg TIM_IT_TRIGGER: Trigger interrupt 1350 * @arg TIM_IT_BREAK: Break interrupt 1351 * @arg TIM_IT_IDX: Index interrupt 1352 * @arg TIM_IT_DIR: Direction change interrupt 1353 * @arg TIM_IT_IERR: Index error interrupt 1354 * @arg TIM_IT_TERR: Transition error interrupt 1355 * @retval None 1356 */ 1357 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 1358 1359 /** @brief Enable the specified DMA request. 1360 * @param __HANDLE__ specifies the TIM Handle. 1361 * @param __DMA__ specifies the TIM DMA request to enable. 1362 * This parameter can be one of the following values: 1363 * @arg TIM_DMA_UPDATE: Update DMA request 1364 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1365 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1366 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1367 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1368 * @arg TIM_DMA_COM: Commutation DMA request 1369 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1370 * @retval None 1371 */ 1372 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 1373 1374 /** @brief Disable the specified DMA request. 1375 * @param __HANDLE__ specifies the TIM Handle. 1376 * @param __DMA__ specifies the TIM DMA request to disable. 1377 * This parameter can be one of the following values: 1378 * @arg TIM_DMA_UPDATE: Update DMA request 1379 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1380 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1381 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1382 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1383 * @arg TIM_DMA_COM: Commutation DMA request 1384 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1385 * @retval None 1386 */ 1387 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 1388 1389 /** @brief Check whether the specified TIM interrupt flag is set or not. 1390 * @param __HANDLE__ specifies the TIM Handle. 1391 * @param __FLAG__ specifies the TIM interrupt flag to check. 1392 * This parameter can be one of the following values: 1393 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1394 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1395 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1396 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1397 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1398 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1399 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1400 * @arg TIM_FLAG_COM: Commutation interrupt flag 1401 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1402 * @arg TIM_FLAG_BREAK: Break interrupt flag 1403 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1404 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1405 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1406 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1407 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1408 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1409 * @arg TIM_FLAG_IDX: Index interrupt flag 1410 * @arg TIM_FLAG_DIR: Direction change interrupt flag 1411 * @arg TIM_FLAG_IERR: Index error interrupt flag 1412 * @arg TIM_FLAG_TERR: Transition error interrupt flag 1413 * @retval The new state of __FLAG__ (TRUE or FALSE). 1414 */ 1415 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 1416 1417 /** @brief Clear the specified TIM interrupt flag. 1418 * @param __HANDLE__ specifies the TIM Handle. 1419 * @param __FLAG__ specifies the TIM interrupt flag to clear. 1420 * This parameter can be one of the following values: 1421 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1422 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1423 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1424 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1425 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1426 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1427 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1428 * @arg TIM_FLAG_COM: Commutation interrupt flag 1429 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1430 * @arg TIM_FLAG_BREAK: Break interrupt flag 1431 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1432 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1433 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1434 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1435 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1436 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1437 * @arg TIM_FLAG_IDX: Index interrupt flag 1438 * @arg TIM_FLAG_DIR: Direction change interrupt flag 1439 * @arg TIM_FLAG_IERR: Index error interrupt flag 1440 * @arg TIM_FLAG_TERR: Transition error interrupt flag 1441 * @retval The new state of __FLAG__ (TRUE or FALSE). 1442 */ 1443 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 1444 1445 /** 1446 * @brief Check whether the specified TIM interrupt source is enabled or not. 1447 * @param __HANDLE__ TIM handle 1448 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 1449 * This parameter can be one of the following values: 1450 * @arg TIM_IT_UPDATE: Update interrupt 1451 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1452 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1453 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1454 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1455 * @arg TIM_IT_COM: Commutation interrupt 1456 * @arg TIM_IT_TRIGGER: Trigger interrupt 1457 * @arg TIM_IT_BREAK: Break interrupt 1458 * @arg TIM_IT_IDX: Index interrupt 1459 * @arg TIM_IT_DIR: Direction change interrupt 1460 * @arg TIM_IT_IERR: Index error interrupt 1461 * @arg TIM_IT_TERR: Transition error interrupt 1462 * @retval The state of TIM_IT (SET or RESET). 1463 */ 1464 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ 1465 == (__INTERRUPT__)) ? SET : RESET) 1466 1467 /** @brief Clear the TIM interrupt pending bits. 1468 * @param __HANDLE__ TIM handle 1469 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1470 * This parameter can be one of the following values: 1471 * @arg TIM_IT_UPDATE: Update interrupt 1472 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1473 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1474 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1475 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1476 * @arg TIM_IT_COM: Commutation interrupt 1477 * @arg TIM_IT_TRIGGER: Trigger interrupt 1478 * @arg TIM_IT_BREAK: Break interrupt 1479 * @arg TIM_IT_IDX: Index interrupt 1480 * @arg TIM_IT_DIR: Direction change interrupt 1481 * @arg TIM_IT_IERR: Index error interrupt 1482 * @arg TIM_IT_TERR: Transition error interrupt 1483 * @retval None 1484 */ 1485 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 1486 1487 /** 1488 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). 1489 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read 1490 * in an atomic way. 1491 * @param __HANDLE__ TIM handle. 1492 * @retval None 1493 mode. 1494 */ 1495 #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) 1496 1497 /** 1498 * @brief Disable update interrupt flag (UIF) remapping. 1499 * @param __HANDLE__ TIM handle. 1500 * @retval None 1501 mode. 1502 */ 1503 #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) 1504 1505 /** 1506 * @brief Get update interrupt flag (UIF) copy status. 1507 * @param __COUNTER__ Counter value. 1508 * @retval The state of UIFCPY (TRUE or FALSE). 1509 mode. 1510 */ 1511 #define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) 1512 1513 /** 1514 * @brief Indicates whether or not the TIM Counter is used as downcounter. 1515 * @param __HANDLE__ TIM handle. 1516 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 1517 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode 1518 * or Encoder mode. 1519 */ 1520 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 1521 1522 /** 1523 * @brief Set the TIM Prescaler on runtime. 1524 * @param __HANDLE__ TIM handle. 1525 * @param __PRESC__ specifies the Prescaler new value. 1526 * @retval None 1527 */ 1528 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 1529 1530 /** 1531 * @brief Set the TIM Counter Register value on runtime. 1532 * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in 1533 * case of 32 bits counter TIM instance. 1534 * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. 1535 * @param __HANDLE__ TIM handle. 1536 * @param __COUNTER__ specifies the Counter register new value. 1537 * @retval None 1538 */ 1539 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 1540 1541 /** 1542 * @brief Get the TIM Counter Register value on runtime. 1543 * @param __HANDLE__ TIM handle. 1544 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 1545 */ 1546 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 1547 1548 /** 1549 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 1550 * @param __HANDLE__ TIM handle. 1551 * @param __AUTORELOAD__ specifies the Counter register new value. 1552 * @retval None 1553 */ 1554 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 1555 do{ \ 1556 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 1557 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 1558 } while(0) 1559 1560 /** 1561 * @brief Get the TIM Autoreload Register value on runtime. 1562 * @param __HANDLE__ TIM handle. 1563 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 1564 */ 1565 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 1566 1567 /** 1568 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 1569 * @param __HANDLE__ TIM handle. 1570 * @param __CKD__ specifies the clock division value. 1571 * This parameter can be one of the following value: 1572 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1573 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1574 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1575 * @retval None 1576 */ 1577 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 1578 do{ \ 1579 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 1580 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 1581 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 1582 } while(0) 1583 1584 /** 1585 * @brief Get the TIM Clock Division value on runtime. 1586 * @param __HANDLE__ TIM handle. 1587 * @retval The clock division can be one of the following values: 1588 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1589 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1590 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1591 */ 1592 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 1593 1594 /** 1595 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() 1596 * function. 1597 * @param __HANDLE__ TIM handle. 1598 * @param __CHANNEL__ TIM Channels to be configured. 1599 * This parameter can be one of the following values: 1600 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1601 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1602 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1603 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1604 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 1605 * This parameter can be one of the following values: 1606 * @arg TIM_ICPSC_DIV1: no prescaler 1607 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1608 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1609 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1610 * @retval None 1611 */ 1612 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1613 do{ \ 1614 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 1615 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 1616 } while(0) 1617 1618 /** 1619 * @brief Get the TIM Input Capture prescaler on runtime. 1620 * @param __HANDLE__ TIM handle. 1621 * @param __CHANNEL__ TIM Channels to be configured. 1622 * This parameter can be one of the following values: 1623 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 1624 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 1625 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 1626 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 1627 * @retval The input capture prescaler can be one of the following values: 1628 * @arg TIM_ICPSC_DIV1: no prescaler 1629 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1630 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1631 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1632 */ 1633 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 1634 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 1635 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 1636 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 1637 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 1638 1639 /** 1640 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 1641 * @param __HANDLE__ TIM handle. 1642 * @param __CHANNEL__ TIM Channels to be configured. 1643 * This parameter can be one of the following values: 1644 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1645 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1646 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1647 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1648 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1649 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1650 * @param __COMPARE__ specifies the Capture Compare register new value. 1651 * @retval None 1652 */ 1653 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1654 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 1655 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 1656 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 1657 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ 1658 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ 1659 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) 1660 1661 /** 1662 * @brief Get the TIM Capture Compare Register value on runtime. 1663 * @param __HANDLE__ TIM handle. 1664 * @param __CHANNEL__ TIM Channel associated with the capture compare register 1665 * This parameter can be one of the following values: 1666 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 1667 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 1668 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 1669 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 1670 * @arg TIM_CHANNEL_5: get capture/compare 5 register value 1671 * @arg TIM_CHANNEL_6: get capture/compare 6 register value 1672 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 1673 */ 1674 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1675 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 1676 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 1677 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 1678 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ 1679 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ 1680 ((__HANDLE__)->Instance->CCR6)) 1681 1682 /** 1683 * @brief Set the TIM Output compare preload. 1684 * @param __HANDLE__ TIM handle. 1685 * @param __CHANNEL__ TIM Channels to be configured. 1686 * This parameter can be one of the following values: 1687 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1688 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1689 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1690 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1691 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1692 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1693 * @retval None 1694 */ 1695 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1696 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 1697 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 1698 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 1699 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ 1700 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ 1701 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) 1702 1703 /** 1704 * @brief Reset the TIM Output compare preload. 1705 * @param __HANDLE__ TIM handle. 1706 * @param __CHANNEL__ TIM Channels to be configured. 1707 * This parameter can be one of the following values: 1708 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1709 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1710 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1711 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1712 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1713 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1714 * @retval None 1715 */ 1716 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1717 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ 1718 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ 1719 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ 1720 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ 1721 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ 1722 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) 1723 1724 /** 1725 * @brief Enable fast mode for a given channel. 1726 * @param __HANDLE__ TIM handle. 1727 * @param __CHANNEL__ TIM Channels to be configured. 1728 * This parameter can be one of the following values: 1729 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1730 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1731 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1732 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1733 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1734 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1735 * @note When fast mode is enabled an active edge on the trigger input acts 1736 * like a compare match on CCx output. Delay to sample the trigger 1737 * input and to activate CCx output is reduced to 3 clock cycles. 1738 * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. 1739 * @retval None 1740 */ 1741 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1742 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ 1743 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ 1744 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ 1745 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ 1746 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ 1747 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) 1748 1749 /** 1750 * @brief Disable fast mode for a given channel. 1751 * @param __HANDLE__ TIM handle. 1752 * @param __CHANNEL__ TIM Channels to be configured. 1753 * This parameter can be one of the following values: 1754 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1755 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1756 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1757 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1758 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1759 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1760 * @note When fast mode is disabled CCx output behaves normally depending 1761 * on counter and CCRx values even when the trigger is ON. The minimum 1762 * delay to activate CCx output when an active edge occurs on the 1763 * trigger input is 5 clock cycles. 1764 * @retval None 1765 */ 1766 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1767 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ 1768 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ 1769 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ 1770 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ 1771 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ 1772 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) 1773 1774 /** 1775 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 1776 * @param __HANDLE__ TIM handle. 1777 * @note When the URS bit of the TIMx_CR1 register is set, only counter 1778 * overflow/underflow generates an update interrupt or DMA request (if 1779 * enabled) 1780 * @retval None 1781 */ 1782 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 1783 1784 /** 1785 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 1786 * @param __HANDLE__ TIM handle. 1787 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 1788 * following events generate an update interrupt or DMA request (if 1789 * enabled): 1790 * _ Counter overflow underflow 1791 * _ Setting the UG bit 1792 * _ Update generation through the slave mode controller 1793 * @retval None 1794 */ 1795 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 1796 1797 /** 1798 * @brief Set the TIM Capture x input polarity on runtime. 1799 * @param __HANDLE__ TIM handle. 1800 * @param __CHANNEL__ TIM Channels to be configured. 1801 * This parameter can be one of the following values: 1802 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1803 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1804 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1805 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1806 * @param __POLARITY__ Polarity for TIx source 1807 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 1808 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 1809 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 1810 * @retval None 1811 */ 1812 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1813 do{ \ 1814 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 1815 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 1816 }while(0) 1817 1818 /** @brief Select the Capture/compare DMA request source. 1819 * @param __HANDLE__ specifies the TIM Handle. 1820 * @param __CCDMA__ specifies Capture/compare DMA request source 1821 * This parameter can be one of the following values: 1822 * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event 1823 * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event 1824 * @retval None 1825 */ 1826 #define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ 1827 MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) 1828 1829 /** 1830 * @} 1831 */ 1832 /* End of exported macros ----------------------------------------------------*/ 1833 1834 /* Private constants ---------------------------------------------------------*/ 1835 /** @defgroup TIM_Private_Constants TIM Private Constants 1836 * @{ 1837 */ 1838 /* The counter of a timer instance is disabled only if all the CCx and CCxN 1839 channels have been disabled */ 1840 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 1841 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) 1842 /** 1843 * @} 1844 */ 1845 /* End of private constants --------------------------------------------------*/ 1846 1847 /* Private macros ------------------------------------------------------------*/ 1848 /** @defgroup TIM_Private_Macros TIM Private Macros 1849 * @{ 1850 */ 1851 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ 1852 ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ 1853 ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR)) 1854 1855 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1856 ((__BASE__) == TIM_DMABASE_CR2) || \ 1857 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1858 ((__BASE__) == TIM_DMABASE_DIER) || \ 1859 ((__BASE__) == TIM_DMABASE_SR) || \ 1860 ((__BASE__) == TIM_DMABASE_EGR) || \ 1861 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1862 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1863 ((__BASE__) == TIM_DMABASE_CCER) || \ 1864 ((__BASE__) == TIM_DMABASE_CNT) || \ 1865 ((__BASE__) == TIM_DMABASE_PSC) || \ 1866 ((__BASE__) == TIM_DMABASE_ARR) || \ 1867 ((__BASE__) == TIM_DMABASE_RCR) || \ 1868 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1869 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1870 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1871 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1872 ((__BASE__) == TIM_DMABASE_BDTR) || \ 1873 ((__BASE__) == TIM_DMABASE_CCMR3) || \ 1874 ((__BASE__) == TIM_DMABASE_CCR5) || \ 1875 ((__BASE__) == TIM_DMABASE_CCR6) || \ 1876 ((__BASE__) == TIM_DMABASE_AF1) || \ 1877 ((__BASE__) == TIM_DMABASE_AF2) || \ 1878 ((__BASE__) == TIM_DMABASE_TISEL) || \ 1879 ((__BASE__) == TIM_DMABASE_DTR2) || \ 1880 ((__BASE__) == TIM_DMABASE_ECR)) 1881 1882 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1883 1884 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 1885 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 1886 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 1887 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 1888 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 1889 1890 #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ 1891 ((__MODE__) == TIM_UIFREMAP_ENABLE)) 1892 1893 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 1894 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 1895 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 1896 1897 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 1898 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 1899 1900 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 1901 ((__STATE__) == TIM_OCFAST_ENABLE)) 1902 1903 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 1904 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 1905 1906 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ 1907 ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 1908 1909 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ 1910 ((__STATE__) == TIM_OCIDLESTATE_RESET)) 1911 1912 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ 1913 ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 1914 1915 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ 1916 ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) 1917 1918 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 1919 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 1920 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 1921 1922 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 1923 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 1924 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 1925 1926 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 1927 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 1928 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 1929 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 1930 1931 #define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \ 1932 ((__CHANNEL__) != (TIM_CHANNEL_5)) && \ 1933 ((__CHANNEL__) != (TIM_CHANNEL_6))) 1934 1935 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 1936 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 1937 1938 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 1939 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 1940 ((__MODE__) == TIM_ENCODERMODE_TI12) || \ 1941 ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) || \ 1942 ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) || \ 1943 ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) || \ 1944 ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) || \ 1945 ((__MODE__) == TIM_ENCODERMODE_X1_TI1) || \ 1946 ((__MODE__) == TIM_ENCODERMODE_X1_TI2)) 1947 1948 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1949 1950 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1951 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1952 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1953 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 1954 ((__CHANNEL__) == TIM_CHANNEL_5) || \ 1955 ((__CHANNEL__) == TIM_CHANNEL_6) || \ 1956 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 1957 1958 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1959 ((__CHANNEL__) == TIM_CHANNEL_2)) 1960 1961 #define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ 1962 ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) 1963 1964 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1965 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1966 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1967 ((__CHANNEL__) == TIM_CHANNEL_4)) 1968 1969 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 1970 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 1971 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 1972 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 1973 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 1974 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 1975 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 1976 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 1977 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 1978 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 1979 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ 1980 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ 1981 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ 1982 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ 1983 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ 1984 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ 1985 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ 1986 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11) || \ 1987 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR12)) 1988 1989 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 1990 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 1991 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 1992 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 1993 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 1994 1995 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 1996 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 1997 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 1998 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 1999 2000 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2001 2002 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 2003 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 2004 2005 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 2006 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 2007 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 2008 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 2009 2010 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2011 2012 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ 2013 ((__STATE__) == TIM_OSSR_DISABLE)) 2014 2015 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ 2016 ((__STATE__) == TIM_OSSI_DISABLE)) 2017 2018 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ 2019 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ 2020 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ 2021 ((__LEVEL__) == TIM_LOCKLEVEL_3)) 2022 2023 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) 2024 2025 2026 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ 2027 ((__STATE__) == TIM_BREAK_DISABLE)) 2028 2029 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ 2030 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 2031 2032 #define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ 2033 ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) 2034 2035 2036 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ 2037 ((__STATE__) == TIM_BREAK2_DISABLE)) 2038 2039 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ 2040 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) 2041 2042 #define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ 2043 ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) 2044 2045 2046 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 2047 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 2048 2049 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) 2050 2051 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 2052 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 2053 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 2054 ((__SOURCE__) == TIM_TRGO_OC1) || \ 2055 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 2056 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 2057 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 2058 ((__SOURCE__) == TIM_TRGO_OC4REF) || \ 2059 ((__SOURCE__) == TIM_TRGO_ENCODER_CLK)) 2060 2061 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ 2062 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ 2063 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ 2064 ((__SOURCE__) == TIM_TRGO2_OC1) || \ 2065 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ 2066 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ 2067 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 2068 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 2069 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ 2070 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ 2071 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ 2072 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ 2073 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ 2074 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ 2075 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ 2076 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ 2077 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) 2078 2079 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 2080 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 2081 2082 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 2083 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 2084 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 2085 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 2086 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ 2087 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER) || \ 2088 ((__MODE__) == TIM_SLAVEMODE_COMBINED_GATEDRESET)) 2089 2090 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 2091 ((__MODE__) == TIM_OCMODE_PWM2) || \ 2092 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ 2093 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ 2094 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ 2095 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) 2096 2097 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 2098 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 2099 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 2100 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 2101 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 2102 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ 2103 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ 2104 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2) || \ 2105 ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \ 2106 ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) 2107 2108 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 2109 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 2110 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 2111 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 2112 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 2113 2114 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 2115 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 2116 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 2117 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 2118 2119 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2120 2121 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 2122 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 2123 2124 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 2125 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 2126 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 2127 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 2128 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 2129 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 2130 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 2131 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 2132 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 2133 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 2134 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 2135 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 2136 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 2137 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 2138 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 2139 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 2140 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 2141 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS) || \ 2142 ((__LENGTH__) == TIM_DMABURSTLENGTH_19TRANSFERS) || \ 2143 ((__LENGTH__) == TIM_DMABURSTLENGTH_20TRANSFERS) || \ 2144 ((__LENGTH__) == TIM_DMABURSTLENGTH_21TRANSFERS) || \ 2145 ((__LENGTH__) == TIM_DMABURSTLENGTH_22TRANSFERS) || \ 2146 ((__LENGTH__) == TIM_DMABURSTLENGTH_23TRANSFERS) || \ 2147 ((__LENGTH__) == TIM_DMABURSTLENGTH_24TRANSFERS) || \ 2148 ((__LENGTH__) == TIM_DMABURSTLENGTH_25TRANSFERS) || \ 2149 ((__LENGTH__) == TIM_DMABURSTLENGTH_26TRANSFERS)) 2150 2151 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) 2152 2153 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2154 2155 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) 2156 2157 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ 2158 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ 2159 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ 2160 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) 2161 2162 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ 2163 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 2164 2165 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 2166 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 2167 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 2168 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 2169 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 2170 2171 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 2172 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ 2173 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ 2174 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ 2175 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) 2176 2177 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 2178 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 2179 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 2180 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 2181 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 2182 2183 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 2184 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 2185 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 2186 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 2187 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) 2188 2189 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ 2190 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ 2191 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ 2192 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ 2193 ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ 2194 ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ 2195 (__HANDLE__)->ChannelState[5]) 2196 2197 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2198 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ 2199 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ 2200 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ 2201 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ 2202 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ 2203 ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) 2204 2205 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 2206 (__HANDLE__)->ChannelState[0] = \ 2207 (__CHANNEL_STATE__); \ 2208 (__HANDLE__)->ChannelState[1] = \ 2209 (__CHANNEL_STATE__); \ 2210 (__HANDLE__)->ChannelState[2] = \ 2211 (__CHANNEL_STATE__); \ 2212 (__HANDLE__)->ChannelState[3] = \ 2213 (__CHANNEL_STATE__); \ 2214 (__HANDLE__)->ChannelState[4] = \ 2215 (__CHANNEL_STATE__); \ 2216 (__HANDLE__)->ChannelState[5] = \ 2217 (__CHANNEL_STATE__); \ 2218 } while(0) 2219 2220 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ 2221 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ 2222 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ 2223 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ 2224 (__HANDLE__)->ChannelNState[3]) 2225 2226 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2227 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ 2228 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ 2229 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ 2230 ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) 2231 2232 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 2233 (__HANDLE__)->ChannelNState[0] = \ 2234 (__CHANNEL_STATE__); \ 2235 (__HANDLE__)->ChannelNState[1] = \ 2236 (__CHANNEL_STATE__); \ 2237 (__HANDLE__)->ChannelNState[2] = \ 2238 (__CHANNEL_STATE__); \ 2239 (__HANDLE__)->ChannelNState[3] = \ 2240 (__CHANNEL_STATE__); \ 2241 } while(0) 2242 2243 /** 2244 * @} 2245 */ 2246 /* End of private macros -----------------------------------------------------*/ 2247 2248 /* Include TIM HAL Extended module */ 2249 #include "stm32h5xx_hal_tim_ex.h" 2250 2251 /* Exported functions --------------------------------------------------------*/ 2252 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 2253 * @{ 2254 */ 2255 2256 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions 2257 * @brief Time Base functions 2258 * @{ 2259 */ 2260 /* Time Base functions ********************************************************/ 2261 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 2262 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 2263 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 2264 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 2265 /* Blocking mode: Polling */ 2266 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 2267 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 2268 /* Non-Blocking mode: Interrupt */ 2269 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 2270 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 2271 /* Non-Blocking mode: DMA */ 2272 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); 2273 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 2274 /** 2275 * @} 2276 */ 2277 2278 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions 2279 * @brief TIM Output Compare functions 2280 * @{ 2281 */ 2282 /* Timer Output Compare functions *********************************************/ 2283 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 2284 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 2285 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 2286 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 2287 /* Blocking mode: Polling */ 2288 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2289 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2290 /* Non-Blocking mode: Interrupt */ 2291 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2292 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2293 /* Non-Blocking mode: DMA */ 2294 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, 2295 uint16_t Length); 2296 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2297 /** 2298 * @} 2299 */ 2300 2301 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions 2302 * @brief TIM PWM functions 2303 * @{ 2304 */ 2305 /* Timer PWM functions ********************************************************/ 2306 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 2307 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 2308 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 2309 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 2310 /* Blocking mode: Polling */ 2311 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2312 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2313 /* Non-Blocking mode: Interrupt */ 2314 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2315 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2316 /* Non-Blocking mode: DMA */ 2317 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, 2318 uint16_t Length); 2319 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2320 /** 2321 * @} 2322 */ 2323 2324 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions 2325 * @brief TIM Input Capture functions 2326 * @{ 2327 */ 2328 /* Timer Input Capture functions **********************************************/ 2329 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 2330 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 2331 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 2332 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 2333 /* Blocking mode: Polling */ 2334 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2335 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2336 /* Non-Blocking mode: Interrupt */ 2337 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2338 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2339 /* Non-Blocking mode: DMA */ 2340 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2341 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2342 /** 2343 * @} 2344 */ 2345 2346 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions 2347 * @brief TIM One Pulse functions 2348 * @{ 2349 */ 2350 /* Timer One Pulse functions **************************************************/ 2351 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 2352 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 2353 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 2354 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 2355 /* Blocking mode: Polling */ 2356 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2357 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2358 /* Non-Blocking mode: Interrupt */ 2359 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2360 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2361 /** 2362 * @} 2363 */ 2364 2365 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions 2366 * @brief TIM Encoder functions 2367 * @{ 2368 */ 2369 /* Timer Encoder functions ****************************************************/ 2370 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); 2371 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 2372 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 2373 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 2374 /* Blocking mode: Polling */ 2375 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2376 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2377 /* Non-Blocking mode: Interrupt */ 2378 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2379 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2380 /* Non-Blocking mode: DMA */ 2381 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, 2382 uint32_t *pData2, uint16_t Length); 2383 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2384 /** 2385 * @} 2386 */ 2387 2388 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 2389 * @brief IRQ handler management 2390 * @{ 2391 */ 2392 /* Interrupt Handler functions ***********************************************/ 2393 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 2394 /** 2395 * @} 2396 */ 2397 2398 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions 2399 * @brief Peripheral Control functions 2400 * @{ 2401 */ 2402 /* Control functions *********************************************************/ 2403 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, 2404 uint32_t Channel); 2405 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, 2406 uint32_t Channel); 2407 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, 2408 uint32_t Channel); 2409 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, 2410 uint32_t OutputChannel, uint32_t InputChannel); 2411 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, 2412 const TIM_ClearInputConfigTypeDef *sClearInputConfig, 2413 uint32_t Channel); 2414 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); 2415 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 2416 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); 2417 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); 2418 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2419 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); 2420 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2421 uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, 2422 uint32_t BurstLength, uint32_t DataLength); 2423 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2424 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2425 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2426 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2427 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, 2428 uint32_t BurstLength, uint32_t DataLength); 2429 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2430 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 2431 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); 2432 /** 2433 * @} 2434 */ 2435 2436 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 2437 * @brief TIM Callbacks functions 2438 * @{ 2439 */ 2440 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 2441 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 2442 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); 2443 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 2444 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 2445 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); 2446 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 2447 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); 2448 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 2449 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); 2450 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 2451 2452 /* Callbacks Register/UnRegister functions ***********************************/ 2453 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2454 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, 2455 pTIM_CallbackTypeDef pCallback); 2456 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 2457 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2458 2459 /** 2460 * @} 2461 */ 2462 2463 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions 2464 * @brief Peripheral State functions 2465 * @{ 2466 */ 2467 /* Peripheral State functions ************************************************/ 2468 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); 2469 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); 2470 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); 2471 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); 2472 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); 2473 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); 2474 2475 /* Peripheral Channel state functions ************************************************/ 2476 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); 2477 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); 2478 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); 2479 /** 2480 * @} 2481 */ 2482 2483 /** 2484 * @} 2485 */ 2486 /* End of exported functions -------------------------------------------------*/ 2487 2488 /* Private functions----------------------------------------------------------*/ 2489 /** @defgroup TIM_Private_Functions TIM Private Functions 2490 * @{ 2491 */ 2492 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); 2493 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 2494 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); 2495 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, 2496 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); 2497 2498 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); 2499 void TIM_DMAError(DMA_HandleTypeDef *hdma); 2500 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 2501 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); 2502 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 2503 HAL_StatusTypeDef TIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst, 2504 uint32_t length); 2505 2506 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2507 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 2508 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2509 2510 /** 2511 * @} 2512 */ 2513 /* End of private functions --------------------------------------------------*/ 2514 2515 /** 2516 * @} 2517 */ 2518 2519 /** 2520 * @} 2521 */ 2522 2523 #ifdef __cplusplus 2524 } 2525 #endif 2526 2527 #endif /* STM32H5xx_HAL_TIM_H */ 2528
