1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_smbus.h 4 * @author MCD Application Team 5 * @brief Header file of SMBUS HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H5xx_HAL_SMBUS_H 21 #define STM32H5xx_HAL_SMBUS_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /** @addtogroup STM32H5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup SMBUS 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types 40 * @{ 41 */ 42 43 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition 44 * @brief SMBUS Configuration Structure definition 45 * @{ 46 */ 47 typedef struct 48 { 49 uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. 50 This parameter calculated by referring to SMBUS initialization section 51 in Reference manual */ 52 uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. 53 This parameter can be a value of @ref SMBUS_Analog_Filter */ 54 55 uint32_t OwnAddress1; /*!< Specifies the first device own address. 56 This parameter can be a 7-bit address. */ 57 58 uint32_t AddressingMode; /*!< Specifies addressing mode selected. 59 This parameter can be a value of @ref SMBUS_addressing_mode */ 60 61 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. 62 This parameter can be a value of @ref SMBUS_dual_addressing_mode */ 63 64 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected 65 This parameter can be a 7-bit address. */ 66 67 uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address 68 if dual addressing mode is selected 69 This parameter can be a value of @ref SMBUS_own_address2_masks. */ 70 71 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. 72 This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ 73 74 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. 75 This parameter can be a value of @ref SMBUS_nostretch_mode */ 76 77 uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. 78 This parameter can be a value of @ref SMBUS_packet_error_check_mode */ 79 80 uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. 81 This parameter can be a value of @ref SMBUS_peripheral_mode */ 82 83 uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. 84 (Enable bits and different timeout values) 85 This parameter calculated by referring to SMBUS initialization section 86 in Reference manual */ 87 } SMBUS_InitTypeDef; 88 /** 89 * @} 90 */ 91 92 /** @defgroup HAL_state_definition HAL state definition 93 * @brief HAL State definition 94 * @{ 95 */ 96 #define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ 97 #define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ 98 #define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ 99 #define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ 100 #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ 101 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ 102 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ 103 #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ 104 #define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ 105 #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ 106 /** 107 * @} 108 */ 109 110 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition 111 * @brief SMBUS Error Code definition 112 * @{ 113 */ 114 #define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ 115 #define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ 116 #define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ 117 #define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ 118 #define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ 119 #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ 120 #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ 121 #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ 122 #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ 123 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 124 #define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ 125 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 126 #define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ 127 /** 128 * @} 129 */ 130 131 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition 132 * @brief SMBUS handle Structure definition 133 * @{ 134 */ 135 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 136 typedef struct __SMBUS_HandleTypeDef 137 #else 138 typedef struct 139 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 140 { 141 I2C_TypeDef *Instance; /*!< SMBUS registers base address */ 142 143 SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ 144 145 uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ 146 147 uint16_t XferSize; /*!< SMBUS transfer size */ 148 149 __IO uint16_t XferCount; /*!< SMBUS transfer counter */ 150 151 __IO uint32_t XferOptions; /*!< SMBUS transfer options */ 152 153 __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */ 154 155 HAL_LockTypeDef Lock; /*!< SMBUS locking object */ 156 157 __IO uint32_t State; /*!< SMBUS communication state */ 158 159 __IO uint32_t ErrorCode; /*!< SMBUS Error code */ 160 161 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 162 void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 163 /*!< SMBUS Master Tx Transfer completed callback */ 164 void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 165 /*!< SMBUS Master Rx Transfer completed callback */ 166 void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 167 /*!< SMBUS Slave Tx Transfer completed callback */ 168 void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 169 /*!< SMBUS Slave Rx Transfer completed callback */ 170 void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 171 /*!< SMBUS Listen Complete callback */ 172 void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 173 /*!< SMBUS Error callback */ 174 175 void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 176 /*!< SMBUS Slave Address Match callback */ 177 178 void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 179 /*!< SMBUS Msp Init callback */ 180 void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 181 /*!< SMBUS Msp DeInit callback */ 182 183 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 184 } SMBUS_HandleTypeDef; 185 186 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 187 /** 188 * @brief HAL SMBUS Callback ID enumeration definition 189 */ 190 typedef enum 191 { 192 HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */ 193 HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */ 194 HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */ 195 HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */ 196 HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */ 197 HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */ 198 199 HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */ 200 HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */ 201 202 } HAL_SMBUS_CallbackIDTypeDef; 203 204 /** 205 * @brief HAL SMBUS Callback pointer definition 206 */ 207 typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); 208 /*!< pointer to an SMBUS callback function */ 209 typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, 210 uint16_t AddrMatchCode); 211 /*!< pointer to an SMBUS Address Match callback function */ 212 213 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 214 /** 215 * @} 216 */ 217 218 /** 219 * @} 220 */ 221 /* Exported constants --------------------------------------------------------*/ 222 223 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants 224 * @{ 225 */ 226 227 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter 228 * @{ 229 */ 230 #define SMBUS_ANALOGFILTER_ENABLE (0x00000000U) 231 #define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF 232 /** 233 * @} 234 */ 235 236 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode 237 * @{ 238 */ 239 #define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U) 240 /** 241 * @} 242 */ 243 244 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode 245 * @{ 246 */ 247 248 #define SMBUS_DUALADDRESS_DISABLE (0x00000000U) 249 #define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN 250 /** 251 * @} 252 */ 253 254 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks 255 * @{ 256 */ 257 258 #define SMBUS_OA2_NOMASK ((uint8_t)0x00U) 259 #define SMBUS_OA2_MASK01 ((uint8_t)0x01U) 260 #define SMBUS_OA2_MASK02 ((uint8_t)0x02U) 261 #define SMBUS_OA2_MASK03 ((uint8_t)0x03U) 262 #define SMBUS_OA2_MASK04 ((uint8_t)0x04U) 263 #define SMBUS_OA2_MASK05 ((uint8_t)0x05U) 264 #define SMBUS_OA2_MASK06 ((uint8_t)0x06U) 265 #define SMBUS_OA2_MASK07 ((uint8_t)0x07U) 266 /** 267 * @} 268 */ 269 270 271 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode 272 * @{ 273 */ 274 #define SMBUS_GENERALCALL_DISABLE (0x00000000U) 275 #define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN 276 /** 277 * @} 278 */ 279 280 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode 281 * @{ 282 */ 283 #define SMBUS_NOSTRETCH_DISABLE (0x00000000U) 284 #define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH 285 /** 286 * @} 287 */ 288 289 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode 290 * @{ 291 */ 292 #define SMBUS_PEC_DISABLE (0x00000000U) 293 #define SMBUS_PEC_ENABLE I2C_CR1_PECEN 294 /** 295 * @} 296 */ 297 298 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode 299 * @{ 300 */ 301 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN 302 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U) 303 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN 304 /** 305 * @} 306 */ 307 308 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition 309 * @{ 310 */ 311 312 #define SMBUS_SOFTEND_MODE (0x00000000U) 313 #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD 314 #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND 315 #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE 316 /** 317 * @} 318 */ 319 320 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition 321 * @{ 322 */ 323 324 #define SMBUS_NO_STARTSTOP (0x00000000U) 325 #define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) 326 #define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) 327 #define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) 328 /** 329 * @} 330 */ 331 332 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition 333 * @{ 334 */ 335 336 /* List of XferOptions in usage of : 337 * 1- Restart condition when direction change 338 * 2- No Restart condition in other use cases 339 */ 340 #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE 341 #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) 342 #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE 343 #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE 344 #define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE)) 345 #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) 346 #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) 347 348 /* List of XferOptions in usage of : 349 * 1- Restart condition in all use cases (direction change or not) 350 */ 351 #define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) 352 #define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) 353 #define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) 354 #define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) 355 /** 356 * @} 357 */ 358 359 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition 360 * @brief SMBUS Interrupt definition 361 * Elements values convention: 0xXXXXXXXX 362 * - XXXXXXXX : Interrupt control mask 363 * @{ 364 */ 365 #define SMBUS_IT_ERRI I2C_CR1_ERRIE 366 #define SMBUS_IT_TCI I2C_CR1_TCIE 367 #define SMBUS_IT_STOPI I2C_CR1_STOPIE 368 #define SMBUS_IT_NACKI I2C_CR1_NACKIE 369 #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE 370 #define SMBUS_IT_RXI I2C_CR1_RXIE 371 #define SMBUS_IT_TXI I2C_CR1_TXIE 372 #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \ 373 SMBUS_IT_NACKI | SMBUS_IT_TXI) 374 #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \ 375 SMBUS_IT_RXI) 376 #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) 377 #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) 378 /** 379 * @} 380 */ 381 382 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition 383 * @brief Flag definition 384 * Elements values convention: 0xXXXXYYYY 385 * - XXXXXXXX : Flag mask 386 * @{ 387 */ 388 389 #define SMBUS_FLAG_TXE I2C_ISR_TXE 390 #define SMBUS_FLAG_TXIS I2C_ISR_TXIS 391 #define SMBUS_FLAG_RXNE I2C_ISR_RXNE 392 #define SMBUS_FLAG_ADDR I2C_ISR_ADDR 393 #define SMBUS_FLAG_AF I2C_ISR_NACKF 394 #define SMBUS_FLAG_STOPF I2C_ISR_STOPF 395 #define SMBUS_FLAG_TC I2C_ISR_TC 396 #define SMBUS_FLAG_TCR I2C_ISR_TCR 397 #define SMBUS_FLAG_BERR I2C_ISR_BERR 398 #define SMBUS_FLAG_ARLO I2C_ISR_ARLO 399 #define SMBUS_FLAG_OVR I2C_ISR_OVR 400 #define SMBUS_FLAG_PECERR I2C_ISR_PECERR 401 #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT 402 #define SMBUS_FLAG_ALERT I2C_ISR_ALERT 403 #define SMBUS_FLAG_BUSY I2C_ISR_BUSY 404 #define SMBUS_FLAG_DIR I2C_ISR_DIR 405 /** 406 * @} 407 */ 408 409 /** 410 * @} 411 */ 412 413 /* Exported macros ------------------------------------------------------------*/ 414 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros 415 * @{ 416 */ 417 418 /** @brief Reset SMBUS handle state. 419 * @param __HANDLE__ specifies the SMBUS Handle. 420 * @retval None 421 */ 422 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 423 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ 424 (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ 425 (__HANDLE__)->MspInitCallback = NULL; \ 426 (__HANDLE__)->MspDeInitCallback = NULL; \ 427 } while(0) 428 #else 429 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) 430 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 431 432 /** @brief Enable the specified SMBUS interrupts. 433 * @param __HANDLE__ specifies the SMBUS Handle. 434 * @param __INTERRUPT__ specifies the interrupt source to enable. 435 * This parameter can be one of the following values: 436 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 437 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 438 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 439 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 440 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 441 * @arg @ref SMBUS_IT_RXI RX interrupt enable 442 * @arg @ref SMBUS_IT_TXI TX interrupt enable 443 * 444 * @retval None 445 */ 446 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) 447 448 /** @brief Disable the specified SMBUS interrupts. 449 * @param __HANDLE__ specifies the SMBUS Handle. 450 * @param __INTERRUPT__ specifies the interrupt source to disable. 451 * This parameter can be one of the following values: 452 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 453 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 454 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 455 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 456 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 457 * @arg @ref SMBUS_IT_RXI RX interrupt enable 458 * @arg @ref SMBUS_IT_TXI TX interrupt enable 459 * 460 * @retval None 461 */ 462 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) 463 464 /** @brief Check whether the specified SMBUS interrupt source is enabled or not. 465 * @param __HANDLE__ specifies the SMBUS Handle. 466 * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. 467 * This parameter can be one of the following values: 468 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 469 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 470 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 471 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 472 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 473 * @arg @ref SMBUS_IT_RXI RX interrupt enable 474 * @arg @ref SMBUS_IT_TXI TX interrupt enable 475 * 476 * @retval The new state of __IT__ (SET or RESET). 477 */ 478 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 479 ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 480 481 /** @brief Check whether the specified SMBUS flag is set or not. 482 * @param __HANDLE__ specifies the SMBUS Handle. 483 * @param __FLAG__ specifies the flag to check. 484 * This parameter can be one of the following values: 485 * @arg @ref SMBUS_FLAG_TXE Transmit data register empty 486 * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status 487 * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty 488 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) 489 * @arg @ref SMBUS_FLAG_AF NACK received flag 490 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag 491 * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) 492 * @arg @ref SMBUS_FLAG_TCR Transfer complete reload 493 * @arg @ref SMBUS_FLAG_BERR Bus error 494 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost 495 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun 496 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception 497 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 498 * @arg @ref SMBUS_FLAG_ALERT SMBus alert 499 * @arg @ref SMBUS_FLAG_BUSY Bus busy 500 * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) 501 * 502 * @retval The new state of __FLAG__ (SET or RESET). 503 */ 504 #define SMBUS_FLAG_MASK (0x0001FFFFU) 505 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ 506 (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ 507 ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) 508 509 /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. 510 * @param __HANDLE__ specifies the SMBUS Handle. 511 * @param __FLAG__ specifies the flag to clear. 512 * This parameter can be any combination of the following values: 513 * @arg @ref SMBUS_FLAG_TXE Transmit data register empty 514 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) 515 * @arg @ref SMBUS_FLAG_AF NACK received flag 516 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag 517 * @arg @ref SMBUS_FLAG_BERR Bus error 518 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost 519 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun 520 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception 521 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 522 * @arg @ref SMBUS_FLAG_ALERT SMBus alert 523 * 524 * @retval None 525 */ 526 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == SMBUS_FLAG_TXE) ? \ 527 ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ 528 ((__HANDLE__)->Instance->ICR = (__FLAG__))) 529 530 /** @brief Enable the specified SMBUS peripheral. 531 * @param __HANDLE__ specifies the SMBUS Handle. 532 * @retval None 533 */ 534 #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) 535 536 /** @brief Disable the specified SMBUS peripheral. 537 * @param __HANDLE__ specifies the SMBUS Handle. 538 * @retval None 539 */ 540 #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) 541 542 /** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. 543 * @param __HANDLE__ specifies the SMBUS Handle. 544 * @retval None 545 */ 546 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) 547 548 /** 549 * @} 550 */ 551 552 553 /* Private constants ---------------------------------------------------------*/ 554 555 /* Private macros ------------------------------------------------------------*/ 556 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros 557 * @{ 558 */ 559 560 #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ 561 ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) 562 563 #define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) 564 565 #define IS_SMBUS_ADDRESSING_MODE(MODE) ((MODE) == SMBUS_ADDRESSINGMODE_7BIT) 566 567 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ 568 ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) 569 570 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ 571 ((MASK) == SMBUS_OA2_MASK01) || \ 572 ((MASK) == SMBUS_OA2_MASK02) || \ 573 ((MASK) == SMBUS_OA2_MASK03) || \ 574 ((MASK) == SMBUS_OA2_MASK04) || \ 575 ((MASK) == SMBUS_OA2_MASK05) || \ 576 ((MASK) == SMBUS_OA2_MASK06) || \ 577 ((MASK) == SMBUS_OA2_MASK07)) 578 579 #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ 580 ((CALL) == SMBUS_GENERALCALL_ENABLE)) 581 582 #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ 583 ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) 584 585 #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ 586 ((PEC) == SMBUS_PEC_ENABLE)) 587 588 #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ 589 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ 590 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) 591 592 #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ 593 ((MODE) == SMBUS_AUTOEND_MODE) || \ 594 ((MODE) == SMBUS_SOFTEND_MODE) || \ 595 ((MODE) == SMBUS_SENDPEC_MODE) || \ 596 ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ 597 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ 598 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ 599 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \ 600 SMBUS_RELOAD_MODE ))) 601 602 603 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ 604 ((REQUEST) == SMBUS_GENERATE_START_READ) || \ 605 ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ 606 ((REQUEST) == SMBUS_NO_STARTSTOP)) 607 608 609 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ 610 ((REQUEST) == SMBUS_FIRST_FRAME) || \ 611 ((REQUEST) == SMBUS_NEXT_FRAME) || \ 612 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ 613 ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ 614 ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ 615 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ 616 ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) 617 618 #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ 619 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ 620 ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ 621 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) 622 623 #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ 624 (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \ 625 I2C_CR1_PECEN))) 626 #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ 627 (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ 628 I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ 629 I2C_CR2_RD_WRN))) 630 631 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \ 632 (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ 633 (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ 634 (~I2C_CR2_RD_WRN)) : \ 635 (uint32_t)((((uint32_t)(__ADDRESS__) & \ 636 (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \ 637 (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) 638 639 #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) 640 #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) 641 #define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) 642 #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) 643 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) 644 645 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ 646 ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) 647 #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) 648 649 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) 650 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) 651 652 /** 653 * @} 654 */ 655 656 /* Include SMBUS HAL Extended module */ 657 #include "stm32h5xx_hal_smbus_ex.h" 658 659 /* Exported functions --------------------------------------------------------*/ 660 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions 661 * @{ 662 */ 663 664 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions 665 * @{ 666 */ 667 668 /* Initialization and de-initialization functions ****************************/ 669 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); 670 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); 671 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); 672 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); 673 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); 674 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); 675 676 /* Callbacks Register/UnRegister functions ***********************************/ 677 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 678 HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, 679 HAL_SMBUS_CallbackIDTypeDef CallbackID, 680 pSMBUS_CallbackTypeDef pCallback); 681 HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, 682 HAL_SMBUS_CallbackIDTypeDef CallbackID); 683 684 HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, 685 pSMBUS_AddrCallbackTypeDef pCallback); 686 HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); 687 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 688 /** 689 * @} 690 */ 691 692 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions 693 * @{ 694 */ 695 696 /* IO operation functions *****************************************************/ 697 /** @addtogroup Blocking_mode_Polling Blocking mode Polling 698 * @{ 699 */ 700 /******* Blocking mode: Polling */ 701 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, 702 uint32_t Timeout); 703 /** 704 * @} 705 */ 706 707 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt 708 * @{ 709 */ 710 /******* Non-Blocking mode: Interrupt */ 711 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, 712 uint8_t *pData, uint16_t Size, uint32_t XferOptions); 713 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, 714 uint8_t *pData, uint16_t Size, uint32_t XferOptions); 715 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); 716 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, 717 uint32_t XferOptions); 718 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, 719 uint32_t XferOptions); 720 721 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); 722 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); 723 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); 724 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); 725 /** 726 * @} 727 */ 728 729 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 730 * @{ 731 */ 732 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ 733 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); 734 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); 735 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 736 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 737 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 738 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 739 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 740 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); 741 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); 742 743 /** 744 * @} 745 */ 746 747 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions 748 * @{ 749 */ 750 751 /* Peripheral State and Errors functions **************************************************/ 752 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); 753 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); 754 755 /** 756 * @} 757 */ 758 759 /** 760 * @} 761 */ 762 763 /* Private Functions ---------------------------------------------------------*/ 764 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions 765 * @{ 766 */ 767 /* Private functions are defined in stm32h5xx_hal_smbus.c file */ 768 /** 769 * @} 770 */ 771 772 /** 773 * @} 774 */ 775 776 /** 777 * @} 778 */ 779 780 /** 781 * @} 782 */ 783 784 #ifdef __cplusplus 785 } 786 #endif 787 788 789 #endif /* STM32H5xx_HAL_SMBUS_H */ 790
