1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_pwr.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H5xx_HAL_PWR_H 21 #define STM32H5xx_HAL_PWR_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif /* __cplusplus */ 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /** @addtogroup STM32H5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup PWR 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup PWR_Exported_Types PWR Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief PWR PVD configuration structure definition 46 */ 47 typedef struct 48 { 49 uint32_t PVDLevel; /*!< Specifies the PVD detection level. 50 This parameter can be a value of 51 @ref PWR_PVD_Detection_Level. */ 52 53 uint32_t Mode; /*!< Specifies the operating mode for the selected pins. 54 This parameter can be a value of @ref PWR_PVD_Mode. */ 55 } PWR_PVDTypeDef; 56 /** 57 * @} 58 */ 59 60 /* Exported constants --------------------------------------------------------*/ 61 62 /** @defgroup PWR_Exported_Constants PWR Exported Constants 63 * @{ 64 */ 65 66 /** @defgroup PWR_PVD_Detection_Level Programmable Voltage Detection Level 67 * @{ 68 */ 69 #define PWR_PVDLEVEL_0 0x00000000UL /*!< PVD threshold around 1.95 V */ 70 #define PWR_PVDLEVEL_1 (PWR_VMCR_PLS_0) /*!< PVD threshold around 2.1 V */ 71 #define PWR_PVDLEVEL_2 (PWR_VMCR_PLS_1) /*!< PVD threshold around 2.25 V */ 72 #define PWR_PVDLEVEL_3 (PWR_VMCR_PLS_0 | PWR_VMCR_PLS_1) /*!< PVD threshold around 2.4 V */ 73 #define PWR_PVDLEVEL_4 (PWR_VMCR_PLS_2) /*!< PVD threshold around 2.55 V */ 74 #define PWR_PVDLEVEL_5 (PWR_VMCR_PLS_0 | PWR_VMCR_PLS_2) /*!< PVD threshold around 2.7 V */ 75 #define PWR_PVDLEVEL_6 (PWR_VMCR_PLS_1 | PWR_VMCR_PLS_2) /*!< PVD threshold around 2.85 V */ 76 #define PWR_PVDLEVEL_7 (PWR_VMCR_PLS) /*!< External input analog voltage 77 (compared internally to VREFINT) */ 78 /** 79 * @} 80 */ 81 82 /** @defgroup PWR_PVD_Mode PWR PVD Mode 83 * @{ 84 */ 85 #define PWR_PVD_MODE_NORMAL (0x00U) /*!< Basic Mode is used */ 86 #define PWR_PVD_MODE_IT_RISING (0x05U) /*!< External Interrupt Mode with Rising edge trigger detection */ 87 #define PWR_PVD_MODE_IT_FALLING (0x06U) /*!< External Interrupt Mode with Falling 88 edge trigger detection */ 89 #define PWR_PVD_MODE_IT_RISING_FALLING (0x07U) /*!< External Interrupt Mode with Rising/Falling 90 edge trigger detection */ 91 #define PWR_PVD_MODE_EVENT_RISING (0x09U) /*!< Event Mode with Rising edge trigger detection */ 92 #define PWR_PVD_MODE_EVENT_FALLING (0x0AU) /*!< Event Mode with Falling edge trigger detection */ 93 #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x0BU) /*!< Event Mode with Rising/Falling edge trigger detection */ 94 /** 95 * @} 96 */ 97 98 /** @defgroup PWR_Regulator_In_LowPower_Mode PWR Regulator State in SLEEP/STOP Mode 99 * @{ 100 */ 101 #define PWR_MAINREGULATOR_ON (0x00U) /*!< Main Regulator ON in Run Mode */ 102 #define PWR_LOWPOWERREGULATOR_ON (0x00U) /*!< Main Regulator ON in Low Power Mode */ 103 /** 104 * @} 105 */ 106 107 /** @defgroup PWR_SLEEP_Mode_Entry PWR SLEEP Mode Entry 108 * @{ 109 */ 110 #define PWR_SLEEPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Sleep mode */ 111 #define PWR_SLEEPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Sleep mode */ 112 /** 113 * @} 114 */ 115 116 /** @defgroup PWR_STOP_Mode_Entry PWR STOP Mode Entry 117 * @{ 118 */ 119 #define PWR_STOPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Stop mode */ 120 #define PWR_STOPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Stop mode */ 121 /** 122 * @} 123 */ 124 125 /** @defgroup PWR_Flags PWR Flags 126 * @{ 127 */ 128 #define PWR_FLAG_STOPF (0x01U) /*!< STOP flag */ 129 #define PWR_FLAG_SBF (0x02U) /*!< STANDBY flag */ 130 #define PWR_FLAG_VOSRDY (0x03U) /*!< Voltage scaling ready flag */ 131 #define PWR_FLAG_ACTVOSRDY (0x04U) /*!< Currently applied VOS ready flag */ 132 #define PWR_FLAG_BRR (0x05U) /*!< Backup regulator ready flag */ 133 #define PWR_FLAG_VBATL (0x06U) /*!< Backup domain voltage level flag (versus low threshold) */ 134 #define PWR_FLAG_VBATH (0x07U) /*!< Backup domain voltage level flag (versus high threshold) */ 135 #define PWR_FLAG_TEMPL (0x08U) /*!< Temperature level flag (versus low threshold) */ 136 #define PWR_FLAG_TEMPH (0x09U) /*!< Temperature level flag (versus high threshold) */ 137 #define PWR_FLAG_AVDO (0x0AU) /*!< VDDA voltage detector output flag */ 138 #define PWR_FLAG_VDDIO2RDY (0x0BU) /*!< VDDIO2 voltage detector output flag */ 139 #define PWR_FLAG_PVDO (0x0CU) /*!< VDD voltage detector output flag */ 140 #define PWR_FLAG_USB33RDY (0x0DU) /*!< VDDUSB33 ready flag */ 141 142 #define PWR_WAKEUP_FLAG1 (0x10U) /*!< Wake up line 1 flag */ 143 #define PWR_WAKEUP_FLAG2 (0x20U) /*!< Wake up line 2 flag */ 144 #define PWR_WAKEUP_FLAG3 (0x30U) /*!< Wake up line 3 flag */ 145 #define PWR_WAKEUP_FLAG4 (0x40U) /*!< Wake up line 4 flag */ 146 #define PWR_WAKEUP_FLAG5 (0x50U) /*!< Wake up line 5 flag */ 147 #define PWR_WAKEUP_FLAG6 (0x60U) /*!< Wake up line 6 flag */ 148 #define PWR_WAKEUP_FLAG7 (0x70U) /*!< Wake up line 7 flag */ 149 #define PWR_WAKEUP_FLAG8 (0x80U) /*!< Wake up line 8 flag */ 150 #define PWR_WAKEUP_ALL_FLAG (0x90U) /*!< Wakeup flag all */ 151 152 /** 153 * @} 154 */ 155 156 /** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins 157 * @{ 158 */ 159 /* High level and No pull (default configuration) */ 160 #define PWR_WAKEUP_PIN1 PWR_WUCR_WUPEN1 161 #define PWR_WAKEUP_PIN2 PWR_WUCR_WUPEN2 162 #define PWR_WAKEUP_PIN3 PWR_WUCR_WUPEN3 163 #define PWR_WAKEUP_PIN4 PWR_WUCR_WUPEN4 164 #define PWR_WAKEUP_PIN5 PWR_WUCR_WUPEN5 165 #if defined (PWR_WUCR_WUPEN6) 166 #define PWR_WAKEUP_PIN6 PWR_WUCR_WUPEN6 167 #define PWR_WAKEUP_PIN7 PWR_WUCR_WUPEN7 168 #define PWR_WAKEUP_PIN8 PWR_WUCR_WUPEN8 169 #endif /* PWR_WUCR_WUPEN6 */ 170 171 /* High level and No pull */ 172 #define PWR_WAKEUP_PIN1_HIGH PWR_WUCR_WUPEN1 173 #define PWR_WAKEUP_PIN2_HIGH PWR_WUCR_WUPEN2 174 #define PWR_WAKEUP_PIN3_HIGH PWR_WUCR_WUPEN3 175 #define PWR_WAKEUP_PIN4_HIGH PWR_WUCR_WUPEN4 176 #define PWR_WAKEUP_PIN5_HIGH PWR_WUCR_WUPEN5 177 #if defined (PWR_WUCR_WUPEN6) 178 #define PWR_WAKEUP_PIN6_HIGH PWR_WUCR_WUPEN6 179 #define PWR_WAKEUP_PIN7_HIGH PWR_WUCR_WUPEN7 180 #define PWR_WAKEUP_PIN8_HIGH PWR_WUCR_WUPEN8 181 #endif /* PWR_WUCR_WUPEN6 */ 182 183 /* Low level and No pull */ 184 #define PWR_WAKEUP_PIN1_LOW (PWR_WUCR_WUPP1 | PWR_WUCR_WUPEN1) 185 #define PWR_WAKEUP_PIN2_LOW (PWR_WUCR_WUPP2 | PWR_WUCR_WUPEN2) 186 #define PWR_WAKEUP_PIN3_LOW (PWR_WUCR_WUPP3 | PWR_WUCR_WUPEN3) 187 #define PWR_WAKEUP_PIN4_LOW (PWR_WUCR_WUPP4 | PWR_WUCR_WUPEN4) 188 #define PWR_WAKEUP_PIN5_LOW (PWR_WUCR_WUPP5 | PWR_WUCR_WUPEN5) 189 #if defined (PWR_WUCR_WUPEN6) 190 #define PWR_WAKEUP_PIN6_LOW (PWR_WUCR_WUPP6 | PWR_WUCR_WUPEN6) 191 #define PWR_WAKEUP_PIN7_LOW (PWR_WUCR_WUPP7 | PWR_WUCR_WUPEN7) 192 #define PWR_WAKEUP_PIN8_LOW (PWR_WUCR_WUPP8 | PWR_WUCR_WUPEN8) 193 #endif /* PWR_WUCR_WUPEN6 */ 194 195 /** 196 * @} 197 */ 198 199 /** @defgroup PWR_Items PWR Items 200 * @{ 201 */ 202 #if defined(PWR_SECCFGR_WUP1SEC) 203 #define PWR_WKUP1 (PWR_SECCFGR_WUP1SEC) /*!< WUP1 secure protection */ 204 #define PWR_WKUP2 (PWR_SECCFGR_WUP2SEC) /*!< WUP2 secure protection */ 205 #define PWR_WKUP3 (PWR_SECCFGR_WUP3SEC) /*!< WUP3 secure protection */ 206 #define PWR_WKUP4 (PWR_SECCFGR_WUP4SEC) /*!< WUP4 secure protection */ 207 #define PWR_WKUP5 (PWR_SECCFGR_WUP5SEC) /*!< WUP5 secure protection */ 208 #define PWR_WKUP6 (PWR_SECCFGR_WUP6SEC) /*!< WUP6 secure protection */ 209 #define PWR_WKUP7 (PWR_SECCFGR_WUP7SEC) /*!< WUP7 secure protection */ 210 #define PWR_WKUP8 (PWR_SECCFGR_WUP8SEC) /*!< WUP8 secure protection */ 211 #define PWR_RET (PWR_SECCFGR_RETSEC) /*!< IO Retention secure protection */ 212 #define PWR_LPM (PWR_SECCFGR_LPMSEC) /*!< Low power modes secure protection */ 213 #define PWR_SCM (PWR_SECCFGR_SCMSEC) /*!< Voltage detection and monitoring secure protection */ 214 #define PWR_VB (PWR_SECCFGR_VBSEC) /*!< Backup domain secure protection */ 215 #define PWR_VUSB (PWR_SECCFGR_VUSBSEC) /*!< Voltage USB secure protection */ 216 #define PWR_ALL (PWR_WKUP1 | PWR_WKUP2 | PWR_WKUP3 | PWR_WKUP4 | \ 217 PWR_WKUP5 | PWR_WKUP6 | PWR_WKUP7 | PWR_WKUP8 | \ 218 PWR_LPM | PWR_SCM | PWR_VB | PWR_VUSB | \ 219 PWR_RET) 220 #else 221 #define PWR_ALL 0xFF /*!< Dummy Value */ 222 #endif /* PWR_SECCFGR_WUP1SEC */ 223 224 /** 225 * @} 226 */ 227 228 /** @defgroup PWR_Attributes PWR Attributes 229 * @brief PWR Privilege/NPrivilege and Secure/NSecure Attributes 230 * @{ 231 */ 232 #if defined(PWR_PRIVCFGR_NSPRIV) 233 #define PWR_NSEC_PRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK | 0x01U) /*!< NSecure and Privileged attribute */ 234 #define PWR_NSEC_NPRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK) /*!< NSecure and NPrivileged attribute */ 235 #else 236 #define PWR_PRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK | 0x01U) /*!< Privileged attribute */ 237 #define PWR_NPRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK) /*!< NPrivileged attribute */ 238 #endif /* PWR_PRIVCFGR_NSPRIV */ 239 #define PWR_SEC_PRIV (PWR_ITEM_ATTR_SEC_PRIV_MASK | 0x02U) /*!< Secure and Privileged attribute */ 240 #define PWR_SEC_NPRIV (PWR_ITEM_ATTR_SEC_PRIV_MASK) /*!< Secure and NPrivileged attribute */ 241 /** 242 * @} 243 */ 244 245 /** 246 * @} 247 */ 248 249 /* Exported macros -----------------------------------------------------------*/ 250 251 /** @defgroup PWR_Exported_Macros PWR Exported Macros 252 * @{ 253 */ 254 255 /** @brief Check PWR flags are set or not. 256 * @param __FLAG__ : Specifies the flag to check. 257 * This parameter can be one of the following values : 258 * @arg @ref PWR_FLAG_STOPF : Stop flag. 259 * Indicates that the device was resumed from Stop mode. 260 * @arg @ref PWR_FLAG_SBF : Standby flag. 261 * Indicates that the device was resumed from Standby mode. 262 * @arg @ref PWR_FLAG_VOSRDY : Voltage scaling ready flag. 263 * Indicates that the Vcore level at or above VOS selected level. 264 * @arg @ref PWR_FLAG_ACTVOSRDY : Currently applied VOS ready flag. 265 * Indicates that Vcore is equal to the current 266 * voltage scaling provided by ACTVOS. 267 * @arg @ref PWR_FLAG_BRR : Backup regulator ready flag. This bit is not 268 * reset when the device wakes up from STANDBY 269 * mode or by a system reset or power-on reset. 270 * @arg @ref PWR_FLAG_VBATL : Backup domain voltage level flag (versus low threshold). 271 * Indicates the backup domain voltage 272 * level is equal or above low threshold. 273 * @arg @ref PWR_FLAG_VBATH : Backup domain voltage level flag (versus high threshold). 274 * Indicates the backup domain voltage 275 * level is equal or above high threshold. 276 * @arg @ref PWR_FLAG_TEMPL : Temperature level flag (versus low threshold). 277 * Indicates the temperature is equal or above low threshold. 278 * @arg @ref PWR_FLAG_TEMPH : Temperature level flag (versus high threshold). 279 * Indicates the temperature is equal or above high threshold. 280 * @arg @ref PWR_FLAG_AVDO : Regulator selection flag. 281 * Indicates the regulator selected. 282 * @arg @ref PWR_FLAG_VDDIO2RDY : VDDIO2 ready flag (versus 0.9 V threshold). 283 * Indicates that VDDIO2 is equal or above the threshold 284 * of the VDDIO2 voltage monitor (around 0.9 V). 285 * @arg @ref PWR_FLAG_PVDO : Voltage detector output flag. 286 * Indicates that Vdd is equal or above 287 * the PVD threshold selected by PVDLS. 288 * @arg @ref PWR_FLAG_USB33RDY : VDDUSB ready flag (versus 1.2 V threshold). 289 * Indicates that VDDUSB is equal or above the threshold 290 * of the VDDUSB voltage monitor (around 1.2 V). 291 * @arg @ref PWR_WAKEUP_FLAG1 : Wakeup flag 1. 292 * Indicates that a wakeup event was received from the WKUP line 1. 293 * @arg @ref PWR_WAKEUP_FLAG2 : Wakeup flag 2. 294 * Indicates that a wakeup event was received from the WKUP line 2. 295 * @arg @ref PWR_WAKEUP_FLAG3 : Wakeup flag 3. 296 * Indicates that a wakeup event was received from the WKUP line 3. 297 * @arg @ref PWR_WAKEUP_FLAG4 : Wakeup flag 4. 298 * Indicates that a wakeup event was received from the WKUP line 4. 299 * @arg @ref PWR_WAKEUP_FLAG5 : Wakeup flag 5. 300 * Indicates that a wakeup event was received from the WKUP line 5. 301 * @arg @ref PWR_WAKEUP_FLAG6 : Wakeup flag 6. 302 * Indicates that a wakeup event was received from the WKUP line 6. 303 * @arg @ref PWR_WAKEUP_FLAG7 : Wakeup flag 7. 304 * Indicates that a wakeup event was received from the WKUP line 7. 305 * @arg @ref PWR_WAKEUP_FLAG8 : Wakeup flag 8. 306 * Indicates that a wakeup event was received from the WKUP line 8. 307 * @note The PWR_WAKEUP_FLAG6, PWR_WAKEUP_FLAG7 AND PWR_WAKEUP_FLAG8 are not available for STM32H503xx devices. 308 * @retval The state of __FLAG__ (TRUE or FALSE). 309 */ 310 #if defined (PWR_WUSR_WUF6) 311 #define __HAL_PWR_GET_FLAG(__FLAG__) \ 312 (((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->PMSR, PWR_PMSR_STOPF) == PWR_PMSR_STOPF) : \ 313 ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->PMSR, PWR_PMSR_SBF) == PWR_PMSR_SBF) : \ 314 ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSSR, PWR_VOSSR_VOSRDY) == PWR_VOSSR_VOSRDY) : \ 315 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? (READ_BIT(PWR->VOSSR, PWR_VOSSR_ACTVOSRDY) == PWR_VOSSR_ACTVOSRDY) : \ 316 ((__FLAG__) == PWR_FLAG_BRR) ? (READ_BIT(PWR->BDSR, PWR_BDSR_BRRDY) == PWR_BDSR_BRRDY) : \ 317 ((__FLAG__) == PWR_FLAG_VBATL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATL) == PWR_BDSR_VBATL) : \ 318 ((__FLAG__) == PWR_FLAG_VBATH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == PWR_BDSR_VBATH) : \ 319 ((__FLAG__) == PWR_FLAG_TEMPL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == PWR_BDSR_TEMPL) : \ 320 ((__FLAG__) == PWR_FLAG_TEMPH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == PWR_BDSR_TEMPH) : \ 321 ((__FLAG__) == PWR_FLAG_AVDO) ? (READ_BIT(PWR->VMSR, PWR_VMSR_AVDO) == PWR_VMSR_AVDO) : \ 322 ((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? (READ_BIT(PWR->VMSR, PWR_VMSR_VDDIO2RDY) == PWR_VMSR_VDDIO2RDY) : \ 323 ((__FLAG__) == PWR_FLAG_PVDO) ? (READ_BIT(PWR->VMSR, PWR_VMSR_PVDO) == PWR_VMSR_PVDO) : \ 324 ((__FLAG__) == PWR_FLAG_USB33RDY) ? (READ_BIT(PWR->VMSR, PWR_VMSR_USB33RDY) == PWR_VMSR_USB33RDY) : \ 325 ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == PWR_WUSR_WUF1) : \ 326 ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == PWR_WUSR_WUF2) : \ 327 ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == PWR_WUSR_WUF3) : \ 328 ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == PWR_WUSR_WUF4) : \ 329 ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == PWR_WUSR_WUF5) : \ 330 ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == PWR_WUSR_WUF6) : \ 331 ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == PWR_WUSR_WUF7) : \ 332 (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) 333 #else 334 #define __HAL_PWR_GET_FLAG(__FLAG__) \ 335 (((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->PMSR, PWR_PMSR_STOPF) == PWR_PMSR_STOPF) : \ 336 ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->PMSR, PWR_PMSR_SBF) == PWR_PMSR_SBF) : \ 337 ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSSR, PWR_VOSSR_VOSRDY) == PWR_VOSSR_VOSRDY) : \ 338 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? (READ_BIT(PWR->VOSSR, PWR_VOSSR_ACTVOSRDY) == PWR_VOSSR_ACTVOSRDY) : \ 339 ((__FLAG__) == PWR_FLAG_BRR) ? (READ_BIT(PWR->BDSR, PWR_BDSR_BRRDY) == PWR_BDSR_BRRDY) : \ 340 ((__FLAG__) == PWR_FLAG_VBATL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATL) == PWR_BDSR_VBATL) : \ 341 ((__FLAG__) == PWR_FLAG_VBATH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == PWR_BDSR_VBATH) : \ 342 ((__FLAG__) == PWR_FLAG_TEMPL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == PWR_BDSR_TEMPL) : \ 343 ((__FLAG__) == PWR_FLAG_TEMPH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == PWR_BDSR_TEMPH) : \ 344 ((__FLAG__) == PWR_FLAG_AVDO) ? (READ_BIT(PWR->VMSR, PWR_VMSR_AVDO) == PWR_VMSR_AVDO) : \ 345 ((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? (READ_BIT(PWR->VMSR, PWR_VMSR_VDDIO2RDY) == PWR_VMSR_VDDIO2RDY) : \ 346 ((__FLAG__) == PWR_FLAG_PVDO) ? (READ_BIT(PWR->VMSR, PWR_VMSR_PVDO) == PWR_VMSR_PVDO) : \ 347 ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == PWR_WUSR_WUF1) : \ 348 ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == PWR_WUSR_WUF2) : \ 349 ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == PWR_WUSR_WUF3) : \ 350 ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == PWR_WUSR_WUF4) : \ 351 (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == PWR_WUSR_WUF5)) 352 #endif /* PWR_WUSR_WUF6 */ 353 354 /** @brief Clear PWR flags. 355 * @param __FLAG__ : Specifies the flag to clear. 356 * This parameter can be one of the following values : 357 * @arg @ref PWR_FLAG_STOPF : STOP flag. 358 * Indicates that the device was resumed from STOP mode. 359 * @arg @ref PWR_FLAG_STANDBY : STANDBY flag. 360 * Indicates that the device was resumed from STANDBY mode. 361 * @arg @ref PWR_WAKEUP_FLAG1 : Wakeup flag 1. 362 * Indicates that a wakeup event was received from the WKUP line 1. 363 * @arg @ref PWR_WAKEUP_FLAG2 : Wakeup flag 2. 364 * Indicates that a wakeup event was received from the WKUP line 2. 365 * @arg @ref PWR_WAKEUP_FLAG3 : Wakeup flag 3. 366 * Indicates that a wakeup event was received from the WKUP line 3. 367 * @arg @ref PWR_WAKEUP_FLAG4 : Wakeup flag 4. 368 * Indicates that a wakeup event was received from the WKUP line 4. 369 * @arg @ref PWR_WAKEUP_FLAG5 : Wakeup flag 5. 370 * Indicates that a wakeup event was received from the WKUP line 5. 371 * @arg @ref PWR_WAKEUP_FLAG6 : Wakeup flag 6. 372 * Indicates that a wakeup event was received from the WKUP line 6. 373 * @arg @ref PWR_WAKEUP_FLAG7 : Wakeup flag 7. 374 * Indicates that a wakeup event was received from the WKUP line 7. 375 * @arg @ref PWR_WAKEUP_FLAG8 : Wakeup flag 8. 376 * Indicates that a wakeup event was received from the WKUP line 8. 377 * @note The PWR_WAKEUP_FLAG6, PWR_WAKEUP_FLAG7 AND PWR_WAKEUP_FLAG8 are not available for STM32H503xx devices. 378 * @retval None. 379 */ 380 #if defined (PWR_WUSCR_CWUF6) 381 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) \ 382 (((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->PMCR, PWR_PMCR_CSSF)) : \ 383 ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->PMCR, PWR_PMCR_CSSF)) : \ 384 ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1)) : \ 385 ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2)) : \ 386 ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3)) : \ 387 ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4)) : \ 388 ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5)) : \ 389 ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6)) : \ 390 ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7)) : \ 391 ((__FLAG__) == PWR_WAKEUP_FLAG8) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8)) : \ 392 (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF))) 393 #else 394 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) \ 395 (((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->PMCR, PWR_PMCR_CSSF)) : \ 396 ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->PMCR, PWR_PMCR_CSSF)) : \ 397 ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1)) : \ 398 ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2)) : \ 399 ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3)) : \ 400 ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4)) : \ 401 ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5)) : \ 402 (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF))) 403 #endif /* PWR_WUSCR_CWUF6 */ 404 405 /** 406 * @brief Enable the PVD Extended Interrupt Line. 407 * @retval None. 408 */ 409 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) 410 411 /** 412 * @brief Disable the PVD Extended Interrupt Line. 413 * @retval None. 414 */ 415 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) 416 417 /** 418 * @brief Enable the PVD Event Line. 419 * @retval None. 420 */ 421 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) 422 423 /** 424 * @brief Disable the PVD Event Line. 425 * @retval None. 426 */ 427 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) 428 429 /** 430 * @brief Enable the PVD Extended Interrupt Rising Trigger. 431 * @retval None. 432 */ 433 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) 434 435 /** 436 * @brief Disable the PVD Extended Interrupt Rising Trigger. 437 * @retval None. 438 */ 439 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) 440 441 /** 442 * @brief Enable the PVD Extended Interrupt Falling Trigger. 443 * @retval None. 444 */ 445 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) 446 447 /** 448 * @brief Disable the PVD Extended Interrupt Falling Trigger. 449 * @retval None. 450 */ 451 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) 452 453 /** 454 * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. 455 * @retval None. 456 */ 457 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ 458 do \ 459 { \ 460 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ 461 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ 462 } while(0) 463 464 /** 465 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. 466 * @retval None. 467 */ 468 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ 469 do \ 470 { \ 471 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ 472 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ 473 } while(0) 474 475 /** 476 * @brief Generate a Software Interrupt on selected EXTI line. 477 * @retval None 478 */ 479 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) 480 481 /** 482 * @brief Check whether the specified PVD EXTI Rising interrupt flag is set or not. 483 * @retval EXTI PVD Line Status. 484 */ 485 #define __HAL_PWR_PVD_EXTI_GET_RISING_FLAG() \ 486 ((READ_BIT(EXTI->RPR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) 487 488 /** 489 * @brief Check whether the specified PVD EXTI Falling interrupt flag is set or not. 490 * @retval EXTI PVD Line Status. 491 */ 492 #define __HAL_PWR_PVD_EXTI_GET_FALLING_FLAG()\ 493 ((READ_BIT(EXTI->FPR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) 494 495 /** 496 * @brief Clear the PVD EXTI Interrupt Rising flag. 497 * @retval None. 498 */ 499 #define __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD); 500 501 /** 502 * @brief Clear the PVD EXTI Interrupt Falling flag. 503 * @retval None. 504 */ 505 #define __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD); 506 507 /** 508 * @brief Clear the PVD EXTI Interrupt flag. 509 * @retval None. 510 */ 511 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() \ 512 do \ 513 { \ 514 WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD); \ 515 WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD); \ 516 } while(0) 517 /** 518 * @} 519 */ 520 521 /* Private constants ---------------------------------------------------------*/ 522 523 /** @addtogroup PWR_Private_Constants PWR Private Constants 524 * @{ 525 */ 526 /* Define PVD extended interrupts and event line */ 527 #define PWR_EXTI_LINE_PVD EXTI_IMR1_IM16 /*!< PVD EXTI Line */ 528 529 /* Defines wake up lines shift */ 530 #define PWR_EWUP_MASK (0x0FFF3F3FU) 531 532 /* Defines attribute */ 533 #define PWR_ITEM_ATTR_NSEC_PRIV_MASK (0x10U) /*!< NSecure Privilege / NPrivilege attribute item mask */ 534 #define PWR_ITEM_ATTR_SEC_PRIV_MASK (0x20U) /*!< Secure Privilege / NPrivilege attribute item mask */ 535 /** 536 * @} 537 */ 538 539 /* Private macros ------------------------------------------------------------*/ 540 541 /** @addtogroup PWR_Private_Macros PWR Private Macros 542 * @{ 543 */ 544 #if defined(PWR_WUCR_WUPEN6) 545 /* Check wake up pin parameter */ 546 #define IS_PWR_WAKEUP_PIN(PIN) \ 547 (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) ||\ 548 ((PIN) == PWR_WAKEUP_PIN3) || ((PIN) == PWR_WAKEUP_PIN4) ||\ 549 ((PIN) == PWR_WAKEUP_PIN5) || ((PIN) == PWR_WAKEUP_PIN6) ||\ 550 ((PIN) == PWR_WAKEUP_PIN7) || ((PIN) == PWR_WAKEUP_PIN8) ||\ 551 ((PIN) == PWR_WAKEUP_PIN1_HIGH) || ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ 552 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ 553 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\ 554 ((PIN) == PWR_WAKEUP_PIN7_HIGH) || ((PIN) == PWR_WAKEUP_PIN8_HIGH) ||\ 555 ((PIN) == PWR_WAKEUP_PIN1_LOW) || ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ 556 ((PIN) == PWR_WAKEUP_PIN3_LOW) || ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ 557 ((PIN) == PWR_WAKEUP_PIN5_LOW) || ((PIN) == PWR_WAKEUP_PIN6_LOW) ||\ 558 ((PIN) == PWR_WAKEUP_PIN7_LOW) || ((PIN) == PWR_WAKEUP_PIN8_LOW)) 559 #else 560 /* Check wake up pin parameter */ 561 #define IS_PWR_WAKEUP_PIN(PIN) \ 562 (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) ||\ 563 ((PIN) == PWR_WAKEUP_PIN3) || ((PIN) == PWR_WAKEUP_PIN4) ||\ 564 ((PIN) == PWR_WAKEUP_PIN5) || ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ 565 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\ 566 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\ 567 ((PIN) == PWR_WAKEUP_PIN1_LOW) || ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ 568 ((PIN) == PWR_WAKEUP_PIN3_LOW) || ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ 569 ((PIN) == PWR_WAKEUP_PIN5_LOW)) 570 #endif /* PWR_WUCR_WUPEN6 */ 571 572 /* PVD level check macro */ 573 #define IS_PWR_PVD_LEVEL(LEVEL) \ 574 (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) ||\ 575 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) ||\ 576 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) ||\ 577 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) 578 579 /* PVD mode check macro */ 580 #define IS_PWR_PVD_MODE(MODE) \ 581 (((MODE) == PWR_PVD_MODE_NORMAL) ||\ 582 ((MODE) == PWR_PVD_MODE_IT_RISING) ||\ 583 ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ 584 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ 585 ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ 586 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ 587 ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) 588 589 /* SLEEP mode entry check macro */ 590 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) 591 592 /* STOP mode entry check macro */ 593 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) 594 595 #if defined (PWR_SECCFGR_WUP1SEC) 596 /* PWR items check macro */ 597 #define IS_PWR_ITEMS_ATTRIBUTES(ITEM) ((((ITEM) & (~PWR_ALL)) == 0U) && ((ITEM) != 0U)) 598 #endif /* PWR_SECCFGR_WUP1SEC */ 599 600 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 601 /* PWR attribute check macro (Secure) */ 602 #define IS_PWR_ATTRIBUTES(ATTRIBUTES) \ 603 ((((~(((ATTRIBUTES) & 0xF0U) >> 4U)) &((ATTRIBUTES) & 0x0FU)) == 0U) && (((ATTRIBUTES) & 0xFFFFFFCCU) == 0U)) 604 #elif defined(PWR_PRIVCFGR_NSPRIV) 605 /* PWR attribute check macro (NSecure) */ 606 #define IS_PWR_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == PWR_NSEC_NPRIV) || ((ATTRIBUTES) == PWR_NSEC_PRIV)) 607 #else 608 /* PWR attribute check macro (NSecure) */ 609 #define IS_PWR_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == PWR_NPRIV) || ((ATTRIBUTES) == PWR_PRIV)) 610 #endif /* __ARM_FEATURE_CMSE */ 611 /** 612 * @} 613 */ 614 615 /* Include PWR HAL Extended module */ 616 #include "stm32h5xx_hal_pwr_ex.h" 617 618 /* Exported functions --------------------------------------------------------*/ 619 620 /** @addtogroup PWR_Exported_Functions PWR Exported Functions 621 * @{ 622 */ 623 624 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions 625 * @{ 626 */ 627 /* Initialization and de-initialization functions *****************************/ 628 void HAL_PWR_DeInit(void); 629 void HAL_PWR_EnableBkUpAccess(void); 630 void HAL_PWR_DisableBkUpAccess(void); 631 /** 632 * @} 633 */ 634 635 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 636 * @{ 637 */ 638 /* Programmable voltage detector functions ************************************/ 639 HAL_StatusTypeDef HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *sConfigPVD); 640 void HAL_PWR_EnablePVD(void); 641 void HAL_PWR_DisablePVD(void); 642 643 /* Wake up pins configuration functions ***************************************/ 644 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); 645 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); 646 647 /* Low power modes configuration functions ************************************/ 648 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); 649 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); 650 void HAL_PWR_EnterSTANDBYMode(void); 651 652 /* Sleep on exit and sev on pending configuration functions *******************/ 653 void HAL_PWR_EnableSleepOnExit(void); 654 void HAL_PWR_DisableSleepOnExit(void); 655 void HAL_PWR_EnableSEVOnPend(void); 656 void HAL_PWR_DisableSEVOnPend(void); 657 658 /* Interrupt handler functions ************************************************/ 659 void HAL_PWR_PVD_IRQHandler(void); 660 void HAL_PWR_PVDCallback(void); 661 /** 662 * @} 663 */ 664 665 /** @addtogroup PWR_Exported_Functions_Group3 Peripheral Security functions 666 * @{ 667 */ 668 /* Privileges and security configuration functions ****************************/ 669 void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes); 670 HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 671 /** 672 * @} 673 */ 674 675 /** 676 * @} 677 */ 678 679 /** 680 * @} 681 */ 682 683 /** 684 * @} 685 */ 686 687 /** 688 * @} 689 */ 690 691 #ifdef __cplusplus 692 } 693 #endif /* __cplusplus */ 694 695 #endif /* STM32H5xx_HAL_PWR_H */ 696
