1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_hcd.h
4 * @author MCD Application Team
5 * @brief Header file of HCD HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H5xx_HAL_HCD_H
21 #define STM32H5xx_HAL_HCD_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h5xx_ll_usb.h"
29
30 #if defined (USB_DRD_FS)
31 /** @addtogroup STM32H5xx_HAL_Driver
32 * @{
33 */
34
35 /** @addtogroup HCD HCD
36 * @{
37 */
38
39 /* Exported types ------------------------------------------------------------*/
40 /** @defgroup HCD_Exported_Types HCD Exported Types
41 * @{
42 */
43
44 /** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
45 * @{
46 */
47 typedef enum
48 {
49 HAL_HCD_STATE_RESET = 0x00,
50 HAL_HCD_STATE_READY = 0x01,
51 HAL_HCD_STATE_ERROR = 0x02,
52 HAL_HCD_STATE_BUSY = 0x03,
53 HAL_HCD_STATE_TIMEOUT = 0x04
54 } HCD_StateTypeDef;
55
56 typedef USB_DRD_TypeDef HCD_TypeDef;
57 typedef USB_DRD_CfgTypeDef HCD_InitTypeDef;
58 typedef USB_DRD_HCTypeDef HCD_HCTypeDef;
59 typedef USB_DRD_URBStateTypeDef HCD_URBStateTypeDef;
60 typedef USB_DRD_HCStateTypeDef HCD_HCStateTypeDef;
61
62 typedef enum
63 {
64 HCD_HCD_STATE_DISCONNECTED = 0x00U,
65 HCD_HCD_STATE_CONNECTED = 0x01U,
66 HCD_HCD_STATE_RESETED = 0x02U,
67 HCD_HCD_STATE_RUN = 0x03U,
68 HCD_HCD_STATE_SUSPEND = 0x04U,
69 HCD_HCD_STATE_RESUME = 0x05U,
70 } HCD_HostStateTypeDef;
71
72 /* PMA lookup Table size depending on PMA Size
73 * 8Bytes each Block 32Bit in each word
74 */
75 #define PMA_BLOCKS ((USB_DRD_PMA_SIZE) / (8U * 32U))
76
77 /**
78 * @}
79 */
80
81 /** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
82 * @{
83 */
84 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
85 typedef struct __HCD_HandleTypeDef
86 #else
87 typedef struct
88 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
89 {
90 HCD_TypeDef *Instance; /*!< Register base address */
91 HCD_InitTypeDef Init; /*!< HCD required parameters */
92 HCD_HCTypeDef hc[16]; /*!< Host channels parameters */
93
94 uint32_t ep0_PmaAllocState; /*!< EP0 PMA allocation State (allocated, virtual Ch, EP0 direction) */
95 uint16_t phy_chin_state[8]; /*!< Physical Channel in State (Used/Free) */
96 uint16_t phy_chout_state[8]; /*!< Physical Channel out State (Used/Free)*/
97 uint32_t PMALookupTable[PMA_BLOCKS]; /*PMA LookUp Table */
98 HCD_HostStateTypeDef HostState; /*!< USB current state DICONNECT/CONNECT/RUN/SUSPEND/RESUME */
99
100 HAL_LockTypeDef Lock; /*!< HCD peripheral status */
101 __IO HCD_StateTypeDef State; /*!< HCD communication state */
102 __IO uint32_t ErrorCode; /*!< HCD Error code */
103 void *pData; /*!< Pointer Stack Handler */
104 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
105 void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */
106 void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */
107 void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */
108 void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */
109 void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */
110 void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,
111 HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */
112
113 void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */
114 void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */
115 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
116 } HCD_HandleTypeDef;
117 /**
118 * @}
119 */
120
121 /**
122 * @}
123 */
124
125 /* Exported constants --------------------------------------------------------*/
126 /** @defgroup HCD_Exported_Constants HCD Exported Constants
127 * @{
128 */
129
130 /** @defgroup HCD_Speed HCD Speed
131 * @{
132 */
133 #define HCD_SPEED_FULL USBH_FSLS_SPEED
134 #define HCD_SPEED_LOW USBH_FSLS_SPEED
135 /**
136 * @}
137 */
138
139 /** @defgroup HCD_Device_Speed HCD Device Speed
140 * @{
141 */
142 #define HCD_DEVICE_SPEED_HIGH 0U
143 #define HCD_DEVICE_SPEED_FULL 1U
144 #define HCD_DEVICE_SPEED_LOW 2U
145 /**
146 * @}
147 */
148
149 /** @defgroup HCD_PHY_Module HCD PHY Module
150 * @{
151 */
152 #define HCD_PHY_ULPI 1U
153 #define HCD_PHY_EMBEDDED 2U
154 /**
155 * @}
156 */
157
158 /** @defgroup HCD_Error_Code_definition HCD Error Code definition
159 * @brief HCD Error Code definition
160 * @{
161 */
162 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
163 #define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
164 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
165
166 /**
167 * @}
168 */
169
170 /**
171 * @}
172 */
173
174 /* Exported macro ------------------------------------------------------------*/
175 /** @defgroup HCD_Exported_Macros HCD Exported Macros
176 * @brief macros to handle interrupts and specific clock configurations
177 * @{
178 */
179 #define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
180 #define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
181
182 #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
183 & (__INTERRUPT__)) == (__INTERRUPT__))
184 #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
185 #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
186
187 #define __HAL_HCD_GET_CHNUM(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_IDN)
188 #define __HAL_HCD_GET_CHDIR(__HANDLE__) (((__HANDLE__)->Instance->ISTR) & USB_ISTR_DIR)
189 /**
190 * @}
191 */
192
193 /* Exported functions --------------------------------------------------------*/
194 /** @addtogroup HCD_Exported_Functions HCD Exported Functions
195 * @{
196 */
197
198 /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
199 * @{
200 */
201 HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
202 HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);
203 HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
204 uint8_t epnum, uint8_t dev_address,
205 uint8_t speed, uint8_t ep_type, uint16_t mps);
206
207 HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
208
209 HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
210
211 void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
212 void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
213
214 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
215 /** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
216 * @brief HAL USB OTG HCD Callback ID enumeration definition
217 * @{
218 */
219 typedef enum
220 {
221 HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
222 HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
223 HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
224 HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
225 HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
226
227 HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
228 HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
229
230 } HAL_HCD_CallbackIDTypeDef;
231 /**
232 * @}
233 */
234
235 /** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
236 * @brief HAL USB OTG HCD Callback pointer definition
237 * @{
238 */
239
240 typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */
241 typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
242 uint8_t epnum,
243 HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */
244 /**
245 * @}
246 */
247
248 HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
249 HAL_HCD_CallbackIDTypeDef CallbackID,
250 pHCD_CallbackTypeDef pCallback);
251
252 HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd,
253 HAL_HCD_CallbackIDTypeDef CallbackID);
254
255 HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
256 pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
257
258 HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
259 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
260 /**
261 * @}
262 */
263
264 /* I/O operation functions ***************************************************/
265 /** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
266 * @{
267 */
268 HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
269 uint8_t direction, uint8_t ep_type,
270 uint8_t token, uint8_t *pbuff,
271 uint16_t length, uint8_t do_ping);
272
273 /* Non-Blocking mode: Interrupt */
274 void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
275 void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
276 void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
277 void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
278 void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
279 void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
280
281 void HAL_HCD_SuspendCallback(HCD_HandleTypeDef *hhcd);
282 void HAL_HCD_ResumeCallback(HCD_HandleTypeDef *hhcd);
283
284 void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum,
285 HCD_URBStateTypeDef urb_state);
286 /**
287 * @}
288 */
289
290 /* Peripheral Control functions **********************************************/
291 /** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
292 * @{
293 */
294 HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
295 HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
296 HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
297
298 HAL_StatusTypeDef HAL_HCD_Suspend(HCD_HandleTypeDef *hhcd);
299 HAL_StatusTypeDef HAL_HCD_Resume(HCD_HandleTypeDef *hhcd);
300 HAL_StatusTypeDef HAL_HCD_ResumePort(HCD_HandleTypeDef *hhcd);
301
302 /**
303 * @}
304 */
305
306 /* Peripheral State functions ************************************************/
307 /** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
308 * @{
309 */
310 HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
311 HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
312 HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
313 uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
314 uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
315 uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
316
317
318 /* PMA Allocation functions **********************************************/
319 /** @addtogroup PMA Allocation
320 * @{
321 */
322 HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
323 uint16_t ch_kind, uint16_t mps);
324
325 HAL_StatusTypeDef HAL_HCD_PMADeAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
326 HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd);
327
328 /**
329 * @}
330 */
331
332
333 /**
334 * @}
335 */
336
337 /* Private macros ------------------------------------------------------------*/
338 /** @defgroup HCD_Private_Macros HCD Private Macros
339 * @{
340 */
341
342 #define HCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
343 #define HCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
344
345 /** @defgroup HCD_LOGICAL_CHANNEL HCD Logical Channel
346 * @{
347 */
348 #define HCD_LOGICAL_CH_NOT_OPENED 0xFFU
349 #define HCD_FREE_CH_NOT_FOUND 0xFFU
350 /**
351 * @}
352 */
353
354 /** @defgroup HCD_ENDP_Kind HCD Endpoint Kind
355 * @{
356 */
357 #define HCD_SNG_BUF 0U
358 #define HCD_DBL_BUF 1U
359 /**
360 * @}
361 */
362
363 /* Set Channel */
364 #define HCD_SET_CHANNEL USB_DRD_SET_CHEP
365
366 /* Get Channel Register */
367 #define HCD_GET_CHANNEL USB_DRD_GET_CHEP
368
369
370 /**
371 * @brief free buffer used from the application realizing it to the line
372 * toggles bit SW_BUF in the double buffered endpoint register
373 * @param USBx USB device.
374 * @param bChNum, bDir
375 * @retval None
376 */
377 #define HCD_FREE_USER_BUFFER USB_DRD_FREE_USER_BUFFER
378
379 /**
380 * @brief Set the Setup bit in the corresponding channel, when a Setup
381 transaction is needed.
382 * @param USBx USB device.
383 * @param bChNum
384 * @retval None
385 */
386 #define HAC_SET_CH_TX_SETUP USB_DRD_CHEP_TX_SETUP
387
388 /**
389 * @brief sets the status for tx transfer (bits STAT_TX[1:0]).
390 * @param USBx USB peripheral instance register address.
391 * @param bChNum Endpoint Number.
392 * @param wState new state
393 * @retval None
394 */
395 #define HCD_SET_CH_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS
396
397 /**
398 * @brief sets the status for rx transfer (bits STAT_TX[1:0])
399 * @param USBx USB peripheral instance register address.
400 * @param bChNum Endpoint Number.
401 * @param wState new state
402 * @retval None
403 */
404 #define HCD_SET_CH_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS
405 /**
406 * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
407 * /STAT_RX[1:0])
408 * @param USBx USB peripheral instance register address.
409 * @param bChNum Endpoint Number.
410 * @retval status
411 */
412 #define HCD_GET_CH_TX_STATUS USB_DRD_GET_CHEP_TX_STATUS
413 #define HCD_GET_CH_RX_STATUS USB_DRD_GET_CHEP_RX_STATUS
414 /**
415 * @brief Sets/clears CH_KIND bit in the Channel register.
416 * @param USBx USB peripheral instance register address.
417 * @param bChNum Endpoint Number.
418 * @retval None
419 */
420 #define HCD_SET_CH_KIND USB_DRD_SET_CH_KIND
421 #define HCD_CLEAR_CH_KIND USB_DRD_CLEAR_CH_KIND
422 #define HCD_SET_BULK_CH_DBUF HCD_SET_CH_KIND
423 #define HCD_CLEAR_BULK_CH_DBUF HCD_CLEAR_CH_KIND
424
425 /**
426 * @brief Clears bit ERR_RX in the Channel register
427 * @param USBx USB peripheral instance register address.
428 * @param bChNum Endpoint Number.
429 * @retval None
430 */
431 #define HCD_CLEAR_RX_CH_ERR USB_DRD_CLEAR_CHEP_RX_ERR
432
433 /**
434 * @brief Clears bit ERR_TX in the Channel register
435 * @param USBx USB peripheral instance register address.
436 * @param bChNum Endpoint Number.
437 * @retval None
438 */
439 #define HCD_CLEAR_TX_CH_ERR USB_DRD_CLEAR_CHEP_TX_ERR
440 /**
441 * @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
442 * @param USBx USB peripheral instance register address.
443 * @param bChNum Endpoint Number.
444 * @retval None
445 */
446 #define HCD_CLEAR_RX_CH_CTR USB_DRD_CLEAR_RX_CHEP_CTR
447 #define HCD_CLEAR_TX_CH_CTR USB_DRD_CLEAR_TX_CHEP_CTR
448
449 /**
450 * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
451 * @param USBx USB peripheral instance register address.
452 * @param bChNum Endpoint Number.
453 * @retval None
454 */
455 #define HCD_RX_DTOG USB_DRD_RX_DTOG
456 #define HCD_TX_DTOG USB_DRD_TX_DTOG
457 /**
458 * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
459 * @param USBx USB peripheral instance register address.
460 * @param bChNum Endpoint Number.
461 * @retval None
462 */
463 #define HCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG
464 #define HCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG
465
466 /**
467 * @brief sets counter for the tx/rx buffer.
468 * @param USBx USB peripheral instance register address.
469 * @param bChNum Endpoint Number.
470 * @param wCount Counter value.
471 * @retval None
472 */
473 #define HCD_SET_CH_TX_CNT USB_DRD_SET_CHEP_TX_CNT
474 #define HCD_SET_CH_RX_CNT USB_DRD_SET_CHEP_RX_CNT
475
476 /**
477 * @brief gets counter of the tx buffer.
478 * @param USBx USB peripheral instance register address.
479 * @param bChNum channel Number.
480 * @retval Counter value
481 */
482 #define HCD_GET_CH_TX_CNT USB_DRD_GET_CHEP_TX_CNT
483
484 /**
485 * @brief gets counter of the rx buffer.
486 * @param Instance USB peripheral instance register address.
487 * @param bChNum channel Number.
488 * @retval Counter value
489 */
HCD_GET_CH_RX_CNT(HCD_TypeDef * Instance,uint16_t bChNum)490 __STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(HCD_TypeDef *Instance, uint16_t bChNum)
491 {
492 uint32_t HostCoreSpeed;
493 __IO uint32_t count = 10U;
494
495 /* Get Host core Speed */
496 HostCoreSpeed = USB_GetHostSpeed(Instance);
497
498 /* Count depends on device LS */
499 if (HostCoreSpeed == USB_DRD_SPEED_LS)
500 {
501 count = (63U * (HAL_RCC_GetHCLKFreq() / 1000000U)) / 100U;
502 }
503
504 if (count > 15U)
505 {
506 count = HCD_MAX(10U, (count - 15U));
507 }
508
509 /* WA: few cycles for RX PMA descriptor to update */
510 while (count > 0U)
511 {
512 count--;
513 }
514
515 return (uint16_t)USB_DRD_GET_CHEP_RX_CNT((Instance), (bChNum));
516 }
517
518 /**
519 * @brief Gets buffer 0/1 address of a double buffer endpoint.
520 * @param USBx USB peripheral instance register address.
521 * @param bChNum Endpoint Number.
522 * @param bDir endpoint dir EP_DBUF_OUT = OUT
523 * EP_DBUF_IN = IN
524 * @param wCount: Counter value
525 * @retval None
526 */
527 #define HCD_SET_CH_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT
528 #define HCD_SET_CH_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT
529 #define HCD_SET_CH_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT
530
531
532 /**
533 * @brief gets counter of the rx buffer0.
534 * @param Instance USB peripheral instance register address.
535 * @param bChNum channel Number.
536 * @retval Counter value
537 */
HCD_GET_CH_DBUF0_CNT(const HCD_TypeDef * Instance,uint16_t bChNum)538 __STATIC_INLINE uint16_t HCD_GET_CH_DBUF0_CNT(const HCD_TypeDef *Instance, uint16_t bChNum)
539 {
540 UNUSED(Instance);
541 __IO uint32_t count = 10U;
542
543 /* WA: few cycles for RX PMA descriptor to update */
544 while (count > 0U)
545 {
546 count--;
547 }
548
549 return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT((Instance), (bChNum));
550 }
551
552 /**
553 * @brief gets counter of the rx buffer1.
554 * @param Instance USB peripheral instance register address.
555 * @param bChNum channel Number.
556 * @retval Counter value
557 */
HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef * Instance,uint16_t bChNum)558 __STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(const HCD_TypeDef *Instance, uint16_t bChNum)
559 {
560 UNUSED(Instance);
561 __IO uint32_t count = 10U;
562
563 /* WA: few cycles for RX PMA descriptor to update */
564 while (count > 0U)
565 {
566 count--;
567 }
568
569 return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bChNum));
570 }
571
572
573 /**
574 * @}
575 */
576 /* Private functions prototypes ----------------------------------------------*/
577
578 /**
579 * @}
580 */
581 /**
582 * @}
583 */
584 /**
585 * @}
586 */
587 #endif /* defined (USB_DRD_FS) */
588
589 #ifdef __cplusplus
590 }
591 #endif
592
593 #endif /* STM32H5xx_HAL_HCD_H */
594
