1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_gtzc.h 4 * @author MCD Application Team 5 * @brief Header file of GTZC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32H5xx_HAL_GTZC_H 20 #define STM32H5xx_HAL_GTZC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32h5xx_hal_def.h" 28 29 /** @addtogroup STM32H5xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup GTZC 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 39 /** @defgroup GTZC_Exported_Types GTZC Exported Types 40 * @{ 41 */ 42 43 /*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */ 44 #define GTZC_MCPBB_NB_VCTR_REG_MAX (32U) 45 #define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX (1U) 46 typedef struct 47 { 48 uint32_t MPCBB_SecConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for 49 a super-block. Each bit corresponds to a block 50 inside the super-block. 0 means non-secure, 51 1 means secure */ 52 uint32_t MPCBB_PrivConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for 53 a super-block. Each bit corresponds to a block 54 inside the super-block. 0 means non-privilege, 55 1 means privilege */ 56 uint32_t MPCBB_LockConfig_array[GTZC_MCPBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of 57 a super-block (32 blocks). 0 means unlocked, 58 1 means locked */ 59 } MPCBB_Attribute_ConfigTypeDef; 60 61 typedef struct 62 { 63 uint32_t SecureRWIllegalMode; /*!< Secure read/write illegal access 64 field. It can be a value of @ref GTZC_MPCBB_SecureRWIllegalMode */ 65 uint32_t InvertSecureState; /*!< Default security state field (can be inverted or not). 66 It can be a value of @ref GTZC_MPCBB_InvertSecureState */ 67 MPCBB_Attribute_ConfigTypeDef AttributeConfig; /*!< MPCBB attribute configuration sub-structure */ 68 } MPCBB_ConfigTypeDef; 69 70 typedef struct 71 { 72 uint32_t AreaId; /*!< Area identifier field. It can be a value of @ref 73 GTZC_MPCWM_AreaId */ 74 uint32_t Offset; /*!< Offset of the watermark area, starting from the selected 75 memory base address. It must aligned on 128KB for FMC 76 and OCTOSPI memories, and on 32-byte for BKPSRAM */ 77 uint32_t Length; /*!< Length of the watermark area, starting from the selected 78 Offset. It must aligned on 128KB for FMC and OCTOSPI 79 memories, and on 32-byte for BKPSRAM */ 80 uint32_t Attribute; /*!< Attributes of the watermark area. It can be a value 81 of @ref GTZC_MPCWM_Attribute */ 82 uint32_t Lock; /*!< Lock of the watermark area. It can be a value 83 of @ref GTZC_MPCWM_Lock */ 84 uint32_t AreaStatus; /*!< Status of the watermark area. It can be set to 85 ENABLE or DISABLE */ 86 } MPCWM_ConfigTypeDef; 87 88 /** 89 * @} 90 */ 91 92 /* Private constants ---------------------------------------------------------*/ 93 94 /** @defgroup GTZC_Private_Constants GTZC Private Constants 95 * @{ 96 */ 97 98 /** @defgroup GTZC_Private_PeriphId_composition GTZC Peripheral identifier composition 99 * @{ 100 */ 101 102 /* composition definition for Peripheral identifier parameter (PeriphId) used in 103 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 104 * functions and also in all HAL_GTZC_TZIC relative functions. 105 * Bitmap Definition 106 * bits[31:28] Field "register". Define the register index a peripheral belongs to. 107 * Each bit is dedicated to a single register. 108 * bit[5] Field "all peripherals". If this bit is set then the PeriphId targets 109 * all peripherals within all registers. 110 * bits[4:0] Field "bit position". Define the bit position within the 111 * register dedicated to the peripheral, value from 0 to 31. 112 */ 113 #define GTZC_PERIPH_REG_SHIFT (28U) 114 #define GTZC_PERIPH_REG (0xF0000000U) 115 #define GTZC1_PERIPH_REG1 (0x00000000U) 116 #define GTZC1_PERIPH_REG2 (0x10000000U) 117 #define GTZC1_PERIPH_REG3 (0x20000000U) 118 #if defined (GTZC_TZIC1) 119 #define GTZC1_PERIPH_REG4 (0x30000000U) 120 #endif /* defined (GTZC_TZIC1) */ 121 #define GTZC_PERIPH_BIT_POSITION (0x0000001FU) 122 123 /** 124 * @} 125 */ 126 127 /** @defgroup GTZC_Private_Attributes_Msk GTZC Attributes Masks 128 * @{ 129 */ 130 #define GTZC_ATTR_SEC_MASK 0x100U 131 #define GTZC_ATTR_PRIV_MASK 0x200U 132 133 /** 134 * @} 135 */ 136 137 /** 138 * @} 139 */ 140 141 /* Exported constants --------------------------------------------------------*/ 142 143 /** @defgroup GTZC_Exported_Constants GTZC Exported Constants 144 * @{ 145 */ 146 147 /** @defgroup GTZC_MPCBB_SecureRWIllegalMode GTZC MPCBB SRWILADIS values 148 * @{ 149 */ 150 151 #define GTZC_MPCBB_SRWILADIS_ENABLE (0U) 152 #define GTZC_MPCBB_SRWILADIS_DISABLE (GTZC_MPCBB_CR_SRWILADIS_Msk) 153 154 /** 155 * @} 156 */ 157 158 /** @defgroup GTZC_MPCBB_InvertSecureState GTZC MPCBB INVSECSTATE values 159 * @{ 160 */ 161 162 #define GTZC_MPCBB_INVSECSTATE_NOT_INVERTED (0U) 163 #define GTZC_MPCBB_INVSECSTATE_INVERTED (GTZC_MPCBB_CR_INVSECSTATE_Msk) 164 165 /** 166 * @} 167 */ 168 169 /** @defgroup GTZC_MPCWM_AreaId GTZC MPCWM area identifier values 170 * @{ 171 */ 172 173 #define GTZC_TZSC_MPCWM_ID1 (0U) 174 #define GTZC_TZSC_MPCWM_ID2 (1U) 175 176 /** 177 * @} 178 */ 179 180 /** @defgroup GTZC_TZSC_TZIC_PeriphId GTZC TZSC and TZIC Peripheral identifier values 181 * @{ 182 */ 183 #define GTZC_PERIPH_TIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM2_Pos) 184 #define GTZC_PERIPH_TIM3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM3_Pos) 185 #if defined (TIM4) 186 #define GTZC_PERIPH_TIM4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM4_Pos) 187 #endif /* defined (TIM4) */ 188 #if defined (TIM5) 189 #define GTZC_PERIPH_TIM5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM5_Pos) 190 #endif /* defined (TIM5) */ 191 #define GTZC_PERIPH_TIM6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM6_Pos) 192 #define GTZC_PERIPH_TIM7 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM7_Pos) 193 #if defined (TIM12) 194 #define GTZC_PERIPH_TIM12 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM12_Pos) 195 #endif /* defined (TIM12) */ 196 #if defined (TIM13) 197 #define GTZC_PERIPH_TIM13 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM13_Pos) 198 #endif /* defined (TIM13) */ 199 #if defined (TIM14) 200 #define GTZC_PERIPH_TIM14 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM14_Pos) 201 #endif /* defined (TIM14) */ 202 #define GTZC_PERIPH_WWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos) 203 #define GTZC_PERIPH_IWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos) 204 #define GTZC_PERIPH_SPI2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos) 205 #define GTZC_PERIPH_SPI3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_SPI3_Pos) 206 #define GTZC_PERIPH_USART2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos) 207 #define GTZC_PERIPH_USART3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART3_Pos) 208 #if defined (UART4) 209 #define GTZC_PERIPH_UART4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART4_Pos) 210 #endif /* defined (UART4) */ 211 #if defined (UART5) 212 #define GTZC_PERIPH_UART5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART5_Pos) 213 #endif /* defined (UART5) */ 214 #define GTZC_PERIPH_I2C1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C1_Pos) 215 #define GTZC_PERIPH_I2C2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C2_Pos) 216 #define GTZC_PERIPH_I3C1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I3C1_Pos) 217 #define GTZC_PERIPH_CRS (GTZC1_PERIPH_REG1 | GTZC_CFGR1_CRS_Pos) 218 #if defined (USART6) 219 #define GTZC_PERIPH_USART6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART6_Pos) 220 #endif /* defined (USART6) */ 221 #if defined (USART10) 222 #define GTZC_PERIPH_USART10 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART10_Pos) 223 #endif /* defined (USART10) */ 224 #if defined (USART11) 225 #define GTZC_PERIPH_USART11 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART11_Pos) 226 #endif /* defined (USART11) */ 227 #if defined (CEC) 228 #define GTZC_PERIPH_HDMICEC (GTZC1_PERIPH_REG1 | GTZC_CFGR1_HDMICEC_Pos) 229 #endif /* defined (CEC) */ 230 #define GTZC_PERIPH_DAC1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_DAC1_Pos) 231 #if defined (UART7) 232 #define GTZC_PERIPH_UART7 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART7_Pos) 233 #endif /* defined (UART7) */ 234 #if defined (UART8) 235 #define GTZC_PERIPH_UART8 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART8_Pos) 236 #endif /* defined (UART8) */ 237 #if defined (UART9) 238 #define GTZC_PERIPH_UART9 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART9_Pos) 239 #endif /* defined (UART9) */ 240 #if defined (UART12) 241 #define GTZC_PERIPH_UART12 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART12_Pos) 242 #endif /* defined (UART12) */ 243 #define GTZC_PERIPH_DTS (GTZC1_PERIPH_REG1 | GTZC_CFGR1_DTS_Pos) 244 #define GTZC_PERIPH_LPTIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos) 245 246 #define GTZC_PERIPH_FDCAN1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_FDCAN1_Pos) 247 #if defined (FDCAN2) 248 #define GTZC_PERIPH_FDCAN2 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_FDCAN2_Pos) 249 #endif /* defined (FDCAN2) */ 250 #if defined (UCPD1) 251 #define GTZC_PERIPH_UCPD1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_UCPD1_Pos) 252 #endif /* defined (UCPD1) */ 253 #if defined (OPAMP1) 254 #define GTZC_PERIPH_OPAMP (GTZC1_PERIPH_REG2 | GTZC_CFGR2_OPAMP_Pos) 255 #endif /* defined (OPAMP1) */ 256 #if defined (COMP1) 257 #define GTZC_PERIPH_COMP (GTZC1_PERIPH_REG2 | GTZC_CFGR2_COMP_Pos) 258 #endif /* defined (COMP1) */ 259 #define GTZC_PERIPH_TIM1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos) 260 #define GTZC_PERIPH_SPI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos) 261 #if defined (TIM8) 262 #define GTZC_PERIPH_TIM8 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM8_Pos) 263 #endif /* defined (TIM8) */ 264 #define GTZC_PERIPH_USART1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos) 265 #if defined (TIM15) 266 #define GTZC_PERIPH_TIM15 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM15_Pos) 267 #endif /* defined (TIM15) */ 268 #if defined (TIM16) 269 #define GTZC_PERIPH_TIM16 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos) 270 #endif /* defined (TIM16) */ 271 #if defined (TIM17) 272 #define GTZC_PERIPH_TIM17 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos) 273 #endif /* defined (TIM17) */ 274 #if defined (SPI4) 275 #define GTZC_PERIPH_SPI4 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI4_Pos) 276 #endif /* defined (SPI4) */ 277 #if defined (SPI6) 278 #define GTZC_PERIPH_SPI6 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI6_Pos) 279 #endif /* defined (SPI6) */ 280 #if defined (SAI1) 281 #define GTZC_PERIPH_SAI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos) 282 #endif /* defined (SAI1) */ 283 #if defined (SAI2) 284 #define GTZC_PERIPH_SAI2 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI2_Pos) 285 #endif /* defined (SAI2) */ 286 #define GTZC_PERIPH_USB (GTZC1_PERIPH_REG2 | GTZC_CFGR2_USB_Pos) 287 #if defined (SPI5) 288 #define GTZC_PERIPH_SPI5 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI5_Pos) 289 #endif /* defined (SPI5) */ 290 #define GTZC_PERIPH_LPUART1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LPUART1_Pos) 291 #if defined (I2C3) 292 #define GTZC_PERIPH_I2C3 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_I2C3_Pos) 293 #endif /* defined (I2C3) */ 294 #if defined (I2C4) 295 #define GTZC_PERIPH_I2C4 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_I2C4_Pos) 296 #endif /* defined (I2C4) */ 297 #define GTZC_PERIPH_LPTIM1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LPTIM1_Pos) 298 #if defined (LPTIM3) 299 #define GTZC_PERIPH_LPTIM3 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LPTIM3_Pos) 300 #endif /* defined (LPTIM3) */ 301 #if defined (LPTIM4) 302 #define GTZC_PERIPH_LPTIM4 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LPTIM4_Pos) 303 #endif /* defined (LPTIM4) */ 304 #if defined (LPTIM5) 305 #define GTZC_PERIPH_LPTIM5 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LPTIM5_Pos) 306 #endif /* defined (LPTIM5) */ 307 308 #if defined (LPTIM6) 309 #define GTZC_PERIPH_LPTIM6 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_LPTIM6_Pos) 310 #endif /* defined (LPTIM6) */ 311 #define GTZC_PERIPH_VREFBUF (GTZC1_PERIPH_REG3 | GTZC_CFGR3_VREFBUF_Pos) 312 #if defined (I3C2) 313 #define GTZC_PERIPH_I3C2 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_I3C2_Pos) 314 #endif /* defined (I3C2) */ 315 #define GTZC_PERIPH_CRC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos) 316 #if defined (CORDIC) 317 #define GTZC_PERIPH_CORDIC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CORDIC_Pos) 318 #endif /* defined (CORDIC) */ 319 #if defined (FMAC) 320 #define GTZC_PERIPH_FMAC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FMAC_Pos) 321 #endif /* defined (FMAC) */ 322 #if defined (ETH) 323 #define GTZC_PERIPH_ETHERNET (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ETHERNET_Pos) 324 #endif /* defined (ETH) */ 325 #define GTZC_PERIPH_ICACHE_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos) 326 #if defined (DCACHE1) 327 #define GTZC_PERIPH_DCACHE1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE1_REG_Pos) 328 #endif /* defined (DCACHE1) */ 329 #define GTZC_PERIPH_ADC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ADC_Pos) 330 #if defined (DCMI) 331 #define GTZC_PERIPH_DCMI_PSSI (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCMI_PSSI_Pos) 332 #endif /* defined (DCMI) */ 333 #if defined (AES) 334 #define GTZC_PERIPH_AES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_AES_Pos) 335 #endif /* defined (AES) */ 336 #if defined (HASH) 337 #define GTZC_PERIPH_HASH (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos) 338 #endif /* defined (HASH) */ 339 #define GTZC_PERIPH_RNG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos) 340 #if defined (PKA) 341 #define GTZC_PERIPH_PKA (GTZC1_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos) 342 #endif /* defined (PKA) */ 343 #if defined (SAES) 344 #define GTZC_PERIPH_SAES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SAES_Pos) 345 #endif /* defined (SAES) */ 346 #if defined (SDMMC1) 347 #define GTZC_PERIPH_SDMMC1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC1_Pos) 348 #endif /* defined (SDMMC1) */ 349 #if defined (SDMMC2) 350 #define GTZC_PERIPH_SDMMC2 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC2_Pos) 351 #endif /* defined (SDMMC2) */ 352 #if defined (FMC_Bank1_R) 353 #define GTZC_PERIPH_FMC_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FMC_REG_Pos) 354 #endif /* defined (FMC_Bank1_R) */ 355 #if defined (OCTOSPI1) 356 #define GTZC_PERIPH_OCTOSPI1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI1_Pos) 357 #endif /* defined (OCTOSPI1) */ 358 #define GTZC_PERIPH_RAMCFG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos) 359 360 #if defined (GTZC_TZIC1) 361 #define GTZC_PERIPH_GPDMA1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos) 362 #define GTZC_PERIPH_GPDMA2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_GPDMA2_Pos) 363 #define GTZC_PERIPH_FLASH (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos) 364 #define GTZC_PERIPH_FLASH_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos) 365 #define GTZC_PERIPH_OTFDEC2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC2_Pos) 366 #define GTZC_PERIPH_OTFDEC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC1_Pos) 367 #define GTZC_PERIPH_SBS (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SBS_Pos) 368 #define GTZC_PERIPH_RTC (GTZC1_PERIPH_REG4 | GTZC_CFGR4_RTC_Pos) 369 #define GTZC_PERIPH_TAMP (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TAMP_Pos) 370 #define GTZC_PERIPH_PWR (GTZC1_PERIPH_REG4 | GTZC_CFGR4_PWR_Pos) 371 #define GTZC_PERIPH_RCC (GTZC1_PERIPH_REG4 | GTZC_CFGR4_RCC_Pos) 372 #define GTZC_PERIPH_EXTI (GTZC1_PERIPH_REG4 | GTZC_CFGR4_EXTI_Pos) 373 #define GTZC_PERIPH_TZSC (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZSC_Pos) 374 #define GTZC_PERIPH_TZIC (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZIC_Pos) 375 #define GTZC_PERIPH_OCTOSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI1_MEM_Pos) 376 #define GTZC_PERIPH_FMC_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FMC_MEM_Pos) 377 #define GTZC_PERIPH_BKPSRAM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_BKPSRAM_Pos) 378 #define GTZC_PERIPH_SRAM1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM1_Pos) 379 #define GTZC_PERIPH_MPCBB1_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos) 380 #define GTZC_PERIPH_SRAM2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos) 381 #define GTZC_PERIPH_MPCBB2_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos) 382 #define GTZC_PERIPH_SRAM3 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM3_Pos) 383 #define GTZC_PERIPH_MPCBB3_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB3_REG_Pos) 384 #endif /* defined (GTZC_TZIC1) */ 385 386 #define GTZC_PERIPH_ALL (0x00000020U) 387 388 /* Note that two maximum values are also defined here: 389 * - max number of securable AHB/APB peripherals or masters 390 * (used in TZSC sub-block) 391 * - max number of securable and TrustZone-aware AHB/APB peripherals or masters 392 * (used in TZIC sub-block) 393 */ 394 #define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_RAMCFG + 1U)) 395 #if defined (GTZC_TZIC1) 396 #define GTZC_TZIC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_MPCBB3_REG + 1U)) 397 #endif /* defined (GTZC_TZIC1) */ 398 399 /** 400 * @} 401 */ 402 403 /** @defgroup GTZC_TZSC_PeriphAttributes GTZC TZSC peripheral attribute values 404 * @note secure and non-secure attributes are only available from secure state when the system 405 * implement the security (TZEN=1) 406 * @{ 407 */ 408 409 /* user-oriented definitions for attribute parameter (PeriphAttributes) used in 410 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 411 * functions 412 */ 413 #if defined (GTZC_TZIC1) 414 #define GTZC_TZSC_PERIPH_SEC (GTZC_ATTR_SEC_MASK | 0x00000001U) /*!< Secure attribute */ 415 #define GTZC_TZSC_PERIPH_NSEC (GTZC_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure attribute */ 416 #endif /* (GTZC_TZIC1) */ 417 #define GTZC_TZSC_PERIPH_PRIV (GTZC_ATTR_PRIV_MASK | 0x00000002U) /*!< Privilege attribute */ 418 #define GTZC_TZSC_PERIPH_NPRIV (GTZC_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privilege attribute */ 419 420 /** 421 * @} 422 */ 423 424 #if defined (GTZC_TZSC_CR_LCK_Msk) 425 /** @defgroup GTZC_TZSC_Lock GTZC TZSC lock values 426 * @{ 427 */ 428 429 /* user-oriented definitions for HAL_GTZC_TZSC_GetLock() returned value */ 430 #define GTZC_TZSC_LOCK_OFF (0U) 431 #define GTZC_TZSC_LOCK_ON GTZC_TZSC_CR_LCK_Msk 432 433 /** 434 * @} 435 */ 436 #endif /* (GTZC_TZSC_CR_LCK_Msk) */ 437 438 /** @defgroup GTZC_MPCWM_Group GTZC MPCWM values 439 * @{ 440 */ 441 442 /* user-oriented definitions for TZSC_MPCWM */ 443 #define GTZC_TZSC_MPCWM_GRANULARITY_1 0x00020000U /* OCTOSPI & FMC granularity: 128 kbytes */ 444 #define GTZC_TZSC_MPCWM_GRANULARITY_2 0x00000020U /* BKPSRAM granularity: 32 bytes */ 445 446 /** 447 * @} 448 */ 449 450 /** @defgroup GTZC_MPCWM_Lock GTZC MPCWM Lock values 451 * @{ 452 */ 453 454 /* user-oriented definitions for TZSC_MPCWM */ 455 #define GTZC_TZSC_MPCWM_LOCK_OFF (0U) 456 #define GTZC_TZSC_MPCWM_LOCK_ON GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk 457 458 /** 459 * @} 460 */ 461 462 /** @defgroup GTZC_MPCWM_Attribute GTZC MPCWM Attribute values 463 * @{ 464 */ 465 466 /* user-oriented definitions for TZSC_MPCWM */ 467 #define GTZC_TZSC_MPCWM_REGION_NSEC (0U) 468 #define GTZC_TZSC_MPCWM_REGION_SEC (1U) 469 #define GTZC_TZSC_MPCWM_REGION_NPRIV (0U) 470 #define GTZC_TZSC_MPCWM_REGION_PRIV (2U) 471 472 /** 473 * @} 474 */ 475 476 /** @defgroup GTZC_MPCBB_Group GTZC MPCBB values 477 * @{ 478 */ 479 480 /* user-oriented definitions for MPCBB */ 481 #define GTZC_MPCBB_BLOCK_SIZE 0x200U /* 512 Bytes */ 482 #define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 16 KBytes */ 483 #define GTZC_MCPBB_SUPERBLOCK_UNLOCKED (0U) 484 #define GTZC_MCPBB_SUPERBLOCK_LOCKED (1U) 485 486 #define GTZC_MCPBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U) 487 #define GTZC_MCPBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U) 488 #define GTZC_MCPBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U) 489 #define GTZC_MCPBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U) 490 491 /* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */ 492 #define GTZC_MCPBB_LOCK_OFF (0U) 493 #define GTZC_MCPBB_LOCK_ON (1U) 494 495 /** 496 * @} 497 */ 498 499 /** @defgroup GTZC_TZIC_Flag GTZC TZIC flag values 500 * @{ 501 */ 502 503 /* user-oriented definitions for HAL_GTZC_TZIC_GetFlag() flag parameter */ 504 #define GTZC_TZIC_NO_ILA_EVENT (0U) 505 #define GTZC_TZIC_ILA_EVENT_PENDING (1U) 506 507 /** 508 * @} 509 */ 510 511 /** 512 * @} 513 */ 514 515 /* Private macros ------------------------------------------------------------*/ 516 517 /** @defgroup GTZC_Private_Macros GTZC Private Macros 518 * @{ 519 */ 520 521 /* retrieve information to access register for a specific PeriphId */ 522 #define GTZC_GET_REG_INDEX(periph_id)\ 523 (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) 524 525 #define GTZC_GET_PERIPH_POS(periph_id) ((periph_id) & GTZC_PERIPH_BIT_POSITION) 526 527 #if defined (GTZC_TZIC1) 528 #define IS_GTZC_BASE_ADDRESS(mem, address)\ 529 ( ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) || \ 530 ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) ) 531 #else 532 #define IS_GTZC_BASE_ADDRESS(mem, address)\ 533 ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) 534 #endif /* defined (GTZC_TZIC1) */ 535 536 #define GTZC_MEM_SIZE(mem)\ 537 ( mem ## _SIZE ) 538 539 #if defined (GTZC_TZIC1) 540 #define GTZC_BASE_ADDRESS_S(mem)\ 541 ( mem ## _BASE_S ) 542 #endif /* defined (GTZC_TZIC1) */ 543 544 #define GTZC_BASE_ADDRESS_NS(mem)\ 545 ( mem ## _BASE_NS ) 546 547 /** 548 * @} 549 */ 550 551 /* Exported macros -----------------------------------------------------------*/ 552 553 /** @defgroup GTZC_Exported_Macros GTZC Exported Macros 554 * @{ 555 */ 556 557 /* user-oriented macro to get array index of a specific PeriphId 558 * in case of GTZC_PERIPH_ALL usage in the two following functions: 559 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 560 */ 561 #define HAL_GTZC_GET_ARRAY_INDEX(periph_id)\ 562 ( (GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id)) ) 563 564 /** 565 * @} 566 */ 567 568 /* Exported functions --------------------------------------------------------*/ 569 570 /** @addtogroup GTZC_Exported_Functions 571 * @{ 572 */ 573 574 /** @addtogroup GTZC_Exported_Functions_Group1 575 * @brief TZSC Initialization and Configuration functions 576 * @{ 577 */ 578 579 HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, 580 uint32_t PeriphAttributes); 581 HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, 582 uint32_t *PeriphAttributes); 583 584 /** 585 * @} 586 */ 587 588 /** @addtogroup GTZC_Exported_Functions_Group2 589 * @brief MPCWM Initialization and Configuration functions 590 * @{ 591 */ 592 593 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, 594 const MPCWM_ConfigTypeDef *pMPCWM_Desc); 595 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, 596 MPCWM_ConfigTypeDef *pMPCWM_Desc); 597 /** 598 * @} 599 */ 600 601 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 602 603 /** @addtogroup GTZC_Exported_Functions_Group3 604 * @brief TZSC and TZSC-MPCWM Lock functions 605 * @{ 606 */ 607 608 void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance); 609 uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance); 610 611 /** 612 * @} 613 */ 614 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 615 /** @addtogroup GTZC_Exported_Functions_Group4 616 * @brief MPCBB Initialization and Configuration functions 617 * @{ 618 */ 619 620 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, 621 const MPCBB_ConfigTypeDef *pMPCBB_desc); 622 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, 623 MPCBB_ConfigTypeDef *pMPCBB_desc); 624 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, 625 uint32_t NbBlocks, 626 const uint32_t *pMemAttributes); 627 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, 628 uint32_t NbBlocks, 629 uint32_t *pMemAttributes); 630 631 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 632 HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, 633 uint32_t NbSuperBlocks, 634 const uint32_t *pLockAttributes); 635 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, 636 uint32_t NbSuperBlocks, 637 uint32_t *pLockAttributes); 638 HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress); 639 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, 640 uint32_t *pLockState); 641 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 642 643 /** 644 * @} 645 */ 646 647 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 648 649 /** @addtogroup GTZC_Exported_Functions_Group5 650 * @brief TZIC functions 651 * @{ 652 */ 653 654 HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId); 655 HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId); 656 HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag); 657 HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId); 658 659 /** 660 * @} 661 */ 662 663 /** @addtogroup GTZC_Exported_Functions_Group6 664 * @brief IRQ related Functions 665 * @{ 666 */ 667 668 void HAL_GTZC_IRQHandler(void); 669 void HAL_GTZC_TZIC_Callback(uint32_t PeriphId); 670 671 /** 672 * @} 673 */ 674 675 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 676 677 /** 678 * @} 679 */ 680 681 /** 682 * @} 683 */ 684 685 /** 686 * @} 687 */ 688 689 #ifdef __cplusplus 690 } 691 #endif 692 693 #endif /* STM32H5xx_HAL_GTZC_H */ 694
