1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_flash_ex.h 4 * @author MCD Application Team 5 * @brief Header file of FLASH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H5xx_HAL_FLASH_EX_H 21 #define STM32H5xx_HAL_FLASH_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /** @addtogroup STM32H5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FLASHEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief FLASH Erase structure definition 45 */ 46 typedef struct 47 { 48 uint32_t TypeErase; /*!< Mass erase or sector Erase. 49 This parameter can be a value of @ref FLASH_Type_Erase */ 50 51 uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. 52 This parameter can be a value of @ref FLASH_Banks 53 (FLASH_BANK_BOTH should be used only for mass erase) */ 54 55 uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled 56 This parameter can be a value of @ref FLASH_Sectors */ 57 58 uint32_t NbSectors; /*!< Number of sectors to be erased. 59 This parameter can be a value between 1 and (max number of sectors in the bank - 60 value of initial sector)*/ 61 } FLASH_EraseInitTypeDef; 62 63 64 /** 65 * @brief FLASH Option Bytes Program structure definition 66 */ 67 typedef struct 68 { 69 uint32_t OptionType; /*!< Option byte to be configured. 70 This parameter can be a value of @ref FLASH_Option_Type */ 71 72 uint32_t ProductState; /*!< Set the product state. 73 This parameter can be a value of @ref FLASH_OB_Product_State */ 74 75 uint32_t USERType; /*!< Select the User Option Byte(s) to be configured (used for OPTIONBYTE_USER). 76 This parameter can be a combination of @ref FLASH_OB_USER_Type */ 77 78 uint32_t USERConfig; /*!< Value of the User Option Byte (used for OPTIONBYTE_USER). 79 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, 80 @ref FLASH_OB_USER_BORH_EN, @ref FLASH_OB_USER_IWDG_SW, 81 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_nRST_STOP, 82 @ref FLASH_OB_USER_nRST_STANDBY, @ref FLASH_OB_USER_IO_VDD_HSLV, 83 @ref FLASH_OB_USER_IO_VDDIO2_HSLV, @ref FLASH_OB_USER_IWDG_STOP, 84 @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_BOOT_UBE, 85 @ref FLASH_OB_USER_SWAP_BANK */ 86 87 uint32_t USERConfig2; /*!< Value of the User Option Byte (used for OPTIONBYTE_USER). 88 This parameter can be a combination of @ref FLASH_OB_USER_SRAM1_3_RST, 89 @ref FLASH_OB_USER_SRAM2_RST, @ref FLASH_OB_USER_BKPRAM_ECC, 90 @ref FLASH_OB_USER_SRAM3_ECC, @ref FLASH_OB_USER_SRAM2_ECC, 91 @ref FLASH_OB_USER_SRAM1_RST, @ref FLASH_OB_USER_SRAM1_ECC, 92 @ref FLASH_OB_USER_TZEN */ 93 94 uint32_t Banks; /*!< Select banks for WRP , HDP and secure area configuration. 95 This parameter must be a value of @ref FLASH_Banks */ 96 97 uint32_t WRPState; /*!< Write protection activation or deactivation. 98 This parameter can be a value of @ref FLASH_WRP_State */ 99 100 uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. 101 The value of this parameter depend on device used within the same series */ 102 103 uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured: secure or non-secure. 104 This parameter must be a value of @ref FLASH_OB_BOOT_CONFIG enumeration */ 105 106 uint32_t BootAddr; /*!< Boot address (used for OPTIONBYTE_BOOTADDR). 107 This parameter must be a value between 0x0 and 0xFFFFFF00 */ 108 109 uint32_t BootLock; /*!< Configuration of the boot lock (used for OPTIONBYTE_BOOT_LOCK). 110 This parameter must be a value of @ref FLASH_OB_BOOT_LOCK */ 111 112 uint32_t OTPBlockLock; /*!< Specifies the OTP block(s) to be locked. 113 This parameter must be a value of @ref FLASH_OTP_Blocks */ 114 115 uint32_t HDPStartSector; /*!< Start sector of HDP area (used for OPTIONBYTE_HDP). 116 This parameter must be a value between 0 and (max number of sectors in the bank - 1) */ 117 118 uint32_t HDPEndSector; /*!< End sector of HDP area (used for OPTIONBYTE_HDP). 119 This parameter must be a value between 0 and (max number of sectors in the bank - 1) */ 120 121 uint32_t EDATASize; /*!< Specifies the number of Flash high-cycle sectors. 122 This parameter must be a value between 0 and 8 (sectors) */ 123 124 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 125 uint32_t WMSecStartSector; /*!< Start sector of secure area (used for OPTIONBYTE_WMSEC). 126 This parameter must be a value between 0 and (max number of sectors in the bank - 1)*/ 127 uint32_t WMSecEndSector; /*!< End sector of secure area (used for OPTIONBYTE_WMSEC). 128 This parameter must be a value between 0 and (max number of sectors in the bank - 1)*/ 129 #endif /* __ARM_FEATURE_CMSE */ 130 131 } FLASH_OBProgramInitTypeDef; 132 133 /** 134 * @brief FLASHEx Block-based attributes structure definition 135 */ 136 typedef struct 137 { 138 uint32_t Bank; /*!< Selection of the associated bank of Block-based Area. 139 This parameter must be a value of @ref FLASH_Banks */ 140 uint32_t BBAttributesType; /*!< Block-Based Attributes type. 141 This parameter must be a value of @ref FLASH_BB_Attributes 142 */ 143 uint32_t BBAttributes_array[FLASH_BLOCKBASED_NB_REG]; /*!< Each bit specifies the block-based attribute configuration 144 of a sector: 145 0 means sector non-protected, 1 means sector protected. 146 Protection (secure or privilege) depends on 147 BBAttributesType value */ 148 } FLASH_BBAttributesTypeDef; 149 150 /** 151 * @brief FLASHEx Operation structure definition 152 */ 153 typedef struct 154 { 155 uint32_t OperationType; /*!< Flash operation Type. 156 This parameter must be a value of @ref FLASH_Operation_Type */ 157 uint32_t FlashArea; /*!< Flash operation memory area. 158 This parameter must be a value of @ref FLASH_Operation_Area */ 159 uint32_t Address; /*!< Flash operation Address offset. 160 This parameter is given by bank, and must be a value between 0x0 and 0xFFFF0 */ 161 } FLASH_OperationTypeDef; 162 163 /** 164 * @brief FLASH HDP Extension structure definition 165 */ 166 typedef struct 167 { 168 uint32_t Banks; /*!< Selection of the associated bank of HDP Area. 169 This parameter must be a value of @ref FLASH_Banks */ 170 uint32_t NbSectors; /*!< Number of sectors to be HDP extended. 171 This parameter can be a value between 1 and max number of sectors in the bank */ 172 } FLASH_HDPExtensionTypeDef; 173 174 /** 175 * @} 176 */ 177 /* Exported constants --------------------------------------------------------*/ 178 179 /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants 180 * @{ 181 */ 182 183 /** @defgroup FLASH_Type_Erase FLASH Type Erase 184 * @{ 185 */ 186 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 187 #define FLASH_TYPEERASE_SECTORS FLASH_CR_SER /*!< Secure flash sectors 188 erase activation */ 189 #define FLASH_TYPEERASE_SECTORS_NS (FLASH_CR_SER | FLASH_NON_SECURE_MASK) /*!< Non-secure flash 190 sectors erase activation */ 191 #define FLASH_TYPEERASE_MASSERASE (FLASH_CR_BER | FLASH_CR_MER) /*!< Secure flash mass erase 192 activation */ 193 #define FLASH_TYPEERASE_MASSERASE_NS (FLASH_CR_BER | FLASH_CR_MER | FLASH_NON_SECURE_MASK) /*!< Non-secure flash mass 194 erase activation */ 195 #if defined (FLASH_SR_OBKERR) 196 #define FLASH_TYPEERASE_OBK_ALT FLASH_OBKCFGR_ALT_SECT_ERASE /*!< Flash OBK erase 197 activation */ 198 #endif /* FLASH_SR_OBKERR */ 199 #else 200 #define FLASH_TYPEERASE_SECTORS FLASH_CR_SER /*!< Flash sectors erase 201 activation */ 202 #define FLASH_TYPEERASE_MASSERASE (FLASH_CR_BER | FLASH_CR_MER) /*!< Flash mass erase 203 activation */ 204 #if defined (FLASH_SR_OBKERR) 205 #define FLASH_TYPEERASE_OBK_ALT (FLASH_OBKCFGR_ALT_SECT_ERASE | FLASH_NON_SECURE_MASK) /*!< Flash OBK erase 206 activation */ 207 #endif /* FLASH_SR_OBKERR */ 208 #endif /* __ARM_FEATURE_CMSE */ 209 /** 210 * @} 211 */ 212 213 /** @defgroup FLASH_Option_Type FLASH Option Type 214 * @{ 215 */ 216 #define OPTIONBYTE_WRP 0x0001U /*!< WRP option byte configuration */ 217 #define OPTIONBYTE_PROD_STATE 0x0002U /*!< RDP option byte configuration */ 218 #define OPTIONBYTE_USER 0x0004U /*!< USER option byte configuration */ 219 #define OPTIONBYTE_BOOTADDR 0x0008U /*!< BOOT address option byte configuration */ 220 #define OPTIONBYTE_BOOT_LOCK 0x0010U /*!< Boot lock option byte configuration */ 221 #define OPTIONBYTE_OTP_LOCK 0x0020U /*!< OTP Lock option byte configuration */ 222 #define OPTIONBYTE_HDP 0x0040U /*!< Hide Protection area option byte configuration */ 223 #if defined (FLASH_EDATAR_EDATA_EN) 224 #define OPTIONBYTE_EDATA 0x0080U /*!< Flash high-cycle data area option byte configuration */ 225 #endif /* FLASH_EDATAR_EDATA_EN */ 226 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 227 #define OPTIONBYTE_WMSEC 0x0200U /*!< Watermark-based secure area option byte configuration */ 228 #endif /* __ARM_FEATURE_CMSE */ 229 230 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 231 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_PROD_STATE | OPTIONBYTE_USER |\ 232 OPTIONBYTE_BOOTADDR | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_OTP_LOCK |\ 233 OPTIONBYTE_HDP | OPTIONBYTE_EDATA | OPTIONBYTE_WMSEC) /*!< All option 234 byte configuration */ 235 #else 236 #if defined (FLASH_EDATAR_EDATA_EN) 237 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_PROD_STATE | OPTIONBYTE_USER |\ 238 OPTIONBYTE_BOOTADDR | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_OTP_LOCK |\ 239 OPTIONBYTE_HDP | OPTIONBYTE_EDATA) /*!< All option byte configuration */ 240 #else 241 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_PROD_STATE | OPTIONBYTE_USER |\ 242 OPTIONBYTE_BOOTADDR | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_OTP_LOCK |\ 243 OPTIONBYTE_HDP) /*!< All option byte configuration */ 244 #endif /* FLASH_EDATAR_EDATA_EN */ 245 #endif /* __ARM_FEATURE_CMSE */ 246 /** 247 * @} 248 */ 249 250 /** @defgroup FLASH_OB_USER_Type FLASH OB USER Type 251 * @{ 252 */ 253 #define OB_USER_BOR_LEV 0x00000001U /*!< BOR reset Level */ 254 #define OB_USER_BORH_EN 0x00000002U /*!< BOR high enable status */ 255 #define OB_USER_IWDG_SW 0x00000004U /*!< Independent watchdog selection */ 256 #define OB_USER_WWDG_SW 0x00000008U /*!< Window watchdog selection */ 257 #define OB_USER_NRST_STOP 0x00000010U /*!< Reset generated when entering the stop mode */ 258 #define OB_USER_NRST_STDBY 0x00000020U /*!< Reset generated when entering the standby mode */ 259 #define OB_USER_IO_VDD_HSLV 0x00000040U /*!< High speed IO at low voltage configuration bit */ 260 #define OB_USER_IO_VDDIO2_HSLV 0x00000080U /*!< High speed IO2 at low voltage configuration bit */ 261 #define OB_USER_IWDG_STOP 0x00000100U /*!< Independent watchdog counter freeze in stop mode */ 262 #define OB_USER_IWDG_STDBY 0x00000200U /*!< Independent watchdog counter freeze in standby mode */ 263 #if defined (FLASH_OPTSR_BOOT_UBE) 264 #define OB_USER_BOOT_UBE 0x00000400U /*!< Unique Boot entry */ 265 #endif /* FLASH_OPTSR_BOOT_UBE */ 266 #define OB_USER_SWAP_BANK 0x00000800U /*!< Swap banks */ 267 268 #if defined (FLASH_OPTSR2_SRAM1_3_RST) 269 #define OB_USER_SRAM1_3_RST 0x00001000U /*!< SRAM1 and SRAM3 erase upon system reset */ 270 #endif /* FLASH_OPTSR2_SRAM1_3_RST */ 271 #if defined (FLASH_OPTSR2_SRAM1_RST) 272 #define OB_USER_SRAM1_RST 0x00001000U /*!< SRAM1 Erase when system reset */ 273 #endif /* FLASH_OPTSR2_SRAM1_RST */ 274 #define OB_USER_SRAM2_RST 0x00002000U /*!< SRAM2 Erase when system reset */ 275 #define OB_USER_BKPRAM_ECC 0x00004000U /*!< Backup RAM ECC detection and correction enable */ 276 #define OB_USER_SRAM3_ECC 0x00008000U /*!< SRAM3 ECC detection and correction enable */ 277 #define OB_USER_SRAM2_ECC 0x00010000U /*!< SRAM2 ECC detection and correction enable */ 278 #define OB_USER_SRAM1_ECC 0x00020000U /*!< SRAM1 ECC detection and correction enable */ 279 #if defined (FLASH_OPTSR2_TZEN) 280 #define OB_USER_TZEN 0x00080000U /*!< Global TrustZone security enable */ 281 #endif /* FLASH_OPTSR2_TZEN */ 282 283 #if defined (FLASH_OPTSR2_SRAM1_3_RST) && defined (FLASH_OPTSR_BOOT_UBE) 284 #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BORH_EN | OB_USER_IWDG_SW |\ 285 OB_USER_WWDG_SW | OB_USER_NRST_STOP | OB_USER_NRST_STDBY |\ 286 OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | OB_USER_IWDG_STOP |\ 287 OB_USER_IWDG_STDBY | OB_USER_BOOT_UBE | OB_USER_SWAP_BANK |\ 288 OB_USER_SRAM1_3_RST | OB_USER_SRAM2_RST | OB_USER_BKPRAM_ECC |\ 289 OB_USER_SRAM3_ECC | OB_USER_SRAM2_ECC | OB_USER_TZEN) 290 #else 291 #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_BORH_EN | OB_USER_IWDG_SW |\ 292 OB_USER_WWDG_SW | OB_USER_NRST_STOP | OB_USER_NRST_STDBY |\ 293 OB_USER_IO_VDD_HSLV | OB_USER_IO_VDDIO2_HSLV | OB_USER_IWDG_STOP |\ 294 OB_USER_IWDG_STDBY | OB_USER_SWAP_BANK | OB_USER_SRAM1_RST |\ 295 OB_USER_SRAM2_RST | OB_USER_BKPRAM_ECC | OB_USER_SRAM3_ECC |\ 296 OB_USER_SRAM2_ECC | OB_USER_SRAM1_ECC) 297 #endif /* FLASH_OPTSR2_SRAM1_3_RST && FLASH_OPTSR_BOOT_UBE */ 298 /** 299 * @} 300 */ 301 302 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH BOR Reset Level 303 * @{ 304 */ 305 #define OB_BOR_LEVEL_1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level 1 threshold */ 306 #define OB_BOR_LEVEL_2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level 2 threshold */ 307 #define OB_BOR_LEVEL_3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level 3 threshold */ 308 /** 309 * @} 310 */ 311 312 /** @defgroup FLASH_OB_USER_BORH_EN FLASH BOR High Enable Status 313 * @{ 314 */ 315 #define OB_BORH_DISABLE 0x00000000U /*!< BOR high status bit disabled */ 316 #define OB_BORH_ENABLE FLASH_OPTSR_BORH_EN /*!< BOR high status bit enabled */ 317 /** 318 * @} 319 */ 320 321 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type 322 * @{ 323 */ 324 #define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ 325 #define OB_IWDG_SW FLASH_OPTSR_IWDG_SW /*!< Software independent watchdog */ 326 /** 327 * @} 328 */ 329 330 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type 331 * @{ 332 */ 333 #define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ 334 #define OB_WWDG_SW FLASH_OPTSR_WWDG_SW /*!< Software window watchdog */ 335 /** 336 * @} 337 */ 338 339 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes nRST_STOP 340 * @{ 341 */ 342 #define OB_STOP_RST 0x00000000U /*!< Reset generated when entering in stop mode */ 343 #define OB_STOP_NORST FLASH_OPTSR_NRST_STOP /*!< No reset generated when entering in stop mode */ 344 /** 345 * @} 346 */ 347 348 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes nRST_STDBY 349 * @{ 350 */ 351 #define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering in standby mode */ 352 #define OB_STANDBY_NORST FLASH_OPTSR_NRST_STDBY /*!< No reset generated when entering in standby mode */ 353 /** 354 * @} 355 */ 356 357 /** @defgroup FLASH_OB_Product_State FLASH Product State 358 * @{ 359 */ 360 #define OB_PROD_STATE_OPEN (0xEDU << FLASH_OPTSR_PRODUCT_STATE_Pos) 361 #define OB_PROD_STATE_PROVISIONING (0x17U << FLASH_OPTSR_PRODUCT_STATE_Pos) 362 #define OB_PROD_STATE_IROT_PROVISIONED (0x2EU << FLASH_OPTSR_PRODUCT_STATE_Pos) 363 #define OB_PROD_STATE_TZ_CLOSED (0xC6U << FLASH_OPTSR_PRODUCT_STATE_Pos) 364 #define OB_PROD_STATE_CLOSED (0x72U << FLASH_OPTSR_PRODUCT_STATE_Pos) 365 #define OB_PROD_STATE_LOCKED (0x5CU << FLASH_OPTSR_PRODUCT_STATE_Pos) 366 #define OB_PROD_STATE_REGRESSION (0x9AU << FLASH_OPTSR_PRODUCT_STATE_Pos) 367 #define OB_PROD_STATE_NS_REGRESSION (0xA3U << FLASH_OPTSR_PRODUCT_STATE_Pos) 368 /** 369 * @} 370 */ 371 372 /** @defgroup FLASH_OB_USER_IO_VDD_HSLV FLASH Option Bytes VDD IO HSLV 373 * @{ 374 */ 375 #define OB_IO_VDD_HSLV_DISABLE 0x00000000U /*!< High-speed IO at low VDD voltage feature disabled */ 376 #define OB_IO_VDD_HSLV_ENABLE FLASH_OPTSR_IO_VDD_HSLV /*!< High-speed IO at low VDD voltage feature enabled */ 377 /** 378 * @} 379 */ 380 381 /** @defgroup FLASH_OB_USER_IO_VDDIO2_HSLV FLASH Option Bytes VDDIO2 IO HSLV 382 * @{ 383 */ 384 #define OB_IO_VDDIO2_HSLV_DISABLE 0x00000000U /*!< High-speed IO at low VDDIO2 voltage feature 385 disabled */ 386 #define OB_IO_VDDIO2_HSLV_ENABLE FLASH_OPTSR_IO_VDDIO2_HSLV /*!< High-speed IO at low VDDIO2 voltage feature 387 enabled */ 388 /** 389 * @} 390 */ 391 392 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH IWDG Counter Freeze in STOP 393 * @{ 394 */ 395 #define OB_IWDG_STOP_FREEZE 0x00000000U /*!< IWDG counter frozen in STOP mode */ 396 #define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_IWDG_STOP /*!< IWDG counter active in STOP mode */ 397 /** 398 * @} 399 */ 400 401 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH IWDG Counter Freeze in STANDBY 402 * @{ 403 */ 404 #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< IWDG counter frozen in STANDBY mode */ 405 #define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_IWDG_STDBY /*!< IWDG counter active in STANDBY mode */ 406 /** 407 * @} 408 */ 409 410 /** @defgroup FLASH_OB_USER_BOOT_UBE FLASH OB Boot UBE 411 * @{ 412 */ 413 #if defined (FLASH_OPTSR_BOOT_UBE) 414 #define OB_UBE_OEM_IROT (0xB4U << FLASH_OPTSR_BOOT_UBE_Pos) /*!< OEM-iRoT (user flash) selected */ 415 #define OB_UBE_ST_IROT (0xC3U << FLASH_OPTSR_BOOT_UBE_Pos) /*!< ST-iRoT (system flash) selected */ 416 #endif /* FLASH_OPTSR_BOOT_UBE */ 417 /** 418 * @} 419 */ 420 421 /** @defgroup FLASH_OB_USER_SWAP_BANK FLASH OB SWAP BANK 422 * @{ 423 */ 424 #define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank swap disabled */ 425 #define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK /*!< Bank swap enabled */ 426 /** 427 * @} 428 */ 429 430 /** @defgroup FLASH_OB_USER_SRAM1_3_RST FLASH Option Bytes SRAM1_3 Erase On Reset 431 * @{ 432 */ 433 #if defined (FLASH_OPTSR2_SRAM1_3_RST) 434 #define OB_SRAM1_3_RST_ERASE 0x00000000U /*!< SRAM1 and SRAM3 erased when a system reset occurs */ 435 #define OB_SRAM1_3_RST_NOT_ERASE FLASH_OPTSR2_SRAM1_3_RST /*!< SRAM1 and SRAM3 are not erased when a system reset 436 occurs */ 437 #endif /* FLASH_OPTSR2_SRAM1_3_RST */ 438 /** 439 * @} 440 */ 441 442 /** @defgroup FLASH_OB_USER_SRAM1_RST FLASH Option Bytes SRAM1 Erase On Reset 443 * @{ 444 */ 445 #if defined (FLASH_OPTSR2_SRAM1_RST) 446 #define OB_SRAM1_RST_ERASE 0x00000000U /*!< SRAM1 erased when a system reset occurs */ 447 #define OB_SRAM1_RST_NOT_ERASE FLASH_OPTSR2_SRAM1_RST /*!< SRAM1 is not erased when a system reset occurs */ 448 #endif /* FLASH_OPTSR2_SRAM1_RST */ 449 /** 450 * @} 451 */ 452 453 454 /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes SRAM2 Erase On Reset 455 * @{ 456 */ 457 #define OB_SRAM2_RST_ERASE 0x00000000U /*!< SRAM2 erased when a system reset occurs */ 458 #define OB_SRAM2_RST_NOT_ERASE FLASH_OPTSR2_SRAM2_RST /*!< SRAM2 is not erased when a system reset occurs */ 459 /** 460 * @} 461 */ 462 463 /** @defgroup FLASH_OB_USER_BKPRAM_ECC FLASH Option Bytes User BKPRAM ECC check 464 * @{ 465 */ 466 #define OB_BKPRAM_ECC_ENABLE 0x00000000U /*!< BKPRAM ECC check enable */ 467 #define OB_BKPRAM_ECC_DISABLE FLASH_OPTSR2_BKPRAM_ECC /*!< BKPRAM ECC check disable */ 468 /** 469 * @} 470 */ 471 472 /** @defgroup FLASH_OB_USER_SRAM3_ECC FLASH Option Bytes User SRAM3 ECC check 473 * @{ 474 */ 475 #if defined (FLASH_OPTSR2_SRAM3_ECC) 476 #define OB_SRAM3_ECC_ENABLE 0x00000000U /*!< SRAM3 ECC check enable */ 477 #define OB_SRAM3_ECC_DISABLE FLASH_OPTSR2_SRAM3_ECC /*!< SRAM3 ECC check disable */ 478 #endif /* FLASH_OPTSR2_SRAM3_ECC */ 479 /** 480 * @} 481 */ 482 483 /** @defgroup FLASH_OB_USER_SRAM2_ECC FLASH Option Bytes User SRAM2 ECC check 484 * @{ 485 */ 486 #define OB_SRAM2_ECC_ENABLE 0x00000000U /*!< SRAM2 ECC check enable */ 487 #define OB_SRAM2_ECC_DISABLE FLASH_OPTSR2_SRAM2_ECC /*!< SRAM2 ECC check disable */ 488 /** 489 * @} 490 */ 491 492 /** @defgroup FLASH_OB_USER_SRAM1_ECC FLASH Option Bytes User SRAM1 ECC check 493 * @{ 494 */ 495 #if defined (FLASH_OPTSR2_SRAM1_ECC) 496 #define OB_SRAM1_ECC_ENABLE 0x00000000U /*!< SRAM1 ECC check enable */ 497 #define OB_SRAM1_ECC_DISABLE FLASH_OPTSR2_SRAM1_ECC /*!< SRAM1 ECC check disable */ 498 #endif /* FLASH_OPTSR2_SRAM1_ECC */ 499 /** 500 * @} 501 */ 502 503 /** @defgroup FLASH_OB_USER_TZEN FLASH Option Bytes Global TrustZone 504 * @{ 505 */ 506 #if defined (FLASH_OPTSR2_TZEN) 507 #define OB_TZEN_DISABLE (0xC3U << FLASH_OPTSR2_TZEN_Pos) /*!< Global TrustZone security disabled */ 508 #define OB_TZEN_ENABLE (0xB4U << FLASH_OPTSR2_TZEN_Pos) /*!< Global TrustZone security enabled */ 509 #endif /* FLASH_OPTSR2_TZEN */ 510 /** 511 * @} 512 */ 513 514 /** @defgroup FLASH_Banks FLASH Banks 515 * @{ 516 */ 517 #define FLASH_BANK_1 0x00000001U /*!< Bank 1 */ 518 #define FLASH_BANK_2 0x00000002U /*!< Bank 2 */ 519 #define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ 520 /** 521 * @} 522 */ 523 524 /** @defgroup FLASH_OB_Write_Protection_Sectors FLASH Option Bytes Write Protection Sectors 525 * @{ 526 */ 527 #if (FLASH_SECTOR_NB == 128) 528 #define OB_WRP_SECTOR_0TO3 0x00000001U /*!< Write protection of Sector0 to Sector3 */ 529 #define OB_WRP_SECTOR_4TO7 0x00000002U /*!< Write protection of Sector4 to Sector7 */ 530 #define OB_WRP_SECTOR_8TO11 0x00000004U /*!< Write protection of Sector8 to Sector11 */ 531 #define OB_WRP_SECTOR_12TO15 0x00000008U /*!< Write protection of Sector12 to Sector15 */ 532 #define OB_WRP_SECTOR_16TO19 0x00000010U /*!< Write protection of Sector16 to Sector19 */ 533 #define OB_WRP_SECTOR_20TO23 0x00000020U /*!< Write protection of Sector20 to Sector23 */ 534 #define OB_WRP_SECTOR_24TO27 0x00000040U /*!< Write protection of Sector24 to Sector27 */ 535 #define OB_WRP_SECTOR_28TO31 0x00000080U /*!< Write protection of Sector28 to Sector31 */ 536 #define OB_WRP_SECTOR_32TO35 0x00000100U /*!< Write protection of Sector32 to Sector35 */ 537 #define OB_WRP_SECTOR_36TO39 0x00000200U /*!< Write protection of Sector36 to Sector39 */ 538 #define OB_WRP_SECTOR_40TO43 0x00000400U /*!< Write protection of Sector40 to Sector43 */ 539 #define OB_WRP_SECTOR_44TO47 0x00000800U /*!< Write protection of Sector44 to Sector47 */ 540 #define OB_WRP_SECTOR_48TO51 0x00001000U /*!< Write protection of Sector48 to Sector51 */ 541 #define OB_WRP_SECTOR_52TO55 0x00002000U /*!< Write protection of Sector52 to Sector55 */ 542 #define OB_WRP_SECTOR_56TO59 0x00004000U /*!< Write protection of Sector56 to Sector59 */ 543 #define OB_WRP_SECTOR_60TO63 0x00008000U /*!< Write protection of Sector60 to Sector63 */ 544 #define OB_WRP_SECTOR_64TO67 0x00010000U /*!< Write protection of Sector64 to Sector67 */ 545 #define OB_WRP_SECTOR_68TO71 0x00020000U /*!< Write protection of Sector68 to Sector71 */ 546 #define OB_WRP_SECTOR_72TO75 0x00040000U /*!< Write protection of Sector72 to Sector75 */ 547 #define OB_WRP_SECTOR_76TO79 0x00080000U /*!< Write protection of Sector76 to Sector79 */ 548 #define OB_WRP_SECTOR_80TO83 0x00100000U /*!< Write protection of Sector80 to Sector83 */ 549 #define OB_WRP_SECTOR_84TO87 0x00200000U /*!< Write protection of Sector84 to Sector87 */ 550 #define OB_WRP_SECTOR_88TO91 0x00400000U /*!< Write protection of Sector88 to Sector91 */ 551 #define OB_WRP_SECTOR_92TO95 0x00800000U /*!< Write protection of Sector92 to Sector95 */ 552 #define OB_WRP_SECTOR_96TO99 0x01000000U /*!< Write protection of Sector96 to Sector99 */ 553 #define OB_WRP_SECTOR_100TO103 0x02000000U /*!< Write protection of Sector100 to Sector103 */ 554 #define OB_WRP_SECTOR_104TO107 0x04000000U /*!< Write protection of Sector104 to Sector107 */ 555 #define OB_WRP_SECTOR_108TO111 0x08000000U /*!< Write protection of Sector108 to Sector111 */ 556 #define OB_WRP_SECTOR_112TO115 0x10000000U /*!< Write protection of Sector112 to Sector115 */ 557 #define OB_WRP_SECTOR_116TO119 0x20000000U /*!< Write protection of Sector116 to Sector119 */ 558 #define OB_WRP_SECTOR_120TO123 0x40000000U /*!< Write protection of Sector120 to Sector123 */ 559 #define OB_WRP_SECTOR_124TO127 0x80000000U /*!< Write protection of Sector124 to Sector127 */ 560 #define OB_WRP_SECTOR_ALL 0xFFFFFFFFU /*!< Write protection of all Sectors */ 561 #else 562 #define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */ 563 #define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */ 564 #define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */ 565 #define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */ 566 #define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */ 567 #define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */ 568 #define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */ 569 #define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */ 570 #define OB_WRP_SECTOR_ALL 0x000000FFU /*!< Write protection of all Sectors */ 571 #endif /* (FLASH_SECTOR_NB == 128) */ 572 /** 573 * @} 574 */ 575 576 /** @defgroup FLASH_Programming_Delay FLASH Programming Delay 577 * @{ 578 */ 579 #define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 70 MHz or 580 below */ 581 #define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz 582 and 185 MHz */ 583 #define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz 584 and 225 MHz */ 585 #define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ /*!< programming delay set for Flash at startup */ 586 /** 587 * @} 588 */ 589 590 /** @defgroup FLASH_OTP_Blocks FLASH OTP blocks 591 * @{ 592 */ 593 #define FLASH_OTP_BLOCK_0 0x00000001U /*!< OTP Block0 */ 594 #define FLASH_OTP_BLOCK_1 0x00000002U /*!< OTP Block1 */ 595 #define FLASH_OTP_BLOCK_2 0x00000004U /*!< OTP Block2 */ 596 #define FLASH_OTP_BLOCK_3 0x00000008U /*!< OTP Block3 */ 597 #define FLASH_OTP_BLOCK_4 0x00000010U /*!< OTP Block4 */ 598 #define FLASH_OTP_BLOCK_5 0x00000020U /*!< OTP Block5 */ 599 #define FLASH_OTP_BLOCK_6 0x00000040U /*!< OTP Block6 */ 600 #define FLASH_OTP_BLOCK_7 0x00000080U /*!< OTP Block7 */ 601 #define FLASH_OTP_BLOCK_8 0x00000100U /*!< OTP Block8 */ 602 #define FLASH_OTP_BLOCK_9 0x00000200U /*!< OTP Block9 */ 603 #define FLASH_OTP_BLOCK_10 0x00000400U /*!< OTP Block10 */ 604 #define FLASH_OTP_BLOCK_11 0x00000800U /*!< OTP Block11 */ 605 #define FLASH_OTP_BLOCK_12 0x00001000U /*!< OTP Block12 */ 606 #define FLASH_OTP_BLOCK_13 0x00002000U /*!< OTP Block13 */ 607 #define FLASH_OTP_BLOCK_14 0x00004000U /*!< OTP Block14 */ 608 #define FLASH_OTP_BLOCK_15 0x00008000U /*!< OTP Block15 */ 609 #define FLASH_OTP_BLOCK_16 0x00010000U /*!< OTP Block16 */ 610 #define FLASH_OTP_BLOCK_17 0x00020000U /*!< OTP Block17 */ 611 #define FLASH_OTP_BLOCK_18 0x00040000U /*!< OTP Block18 */ 612 #define FLASH_OTP_BLOCK_19 0x00080000U /*!< OTP Block19 */ 613 #define FLASH_OTP_BLOCK_20 0x00100000U /*!< OTP Block20 */ 614 #define FLASH_OTP_BLOCK_21 0x00200000U /*!< OTP Block21 */ 615 #define FLASH_OTP_BLOCK_22 0x00400000U /*!< OTP Block22 */ 616 #define FLASH_OTP_BLOCK_23 0x00800000U /*!< OTP Block23 */ 617 #define FLASH_OTP_BLOCK_24 0x01000000U /*!< OTP Block24 */ 618 #define FLASH_OTP_BLOCK_25 0x02000000U /*!< OTP Block25 */ 619 #define FLASH_OTP_BLOCK_26 0x04000000U /*!< OTP Block26 */ 620 #define FLASH_OTP_BLOCK_27 0x08000000U /*!< OTP Block27 */ 621 #define FLASH_OTP_BLOCK_28 0x10000000U /*!< OTP Block28 */ 622 #define FLASH_OTP_BLOCK_29 0x20000000U /*!< OTP Block29 */ 623 #define FLASH_OTP_BLOCK_30 0x40000000U /*!< OTP Block30 */ 624 #define FLASH_OTP_BLOCK_31 0x80000000U /*!< OTP Block31 */ 625 #define FLASH_OTP_BLOCK_ALL 0xFFFFFFFFU /*!< OTP All Blocks */ 626 /** 627 * @} 628 */ 629 630 /** @defgroup FLASH_WRP_State FLASH WRP State 631 * @{ 632 */ 633 #define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired flash sectors */ 634 #define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired flash sectors */ 635 /** 636 * @} 637 */ 638 639 /** @defgroup FLASH_OB_BOOT_CONFIG FLASH Option Bytes Boot configuration 640 * @{ 641 */ 642 #define OB_BOOT_NS 0x00000001U /*!< Non-secure boot address */ 643 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 644 #define OB_BOOT_SEC 0x00000002U /*!< Secure boot address */ 645 #endif /* __ARM_FEATURE_CMSE */ 646 /** 647 * @} 648 */ 649 650 /** @defgroup FLASH_OB_BOOT_LOCK FLASH Option Bytes Boot Lock 651 * @{ 652 */ 653 #define OB_BOOT_LOCK_DISABLE 0xC3U /*!< Boot lock disable */ 654 #define OB_BOOT_LOCK_ENABLE 0xB4U /*!< Boot lock enable */ 655 /** 656 * @} 657 */ 658 659 /** @defgroup FLASH_BB_Attributes FLASH Block-Base Attributes 660 * @{ 661 */ 662 #define FLASH_BB_SEC 0x01U /*!< Flash Block-Based Security Attributes */ 663 #define FLASH_BB_PRIV 0x02U /*!< Flash Block-Based Privilege Attributes */ 664 /** 665 * @} 666 */ 667 668 /** @defgroup FLASH_PRIV_MODE FLASH privilege mode 669 * @{ 670 */ 671 #define FLASH_NSPRIV_GRANTED 0x00000000U /*!< access to non-secure Flash registers is granted to privileged 672 or unprivileged access */ 673 #define FLASH_NSPRIV_DENIED FLASH_PRIVCFGR_NSPRIV /*!< access to non-secure Flash registers is denied to 674 non-privilege access */ 675 676 #define FLASH_SPRIV_GRANTED 0x00000000U /*!< access to secure Flash registers is granted to privileged or 677 unprivileged access */ 678 #if defined (FLASH_PRIVCFGR_SPRIV) 679 #define FLASH_SPRIV_DENIED FLASH_PRIVCFGR_SPRIV /*!< access to secure Flash registers is denied to non-privilege 680 access */ 681 #endif /* FLASH_PRIVCFGR_SPRIV */ 682 /** 683 * @} 684 */ 685 686 #if defined (FLASH_SR_OBKERR) 687 /** @defgroup FLASH_OBK_SWAP_Offset FLASH OBK Swap Offset 688 * @{ 689 */ 690 #define FLASH_OBK_SWAP_OFFSET_NO_DATA 0x000U /*!< No data will be copied from current to alternate OBK */ 691 #define FLASH_OBK_SWAP_OFFSET_HDPL0 0x010U /*!< HDPL0 data will be copied from current to alternate OBK */ 692 #define FLASH_OBK_SWAP_OFFSET_HDPL1 0x090U /*!< HDPL0/1 data will be copied from current to alternate OBK */ 693 #define FLASH_OBK_SWAP_OFFSET_HDPL2 0x0C0U /*!< HDPL0/1/2 data will be copied from current to alternate OBK */ 694 #define FLASH_OBK_SWAP_OFFSET_HDPL3_S 0x180U /*!< HDPL0/1/2/3_S data will be copied from current to alternate 695 OBK */ 696 #define FLASH_OBK_SWAP_OFFSET_ALL 0x1FFU /*!< All OBK data (511) will be copied from current to alternate 697 OBK */ 698 /** 699 * @} 700 */ 701 #endif /* FLASH_SR_OBKERR */ 702 703 /** @defgroup FLASH_Operation_Type FLASH Operation Type 704 * @{ 705 */ 706 #define FLASH_OPERATION_TYPE_NONE 00000000U /*!< No Flash operation */ 707 #define FLASH_OPERATION_TYPE_QUADWORD FLASH_OPSR_CODE_OP_0 /*!< Single write operation */ 708 #if defined (FLASH_SR_OBKERR) 709 #define FLASH_OPERATION_TYPE_OBKALTERASE FLASH_OPSR_CODE_OP_1 /*!< OBK alternate sector erase 710 operation */ 711 #endif /* FLASH_SR_OBKERR */ 712 #define FLASH_OPERATION_TYPE_SECTORERASE (FLASH_OPSR_CODE_OP_1 | FLASH_OPSR_CODE_OP_0) /*!< Sector erase operation */ 713 #define FLASH_OPERATION_TYPE_BANKERASE FLASH_OPSR_CODE_OP_2 /*!< Bank erase operation */ 714 #define FLASH_OPERATION_TYPE_MASSERASE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_0) /*!< Mass erase operation */ 715 #define FLASH_OPERATION_TYPE_OPTIONCHANGE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1) /*!< Option change operation */ 716 #if defined (FLASH_SR_OBKERR) 717 #define FLASH_OPERATION_TYPE_OBKSWAP (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1 | FLASH_OPSR_CODE_OP_0) /*!< OBK 718 swap operation */ 719 #endif /* FLASH_SR_OBKERR */ 720 /** 721 * @} 722 */ 723 724 /** @defgroup FLASH_Operation_Area FLASH Operation Area 725 * @{ 726 */ 727 #define FLASH_OPERATION_AREA_BANK_1 00000000U /*!< Operation in Flash Bank 1 */ 728 #define FLASH_OPERATION_AREA_BANK_2 FLASH_OPSR_BK_OP /*!< Operation in Flash Bank 2 */ 729 #define FLASH_OPERATION_AREA_SYSF FLASH_OPSR_SYSF_OP /*!< Operation in System Flash memory */ 730 #if defined (FLASH_EDATAR_EDATA_EN) 731 #define FLASH_OPERATION_AREA_DATA FLASH_OPSR_DATA_OP /*!< Operation in Flash high-cycle data area */ 732 #endif /* FLASH_EDATAR_EDATA_EN */ 733 #define FLASH_OPERATION_AREA_OTP FLASH_OPSR_OTP_OP /*!< Operation in Flash OTP area */ 734 /** 735 * @} 736 */ 737 738 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 739 /** @defgroup SEC_INVERSION_CFG FLASH security inversion configuration 740 * @{ 741 */ 742 #define FLASH_INV_DISABLE 0x00000000U /*!< Security state of Flash is not inverted */ 743 #define FLASH_INV_ENABLE FLASH_CR_INV /*!< Security state of Flash is inverted */ 744 /** 745 * @} 746 */ 747 #endif /* __ARM_FEATURE_CMSE */ 748 /** 749 * @} 750 */ 751 /* Exported macros ------------------------------------------------------------*/ 752 /** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros 753 * @{ 754 */ 755 756 /** 757 * @brief Enable the FLASH prefetch buffer. 758 * @retval None 759 */ 760 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 761 762 /** 763 * @brief Disable the FLASH prefetch buffer. 764 * @retval None 765 */ 766 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 767 768 /** 769 * @brief Enable the FLASH smart prefetch buffer. 770 * @retval None 771 */ 772 #define __HAL_FLASH_SMART_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_S_PRFTEN) 773 774 /** 775 * @brief Disable the FLASH smart prefetch buffer. 776 * @retval None 777 */ 778 #define __HAL_FLASH_SMART_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_S_PRFTEN) 779 780 /** 781 * @brief Set the FLASH Programming Delay. 782 * @param __DELAY__ FLASH Programming Delay 783 * This parameter can be a value of @ref FLASH_Programming_Delay 784 * @retval none 785 */ 786 #define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__)) 787 788 /** 789 * @brief Get the FLASH Programming Delay. 790 * @retval FLASH Programming Delay 791 * This return value can be a value of @ref FLASH_Programming_Delay 792 */ 793 #define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ) 794 795 /** 796 * @} 797 */ 798 /* Exported functions --------------------------------------------------------*/ 799 /** @addtogroup FLASHEx_Exported_Functions 800 * @{ 801 */ 802 803 /** @addtogroup FLASHEx_Exported_Functions_Group1 804 * @{ 805 */ 806 /* Extension Erase and OB Program operation functions ******************************/ 807 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); 808 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); 809 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); 810 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); 811 #if defined (FLASH_SR_OBKERR) 812 HAL_StatusTypeDef HAL_FLASHEx_OBK_Unlock(void); 813 HAL_StatusTypeDef HAL_FLASHEx_OBK_Lock(void); 814 HAL_StatusTypeDef HAL_FLASHEx_OBK_Swap(uint32_t SwapOffset); 815 #endif /* FLASH_SR_OBKERR */ 816 void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation); 817 /** 818 * @} 819 */ 820 821 /** @addtogroup FLASHEx_Exported_Functions_Group2 822 * @{ 823 */ 824 /* Extension Protection configuration functions *************************************/ 825 HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); 826 void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); 827 void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode); 828 uint32_t HAL_FLASHEx_GetPrivMode(void); 829 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 830 HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState); 831 uint32_t HAL_FLASHEx_GetSecInversion(void); 832 #endif /* __ARM_FEATURE_CMSE */ 833 HAL_StatusTypeDef HAL_FLASHEx_ConfigHDPExtension(FLASH_HDPExtensionTypeDef *pHDPExtension); 834 /** 835 * @} 836 */ 837 838 /** 839 * @} 840 */ 841 /* Private types -------------------------------------------------------------*/ 842 /* Private variables ---------------------------------------------------------*/ 843 /* Private constants ---------------------------------------------------------*/ 844 /** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants 845 * @{ 846 */ 847 #define FLASH_TYPEPROGRAM_OB (0x00008000U | FLASH_NON_SECURE_MASK) /*!< Program Option Bytes operation type */ 848 /** 849 * @} 850 */ 851 /* Private macros ------------------------------------------------------------*/ 852 /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros 853 * @{ 854 */ 855 856 /** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters 857 * @{ 858 */ 859 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 860 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ 861 ((VALUE) == FLASH_TYPEERASE_SECTORS_NS) || \ 862 ((VALUE) == FLASH_TYPEERASE_MASSERASE) || \ 863 ((VALUE) == FLASH_TYPEERASE_MASSERASE_NS) || \ 864 ((VALUE) == FLASH_TYPEERASE_OBK_ALT)) 865 #else 866 #if defined (FLASH_SR_OBKERR) 867 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ 868 ((VALUE) == FLASH_TYPEERASE_MASSERASE) || \ 869 ((VALUE) == FLASH_TYPEERASE_OBK_ALT)) 870 #else 871 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ 872 ((VALUE) == FLASH_TYPEERASE_MASSERASE)) 873 #endif /* FLASH_SR_OBKERR */ 874 #endif /* __ARM_FEATURE_CMSE */ 875 876 #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ 877 ((VALUE) == OB_WRPSTATE_ENABLE)) 878 879 #define IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && \ 880 (((VALUE) & ~OPTIONBYTE_ALL) == 0U)) 881 882 #define IS_OB_PRODUCT_STATE(STATE) (((STATE) == OB_PROD_STATE_OPEN) || \ 883 ((STATE) == OB_PROD_STATE_PROVISIONING) || \ 884 ((STATE) == OB_PROD_STATE_IROT_PROVISIONED) || \ 885 ((STATE) == OB_PROD_STATE_TZ_CLOSED) || \ 886 ((STATE) == OB_PROD_STATE_CLOSED) || \ 887 ((STATE) == OB_PROD_STATE_LOCKED) || \ 888 ((STATE) == OB_PROD_STATE_REGRESSION) || \ 889 ((STATE) == OB_PROD_STATE_NS_REGRESSION)) 890 891 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_1) || ((LEVEL) == OB_BOR_LEVEL_2) || \ 892 ((LEVEL) == OB_BOR_LEVEL_3)) 893 894 #define IS_OB_USER_BORH_EN(VALUE) (((VALUE) == OB_BORH_DISABLE) || ((VALUE) == OB_BORH_ENABLE)) 895 896 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) 897 898 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) 899 900 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) 901 902 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) 903 904 #define IS_OB_USER_IO_VDD_HSLV(VALUE) (((VALUE) == OB_IO_VDD_HSLV_DISABLE) || \ 905 ((VALUE) == OB_IO_VDD_HSLV_ENABLE)) 906 907 #define IS_OB_USER_IO_VDDIO2_HSLV(VALUE) (((VALUE) == OB_IO_VDDIO2_HSLV_DISABLE) || \ 908 ((VALUE) == OB_IO_VDDIO2_HSLV_ENABLE)) 909 910 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE)) 911 912 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE)) 913 914 #define IS_OB_USER_BOOT_UBE(VALUE) (((VALUE) == OB_UBE_OEM_IROT) || ((VALUE) == OB_UBE_ST_IROT)) 915 916 #define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) 917 918 #if defined (FLASH_OPTSR2_SRAM1_3_RST) 919 #define IS_OB_USER_SRAM1_3_RST(VALUE) (((VALUE) == OB_SRAM1_3_RST_ERASE) || ((VALUE) == OB_SRAM1_3_RST_NOT_ERASE)) 920 #endif /* FLASH_OPTSR2_SRAM1_3_RST */ 921 922 #if defined (FLASH_OPTSR2_SRAM1_RST) 923 #define IS_OB_USER_SRAM1_RST(VALUE) (((VALUE) == OB_SRAM1_RST_ERASE) || ((VALUE) == OB_SRAM1_RST_NOT_ERASE)) 924 #endif /* FLASH_OPTSR2_SRAM1_RST */ 925 926 #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) 927 928 #define IS_OB_USER_BKPRAM_ECC(VALUE) (((VALUE) == OB_BKPRAM_ECC_ENABLE) || ((VALUE) == OB_BKPRAM_ECC_DISABLE)) 929 930 #if defined (FLASH_OPTSR2_SRAM3_ECC) 931 #define IS_OB_USER_SRAM3_ECC(VALUE) (((VALUE) == OB_SRAM3_ECC_ENABLE) || ((VALUE) == OB_SRAM3_ECC_DISABLE)) 932 #endif /* FLASH_OPTSR2_SRAM3_ECC */ 933 934 #if defined (FLASH_OPTSR2_SRAM1_ECC) 935 #define IS_OB_USER_SRAM1_ECC(VALUE) (((VALUE) == OB_SRAM1_ECC_ENABLE) || ((VALUE) == OB_SRAM1_ECC_DISABLE)) 936 #endif /* FLASH_OPTSR2_SRAM1_ECC */ 937 938 #define IS_OB_USER_SRAM2_ECC(VALUE) (((VALUE) == OB_SRAM2_ECC_ENABLE) || ((VALUE) == OB_SRAM2_ECC_DISABLE)) 939 940 #define IS_OB_USER_TZEN(VALUE) (((VALUE) == OB_TZEN_DISABLE) || ((VALUE) == OB_TZEN_ENABLE)) 941 942 #define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \ 943 (((TYPE) & ~OB_USER_ALL) == 0U)) 944 945 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 946 #define IS_OB_BOOT_CONFIG(CFG) (((CFG) == OB_BOOT_NS) || ((CFG) == OB_BOOT_SEC)) 947 #else 948 #define IS_OB_BOOT_CONFIG(CFG) ((CFG) == OB_BOOT_NS) 949 #endif /* __ARM_FEATURE_CMSE */ 950 951 #define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_DISABLE) || ((VALUE) == OB_BOOT_LOCK_ENABLE)) 952 953 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 954 #define IS_FLASH_BB_EXCLUSIVE(CFG) (((CFG) == FLASH_BB_SEC) || ((CFG) == FLASH_BB_PRIV)) 955 #else 956 #define IS_FLASH_BB_EXCLUSIVE(CFG) ((CFG) == FLASH_BB_PRIV) 957 #endif /* __ARM_FEATURE_CMSE */ 958 959 #define IS_FLASH_CFGPRIVMODE(CFG) (((CFG) & 0xFFFFFFFCU) == 0U) 960 961 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 962 #define IS_FLASH_CFGSECINV(CFG) (((CFG) == FLASH_INV_DISABLE) || ((CFG) == FLASH_INV_ENABLE)) 963 #endif /* __ARM_FEATURE_CMSE */ 964 965 #define IS_FLASH_EDATA_SIZE(SECTOR) ((SECTOR) <= FLASH_EDATA_SECTOR_NB) 966 /** 967 * @} 968 */ 969 970 /** 971 * @} 972 */ 973 /* Private functions ---------------------------------------------------------*/ 974 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions 975 * @{ 976 */ 977 void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks); 978 /** 979 * @} 980 */ 981 982 /** 983 * @} 984 */ 985 986 /** 987 * @} 988 */ 989 990 /** 991 * @} 992 */ 993 994 #ifdef __cplusplus 995 } 996 #endif 997 998 #endif /* STM32H5xx_HAL_FLASH_EX_H */ 999
