1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_dcache.h 4 * @author MCD Application Team 5 * @brief Header file of DCACHE HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion ------------------------------------*/ 20 #ifndef STM32H5xx_HAL_DCACHE_H 21 #define STM32H5xx_HAL_DCACHE_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes -----------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /** @addtogroup STM32H5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DCACHE 35 * @{ 36 */ 37 /* Exported types ------------------------------------------------------------*/ 38 39 /** @defgroup DCACHE_Exported_Types DCACHE Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief DCACHE Init structure definition 45 */ 46 typedef struct 47 { 48 uint32_t ReadBurstType; /*!< Burst type to be applied for Data Cache */ 49 } DCACHE_InitTypeDef; 50 51 /** 52 * @brief HAL State structures definition 53 */ 54 typedef enum 55 { 56 HAL_DCACHE_STATE_RESET = 0x00U, /* !< DCACHE not yet initialized or disabled */ 57 HAL_DCACHE_STATE_READY = 0x01U, /* !< Peripheral initialized and ready for use */ 58 HAL_DCACHE_STATE_BUSY = 0x02U, /* !< An internal process is ongoing */ 59 HAL_DCACHE_STATE_TIMEOUT = 0x05U, /* !< Timeout state */ 60 HAL_DCACHE_STATE_ERROR = 0x06U, /* !< DCACHE state error */ 61 62 } HAL_DCACHE_StateTypeDef; 63 64 /** @defgroup DCACHE_Configuration_Structure_definition DCACHE Configuration Structure definition 65 * @brief DCACHE Configuration Structure definition 66 * @{ 67 */ 68 typedef struct __DCACHE_HandleTypeDef 69 { 70 DCACHE_TypeDef *Instance; /*!< DCACHE register base address. */ 71 DCACHE_InitTypeDef Init; /*!< DCACHE Initialization Structure. */ 72 73 void (* ErrorCallback)(struct __DCACHE_HandleTypeDef *hdcache); 74 void (* CleanByAddrCallback)(struct __DCACHE_HandleTypeDef *hdcache); 75 void (* InvalidateByAddrCallback)(struct __DCACHE_HandleTypeDef *hdcache); 76 void (* InvalidateCompleteCallback)(struct __DCACHE_HandleTypeDef *hdcache); 77 void (* CleanAndInvalidateByAddrCallback)(struct __DCACHE_HandleTypeDef *hdcache); 78 79 void (* MspInitCallback)(struct __DCACHE_HandleTypeDef *hdcache); 80 void (* MspDeInitCallback)(struct __DCACHE_HandleTypeDef *hdcache); 81 82 __IO HAL_DCACHE_StateTypeDef State; 83 __IO uint32_t ErrorCode; 84 85 } DCACHE_HandleTypeDef; 86 87 /** 88 * @brief HAL DCACHE Callback pointer definition 89 */ 90 /*!< Pointer to a DCACHE common callback function */ 91 typedef void (*pDCACHE_CallbackTypeDef)(DCACHE_HandleTypeDef *hdcache); 92 93 /** 94 * @brief HAL DCACHE Callback ID enumeration definition 95 */ 96 typedef enum 97 { 98 HAL_DCACHE_CLEAN_BY_ADDRESS_CB_ID = 0x00U, /*!< DCACHE Clean By Address callback ID */ 99 HAL_DCACHE_INVALIDATE_BY_ADDRESS_CB_ID = 0x01U, /*!< DCACHE Invalidate By Address callback ID */ 100 HAL_DCACHE_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID = 0x02U, /*!< DCACHE Clean And Invalidate By Address callback ID */ 101 HAL_DCACHE_INVALIDATE_COMPLETE_CB_ID = 0x03U, /*!< DCACHE Invalidate Complete ID */ 102 HAL_DCACHE_ERROR_CB_ID = 0x04U, /*!< DCACHE Error callback ID */ 103 104 HAL_DCACHE_MSPINIT_CB_ID = 0x05U, /*!< DCACHE Msp Init callback ID */ 105 HAL_DCACHE_MSPDEINIT_CB_ID = 0x06U /*!< DCACHE Msp DeInit callback ID */ 106 107 } HAL_DCACHE_CallbackIDTypeDef; 108 109 /** 110 * @} 111 */ 112 113 /** 114 * @} 115 */ 116 117 /* Exported constants -------------------------------------------------------*/ 118 /** @defgroup DCACHE_Exported_Constants DCACHE Exported Constants 119 * @{ 120 */ 121 122 /** @defgroup DCACHE_Error_Code DCACHE Error Code 123 * @{ 124 */ 125 #define HAL_DCACHE_ERROR_NONE 0x00000000U /*!< No error */ 126 #define HAL_DCACHE_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */ 127 #define HAL_DCACHE_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error */ 128 #define HAL_DCACHE_ERROR_EVICTION_CLEAN 0x00000040U /*!< Eviction or clean operation write-back error */ 129 #define HAL_DCACHE_ERROR_INVALID_OPERATION 0x00000080U /*!< Invalid operation */ 130 131 /** 132 * @} 133 */ 134 135 /** @defgroup DCACHE_Monitor_Type Monitor type 136 * @{ 137 */ 138 #define DCACHE_MONITOR_READ_HIT DCACHE_CR_RHITMEN /*!< Read Hit monitoring */ 139 #define DCACHE_MONITOR_READ_MISS DCACHE_CR_RMISSMEN /*!< Read Miss monitoring */ 140 #define DCACHE_MONITOR_WRITE_HIT DCACHE_CR_WHITMEN /*!< Write Hit monitoring */ 141 #define DCACHE_MONITOR_WRITE_MISS DCACHE_CR_WMISSMEN /*!< Write Miss monitoring */ 142 #define DCACHE_MONITOR_ALL (DCACHE_CR_RHITMEN | DCACHE_CR_RMISSMEN | \ 143 DCACHE_CR_WHITMEN | DCACHE_CR_WMISSMEN) 144 /** 145 * @} 146 */ 147 148 /** @defgroup DCACHE_Read_Burst_Type Remapped Output burst type 149 * @{ 150 */ 151 #define DCACHE_READ_BURST_WRAP 0U /*!< WRAP */ 152 #define DCACHE_READ_BURST_INCR DCACHE_CR_HBURST /*!< INCR */ 153 /** 154 * @} 155 */ 156 157 /** @defgroup DCACHE_Interrupts Interrupts 158 * @{ 159 */ 160 #define DCACHE_IT_BUSYEND DCACHE_IER_BSYENDIE /*!< Busy end interrupt */ 161 #define DCACHE_IT_ERROR DCACHE_IER_ERRIE /*!< Cache error interrupt */ 162 #define DCACHE_IT_CMDEND DCACHE_IER_CMDENDIE /*!< Command end interrupt */ 163 /** 164 * @} 165 */ 166 167 /** @defgroup DCACHE_Flags Flags 168 * @{ 169 */ 170 #define DCACHE_FLAG_BUSY DCACHE_SR_BUSYF /*!< Busy flag */ 171 #define DCACHE_FLAG_BUSYEND DCACHE_SR_BSYENDF /*!< Busy end flag */ 172 #define DCACHE_FLAG_ERROR DCACHE_SR_ERRF /*!< Cache error flag */ 173 #define DCACHE_FLAG_BUSYCMD DCACHE_SR_BUSYCMDF /*!< Busy command flag */ 174 #define DCACHE_FLAG_CMDEND DCACHE_SR_CMDENDF /*!< Command end flag */ 175 /** 176 * @} 177 */ 178 179 /** 180 * @} 181 */ 182 183 /* Exported macros ----------------------------------------------------------*/ 184 /** @defgroup DCACHE_Exported_Macros DCACHE Exported Macros 185 * @{ 186 */ 187 188 /** @brief Enable DCACHE interrupts. 189 * @param __HANDLE__ specifies the DCACHE handle. 190 * @param __INTERRUPT__ specifies the DCACHE interrupt sources to be enabled. 191 * This parameter can be any combination of the following values: 192 * @arg @ref DCACHE_IT_BUSYEND Busy end interrupt 193 * @arg @ref DCACHE_IT_ERROR Cache error interrupt 194 * @arg @ref DCACHE_IT_CMDEND Cache Command end interrupt 195 * @retval None 196 */ 197 #define __HAL_DCACHE_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)) 198 199 /** @brief Disable DCACHE interrupts. 200 * @param __HANDLE__ specifies the DCACHE handle. 201 * @param __INTERRUPT__ specifies the DCACHE interrupt sources to be disabled. 202 * This parameter can be any combination of the following values: 203 * @arg @ref DCACHE_IT_BUSYEND Busy end interrupt 204 * @arg @ref DCACHE_IT_ERROR Cache error interrupt 205 * @arg @ref DCACHE_IT_CMDEND Cache Command end interrupt 206 * @retval None 207 */ 208 #define __HAL_DCACHE_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)) 209 210 /** @brief Check whether the specified DCACHE interrupt source is enabled or not. 211 * @param __HANDLE__ specifies the DCACHE handle. 212 * @param __INTERRUPT__ specifies the DCACHE interrupt source to check. 213 * This parameter can be any combination of the following values: 214 * @arg @ref DCACHE_IT_BUSYEND Busy end interrupt 215 * @arg @ref DCACHE_IT_ERROR Cache error interrupt 216 * @arg @ref DCACHE_IT_CMDEND Cache Command end interrupt 217 * 218 * @retval The state of __INTERRUPT__ (SET or RESET). 219 */ 220 #define __HAL_DCACHE_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 221 ((READ_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 222 223 /** @brief Check whether the selected DCACHE flag is set or not. 224 * @param __HANDLE__ specifies the DCACHE handle. 225 * @param __FLAG__ specifies the flag to check. 226 * This parameter can be one of the following values: 227 * @arg @ref DCACHE_FLAG_BUSY Busy flag 228 * @arg @ref DCACHE_FLAG_BUSYEND Busy end flag 229 * @arg @ref DCACHE_FLAG_ERROR Cache error flag 230 * @arg @ref DCACHE_FLAG_BUSYCMD Cache Busy command flag 231 * @arg @ref DCACHE_FLAG_CMDEND Cache command end flag 232 * @retval The state of __FLAG__ (0 or 1). 233 */ 234 #define __HAL_DCACHE_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? 1U : 0U) 235 236 /** @brief Clear the selected DCACHE flags. 237 * @param __HANDLE__ specifies the DCACHE handle. 238 * @param __FLAG__ specifies the DCACHE flags to clear. 239 * This parameter can be any combination of the following values: 240 * @arg @ref DCACHE_FLAG_BUSYEND Busy end flag 241 * @arg @ref DCACHE_FLAG_ERROR Cache error flag 242 * @arg @ref DCACHE_FLAG_CMDEND Cache command end flag 243 */ 244 #define __HAL_DCACHE_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 245 246 /** 247 * @} 248 */ 249 250 /* Exported functions -------------------------------------------------------*/ 251 /** @defgroup DCACHE_Exported_Functions DCACHE Exported Functions 252 * @{ 253 */ 254 /* Initialization and de-initialization functions ***/ 255 HAL_StatusTypeDef HAL_DCACHE_Init(DCACHE_HandleTypeDef *hdcache); 256 HAL_StatusTypeDef HAL_DCACHE_DeInit(DCACHE_HandleTypeDef *hdcache); 257 void HAL_DCACHE_MspInit(DCACHE_HandleTypeDef *hdcache); 258 void HAL_DCACHE_MspDeInit(DCACHE_HandleTypeDef *hdcache); 259 260 /* Peripheral Control functions ***/ 261 HAL_StatusTypeDef HAL_DCACHE_Enable(DCACHE_HandleTypeDef *hdcache); 262 HAL_StatusTypeDef HAL_DCACHE_Disable(DCACHE_HandleTypeDef *hdcache); 263 uint32_t HAL_DCACHE_IsEnabled(DCACHE_HandleTypeDef *hdcache); 264 HAL_StatusTypeDef HAL_DCACHE_SetReadBurstType(DCACHE_HandleTypeDef *hdcache, uint32_t ReadBurstType); 265 266 /*** Cache maintenance in blocking mode (Polling) ***/ 267 HAL_StatusTypeDef HAL_DCACHE_Invalidate(DCACHE_HandleTypeDef *hdcache); 268 HAL_StatusTypeDef HAL_DCACHE_InvalidateByAddr(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr, 269 uint32_t dSize); 270 HAL_StatusTypeDef HAL_DCACHE_CleanByAddr(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr, uint32_t dSize); 271 HAL_StatusTypeDef HAL_DCACHE_CleanInvalidByAddr(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr, 272 uint32_t dSize); 273 274 /*** Cache maintenance in non-blocking mode (Interrupt) ***/ 275 HAL_StatusTypeDef HAL_DCACHE_Invalidate_IT(DCACHE_HandleTypeDef *hdcache); 276 HAL_StatusTypeDef HAL_DCACHE_InvalidateByAddr_IT(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr, 277 uint32_t dSize); 278 HAL_StatusTypeDef HAL_DCACHE_CleanByAddr_IT(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr, 279 uint32_t dSize); 280 HAL_StatusTypeDef HAL_DCACHE_CleanInvalidByAddr_IT(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr, 281 uint32_t dSize); 282 283 /*** IRQHandler and Callbacks ***/ 284 void HAL_DCACHE_IRQHandler(DCACHE_HandleTypeDef *hdcache); 285 void HAL_DCACHE_ErrorCallback(DCACHE_HandleTypeDef *hdcache); 286 void HAL_DCACHE_CleanByAddrCallback(DCACHE_HandleTypeDef *hdcache); 287 void HAL_DCACHE_InvalidateByAddrCallback(DCACHE_HandleTypeDef *hdcache); 288 void HAL_DCACHE_InvalidateCompleteCallback(DCACHE_HandleTypeDef *hdcache); 289 void HAL_DCACHE_CleanAndInvalidateByAddrCallback(DCACHE_HandleTypeDef *hdcache); 290 291 /* Callbacks Register/UnRegister functions ***/ 292 HAL_StatusTypeDef HAL_DCACHE_RegisterCallback(DCACHE_HandleTypeDef *hdcache, HAL_DCACHE_CallbackIDTypeDef CallbackID, 293 pDCACHE_CallbackTypeDef pCallback); 294 HAL_StatusTypeDef HAL_DCACHE_UnRegisterCallback(DCACHE_HandleTypeDef *hdcache, HAL_DCACHE_CallbackIDTypeDef CallbackID); 295 296 /*** Performance instruction cache monitoring functions ***/ 297 uint32_t HAL_DCACHE_Monitor_GetReadHitValue(DCACHE_HandleTypeDef *hdcache); 298 uint32_t HAL_DCACHE_Monitor_GetReadMissValue(DCACHE_HandleTypeDef *hdcache); 299 uint32_t HAL_DCACHE_Monitor_GetWriteHitValue(DCACHE_HandleTypeDef *hdcache); 300 uint32_t HAL_DCACHE_Monitor_GetWriteMissValue(DCACHE_HandleTypeDef *hdcache); 301 HAL_StatusTypeDef HAL_DCACHE_Monitor_Reset(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType); 302 HAL_StatusTypeDef HAL_DCACHE_Monitor_Start(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType); 303 HAL_StatusTypeDef HAL_DCACHE_Monitor_Stop(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType); 304 305 /* Peripheral State functions ***************************************************/ 306 HAL_DCACHE_StateTypeDef HAL_DCACHE_GetState(DCACHE_HandleTypeDef *hdcache); 307 uint32_t HAL_DCACHE_GetError(DCACHE_HandleTypeDef *hdcache); 308 /** 309 * @} 310 */ 311 312 /* Private types -------------------------------------------------------------*/ 313 /* Private variables ---------------------------------------------------------*/ 314 /* Private constants ---------------------------------------------------------*/ 315 /* Private macros ------------------------------------------------------------*/ 316 317 /** 318 * @} 319 */ 320 321 /** 322 * @} 323 */ 324 325 #ifdef __cplusplus 326 } 327 #endif 328 329 #endif /* STM32H5xx_HAL_DCACHE_H */ 330
