1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32H5xx_HAL_CORTEX_H 21 #define __STM32H5xx_HAL_CORTEX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /** @addtogroup STM32H5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @defgroup CORTEX CORTEX 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 40 * @{ 41 */ 42 43 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 44 * @{ 45 */ 46 typedef struct 47 { 48 uint8_t Enable; /*!< Specifies the status of the region. 49 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 50 uint8_t Number; /*!< Specifies the index of the region to protect. 51 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 52 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 53 uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */ 54 uint8_t AttributesIndex; /*!< Specifies the memory attributes index. 55 This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ 56 uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter 57 can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 58 uint8_t DisableExec; /*!< Specifies the instruction access status. 59 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 60 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 61 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 62 } MPU_Region_InitTypeDef; 63 /** 64 * @} 65 */ 66 67 /** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes 68 * Initialization Structure Definition 69 * @{ 70 */ 71 typedef struct 72 { 73 uint8_t Number; /*!< Specifies the number of the memory attributes to configure. 74 This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ 75 76 uint8_t Attributes; /*!< Specifies the memory attributes value. Attributes This parameter 77 can be a combination of @ref CORTEX_MPU_Attributes */ 78 79 } MPU_Attributes_InitTypeDef; 80 /** 81 * @} 82 */ 83 84 85 /** 86 * @} 87 */ 88 89 /* Exported constants --------------------------------------------------------*/ 90 91 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 92 * @{ 93 */ 94 95 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 96 * @{ 97 */ 98 #define NVIC_PRIORITYGROUP_0 0x7U /*!< 0 bit for pre-emption priority, 99 4 bits for subpriority */ 100 #define NVIC_PRIORITYGROUP_1 0x6U /*!< 1 bit for pre-emption priority, 101 3 bits for subpriority */ 102 #define NVIC_PRIORITYGROUP_2 0x5U /*!< 2 bits for pre-emption priority, 103 2 bits for subpriority */ 104 #define NVIC_PRIORITYGROUP_3 0x4U /*!< 3 bits for pre-emption priority, 105 1 bit for subpriority */ 106 #define NVIC_PRIORITYGROUP_4 0x3U /*!< 4 bits for pre-emption priority, 107 0 bit for subpriority */ 108 /** 109 * @} 110 */ 111 112 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 113 * @{ 114 */ 115 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x0U /*!< AHB clock divided by 8 selected as SysTick clock source */ 116 #define SYSTICK_CLKSOURCE_LSI 0x1U /*!< LSI clock selected as SysTick clock source */ 117 #define SYSTICK_CLKSOURCE_LSE 0x2U /*!< LSE clock selected as SysTick clock source */ 118 #define SYSTICK_CLKSOURCE_HCLK 0x4U /*!< AHB clock selected as SysTick clock source */ 119 /** 120 * @} 121 */ 122 123 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 124 * @{ 125 */ 126 #define MPU_HFNMI_PRIVDEF_NONE 0U /*!< MPU is disabled during HardFault and NMI handlers, 127 privileged software access to the default memory map is disabled */ 128 #define MPU_HARDFAULT_NMI 2U /*!< MPU is enabled during HardFault and NMI handlers, 129 privileged software access to the default memory map is disabled */ 130 #define MPU_PRIVILEGED_DEFAULT 4U /*!< MPU is disabled during HardFault and NMI handlers, 131 privileged software access to the default memory map is enabled */ 132 #define MPU_HFNMI_PRIVDEF 6U /*!< MPU is enabled during HardFault and NMI handlers, 133 privileged software access to the default memory map is enabled */ 134 /** 135 * @} 136 */ 137 138 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 139 * @{ 140 */ 141 #define MPU_REGION_ENABLE 1U /*!< MPU region enabled */ 142 #define MPU_REGION_DISABLE 0U /*!< MPU region disabled */ 143 /** 144 * @} 145 */ 146 147 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 148 * @{ 149 */ 150 #define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< MPU region execution permitted (if read permitted) */ 151 #define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< MPU region execution not permitted */ 152 /** 153 * @} 154 */ 155 156 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 157 * @{ 158 */ 159 #define MPU_ACCESS_NOT_SHAREABLE 0U /*!< MPU region not shareable */ 160 #define MPU_ACCESS_OUTER_SHAREABLE 1U /*!< MPU region outer shareable */ 161 #define MPU_ACCESS_INNER_SHAREABLE 3U /*!< MPU region inner shareable */ 162 /** 163 * @} 164 */ 165 166 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 167 * @{ 168 */ 169 #define MPU_REGION_PRIV_RW 0U /*!< MPU region Read/write by privileged code only */ 170 #define MPU_REGION_ALL_RW 1U /*!< MPU region Read/write by any privilege level */ 171 #define MPU_REGION_PRIV_RO 2U /*!< MPU region Read-only by privileged code only */ 172 #define MPU_REGION_ALL_RO 3U /*!< MPU region Read-only by any privilege level */ 173 /** 174 * @} 175 */ 176 177 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 178 * @{ 179 */ 180 #define MPU_REGION_NUMBER0 0U /*!< MPU region number 0 */ 181 #define MPU_REGION_NUMBER1 1U /*!< MPU region number 1 */ 182 #define MPU_REGION_NUMBER2 2U /*!< MPU region number 2 */ 183 #define MPU_REGION_NUMBER3 3U /*!< MPU region number 3 */ 184 #define MPU_REGION_NUMBER4 4U /*!< MPU region number 4 */ 185 #define MPU_REGION_NUMBER5 5U /*!< MPU region number 5 */ 186 #define MPU_REGION_NUMBER6 6U /*!< MPU region number 6 */ 187 #define MPU_REGION_NUMBER7 7U /*!< MPU region number 7 */ 188 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 189 #define MPU_REGION_NUMBER8 8U /*!< MPU region number 8 */ 190 #define MPU_REGION_NUMBER9 9U /*!< MPU region number 9 */ 191 #define MPU_REGION_NUMBER10 10U /*!< MPU region number 10 */ 192 #define MPU_REGION_NUMBER11 11U /*!< MPU region number 11 */ 193 #endif /* __ARM_FEATURE_CMSE */ 194 /** 195 * @} 196 */ 197 198 /** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number 199 * @{ 200 */ 201 #define MPU_ATTRIBUTES_NUMBER0 0U /*!< MPU attribute number 0 */ 202 #define MPU_ATTRIBUTES_NUMBER1 1U /*!< MPU attribute number 1 */ 203 #define MPU_ATTRIBUTES_NUMBER2 2U /*!< MPU attribute number 2 */ 204 #define MPU_ATTRIBUTES_NUMBER3 3U /*!< MPU attribute number 3 */ 205 #define MPU_ATTRIBUTES_NUMBER4 4U /*!< MPU attribute number 4 */ 206 #define MPU_ATTRIBUTES_NUMBER5 5U /*!< MPU attribute number 5 */ 207 #define MPU_ATTRIBUTES_NUMBER6 6U /*!< MPU attribute number 6 */ 208 #define MPU_ATTRIBUTES_NUMBER7 7U /*!< MPU attribute number 7 */ 209 /** 210 * @} 211 */ 212 213 /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes 214 * @{ 215 */ 216 #define MPU_DEVICE_nGnRnE 0x0U /*!< Device, noGather, noReorder, noEarly acknowledge. */ 217 #define MPU_DEVICE_nGnRE 0x4U /*!< Device, noGather, noReorder, Early acknowledge. */ 218 #define MPU_DEVICE_nGRE 0x8U /*!< Device, noGather, Reorder, Early acknowledge. */ 219 #define MPU_DEVICE_GRE 0xCU /*!< Device, Gather, Reorder, Early acknowledge. */ 220 221 #define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */ 222 #define MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable. */ 223 #define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */ 224 225 #define MPU_TRANSIENT 0x0U /*!< Normal memory, transient. */ 226 #define MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient. */ 227 228 #define MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate. */ 229 #define MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate. */ 230 #define MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate. */ 231 #define MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate. */ 232 233 /** 234 * @} 235 */ 236 237 /** 238 * @} 239 */ 240 241 /* Exported macros -----------------------------------------------------------*/ 242 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 243 * @{ 244 */ 245 #define OUTER(__ATTR__) ((__ATTR__) << 4U) 246 #define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U)) 247 248 /** 249 * @} 250 */ 251 252 /* Exported functions --------------------------------------------------------*/ 253 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 254 * @{ 255 */ 256 257 /** @defgroup CORTEX_Exported_Functions_Group1 NVIC functions 258 * @brief NVIC functions 259 * @{ 260 */ 261 /* NVIC functions *****************************/ 262 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 263 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 264 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 265 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 266 void HAL_NVIC_SystemReset(void); 267 uint32_t HAL_NVIC_GetPriorityGrouping(void); 268 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, 269 uint32_t *const pSubPriority); 270 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 271 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 272 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 273 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 274 /** 275 * @} 276 */ 277 278 /** @defgroup CORTEX_Exported_Functions_Group2 SYSTICK functions 279 * @brief SYSTICK functions 280 * @{ 281 */ 282 /* SYSTICK functions ***********************************************/ 283 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 284 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 285 void HAL_SYSTICK_IRQHandler(void); 286 void HAL_SYSTICK_Callback(void); 287 /** 288 * @} 289 */ 290 291 /** @defgroup CORTEX_Exported_Functions_Group3 MPU functions 292 * @brief MPU functions 293 * @{ 294 */ 295 /* MPU functions ***********************************************/ 296 void HAL_MPU_Enable(uint32_t MPU_Control); 297 void HAL_MPU_Disable(void); 298 void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit); 299 void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); 300 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 301 /* MPU_NS Control functions ***********************************************/ 302 void HAL_MPU_Enable_NS(uint32_t MPU_Control); 303 void HAL_MPU_Disable_NS(void); 304 void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit); 305 void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); 306 #endif /* __ARM_FEATURE_CMSE */ 307 /** 308 * @} 309 */ 310 311 /** 312 * @} 313 */ 314 315 /* Private types -------------------------------------------------------------*/ 316 /* Private variables ---------------------------------------------------------*/ 317 /* Private constants ---------------------------------------------------------*/ 318 /* Private macros ------------------------------------------------------------*/ 319 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 320 * @{ 321 */ 322 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 323 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 324 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 325 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 326 ((GROUP) == NVIC_PRIORITYGROUP_4)) 327 328 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) 329 330 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) 331 332 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) 333 334 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_LSI) || \ 335 ((SOURCE) == SYSTICK_CLKSOURCE_LSE) || \ 336 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK)|| \ 337 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 338 339 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 340 #define IS_MPU_INSTANCE(INSTANCE) (((INSTANCE) == MPU) || ((INSTANCE) == MPU_NS)) 341 #endif /* __ARM_FEATURE_CMSE */ 342 343 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 344 ((STATE) == MPU_REGION_DISABLE)) 345 346 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 347 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 348 349 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \ 350 ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \ 351 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 352 353 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \ 354 ((TYPE) == MPU_REGION_ALL_RW) || \ 355 ((TYPE) == MPU_REGION_PRIV_RO) || \ 356 ((TYPE) == MPU_REGION_ALL_RO)) 357 358 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 359 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 360 ((NUMBER) == MPU_REGION_NUMBER1) || \ 361 ((NUMBER) == MPU_REGION_NUMBER2) || \ 362 ((NUMBER) == MPU_REGION_NUMBER3) || \ 363 ((NUMBER) == MPU_REGION_NUMBER4) || \ 364 ((NUMBER) == MPU_REGION_NUMBER5) || \ 365 ((NUMBER) == MPU_REGION_NUMBER6) || \ 366 ((NUMBER) == MPU_REGION_NUMBER7) || \ 367 ((NUMBER) == MPU_REGION_NUMBER8) || \ 368 ((NUMBER) == MPU_REGION_NUMBER9) || \ 369 ((NUMBER) == MPU_REGION_NUMBER10)|| \ 370 ((NUMBER) == MPU_REGION_NUMBER11)) 371 #else 372 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 373 ((NUMBER) == MPU_REGION_NUMBER1) || \ 374 ((NUMBER) == MPU_REGION_NUMBER2) || \ 375 ((NUMBER) == MPU_REGION_NUMBER3) || \ 376 ((NUMBER) == MPU_REGION_NUMBER4) || \ 377 ((NUMBER) == MPU_REGION_NUMBER5) || \ 378 ((NUMBER) == MPU_REGION_NUMBER6) || \ 379 ((NUMBER) == MPU_REGION_NUMBER7)) 380 #endif /* __ARM_FEATURE_CMSE */ 381 382 #define IS_MPU_ATTRIBUTES_NUMBER(NUMBER) (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \ 383 ((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \ 384 ((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \ 385 ((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \ 386 ((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \ 387 ((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \ 388 ((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \ 389 ((NUMBER) == MPU_ATTRIBUTES_NUMBER7)) 390 391 /** 392 * @} 393 */ 394 395 /* Private functions ---------------------------------------------------------*/ 396 397 /** 398 * @} 399 */ 400 401 /** 402 * @} 403 */ 404 405 #ifdef __cplusplus 406 } 407 #endif 408 409 #endif /* __STM32H5xx_HAL_CORTEX_H */ 410
