1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_adc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H5xx_HAL_ADC_EX_H 21 #define STM32H5xx_HAL_ADC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /** @addtogroup STM32H5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup ADCEx 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief ADC Injected Conversion Oversampling structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Ratio; /*!< Configures the oversampling ratio. 49 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 50 51 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 52 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 53 } ADC_InjOversamplingTypeDef; 54 55 /** 56 * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected 57 * @note Parameters of this structure are shared within 2 scopes: 58 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, 59 * InjectedOffsetNumber, InjectedOffset, InjectedOffsetSign, InjectedOffsetSaturation 60 * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, 61 * InjectedDiscontinuousConvMode, 62 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, 63 * InjecOversamplingMode, InjecOversampling. 64 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 65 * ADC state can be either: 66 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 67 * 'InjectedSingleDiff') 68 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled 69 * without conversion on going on injected group. 70 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'InjectedOffsetSign', 71 * 'InjectedOffsetSaturation', 'AutoInjectedConv': ADC enabled without conversion on going on regular and 72 * injected groups. 73 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 74 * 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going 75 * on ADC groups regular and injected. 76 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 77 * without error reporting (as it can be the expected behavior in case of intended action to update another 78 * parameter (which fulfills the ADC state condition) on the fly). 79 */ 80 typedef struct 81 { 82 uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. 83 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 84 Note: Depending on devices and ADC instances, some channels may not be 85 available on device package pins. Refer to device datasheet for 86 channels availability. */ 87 88 uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. 89 This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. 90 Note: to disable a channel or change order of conversion sequencer, 91 rank containing a previous channel setting can be overwritten by 92 the new channel setting (or parameter number of conversions 93 adjusted) */ 94 95 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 96 Unit: ADC clock cycles. 97 Conversion time is the addition of sampling time and processing time 98 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 99 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 100 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. 101 Caution: This parameter applies to a channel that can be used in a 102 regular and/or injected group. It overwrites the last setting. 103 Note: In case of usage of internal measurement channels (VrefInt, ...), 104 sampling time constraints must be respected (sampling time can be 105 adjusted in function of ADC clock frequency and sampling time 106 setting). Refer to device datasheet for timings values. */ 107 108 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. 109 In differential mode: Differential measurement is between the selected 110 channel 'i' (positive input) and channel 'i+1' (negative input). 111 Only channel 'i' has to be configured, channel 'i+1' is configured 112 automatically. 113 This parameter must be a value of 114 @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. 115 Caution: This parameter applies to a channel that can be used in a 116 regular and/or injected group. It overwrites the last setting. 117 Note: Refer to Reference Manual to ensure the selected channel is 118 available in differential mode. 119 Note: When configuring a channel 'i' in differential mode, the channel 120 'i+1' is not usable separately. 121 Note: This parameter must be modified when ADC is disabled (before ADC 122 start conversion or after ADC stop conversion). 123 If ADC is enabled, this parameter setting is bypassed without error 124 reporting (as it can be the expected behavior in case of another 125 parameter update on the fly) */ 126 127 uint32_t InjectedOffsetNumber; /*!< Selects the offset number. 128 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. 129 Caution: Only one offset is allowed per channel. This parameter 130 overwrites the last setting. */ 131 132 uint32_t InjectedOffset; /*!< Defines the offset to be applied on the raw converted data. 133 Offset value must be a positive number. 134 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this 135 parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 136 0x3FF, 0xFF or 0x3F respectively. 137 Note: This parameter must be modified when no conversion is on going 138 on both regular and injected groups (ADC disabled, or ADC enabled 139 without continuous mode or external trigger that could launch a 140 conversion). */ 141 142 uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added 143 (positive sign) from or to the raw converted data. 144 This parameter can be a value of @ref ADCEx_OffsetSign. 145 Note: This parameter must be modified when no conversion is on going 146 on both regular and injected groups (ADC disabled, or ADC 147 enabled without continuous mode or external trigger that could 148 launch a conversion). */ 149 FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. 150 This parameter value can be ENABLE or DISABLE. 151 Note: This parameter must be modified when no conversion is on going 152 on both regular and injected groups (ADC disabled, or ADC enabled 153 without continuous mode or external trigger that could launch a 154 conversion). */ 155 156 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group 157 injected sequencer. 158 To use the injected group sequencer and convert several ranks, parameter 159 'ScanConvMode' must be enabled. 160 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 161 Caution: this setting impacts the entire injected group. Therefore, 162 call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on 163 injected group can impact the configuration of other channels previously 164 set. */ 165 166 FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected 167 is performed in Complete-sequence/Discontinuous-sequence 168 (main sequence subdivided in successive parts). 169 Discontinuous mode is used only if sequencer is enabled (parameter 170 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 171 Discontinuous mode can be enabled only if continuous mode is disabled. 172 This parameter can be set to ENABLE or DISABLE. 173 Note: This parameter must be modified when ADC is disabled (before ADC 174 start conversion or after ADC stop conversion). 175 Note: For injected group, discontinuous mode converts the sequence 176 channel by channel (discontinuous length fixed to 1 rank). 177 Caution: this setting impacts the entire injected group. Therefore, 178 call of HAL_ADCEx_InjectedConfigChannel() to 179 configure a channel on injected group can impact the 180 configuration of other channels previously set. */ 181 182 FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion 183 after regular one 184 This parameter can be set to ENABLE or DISABLE. 185 Note: To use Automatic injected conversion, discontinuous mode must 186 be disabled ('DiscontinuousConvMode' and 187 'InjectedDiscontinuousConvMode' set to DISABLE) 188 Note: To use Automatic injected conversion, injected group external 189 triggers must be disabled ('ExternalTrigInjecConv' set to 190 ADC_INJECTED_SOFTWARE_START) 191 Note: In case of DMA used with regular group: if DMA configured in 192 normal mode (single shot) JAUTO will be stopped upon DMA transfer 193 complete. 194 To maintain JAUTO always enabled, DMA must be configured in 195 circular mode. 196 Caution: this setting impacts the entire injected group. Therefore, 197 call of HAL_ADCEx_InjectedConfigChannel() to configure a channel 198 on injected group can impact the configuration of other channels 199 previously set. */ 200 201 FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. 202 This parameter can be set to ENABLE or DISABLE. 203 If context queue is enabled, injected sequencer&channels configurations 204 are queued on up to 2 contexts. If a 205 new injected context is set when queue is full, error is triggered by 206 interruption and through function 207 'HAL_ADCEx_InjectedQueueOverflowCallback'. 208 Caution: This feature request that the sequence is fully configured 209 before injected conversion start. 210 Therefore, configure channels with as many calls to 211 HAL_ADCEx_InjectedConfigChannel() as the 212 'InjectedNbrOfConversion' parameter. 213 Caution: this setting impacts the entire injected group. Therefore, 214 call of HAL_ADCEx_InjectedConfigChannel() to 215 configure a channel on injected group can impact the 216 configuration of other channels previously set. 217 Note: This parameter must be modified when ADC is disabled (before ADC 218 start conversion or after ADC stop conversion). */ 219 220 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of 221 injected group. 222 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled 223 and software trigger is used instead. 224 This parameter can be a value of 225 @ref ADC_injected_external_trigger_source. 226 Caution: this setting impacts the entire injected group. Therefore, 227 call of HAL_ADCEx_InjectedConfigChannel() to configure a channel 228 on injected group can impact the configuration of other channels 229 previously set. */ 230 231 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 232 This parameter can be a value of @ref ADC_injected_external_trigger_edge. 233 If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter 234 is discarded. 235 Caution: this setting impacts the entire injected group. Therefore, 236 call of HAL_ADCEx_InjectedConfigChannel() to 237 configure a channel on injected group can impact the 238 configuration of other channels previously set. */ 239 240 FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. 241 This parameter can be set to ENABLE or DISABLE. 242 Note: This parameter can be modified only if there is no 243 conversion is ongoing (both ADSTART and JADSTART cleared). */ 244 245 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. 246 Caution: this setting overwrites the previous oversampling 247 configuration if oversampling already enabled. 248 Note: This parameter can be modified only if there is no 249 conversion is ongoing (both ADSTART and JADSTART cleared).*/ 250 } ADC_InjectionConfTypeDef; 251 252 #if defined(ADC_MULTIMODE_SUPPORT) 253 /** 254 * @brief Structure definition of ADC multimode 255 * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state 256 * (both Master and Slave ADCs). 257 * Both Master and Slave ADCs must be disabled. 258 */ 259 typedef struct 260 { 261 uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. 262 This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ 263 264 uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC: 265 selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel 266 (one DMA channel for both ADC, DMA of ADC master). 267 This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */ 268 269 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 270 This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. 271 Delay range depends on selected resolution: 272 from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, 273 from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */ 274 } ADC_MultiModeTypeDef; 275 #endif /* ADC_MULTIMODE_SUPPORT */ 276 277 /** 278 * @} 279 */ 280 281 /* Exported constants --------------------------------------------------------*/ 282 283 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants 284 * @{ 285 */ 286 287 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source 288 * @{ 289 */ 290 /* ADC group regular trigger sources for all ADC instances */ 291 #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< ADC group injected conversion 292 trigger software start */ 293 /* Triggers common to all devices of STM32H5 series */ 294 #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion 295 trigger from external peripheral: TIM1 TRGO event. */ 296 #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion 297 trigger from external peripheral: TIM1 channel 4 event (capture compare). */ 298 #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion 299 trigger from external peripheral: TIM2 TRGO event. */ 300 #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion 301 trigger from external peripheral: TIM2 channel 1 event (capture compare). */ 302 #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion 303 trigger from external peripheral: TIM3 channel 4 event (capture compare). */ 304 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion 305 trigger from external peripheral: external interrupt line 15. */ 306 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion 307 trigger from external peripheral: TIM1 TRGO2 event. */ 308 #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion 309 trigger from external peripheral: TIM3 channel 3 event (capture compare). */ 310 #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion 311 trigger from external peripheral: TIM3 TRGO event. */ 312 #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion 313 trigger from external peripheral: TIM3 channel 1 event (capture compare). */ 314 #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion 315 trigger from external peripheral: TIM6 TRGO event. */ 316 #define ADC_EXTERNALTRIGINJEC_LPTIM1_CH1 (LL_ADC_INJ_TRIG_EXT_LPTIM1_CH1) /*!< ADC group injected conversion 317 trigger from external peripheral: LPTIM1 channel 1 event. */ 318 #define ADC_EXTERNALTRIGINJEC_LPTIM2_CH1 (LL_ADC_INJ_TRIG_EXT_LPTIM2_CH1) /*!< ADC group injected conversion 319 trigger from external peripheral: LPTIM2 channel 1 event. */ 320 321 /* Triggers specific to some devices of STM32H5 series */ 322 #if defined(TIM8) 323 /* Devices STM32H563/H573xx */ 324 #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion 325 trigger from external peripheral: TIM4 TRGO event. 326 Specific to devices STM32H563/H573xx. */ 327 #define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion 328 trigger from external peripheral: TIM8 channel 4 event (capture compare). */ 329 #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion 330 trigger from external peripheral: TIM8 TRGO event. 331 Specific to devices STM32H563/H573xx. */ 332 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion 333 trigger from external peripheral: TIM8 TRGO2 event. 334 Specific to devices STM32H563/H573xx. */ 335 #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion 336 trigger from external peripheral: TIM15 TRGO event. 337 Specific to devices STM32H563/H573xx. */ 338 #else 339 /* Devices STM32H503xx */ 340 #define ADC_EXTERNALTRIGINJEC_T7_TRGO (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) /*!< ADC group injected conversion 341 trigger from external peripheral: TIM7 TRGO event. 342 Specific to devices STM32H503xx. */ 343 #endif /* Devices STM32H563/H573xx or STM32H503xx */ 344 /** 345 * @} 346 */ 347 348 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) 349 * @{ 350 */ 351 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions trigger 352 disabled (SW start)*/ 353 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions trigger 354 polarity set to rising edge */ 355 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions trigger 356 polarity set to falling edge */ 357 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions trigger 358 polarity set to both rising and falling edges */ 359 /** 360 * @} 361 */ 362 363 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending 364 * @{ 365 */ 366 #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended */ 367 #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential */ 368 /** 369 * @} 370 */ 371 372 /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number 373 * @{ 374 */ 375 #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected 376 ADC channel */ 377 #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which 378 the offset programmed will be applied (independently of channel mapped 379 on ADC group regular or group injected) */ 380 #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which 381 the offset programmed will be applied (independently of channel mapped 382 on ADC group regular or group injected) */ 383 #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which 384 the offset programmed will be applied (independently of channel mapped 385 on ADC group regular or group injected) */ 386 #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which 387 the offset programmed will be applied (independently of channel mapped 388 on ADC group regular or group injected) */ 389 /** 390 * @} 391 */ 392 393 /** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign 394 * @{ 395 */ 396 #define ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is subtracted */ 397 #define ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */ 398 /** 399 * @} 400 */ 401 402 /** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 403 * @{ 404 */ 405 #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ 406 #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ 407 #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ 408 #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ 409 /** 410 * @} 411 */ 412 413 #if defined(ADC_MULTIMODE_SUPPORT) 414 /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode 415 * @{ 416 */ 417 #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled 418 (ADC independent mode) */ 419 #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular 420 simultaneous */ 421 #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined 422 group regular interleaved */ 423 #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group 424 injected simultaneous */ 425 #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group 426 injected alternate trigger. Works only with external triggers (not internal 427 SW start) */ 428 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined 429 group regular simultaneous + group injected simultaneous */ 430 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined 431 group regular simultaneous + group injected alternate trigger */ 432 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined 433 group regular interleaved + group injected simultaneous */ 434 435 /** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution 436 * @{ 437 */ 438 #define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own 439 DMA channel */ 440 #define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, 441 DMA of ADC master) for 12 and 10 bits resolution */ 442 #define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, 443 DMA of ADC master) for 8 and 6 bits resolution */ 444 /** 445 * @} 446 */ 447 448 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 449 * @{ 450 */ 451 #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two 452 sampling phases: 1 ADC clock cycle */ 453 #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two 454 sampling phases: 2 ADC clock cycles */ 455 #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two 456 sampling phases: 3 ADC clock cycles */ 457 #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two 458 sampling phases: 4 ADC clock cycles */ 459 #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two 460 sampling phases: 5 ADC clock cycles */ 461 #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two 462 sampling phases: 6 ADC clock cycles */ 463 #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two 464 sampling phases: 7 ADC clock cycles */ 465 #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two 466 sampling phases: 8 ADC clock cycles */ 467 #define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two 468 sampling phases: 9 ADC clock cycles */ 469 #define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two 470 sampling phases: 10 ADC clock cycles */ 471 #define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two 472 sampling phases: 11 ADC clock cycles */ 473 #define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two 474 sampling phases: 12 ADC clock cycles */ 475 /** 476 * @} 477 */ 478 479 /** 480 * @} 481 */ 482 #endif /* ADC_MULTIMODE_SUPPORT */ 483 484 /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups 485 * @{ 486 */ 487 #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on 488 all STM32 devices) */ 489 #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on 490 all STM32 devices) */ 491 #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ 492 /** 493 * @} 494 */ 495 496 /** @defgroup ADC_CFGR_fields ADCx CFGR fields 497 * @{ 498 */ 499 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 500 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 501 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 502 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 503 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 504 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) 505 /** 506 * @} 507 */ 508 509 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields 510 * @{ 511 */ 512 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 513 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 514 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 515 ADC_SMPR1_SMP0) 516 /** 517 * @} 518 */ 519 520 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 521 * @{ 522 */ 523 /* ADC_CFGR fields of parameters that can be updated when no conversion 524 (neither regular nor injected) is on-going */ 525 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY)) 526 /** 527 * @} 528 */ 529 530 /** 531 * @} 532 */ 533 534 /* Exported macros -----------------------------------------------------------*/ 535 536 #if defined(ADC_MULTIMODE_SUPPORT) 537 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros 538 * @{ 539 */ 540 541 /** @brief Force ADC instance in multimode mode independent (multimode disable). 542 * @note This macro must be used only in case of transition from multimode 543 * to mode independent and in case of unknown previous state, 544 * to ensure ADC configuration is in mode independent. 545 * @note Standard way of multimode configuration change is done from 546 * HAL ADC handle of ADC master using function 547 * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". 548 * Usage of this macro is not the Standard way of multimode 549 * configuration and can lead to have HAL ADC handles status 550 * misaligned. Usage of this macro must be limited to cases 551 * mentioned above. 552 * @param __HANDLE__ ADC handle. 553 * @retval None 554 */ 555 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ 556 LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) 557 558 /** 559 * @} 560 */ 561 #endif /* ADC_MULTIMODE_SUPPORT */ 562 563 /* Private macros ------------------------------------------------------------*/ 564 565 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros 566 * @{ 567 */ 568 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 569 /* code of final user. */ 570 571 /** 572 * @brief Test if conversion trigger of injected group is software start 573 * or external trigger. 574 * @param __HANDLE__ ADC handle. 575 * @retval SET (software start) or RESET (external trigger). 576 */ 577 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 578 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) 579 580 /** 581 * @brief Check whether or not ADC is independent. 582 * @param __HANDLE__ ADC handle. 583 * @note When multimode feature is not available, the macro always returns SET. 584 * @retval SET (ADC is independent) or RESET (ADC is not). 585 */ 586 #define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) 587 588 /** 589 * @brief Set the selected injected Channel rank. 590 * @param __CHANNELNB__ Channel number. 591 * @param __RANKNB__ Rank number. 592 * @retval None 593 */ 594 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) \ 595 ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \ 596 << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) 597 598 /** 599 * @brief Configure ADC injected context queue 600 * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. 601 * @retval None 602 */ 603 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) \ 604 ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) 605 606 /** 607 * @brief Configure ADC discontinuous conversion mode for injected group 608 * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. 609 * @retval None 610 */ 611 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) \ 612 ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) 613 614 /** 615 * @brief Configure ADC discontinuous conversion mode for regular group 616 * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. 617 * @retval None 618 */ 619 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) \ 620 ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) 621 622 /** 623 * @brief Configure the number of discontinuous conversions for regular group. 624 * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. 625 * @retval None 626 */ 627 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) \ 628 (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) 629 630 /** 631 * @brief Configure the ADC auto delay mode. 632 * @param __AUTOWAIT__ Auto delay bit enable or disable. 633 * @retval None 634 */ 635 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) 636 637 /** 638 * @brief Configure ADC continuous conversion mode. 639 * @param __CONTINUOUS_MODE__ Continuous mode. 640 * @retval None 641 */ 642 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) 643 644 /** 645 * @brief Configure the ADC DMA continuous request. 646 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 647 * @retval None 648 */ 649 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos) 650 651 #if defined(ADC_MULTIMODE_SUPPORT) 652 /** 653 * @brief Configure the ADC DMA continuous request for ADC multimode. 654 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 655 * @retval None 656 */ 657 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) 658 #endif /* ADC_MULTIMODE_SUPPORT */ 659 660 /** 661 * @brief Shift the offset with respect to the selected ADC resolution. 662 * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. 663 * If resolution 12 bits, no shift. 664 * If resolution 10 bits, shift of 2 ranks on the left. 665 * If resolution 8 bits, shift of 4 ranks on the left. 666 * If resolution 6 bits, shift of 6 ranks on the left. 667 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 668 * @param __HANDLE__ ADC handle 669 * @param __OFFSET__ Value to be shifted 670 * @retval None 671 */ 672 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 673 ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) 674 675 /** 676 * @brief Shift the AWD1 threshold with respect to the selected ADC resolution. 677 * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. 678 * If resolution 12 bits, no shift. 679 * If resolution 10 bits, shift of 2 ranks on the left. 680 * If resolution 8 bits, shift of 4 ranks on the left. 681 * If resolution 6 bits, shift of 6 ranks on the left. 682 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 683 * @param __HANDLE__ ADC handle 684 * @param __THRESHOLD__ Value to be shifted 685 * @retval None 686 */ 687 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 688 ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) 689 690 /** 691 * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. 692 * @note Thresholds have to be left-aligned on bit 7. 693 * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded). 694 * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). 695 * If resolution 8 bits, no shift. 696 * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0). 697 * @param __HANDLE__ ADC handle 698 * @param __THRESHOLD__ Value to be shifted 699 * @retval None 700 */ 701 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 702 ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \ 703 ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ 704 ((__THRESHOLD__) << 2UL) \ 705 ) 706 707 /** 708 * @brief Clear Common Control Register. 709 * @param __HANDLE__ ADC handle. 710 * @retval None 711 */ 712 #if defined(ADC_MULTIMODE_SUPPORT) 713 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ 714 ADC_CCR_CKMODE | \ 715 ADC_CCR_PRESC | \ 716 ADC_CCR_VBATEN | \ 717 ADC_CCR_TSEN | \ 718 ADC_CCR_VREFEN | \ 719 ADC_CCR_MDMA | \ 720 ADC_CCR_DMACFG | \ 721 ADC_CCR_DELAY | \ 722 ADC_CCR_DUAL) 723 #else 724 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ 725 ADC_CCR_CKMODE | \ 726 ADC_CCR_PRESC | \ 727 ADC_CCR_VBATEN | \ 728 ADC_CCR_TSEN | \ 729 ADC_CCR_VREFEN) 730 731 #endif /* ADC_MULTIMODE_SUPPORT */ 732 733 /** 734 * @brief Set handle instance of the ADC slave associated to the ADC master. 735 * @param __HANDLE_MASTER__ ADC master handle. 736 * @param __HANDLE_SLAVE__ ADC slave handle. 737 * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC, __HANDLE_SLAVE__ instance is 738 * set to NULL. 739 * @retval None 740 */ 741 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 742 ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? \ 743 ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) ) 744 745 746 /** 747 * @brief Verify the ADC instance connected to the temperature sensor. 748 * @param __HANDLE__ ADC handle. 749 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 750 */ 751 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 752 753 /** 754 * @brief Verify the ADC instance connected to the battery voltage VBAT. 755 * @param __HANDLE__ ADC handle. 756 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 757 */ 758 #if defined(ADC2) 759 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) 760 #else 761 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 762 #endif /* ADC2 */ 763 764 /** 765 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. 766 * @param __HANDLE__ ADC handle. 767 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 768 */ 769 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 770 771 /** 772 * @brief Verify the ADC instance connected to the internal voltage reference VDDCORE. 773 * @param __HANDLE__ ADC handle. 774 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 775 */ 776 /* The internal voltage reference VDDCORE measurement path (channel 0) is available on ADC2 */ 777 #define ADC_VDDCORE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC1) 778 779 /** 780 * @brief Verify the length of scheduled injected conversions group. 781 * @param __LENGTH__ number of programmed conversions. 782 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) 783 * or RESET (__LENGTH__ is null or too large) 784 */ 785 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) 786 787 /** 788 * @brief Calibration factor size verification (7 bits maximum). 789 * @param __CALIBRATION_FACTOR__ Calibration factor value. 790 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 791 */ 792 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) 793 794 795 /** 796 * @brief Verify the ADC channel setting. 797 * @param __HANDLE__ ADC handle. 798 * @param __CHANNEL__ programmed ADC channel. 799 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 800 */ 801 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \ 802 ((__CHANNEL__) == ADC_CHANNEL_1) || \ 803 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 804 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 805 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 806 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 807 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 808 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 809 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 810 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 811 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 812 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 813 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 814 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 815 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 816 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 817 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 818 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 819 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 820 ((__CHANNEL__) == ADC_CHANNEL_19) || \ 821 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 822 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 823 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 824 ((__CHANNEL__) == ADC_CHANNEL_VDDCORE) ) 825 826 /** 827 * @brief Verify the ADC channel setting in differential mode. 828 * @param __HANDLE__ ADC handle. 829 * @param __CHANNEL__ programmed ADC channel. 830 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 831 */ 832 /** 833 * @brief Verify the ADC channel setting in differential mode for ADCx. 834 * @param __HANDLE__ ADC instance 835 * @param __CHANNEL__: programmed ADC channel. 836 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 837 */ 838 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) \ 839 ( ( ((__HANDLE__)->Instance == ADC1) \ 840 )? \ 841 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 842 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 843 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 844 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 845 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 846 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 847 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 848 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 849 ((__CHANNEL__) == ADC_CHANNEL_18) ) \ 850 : \ 851 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 852 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 853 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 854 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 855 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 856 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 857 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 858 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 859 ((__CHANNEL__) == ADC_CHANNEL_18) ) \ 860 ) 861 862 /** 863 * @brief Verify the ADC single-ended input or differential mode setting. 864 * @param __SING_DIFF__ programmed channel setting. 865 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) 866 */ 867 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ 868 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) 869 870 /** 871 * @brief Verify the ADC offset management setting. 872 * @param __OFFSET_NUMBER__ ADC offset management. 873 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) 874 */ 875 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ 876 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ 877 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ 878 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ 879 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) 880 881 /** 882 * @brief Verify the ADC offset sign setting. 883 * @param __OFFSET_SIGN__ ADC offset sign. 884 * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid) 885 */ 886 #define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__) (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \ 887 ((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE) ) 888 889 /** 890 * @brief Verify the ADC injected channel setting. 891 * @param __CHANNEL__ programmed ADC injected channel. 892 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 893 */ 894 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ 895 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ 896 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ 897 ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) 898 899 /** 900 * @brief Verify the ADC injected conversions external trigger. 901 * @param __HANDLE__ ADC handle. 902 * @param __INJTRIG__ programmed ADC injected conversions external trigger. 903 * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) 904 */ 905 #if defined(TIM8) 906 /* Devices STM32H563/H573xx */ 907 #define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 908 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 909 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 910 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 911 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 912 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 913 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 914 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 915 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 916 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 917 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 918 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 919 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 920 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 921 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 922 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 923 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_CH1) || \ 924 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_CH1) || \ 925 ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) 926 #else 927 /* Devices STM32H503xx */ 928 #define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 929 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 930 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 931 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 932 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 933 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 934 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 935 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 936 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 937 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 938 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 939 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ 940 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_CH1) || \ 941 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_CH1) || \ 942 ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) 943 #endif /* Devices STM32H563/H573xx or STM32H503xx */ 944 945 /** 946 * @brief Verify the ADC edge trigger setting for injected group. 947 * @param __EDGE__ programmed ADC edge trigger setting. 948 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 949 */ 950 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 951 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 952 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 953 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 954 955 #if defined(ADC_MULTIMODE_SUPPORT) 956 /** 957 * @brief Verify the ADC multimode setting. 958 * @param __MODE__ programmed ADC multimode setting. 959 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 960 */ 961 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ 962 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ 963 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ 964 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ 965 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ 966 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ 967 ((__MODE__) == ADC_DUALMODE_INTERL) || \ 968 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) 969 970 /** 971 * @brief Verify the ADC multimode DMA access setting. 972 * @param __MODE__ programmed ADC multimode DMA access setting. 973 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 974 */ 975 #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ 976 ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \ 977 ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) ) 978 979 /** 980 * @brief Verify the ADC multimode delay setting. 981 * @param __DELAY__ programmed ADC multimode delay setting. 982 * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) 983 */ 984 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ 985 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ 986 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ 987 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ 988 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 989 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 990 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 991 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 992 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ 993 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ 994 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ 995 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) 996 #endif /* ADC_MULTIMODE_SUPPORT */ 997 998 /** 999 * @brief Verify the ADC analog watchdog setting. 1000 * @param __WATCHDOG__ programmed ADC analog watchdog setting. 1001 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) 1002 */ 1003 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ 1004 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ 1005 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) 1006 1007 /** 1008 * @brief Verify the ADC analog watchdog mode setting. 1009 * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. 1010 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) 1011 */ 1012 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ 1013 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 1014 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 1015 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 1016 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 1017 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 1018 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 1019 1020 /** 1021 * @brief Verify the ADC analog watchdog filtering setting. 1022 * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting. 1023 * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid) 1024 */ 1025 #define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) \ 1026 (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE) || \ 1027 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES) || \ 1028 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES) || \ 1029 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES) || \ 1030 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES) || \ 1031 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES) || \ 1032 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES) || \ 1033 ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES) ) 1034 1035 1036 /** 1037 * @brief Verify the ADC conversion (regular or injected or both). 1038 * @param __CONVERSION__ ADC conversion group. 1039 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) 1040 */ 1041 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ 1042 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ 1043 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) 1044 1045 /** 1046 * @brief Verify the ADC event type. 1047 * @param __EVENT__ ADC event. 1048 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) 1049 */ 1050 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ 1051 ((__EVENT__) == ADC_AWD_EVENT) || \ 1052 ((__EVENT__) == ADC_AWD2_EVENT) || \ 1053 ((__EVENT__) == ADC_AWD3_EVENT) || \ 1054 ((__EVENT__) == ADC_OVR_EVENT) || \ 1055 ((__EVENT__) == ADC_JQOVF_EVENT) ) 1056 1057 /** 1058 * @brief Verify the ADC oversampling ratio. 1059 * @param __RATIO__ programmed ADC oversampling ratio. 1060 * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) 1061 */ 1062 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ 1063 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ 1064 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ 1065 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ 1066 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ 1067 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ 1068 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ 1069 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) 1070 1071 /** 1072 * @brief Verify the ADC oversampling shift. 1073 * @param __SHIFT__ programmed ADC oversampling shift. 1074 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 1075 */ 1076 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 1077 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 1078 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 1079 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 1080 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 1081 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 1082 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 1083 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 1084 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) 1085 1086 /** 1087 * @brief Verify the ADC oversampling triggered mode. 1088 * @param __MODE__ programmed ADC oversampling triggered mode. 1089 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1090 */ 1091 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 1092 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 1093 1094 /** 1095 * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 1096 * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. 1097 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1098 */ 1099 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ 1100 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) 1101 1102 /** 1103 * @brief Verify the DFSDM mode configuration. 1104 * @param __HANDLE__ ADC handle. 1105 * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For 1106 * this reason, the input parameter is the ADC handle and not the configuration parameter 1107 * directly. 1108 * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) 1109 */ 1110 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) 1111 1112 /** 1113 * @brief Return the DFSDM configuration mode. 1114 * @param __HANDLE__ ADC handle. 1115 * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). 1116 * For this reason, the input parameter is the ADC handle and not the configuration parameter 1117 * directly. 1118 * @retval DFSDM configuration mode 1119 */ 1120 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) 1121 1122 /** 1123 * @} 1124 */ 1125 1126 1127 /* Exported functions --------------------------------------------------------*/ 1128 /** @addtogroup ADCEx_Exported_Functions 1129 * @{ 1130 */ 1131 1132 /** @addtogroup ADCEx_Exported_Functions_Group1 1133 * @{ 1134 */ 1135 /* IO operation functions *****************************************************/ 1136 1137 /* ADC calibration */ 1138 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 1139 uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 1140 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, 1141 uint32_t CalibrationFactor); 1142 1143 /* Blocking mode: Polling */ 1144 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); 1145 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); 1146 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1147 1148 /* Non-blocking mode: Interruption */ 1149 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); 1150 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); 1151 1152 #if defined(ADC_MULTIMODE_SUPPORT) 1153 /* ADC multimode */ 1154 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1155 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1156 uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc); 1157 #endif /* ADC_MULTIMODE_SUPPORT */ 1158 1159 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1160 uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank); 1161 1162 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 1163 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); 1164 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); 1165 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); 1166 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); 1167 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); 1168 1169 /* ADC group regular conversions stop */ 1170 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); 1171 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); 1172 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); 1173 #if defined(ADC_MULTIMODE_SUPPORT) 1174 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1175 #endif /* ADC_MULTIMODE_SUPPORT */ 1176 1177 /** 1178 * @} 1179 */ 1180 1181 /** @addtogroup ADCEx_Exported_Functions_Group2 1182 * @{ 1183 */ 1184 /* Peripheral Control functions ***********************************************/ 1185 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, 1186 const ADC_InjectionConfTypeDef *pConfigInjected); 1187 #if defined(ADC_MULTIMODE_SUPPORT) 1188 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, 1189 const ADC_MultiModeTypeDef *pMultimode); 1190 #endif /* ADC_MULTIMODE_SUPPORT */ 1191 1192 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); 1193 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); 1194 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); 1195 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); 1196 1197 /** 1198 * @} 1199 */ 1200 1201 /** 1202 * @} 1203 */ 1204 1205 /** 1206 * @} 1207 */ 1208 1209 /** 1210 * @} 1211 */ 1212 1213 #ifdef __cplusplus 1214 } 1215 #endif 1216 1217 #endif /* STM32H5xx_HAL_ADC_EX_H */ 1218
