1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H5xx_HAL_ADC_H 21 #define STM32H5xx_HAL_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /* Include low level driver */ 31 #include "stm32h5xx_ll_adc.h" 32 33 /** @addtogroup STM32H5xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup ADC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup ADC_Exported_Types ADC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief ADC group regular oversampling structure definition 48 */ 49 typedef struct 50 { 51 uint32_t Ratio; /*!< Configures the oversampling ratio. 52 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 53 54 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 55 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 56 57 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 58 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 59 60 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. 61 The oversampling is either temporary stopped or reset upon an injected 62 sequence interruption. 63 If oversampling is enabled on both regular and injected groups, this 64 parameter is discarded and forced to setting 65 "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed 66 during injection sequence). 67 This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ 68 69 } ADC_OversamplingTypeDef; 70 71 /** 72 * @brief Structure definition of ADC instance and ADC group regular. 73 * @note Parameters of this structure are shared within 2 scopes: 74 * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, 75 * ScanConvMode, EOCSelection, LowPowerAutoWait. 76 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, 77 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling, 78 * SamplingMode. 79 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 80 * ADC state can be either: 81 * - For all parameters: ADC disabled 82 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled 83 * without conversion on going on group regular. 84 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going 85 * on groups regular and injected. 86 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 87 * without error reporting (as it can be the expected behavior in case of intended action to update another 88 * parameter (which fulfills the ADC state condition) on the fly). 89 */ 90 typedef struct 91 { 92 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous 93 clock derived from system clock or PLL (Refer to reference manual for list of 94 clocks available)) and clock prescaler. 95 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. 96 Note: The ADC clock configuration is common to all ADC instances. 97 Note: In case of usage of channels on injected group, ADC frequency should be 98 lower than AHB clock frequency /4 for resolution 12 or 10 bits, 99 AHB clock frequency /3 for resolution 8 bits, 100 AHB clock frequency /2 for resolution 6 bits. 101 Note: In case of synchronous clock mode based on HCLK/1, the configuration must 102 be enabled only if the system clock has a 50% duty clock cycle (APB 103 prescaler configured inside RCC must be bypassed and PCLK clock must have 104 50% duty cycle). Refer to reference manual for details. 105 Note: In case of usage of asynchronous clock, the selected clock must be 106 preliminarily enabled at RCC top level. 107 Note: This parameter can be modified only if all ADC instances are disabled. */ 108 109 uint32_t Resolution; /*!< Configure the ADC resolution. 110 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 111 112 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). 113 Refer to reference manual for alignments formats versus resolutions. 114 This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ 115 116 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. 117 This parameter can be associated to parameter 'DiscontinuousConvMode' to have 118 main sequence subdivided in successive parts. 119 If disabled: Conversion is performed in single mode (one channel converted, the 120 one defined in rank 1). Parameters 'NbrOfConversion' and 121 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 122 If enabled: Conversions are performed in sequence mode (multiple ranks defined 123 by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each 124 channel in sequencer). Scan direction is upward: from rank 1 to 125 rank 'n'. 126 This parameter can be a value of @ref ADC_Scan_mode */ 127 128 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and 129 interruption: end of unitary conversion or end of sequence conversions. 130 This parameter can be a value of @ref ADC_EOCSelection. */ 131 132 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the 133 previous conversion (for ADC group regular) or previous sequence (for ADC group 134 injected) has been retrieved by user software, using function HAL_ADC_GetValue() 135 or HAL_ADCEx_InjectedGetValue(). 136 This feature automatically adapts the frequency of ADC conversions triggers to 137 the speed of the system that reads the data. Moreover, this avoids risk of 138 overrun for low frequency applications. 139 This parameter can be set to ENABLE or DISABLE. 140 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), 141 HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC 142 flag (by CPU to free the IRQ pending event or by DMA). 143 Auto wait will work but fort a very short time, discarding its intended 144 benefit (except specific case of high load of CPU or DMA transfers which 145 can justify usage of auto wait). 146 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, 147 when ADC conversion data is needed: 148 use HAL_ADC_PollForConversion() to ensure that conversion is completed and 149 HAL_ADC_GetValue() to retrieve conversion result and trig another 150 conversion start. (in case of usage of ADC group injected, use the 151 equivalent functions HAL_ADCExInjected_Start(), 152 HAL_ADCEx_InjectedGetValue(), ...). */ 153 154 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) 155 or continuous mode for ADC group regular, after the first ADC conversion 156 start trigger occurred (software start or external trigger). This parameter 157 can be set to ENABLE or DISABLE. */ 158 159 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group 160 sequencer. 161 This parameter is dependent on ScanConvMode: 162 - sequencer configured to fully configurable: 163 Number of ranks in the scan sequence is configurable using this parameter. 164 Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to 165 parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. 166 Afterwards, when all needed sequencer ranks are set, parameter 167 'NbrOfConversion' can be updated without modifying configuration of 168 sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded). 169 - sequencer configured to not fully configurable: 170 Number of ranks in the scan sequence is defined by number of channels set in 171 the sequence. This parameter is discarded. 172 This parameter must be a number between Min_Data = 1 and Max_Data = 8. 173 Note: This parameter must be modified when no conversion is on going on regular 174 group (ADC disabled, or ADC enabled without continuous mode or external 175 trigger that could launch a conversion). */ 176 177 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed 178 in Complete-sequence/Discontinuous-sequence (main sequence subdivided in 179 successive parts). 180 Discontinuous mode is used only if sequencer is enabled (parameter 181 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 182 Discontinuous mode can be enabled only if continuous mode is disabled. 183 If continuous mode is enabled, this parameter setting is discarded. 184 This parameter can be set to ENABLE or DISABLE. 185 Note: On this STM32 series, ADC group regular number of discontinuous 186 ranks increment is fixed to one-by-one. */ 187 188 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence 189 of ADC group regular (parameter NbrOfConversion) will be subdivided. 190 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 191 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 192 193 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion 194 start. 195 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger 196 is used instead. 197 This parameter can be a value of @ref ADC_regular_external_trigger_source. 198 Caution: external trigger source is common to all ADC instances. */ 199 200 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start 201 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 202 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 203 204 uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion. 205 This parameter can be a value of @ref ADC_regular_sampling_mode */ 206 207 FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA 208 transfer stops when number of conversions is reached) or in continuous 209 mode (DMA transfer unlimited, whatever number of conversions). 210 This parameter can be set to ENABLE or DISABLE. 211 Note: In continuous mode, DMA must be configured in circular mode. 212 Otherwise an overrun will be triggered when DMA buffer maximum 213 pointer is reached. */ 214 215 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 216 This parameter applies to ADC group regular only. 217 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 218 Note: In case of overrun set to data preserved and usage with programming model 219 with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of 220 conversion flags, this induces the release of the preserved data. If 221 needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), 222 placed in user program code (called before end of conversion flags clear) 223 Note: Error reporting with respect to the conversion mode: 224 - Usage with ADC conversion by polling for event or interruption: Error is 225 reported only if overrun is set to data preserved. If overrun is set to 226 data overwritten, user can willingly not read all the converted data, 227 this is not considered as an erroneous case. 228 - Usage with ADC conversion by DMA: Error is reported whatever overrun 229 setting (DMA is expected to process all data from data register). */ 230 231 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 232 This parameter can be set to ENABLE or DISABLE. 233 Note: This parameter can be modified only if there is no conversion is 234 ongoing on ADC groups regular and injected */ 235 236 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 237 Caution: this setting overwrites the previous oversampling configuration 238 if oversampling is already enabled. */ 239 240 } ADC_InitTypeDef; 241 242 /** 243 * @brief Structure definition of ADC channel for regular group 244 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 245 * ADC state can be either: 246 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') 247 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion 248 * on going on regular group. 249 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on 250 * regular and injected groups. 251 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 252 * without error reporting (as it can be the expected behavior in case of intended action to update another 253 * parameter (which fulfills the ADC state condition) on the fly). 254 */ 255 typedef struct 256 { 257 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 258 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 259 Note: Depending on devices and ADC instances, some channels may not be available 260 on device package pins. Refer to device datasheet for channels 261 availability. */ 262 263 uint32_t Rank; /*!< Specify the rank in the regular group sequencer. 264 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS 265 Note: to disable a channel or change order of conversion sequencer, rank 266 containing a previous channel setting can be overwritten by the new channel 267 setting (or parameter number of conversions adjusted) */ 268 269 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 270 Unit: ADC clock cycles 271 Conversion time is the addition of sampling time and processing time 272 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 273 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 274 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 275 Caution: This parameter applies to a channel that can be used into regular 276 and/or injected group. It overwrites the last setting. 277 Note: In case of usage of internal measurement channels (VrefInt, Vbat, ...), 278 sampling time constraints must be respected (sampling time can be adjusted 279 in function of ADC clock frequency and sampling time setting). 280 Refer to device datasheet for timings values. */ 281 282 uint32_t SingleDiff; /*!< Select single-ended or differential input. 283 In differential mode: Differential measurement is carried out between the 284 selected channel 'i' (positive input) and channel 'i+1' (negative input). 285 Only channel 'i' has to be configured, channel 'i+1' is configured automatically 286 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING 287 Caution: This parameter applies to a channel that can be used in a regular 288 and/or injected group. 289 It overwrites the last setting. 290 Note: Refer to Reference Manual to ensure the selected channel is available in 291 differential mode. 292 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is 293 not usable separately. 294 Note: This parameter must be modified when ADC is disabled (before ADC start 295 conversion or after ADC stop conversion). 296 If ADC is enabled, this parameter setting is bypassed without error 297 reporting (as it can be the expected behavior in case of another parameter 298 update on the fly) */ 299 300 uint32_t OffsetNumber; /*!< Select the offset number 301 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB 302 Caution: Only one offset is allowed per channel. This parameter overwrites the 303 last setting. */ 304 305 uint32_t Offset; /*!< Define the offset to be applied on the raw converted data. 306 Offset value must be a positive number. 307 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter 308 must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 309 0x3FF, 0xFF or 0x3F respectively. 310 Note: This parameter must be modified when no conversion is on going on both 311 regular and injected groups (ADC disabled, or ADC enabled without 312 continuous mode or external trigger that could launch a conversion). */ 313 314 uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive 315 sign) from or to the raw converted data. 316 This parameter can be a value of @ref ADCEx_OffsetSign. 317 Note: This parameter must be modified when no conversion is on going on both 318 regular and injected groups (ADC disabled, or ADC enabled without 319 continuous mode or external trigger that could launch a conversion).*/ 320 FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. 321 This parameter value can be ENABLE or DISABLE. 322 Note: This parameter must be modified when no conversion is on going on both 323 regular and injected groups (ADC disabled, or ADC enabled without 324 continuous mode or external trigger that could launch a conversion). */ 325 326 } ADC_ChannelConfTypeDef; 327 328 /** 329 * @brief Structure definition of ADC analog watchdog 330 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 331 * ADC state can be either: 332 * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion 333 on going on ADC groups regular and injected. 334 * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and 335 injected groups. 336 */ 337 typedef struct 338 { 339 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 340 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels 341 by setting parameter 'WatchdogMode') 342 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls 343 of 'HAL_ADC_AnalogWDGConfig()' for each channel) 344 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 345 346 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 347 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all 348 channels, ADC groups regular and-or injected. 349 For Analog Watchdog 2 and 3: Several channels can be monitored by applying 350 successively the AWD init structure. Channels on ADC 351 group regular and injected are not differentiated: Set 352 value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 353 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor 354 all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no 355 channel. 356 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 357 358 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 359 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' 360 is configured on single channel (only 1 channel can be 361 monitored). 362 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, 363 call successively the function HAL_ADC_AnalogWDGConfig() 364 for each channel to be added (or removed with value 365 'ADC_ANALOGWATCHDOG_NONE'). 366 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 367 368 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 369 This parameter can be set to ENABLE or DISABLE */ 370 371 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 372 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a 373 number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F 374 respectively. 375 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC 376 resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 377 LSB are ignored. 378 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 379 impacted: the comparison of analog watchdog thresholds is done on 380 oversampling final computation (after ratio and shift application): 381 ADC data register bitfield [15:4] (12 most significant bits). */ 382 383 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 384 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a 385 number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F 386 respectively. 387 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC 388 resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 389 LSB are ignored. 390 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 391 impacted: the comparison of analog watchdog thresholds is done on 392 oversampling final computation (after ratio and shift application): 393 ADC data register bitfield [15:4] (12 most significant bits).*/ 394 395 uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider. 396 Before setting flag or raising interrupt, analog watchdog can wait to have several 397 consecutive out-of-window samples. This parameter allows to configure this number. 398 This parameter only applies to Analog watchdog 1. For others, use value 399 ADC_AWD_FILTERING_NONE. 400 This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */ 401 } ADC_AnalogWDGConfTypeDef; 402 403 /** 404 * @brief ADC group injected contexts queue configuration 405 * @note Structure intended to be used only through structure "ADC_HandleTypeDef" 406 */ 407 typedef struct 408 { 409 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each 410 HAL_ADCEx_InjectedConfigChannel() call to finally initialize 411 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ 412 413 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ 414 } ADC_InjectionConfigTypeDef; 415 416 /** @defgroup ADC_States ADC States 417 * @{ 418 */ 419 420 /** 421 * @brief HAL ADC state machine: ADC states definition (bitfields) 422 * @note ADC state machine is managed by bitfields, state must be compared 423 * with bit by bit. 424 * For example: 425 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " 426 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " 427 */ 428 /* States of ADC global scope */ 429 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ 430 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ 431 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, 432 calibration, ...) */ 433 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ 434 435 /* States of ADC errors */ 436 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ 437 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ 438 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ 439 440 /* States of ADC group regular */ 441 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur 442 (either by continuous mode, external trigger, low power 443 auto power-on (if feature available), multimode ADC master 444 control (if feature available)) */ 445 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ 446 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ 447 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag 448 raised */ 449 450 /* States of ADC group injected */ 451 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur 452 (either by auto-injection mode, external trigger, low 453 power auto power-on (if feature available), multimode 454 ADC master control (if feature available)) */ 455 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ 456 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ 457 458 /* States of ADC analog watchdogs */ 459 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 460 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ 461 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ 462 463 /* States of ADC multi-mode */ 464 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC 465 master (when feature available) */ 466 467 /** 468 * @} 469 */ 470 471 /** 472 * @brief ADC handle Structure definition 473 */ 474 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 475 typedef struct __ADC_HandleTypeDef 476 #else 477 typedef struct 478 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 479 { 480 ADC_TypeDef *Instance; /*!< Register base address */ 481 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular 482 conversions setting */ 483 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 484 HAL_LockTypeDef Lock; /*!< ADC locking object */ 485 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 486 __IO uint32_t ErrorCode; /*!< ADC Error code */ 487 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up 488 structure */ 489 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 490 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 491 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer 492 callback */ 493 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 494 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 495 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete 496 callback */ 497 void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue 498 overflow callback */ 499 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 500 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 501 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 502 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 503 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 504 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 505 } ADC_HandleTypeDef; 506 507 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 508 /** 509 * @brief HAL ADC Callback ID enumeration definition 510 */ 511 typedef enum 512 { 513 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 514 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 515 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 516 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 517 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 518 HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ 519 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 520 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 521 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 522 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 523 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 524 } HAL_ADC_CallbackIDTypeDef; 525 526 /** 527 * @brief HAL ADC Callback pointer definition 528 */ 529 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 530 531 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 532 533 /** 534 * @} 535 */ 536 537 538 /* Exported constants --------------------------------------------------------*/ 539 540 /** @defgroup ADC_Exported_Constants ADC Exported Constants 541 * @{ 542 */ 543 544 /** @defgroup ADC_Error_Code ADC Error Code 545 * @{ 546 */ 547 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 548 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, 549 enable/disable, erroneous state, ...) */ 550 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 551 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 552 #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ 553 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 554 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 555 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 556 /** 557 * @} 558 */ 559 560 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 561 * @{ 562 */ 563 564 #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock 565 without prescaler */ 566 #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock 567 with prescaler division by 2 */ 568 #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock 569 with prescaler division by 4 */ 570 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without 571 prescaler */ 572 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler 573 division by 2 */ 574 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler 575 division by 4 */ 576 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler 577 division by 6 */ 578 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler 579 division by 8 */ 580 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler 581 division by 10 */ 582 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler 583 division by 12 */ 584 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler 585 division by 16 */ 586 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler 587 division by 32 */ 588 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler 589 division by 64 */ 590 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler 591 division by 128 */ 592 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler 593 division by 256 */ 594 /** 595 * @} 596 */ 597 598 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 599 * @{ 600 */ 601 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 602 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 603 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 604 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ 605 /** 606 * @} 607 */ 608 609 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment 610 * @{ 611 */ 612 #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned 613 (alignment on data register LSB bit 0)*/ 614 #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned 615 (alignment on data register MSB bit 15)*/ 616 /** 617 * @} 618 */ 619 620 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 621 * @{ 622 */ 623 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ 624 #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ 625 /** 626 * @} 627 */ 628 629 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 630 * @{ 631 */ 632 /* ADC group regular trigger sources for all ADC instances */ 633 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion 634 trigger software start */ 635 /* Triggers common to all devices of STM32H5 series */ 636 #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion 637 trigger from external peripheral: TIM1 channel 1 event (capture compare). */ 638 #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion 639 trigger from external peripheral: TIM1 channel 2 event (capture compare). */ 640 #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion 641 trigger from external peripheral: TIM1 channel 3 event (capture compare). */ 642 #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion 643 trigger from external peripheral: TIM2 channel 2 event (capture compare). */ 644 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion 645 trigger from external peripheral: TIM3 TRGO event. */ 646 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion 647 trigger from external peripheral: external interrupt line 11 event. */ 648 #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion 649 trigger from external peripheral: TIM1 TRGO event. */ 650 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion 651 trigger from external peripheral: TIM1 TRGO2 event. */ 652 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion 653 trigger from external peripheral: TIM2 TRGO event. */ 654 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion 655 trigger from external peripheral: TIM6 TRGO event. */ 656 #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion 657 trigger from external peripheral: TIM3 channel 4 event (capture compare). */ 658 #define ADC_EXTERNALTRIG_EXT_IT15 (LL_ADC_REG_TRIG_EXT_EXTI_LINE15) /*!< ADC group regular conversion 659 trigger from external peripheral: external interrupt line 15 event. */ 660 #define ADC_EXTERNALTRIG_LPTIM1_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) /*!< ADC group regular conversion 661 trigger from external peripheral: LPTIM1 channel 1 event. */ 662 #define ADC_EXTERNALTRIG_LPTIM2_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) /*!< ADC group regular conversion 663 trigger from external peripheral: LPTIM2 channel 1 event. */ 664 665 /* Triggers specific to some devices of STM32H5 series */ 666 #if defined(TIM8) 667 /* Devices STM32H563/H573xx */ 668 #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion 669 trigger from external peripheral: TIM4 channel 4 event (capture compare). 670 Specific to devices STM32H563/H573xx. */ 671 #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion 672 trigger from external peripheral: TIM8 TRGO event. 673 Specific to devices STM32H563/H573xx. */ 674 #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion 675 trigger from external peripheral: TIM8 TRGO2 event. 676 Specific to devices STM32H563/H573xx. */ 677 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion 678 trigger from external peripheral: TIM4 TRGO event. 679 Specific to devices STM32H563/H573xx. */ 680 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion 681 trigger from external peripheral: TIM15 TRGO event. 682 Specific to devices STM32H563/H573xx. */ 683 #else 684 /* Devices STM32H503xx */ 685 #define ADC_EXTERNALTRIG_T7_TRGO (LL_ADC_REG_TRIG_EXT_TIM7_TRGO) /*!< ADC group regular conversion 686 trigger from external peripheral: TIM7 TRGO event. 687 Specific to devices STM32H503xx. */ 688 #endif /* Devices STM32H563/H573xx or STM32H503xx */ 689 /** 690 * @} 691 */ 692 693 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 694 * @{ 695 */ 696 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger 697 disabled (SW start)*/ 698 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion 699 trigger polarity set to rising edge */ 700 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion 701 trigger polarity set to falling edge */ 702 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion 703 trigger polarity set to both rising and falling edges */ 704 /** 705 * @} 706 */ 707 708 /** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode 709 * @{ 710 */ 711 #define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is 712 defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */ 713 #define ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts 714 immediately after end of conversion, and stops upon trigger event. 715 Note: First conversion is using minimal sampling time 716 (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */ 717 #define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled 718 by trigger events: 719 Trigger rising edge = start sampling 720 Trigger falling edge = stop sampling and start conversion */ 721 /** 722 * @} 723 */ 724 725 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 726 * @{ 727 */ 728 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 729 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 730 /** 731 * @} 732 */ 733 734 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 735 * @{ 736 */ 737 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case 738 of overrun: data preserved */ 739 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case 740 of overrun: data overwritten */ 741 /** 742 * @} 743 */ 744 745 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 746 * @{ 747 */ 748 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 749 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 750 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 751 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 752 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 753 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 754 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 755 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 756 #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ 757 #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ 758 #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ 759 #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ 760 #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ 761 #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ 762 #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ 763 #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ 764 /** 765 * @} 766 */ 767 768 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 769 * @{ 770 */ 771 #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ 772 #define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */ 773 #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ 774 #define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */ 775 #define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */ 776 #define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */ 777 #define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */ 778 #define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */ 779 #define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 780 ADC clock cycles. If selected, this sampling time replaces sampling time 781 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */ 782 /** 783 * @} 784 */ 785 786 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 787 * @{ 788 */ 789 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ 790 /* all ADC instances (refer to Reference Manual). */ 791 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */ 792 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */ 793 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */ 794 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */ 795 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */ 796 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */ 797 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */ 798 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */ 799 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */ 800 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */ 801 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */ 802 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */ 803 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */ 804 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */ 805 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */ 806 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */ 807 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */ 808 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */ 809 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< External channel (GPIO pin) ADCx_IN18 */ 810 #define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19) /*!< External channel (GPIO pin) ADCx_IN19 */ 811 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: Internal 812 voltage reference, channel specific to ADC1. */ 813 #define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor, 814 channel specific to ADC1. */ 815 #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/4: Vbat voltage 816 through a divider ladder of factor 1/4 to have channel voltage always below 817 Vdda, channel specific to ADC2. */ 818 #define ADC_CHANNEL_VDDCORE (LL_ADC_CHANNEL_VDDCORE) /*!< Internal channel Vddcore, channel 819 specific to ADC2. */ 820 /** 821 * @} 822 */ 823 824 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number 825 * @{ 826 */ 827 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 828 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 829 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 830 /** 831 * @} 832 */ 833 834 /** @defgroup ADC_analog_watchdog_filtering_config ADC analog watchdog (AWD) filtering configuration 835 * @{ 836 */ 837 #define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC AWD no filtering, one 838 out-of-window sample to raise flag or interrupt */ 839 #define ADC_AWD_FILTERING_2SAMPLES ((ADC_TR1_AWDFILT_0)) /*!< ADC AWD 2 consecutives 840 out-of-window samples to raise flag or interrupt */ 841 #define ADC_AWD_FILTERING_3SAMPLES ((ADC_TR1_AWDFILT_1)) /*!< ADC AWD 3 consecutives 842 out-of-window samples to raise flag or interrupt */ 843 #define ADC_AWD_FILTERING_4SAMPLES ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 4 consecutives 844 out-of-window samples to raise flag or interrupt */ 845 #define ADC_AWD_FILTERING_5SAMPLES ((ADC_TR1_AWDFILT_2)) /*!< ADC AWD 5 consecutives 846 out-of-window samples to raise flag or interrupt */ 847 #define ADC_AWD_FILTERING_6SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 6 consecutives 848 out-of-window samples to raise flag or interrupt */ 849 #define ADC_AWD_FILTERING_7SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)) /*!< ADC AWD 7 consecutives 850 out-of-window samples to raise flag or interrupt */ 851 #define ADC_AWD_FILTERING_8SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \ 852 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 8 consecutives 853 out-of-window samples to raise flag or interrupt */ 854 /** 855 * @} 856 */ 857 858 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode 859 * @{ 860 */ 861 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */ 862 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< ADC AWD applied to a regular 863 group single channel */ 864 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to an 865 injected group single channel */ 866 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN\ 867 | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to a regular 868 and injected groups single channel */ 869 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< ADC AWD applied to regular 870 group all channels */ 871 #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to injected 872 group all channels */ 873 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to regular 874 and injected groups all channels */ 875 /** 876 * @} 877 */ 878 879 /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio 880 * @{ 881 */ 882 /** 883 * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed 884 * to result as the ADC oversampling conversion data (before potential shift) 885 */ 886 #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */ 887 #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */ 888 #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */ 889 #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */ 890 #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */ 891 #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */ 892 #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */ 893 #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */ 894 /** 895 * @} 896 */ 897 898 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 899 * @{ 900 */ 901 /** 902 * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling 903 * conversion data) 904 */ 905 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */ 906 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */ 907 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */ 908 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */ 909 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */ 910 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */ 911 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */ 912 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */ 913 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */ 914 /** 915 * @} 916 */ 917 918 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 919 * @{ 920 */ 921 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: 922 continuous mode (all conversions of OVS ratio are done from 1 trigger) */ 923 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: 924 discontinuous mode (each conversion of OVS ratio needs a trigger) */ 925 /** 926 * @} 927 */ 928 929 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular 930 * @{ 931 */ 932 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained 933 during injection sequence */ 934 #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during 935 injection sequence */ 936 /** 937 * @} 938 */ 939 940 /** @defgroup ADC_Event_type ADC Event type 941 * @{ 942 */ 943 /** 944 * @note Analog watchdog 1 is available on all stm32 series 945 * Analog watchdog 2 and 3 are not available on all series 946 */ 947 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 948 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */ 949 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */ 950 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */ 951 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 952 #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ 953 /** 954 * @} 955 */ 956 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility 957 with other STM32 devices having only one analog watchdog */ 958 959 /** @defgroup ADC_interrupts_definition ADC interrupts definition 960 * @{ 961 */ 962 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 963 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 964 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 965 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 966 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 967 #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ 968 #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ 969 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 970 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog 971 watchdog) */ 972 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog 973 watchdog) */ 974 #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ 975 976 /** 977 * @} 978 */ 979 980 /** @defgroup ADC_flags_definition ADC flags definition 981 * @{ 982 */ 983 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 984 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 985 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 986 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 987 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 988 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ 989 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ 990 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ 991 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ 992 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ 993 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ 994 995 /** 996 * @} 997 */ 998 999 /** 1000 * @} 1001 */ 1002 1003 /* Private macro -------------------------------------------------------------*/ 1004 1005 /** @defgroup ADC_Private_Macros ADC Private Macros 1006 * @{ 1007 */ 1008 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 1009 /* code of final user. */ 1010 1011 /** 1012 * @brief Return resolution bits in CFGR register RES[1:0] field. 1013 * @param __HANDLE__ ADC handle 1014 * @retval Value of bitfield RES in CFGR register. 1015 */ 1016 #define ADC_GET_RESOLUTION(__HANDLE__) \ 1017 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 1018 1019 /** 1020 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 1021 * @param __HANDLE__ ADC handle 1022 * @retval None 1023 */ 1024 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 1025 1026 /** 1027 * @brief Simultaneously clear and set specific bits of the handle State. 1028 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 1029 * the first parameter is the ADC handle State, the second parameter is the 1030 * bit field to clear, the third and last parameter is the bit field to set. 1031 * @retval None 1032 */ 1033 #define ADC_STATE_CLR_SET MODIFY_REG 1034 1035 /** 1036 * @brief Verify that a given value is aligned with the ADC resolution range. 1037 * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). 1038 * @param __ADC_VALUE__ value checked against the resolution. 1039 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 1040 */ 1041 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 1042 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) 1043 1044 /** 1045 * @brief Verify the length of the scheduled regular conversions group. 1046 * @param __LENGTH__ number of programmed conversions. 1047 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) 1048 * or RESET (__LENGTH__ is null or too large) 1049 */ 1050 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) 1051 1052 1053 /** 1054 * @brief Verify the number of scheduled regular conversions in discontinuous mode. 1055 * @param NUMBER number of scheduled regular conversions in discontinuous mode. 1056 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) 1057 * or RESET (NUMBER is null or too large) 1058 */ 1059 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) 1060 1061 1062 /** 1063 * @brief Verify the ADC clock setting. 1064 * @param __ADC_CLOCK__ programmed ADC clock. 1065 * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) 1066 */ 1067 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ 1068 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 1069 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 1070 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ 1071 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ 1072 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ 1073 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ 1074 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ 1075 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ 1076 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ 1077 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ 1078 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ 1079 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ 1080 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ 1081 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) 1082 1083 /** 1084 * @brief Verify the ADC resolution setting. 1085 * @param __RESOLUTION__ programmed ADC resolution. 1086 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 1087 */ 1088 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 1089 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 1090 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 1091 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 1092 1093 /** 1094 * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. 1095 * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. 1096 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 1097 */ 1098 #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 1099 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 1100 1101 /** 1102 * @brief Verify the ADC converted data alignment. 1103 * @param __ALIGN__ programmed ADC converted data alignment. 1104 * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) 1105 */ 1106 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ 1107 ((__ALIGN__) == ADC_DATAALIGN_LEFT) ) 1108 1109 /** 1110 * @brief Verify the ADC scan mode. 1111 * @param __SCAN_MODE__ programmed ADC scan mode. 1112 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) 1113 */ 1114 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ 1115 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) 1116 1117 /** 1118 * @brief Verify the ADC edge trigger setting for regular group. 1119 * @param __EDGE__ programmed ADC edge trigger setting. 1120 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 1121 */ 1122 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 1123 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 1124 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 1125 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 1126 1127 /** 1128 * @brief Verify the ADC regular conversions external trigger. 1129 * @param __HANDLE__ ADC handle 1130 * @param __REGTRIG__ programmed ADC regular conversions external trigger. 1131 * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) 1132 */ 1133 #if defined(TIM8) 1134 /* Devices STM32H563/H573xx */ 1135 #define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 1136 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 1137 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 1138 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 1139 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 1140 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 1141 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 1142 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 1143 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 1144 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 1145 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1146 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1147 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 1148 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 1149 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 1150 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 1151 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT15) || \ 1152 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_CH1) || \ 1153 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_CH1) || \ 1154 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1155 #else 1156 /* Devices STM32H503xx */ 1157 #define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 1158 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 1159 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 1160 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 1161 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 1162 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 1163 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 1164 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1165 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1166 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 1167 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 1168 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ 1169 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_CH1) || \ 1170 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_CH1) || \ 1171 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1172 #endif /* Devices STM32H563/H573xx or STM32H503xx */ 1173 1174 /** 1175 * @brief Verify the ADC regular conversions external trigger. 1176 * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger. 1177 * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid) 1178 */ 1179 #define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \ 1180 ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \ 1181 ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED) ) 1182 1183 /** 1184 * @brief Verify the ADC regular conversions check for converted data availability. 1185 * @param __EOC_SELECTION__ converted data availability check. 1186 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) 1187 */ 1188 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ 1189 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) 1190 1191 /** 1192 * @brief Verify the ADC regular conversions overrun handling. 1193 * @param __OVR__ ADC regular conversions overrun handling. 1194 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) 1195 */ 1196 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ 1197 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) 1198 1199 /** 1200 * @brief Verify the ADC conversions sampling time. 1201 * @param __TIME__ ADC conversions sampling time. 1202 * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) 1203 */ 1204 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 1205 ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \ 1206 ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ 1207 ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ 1208 ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ 1209 ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ 1210 ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ 1211 ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ 1212 ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) 1213 1214 /** 1215 * @brief Verify the ADC regular channel setting. 1216 * @param __CHANNEL__ programmed ADC regular channel. 1217 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 1218 */ 1219 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ 1220 ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ 1221 ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ 1222 ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ 1223 ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ 1224 ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ 1225 ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ 1226 ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ 1227 ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ 1228 ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ 1229 ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ 1230 ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ 1231 ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ 1232 ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ 1233 ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ 1234 ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) 1235 1236 /** 1237 * @} 1238 */ 1239 1240 1241 /* Private constants ---------------------------------------------------------*/ 1242 1243 /** @defgroup ADC_Private_Constants ADC Private Constants 1244 * @{ 1245 */ 1246 1247 /* Fixed timeout values for ADC conversion (including sampling time) */ 1248 /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */ 1249 /* Maximum conversion time is 12.5 + Maximum sampling time */ 1250 /* or 12.5 + 640.5 = 653 ADC clock cycles */ 1251 /* Minimum ADC Clock frequency is 0.14 MHz */ 1252 /* Maximum conversion time is */ 1253 /* 653 / 0.14 MHz = 4.66 ms */ 1254 #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ 1255 1256 /* Delay for temperature sensor stabilization time. */ 1257 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ 1258 /* Unit: us */ 1259 #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) 1260 1261 /** 1262 * @} 1263 */ 1264 1265 /* Exported macro ------------------------------------------------------------*/ 1266 1267 /** @defgroup ADC_Exported_Macros ADC Exported Macros 1268 * @{ 1269 */ 1270 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 1271 /* final user. */ 1272 1273 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 1274 * @{ 1275 */ 1276 1277 /** @brief Reset ADC handle state. 1278 * @param __HANDLE__ ADC handle 1279 * @retval None 1280 */ 1281 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1282 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1283 do{ \ 1284 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 1285 (__HANDLE__)->MspInitCallback = NULL; \ 1286 (__HANDLE__)->MspDeInitCallback = NULL; \ 1287 } while(0) 1288 #else 1289 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1290 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 1291 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1292 1293 /** 1294 * @brief Enable ADC interrupt. 1295 * @param __HANDLE__ ADC handle 1296 * @param __INTERRUPT__ ADC Interrupt 1297 * This parameter can be one of the following values: 1298 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1299 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1300 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1301 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1302 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1303 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1304 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1305 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1306 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1307 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1308 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1309 * @retval None 1310 */ 1311 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1312 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 1313 1314 /** 1315 * @brief Disable ADC interrupt. 1316 * @param __HANDLE__ ADC handle 1317 * @param __INTERRUPT__ ADC Interrupt 1318 * This parameter can be one of the following values: 1319 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1320 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1321 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1322 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1323 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1324 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1325 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1326 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1327 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1328 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1329 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1330 * @retval None 1331 */ 1332 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1333 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 1334 1335 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 1336 * @param __HANDLE__ ADC handle 1337 * @param __INTERRUPT__ ADC interrupt source to check 1338 * This parameter can be one of the following values: 1339 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1340 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1341 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1342 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1343 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1344 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1345 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1346 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1347 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1348 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1349 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1350 * @retval State of interruption (SET or RESET) 1351 */ 1352 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 1353 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 1354 1355 /** 1356 * @brief Check whether the specified ADC flag is set or not. 1357 * @param __HANDLE__ ADC handle 1358 * @param __FLAG__ ADC flag 1359 * This parameter can be one of the following values: 1360 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1361 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1362 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1363 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1364 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1365 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1366 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1367 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1368 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1369 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1370 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1371 * @retval State of flag (TRUE or FALSE). 1372 */ 1373 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 1374 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 1375 1376 /** 1377 * @brief Clear the specified ADC flag. 1378 * @param __HANDLE__ ADC handle 1379 * @param __FLAG__ ADC flag 1380 * This parameter can be one of the following values: 1381 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1382 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1383 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1384 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1385 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1386 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1387 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1388 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1389 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1390 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1391 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1392 * @retval None 1393 */ 1394 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 1395 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1396 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 1397 1398 /** 1399 * @} 1400 */ 1401 1402 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 1403 * @{ 1404 */ 1405 1406 /** 1407 * @brief Helper macro to get ADC channel number in decimal format 1408 * from literals ADC_CHANNEL_x. 1409 * @note Example: 1410 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 1411 * will return decimal number "4". 1412 * @note The input can be a value from functions where a channel 1413 * number is returned, either defined with number 1414 * or with bitfield (only one bit must be set). 1415 * @param __CHANNEL__ This parameter can be one of the following values: 1416 * @arg @ref ADC_CHANNEL_0 (3) 1417 * @arg @ref ADC_CHANNEL_1 (3) 1418 * @arg @ref ADC_CHANNEL_2 (3) 1419 * @arg @ref ADC_CHANNEL_3 (3) 1420 * @arg @ref ADC_CHANNEL_4 (3) 1421 * @arg @ref ADC_CHANNEL_5 (3) 1422 * @arg @ref ADC_CHANNEL_6 1423 * @arg @ref ADC_CHANNEL_7 1424 * @arg @ref ADC_CHANNEL_8 1425 * @arg @ref ADC_CHANNEL_9 1426 * @arg @ref ADC_CHANNEL_10 1427 * @arg @ref ADC_CHANNEL_11 1428 * @arg @ref ADC_CHANNEL_12 1429 * @arg @ref ADC_CHANNEL_13 1430 * @arg @ref ADC_CHANNEL_14 1431 * @arg @ref ADC_CHANNEL_15 1432 * @arg @ref ADC_CHANNEL_16 1433 * @arg @ref ADC_CHANNEL_17 1434 * @arg @ref ADC_CHANNEL_18 1435 * @arg @ref ADC_CHANNEL_19 1436 * @arg @ref ADC_CHANNEL_VREFINT (1) 1437 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1438 * @arg @ref ADC_CHANNEL_VBAT (2) 1439 * @arg @ref ADC_CHANNEL_VDDCORE (2) 1440 * 1441 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n 1442 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n 1443 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) 1444 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) 1445 * @retval Value between Min_Data=0 and Max_Data=18 1446 */ 1447 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 1448 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 1449 1450 /** 1451 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 1452 * from number in decimal format. 1453 * @note Example: 1454 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 1455 * will return a data equivalent to "ADC_CHANNEL_4". 1456 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 1457 * @retval Returned value can be one of the following values: 1458 * @arg @ref ADC_CHANNEL_0 (3) 1459 * @arg @ref ADC_CHANNEL_1 (3) 1460 * @arg @ref ADC_CHANNEL_2 (3) 1461 * @arg @ref ADC_CHANNEL_3 (3) 1462 * @arg @ref ADC_CHANNEL_4 (3) 1463 * @arg @ref ADC_CHANNEL_5 (3) 1464 * @arg @ref ADC_CHANNEL_6 1465 * @arg @ref ADC_CHANNEL_7 1466 * @arg @ref ADC_CHANNEL_8 1467 * @arg @ref ADC_CHANNEL_9 1468 * @arg @ref ADC_CHANNEL_10 1469 * @arg @ref ADC_CHANNEL_11 1470 * @arg @ref ADC_CHANNEL_12 1471 * @arg @ref ADC_CHANNEL_13 1472 * @arg @ref ADC_CHANNEL_14 1473 * @arg @ref ADC_CHANNEL_15 1474 * @arg @ref ADC_CHANNEL_16 1475 * @arg @ref ADC_CHANNEL_17 1476 * @arg @ref ADC_CHANNEL_18 1477 * @arg @ref ADC_CHANNEL_19 1478 * @arg @ref ADC_CHANNEL_VREFINT (1)(4) 1479 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1)(4) 1480 * @arg @ref ADC_CHANNEL_VBAT (2)(4) 1481 * @arg @ref ADC_CHANNEL_VDDCORE (2)(4) 1482 * 1483 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n 1484 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n 1485 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) 1486 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) 1487 * (4) For ADC channel read back from ADC register, 1488 * comparison with internal channel parameter to be done 1489 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1490 */ 1491 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 1492 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 1493 1494 /** 1495 * @brief Helper macro to determine whether the selected channel 1496 * corresponds to literal definitions of driver. 1497 * @note The different literal definitions of ADC channels are: 1498 * - ADC internal channel: 1499 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... 1500 * - ADC external channel (channel connected to a GPIO pin): 1501 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 1502 * @note The channel parameter must be a value defined from literal 1503 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1504 * ADC_CHANNEL_TEMPSENSOR, ...), 1505 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 1506 * must not be a value from functions where a channel number is 1507 * returned from ADC registers, 1508 * because internal and external channels share the same channel 1509 * number in ADC registers. The differentiation is made only with 1510 * parameters definitions of driver. 1511 * @param __CHANNEL__ This parameter can be one of the following values: 1512 * @arg @ref ADC_CHANNEL_0 (3) 1513 * @arg @ref ADC_CHANNEL_1 (3) 1514 * @arg @ref ADC_CHANNEL_2 (3) 1515 * @arg @ref ADC_CHANNEL_3 (3) 1516 * @arg @ref ADC_CHANNEL_4 (3) 1517 * @arg @ref ADC_CHANNEL_5 (3) 1518 * @arg @ref ADC_CHANNEL_6 1519 * @arg @ref ADC_CHANNEL_7 1520 * @arg @ref ADC_CHANNEL_8 1521 * @arg @ref ADC_CHANNEL_9 1522 * @arg @ref ADC_CHANNEL_10 1523 * @arg @ref ADC_CHANNEL_11 1524 * @arg @ref ADC_CHANNEL_12 1525 * @arg @ref ADC_CHANNEL_13 1526 * @arg @ref ADC_CHANNEL_14 1527 * @arg @ref ADC_CHANNEL_15 1528 * @arg @ref ADC_CHANNEL_16 1529 * @arg @ref ADC_CHANNEL_17 1530 * @arg @ref ADC_CHANNEL_18 1531 * @arg @ref ADC_CHANNEL_19 1532 * @arg @ref ADC_CHANNEL_VREFINT (1) 1533 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1534 * @arg @ref ADC_CHANNEL_VBAT (2) 1535 * @arg @ref ADC_CHANNEL_VDDCORE (2) 1536 * 1537 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n 1538 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n 1539 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) 1540 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) 1541 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel 1542 * connected to a GPIO pin). 1543 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 1544 */ 1545 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 1546 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 1547 1548 /** 1549 * @brief Helper macro to convert a channel defined from parameter 1550 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1551 * ADC_CHANNEL_TEMPSENSOR, ...), 1552 * to its equivalent parameter definition of a ADC external channel 1553 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 1554 * @note The channel parameter can be, additionally to a value 1555 * defined from parameter definition of a ADC internal channel 1556 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), 1557 * a value defined from parameter definition of 1558 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1559 * or a value from functions where a channel number is returned 1560 * from ADC registers. 1561 * @param __CHANNEL__ This parameter can be one of the following values: 1562 * @arg @ref ADC_CHANNEL_0 (3) 1563 * @arg @ref ADC_CHANNEL_1 (3) 1564 * @arg @ref ADC_CHANNEL_2 (3) 1565 * @arg @ref ADC_CHANNEL_3 (3) 1566 * @arg @ref ADC_CHANNEL_4 (3) 1567 * @arg @ref ADC_CHANNEL_5 (3) 1568 * @arg @ref ADC_CHANNEL_6 1569 * @arg @ref ADC_CHANNEL_7 1570 * @arg @ref ADC_CHANNEL_8 1571 * @arg @ref ADC_CHANNEL_9 1572 * @arg @ref ADC_CHANNEL_10 1573 * @arg @ref ADC_CHANNEL_11 1574 * @arg @ref ADC_CHANNEL_12 1575 * @arg @ref ADC_CHANNEL_13 1576 * @arg @ref ADC_CHANNEL_14 1577 * @arg @ref ADC_CHANNEL_15 1578 * @arg @ref ADC_CHANNEL_16 1579 * @arg @ref ADC_CHANNEL_17 1580 * @arg @ref ADC_CHANNEL_18 1581 * @arg @ref ADC_CHANNEL_19 1582 * @arg @ref ADC_CHANNEL_VREFINT (1) 1583 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1584 * @arg @ref ADC_CHANNEL_VBAT (2) 1585 * @arg @ref ADC_CHANNEL_VDDCORE (2) 1586 * 1587 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1.\n 1588 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2.\n 1589 * (3) On STM32H5, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) 1590 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) 1591 * @retval Returned value can be one of the following values: 1592 * @arg @ref ADC_CHANNEL_0 1593 * @arg @ref ADC_CHANNEL_1 1594 * @arg @ref ADC_CHANNEL_2 1595 * @arg @ref ADC_CHANNEL_3 1596 * @arg @ref ADC_CHANNEL_4 1597 * @arg @ref ADC_CHANNEL_5 1598 * @arg @ref ADC_CHANNEL_6 1599 * @arg @ref ADC_CHANNEL_7 1600 * @arg @ref ADC_CHANNEL_8 1601 * @arg @ref ADC_CHANNEL_9 1602 * @arg @ref ADC_CHANNEL_10 1603 * @arg @ref ADC_CHANNEL_11 1604 * @arg @ref ADC_CHANNEL_12 1605 * @arg @ref ADC_CHANNEL_13 1606 * @arg @ref ADC_CHANNEL_14 1607 * @arg @ref ADC_CHANNEL_15 1608 * @arg @ref ADC_CHANNEL_16 1609 * @arg @ref ADC_CHANNEL_17 1610 * @arg @ref ADC_CHANNEL_18 1611 */ 1612 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 1613 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 1614 1615 /** 1616 * @brief Helper macro to determine whether the internal channel 1617 * selected is available on the ADC instance selected. 1618 * @note The channel parameter must be a value defined from parameter 1619 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1620 * ADC_CHANNEL_TEMPSENSOR, ...), 1621 * must not be a value defined from parameter definition of 1622 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1623 * or a value from functions where a channel number is 1624 * returned from ADC registers, 1625 * because internal and external channels share the same channel 1626 * number in ADC registers. The differentiation is made only with 1627 * parameters definitions of driver. 1628 * @param __ADC_INSTANCE__ ADC instance 1629 * @param __CHANNEL__ This parameter can be one of the following values: 1630 * @arg @ref ADC_CHANNEL_VREFINT (1) 1631 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1632 * @arg @ref ADC_CHANNEL_VBAT (2) 1633 * @arg @ref ADC_CHANNEL_VDDCORE (2) 1634 * 1635 * (1) On STM32H563xx/573xx, parameter available only on ADC instance: ADC1. 1636 * (2) On STM32H563xx/573xx, parameter available only on ADC instance: ADC2. 1637 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 1638 * Value "1" if the internal channel selected is available on the ADC instance selected. 1639 */ 1640 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 1641 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 1642 1643 #if defined(ADC_MULTIMODE_SUPPORT) 1644 /** 1645 * @brief Helper macro to get the ADC multimode conversion data of ADC master 1646 * or ADC slave from raw value with both ADC conversion data concatenated. 1647 * @note This macro is intended to be used when multimode transfer by DMA 1648 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 1649 * In this case the transferred data need to processed with this macro 1650 * to separate the conversion data of ADC master and ADC slave. 1651 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 1652 * @arg @ref LL_ADC_MULTI_MASTER 1653 * @arg @ref LL_ADC_MULTI_SLAVE 1654 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 1655 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 1656 */ 1657 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 1658 __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) 1659 #endif /* ADC_MULTIMODE_SUPPORT */ 1660 1661 /** 1662 * @brief Helper macro to select the ADC common instance 1663 * to which is belonging the selected ADC instance. 1664 * @note ADC common register instance can be used for: 1665 * - Set parameters common to several ADC instances 1666 * - Multimode (for devices with several ADC instances) 1667 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1668 * @param __ADCx__ ADC instance 1669 * @retval ADC common register instance 1670 */ 1671 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 1672 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 1673 1674 /** 1675 * @brief Helper macro to check if all ADC instances sharing the same 1676 * ADC common instance are disabled. 1677 * @note This check is required by functions with setting conditioned to 1678 * ADC state: 1679 * All ADC instances of the ADC common group must be disabled. 1680 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1681 * @note On devices with only 1 ADC common instance, parameter of this macro 1682 * is useless and can be ignored (parameter kept for compatibility 1683 * with devices featuring several ADC common instances). 1684 * @param __ADCXY_COMMON__ ADC common instance 1685 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1686 * @retval Value "0" if all ADC instances sharing the same ADC common instance 1687 * are disabled. 1688 * Value "1" if at least one ADC instance sharing the same ADC common instance 1689 * is enabled. 1690 */ 1691 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1692 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 1693 1694 /** 1695 * @brief Helper macro to define the ADC conversion data full-scale digital 1696 * value corresponding to the selected ADC resolution. 1697 * @note ADC conversion data full-scale corresponds to voltage range 1698 * determined by analog voltage references Vref+ and Vref- 1699 * (refer to reference manual). 1700 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1701 * @arg @ref ADC_RESOLUTION_12B 1702 * @arg @ref ADC_RESOLUTION_10B 1703 * @arg @ref ADC_RESOLUTION_8B 1704 * @arg @ref ADC_RESOLUTION_6B 1705 * @retval ADC conversion data full-scale digital value 1706 */ 1707 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1708 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 1709 1710 /** 1711 * @brief Helper macro to convert the ADC conversion data from 1712 * a resolution to another resolution. 1713 * @param __DATA__ ADC conversion data to be converted 1714 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 1715 * This parameter can be one of the following values: 1716 * @arg @ref ADC_RESOLUTION_12B 1717 * @arg @ref ADC_RESOLUTION_10B 1718 * @arg @ref ADC_RESOLUTION_8B 1719 * @arg @ref ADC_RESOLUTION_6B 1720 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 1721 * This parameter can be one of the following values: 1722 * @arg @ref ADC_RESOLUTION_12B 1723 * @arg @ref ADC_RESOLUTION_10B 1724 * @arg @ref ADC_RESOLUTION_8B 1725 * @arg @ref ADC_RESOLUTION_6B 1726 * @retval ADC conversion data to the requested resolution 1727 */ 1728 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 1729 __ADC_RESOLUTION_CURRENT__,\ 1730 __ADC_RESOLUTION_TARGET__) \ 1731 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ 1732 (__ADC_RESOLUTION_CURRENT__),\ 1733 (__ADC_RESOLUTION_TARGET__)) 1734 1735 /** 1736 * @brief Helper macro to calculate the voltage (unit: mVolt) 1737 * corresponding to a ADC conversion data (unit: digital value). 1738 * @note Analog reference voltage (Vref+) must be either known from 1739 * user board environment or can be calculated using ADC measurement 1740 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1741 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1742 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 1743 * (unit: digital value). 1744 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1745 * @arg @ref ADC_RESOLUTION_12B 1746 * @arg @ref ADC_RESOLUTION_10B 1747 * @arg @ref ADC_RESOLUTION_8B 1748 * @arg @ref ADC_RESOLUTION_6B 1749 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1750 */ 1751 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 1752 __ADC_DATA__,\ 1753 __ADC_RESOLUTION__) \ 1754 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 1755 (__ADC_DATA__),\ 1756 (__ADC_RESOLUTION__)) 1757 1758 /** 1759 * @brief Helper macro to calculate analog reference voltage (Vref+) 1760 * (unit: mVolt) from ADC conversion data of internal voltage 1761 * reference VrefInt. 1762 * @note Computation is using VrefInt calibration value 1763 * stored in system memory for each device during production. 1764 * @note This voltage depends on user board environment: voltage level 1765 * connected to pin Vref+. 1766 * On devices with small package, the pin Vref+ is not present 1767 * and internally bonded to pin Vdda. 1768 * @note On this STM32 series, calibration data of internal voltage reference 1769 * VrefInt corresponds to a resolution of 12 bits, 1770 * this is the recommended ADC resolution to convert voltage of 1771 * internal voltage reference VrefInt. 1772 * Otherwise, this macro performs the processing to scale 1773 * ADC conversion data to 12 bits. 1774 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 1775 * of internal voltage reference VrefInt (unit: digital value). 1776 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1777 * @arg @ref ADC_RESOLUTION_12B 1778 * @arg @ref ADC_RESOLUTION_10B 1779 * @arg @ref ADC_RESOLUTION_8B 1780 * @arg @ref ADC_RESOLUTION_6B 1781 * @retval Analog reference voltage (unit: mV) 1782 */ 1783 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 1784 __ADC_RESOLUTION__) \ 1785 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ 1786 (__ADC_RESOLUTION__)) 1787 1788 /** 1789 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1790 * from ADC conversion data of internal temperature sensor. 1791 * @note Computation is using temperature sensor calibration values 1792 * stored in system memory for each device during production. 1793 * @note Calculation formula: 1794 * Temperature = ((TS_ADC_DATA - TS_CAL1) 1795 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 1796 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 1797 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1798 * Avg_Slope = (TS_CAL2 - TS_CAL1) 1799 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 1800 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 1801 * TEMP_DEGC_CAL1 (calibrated in factory) 1802 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 1803 * TEMP_DEGC_CAL2 (calibrated in factory) 1804 * Caution: Calculation relevancy under reserve that calibration 1805 * parameters are correct (address and data). 1806 * To calculate temperature using temperature sensor 1807 * datasheet typical values (generic values less, therefore 1808 * less accurate than calibrated values), 1809 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 1810 * @note As calculation input, the analog reference voltage (Vref+) must be 1811 * defined as it impacts the ADC LSB equivalent voltage. 1812 * @note Analog reference voltage (Vref+) must be either known from 1813 * user board environment or can be calculated using ADC measurement 1814 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1815 * @note On this STM32 series, calibration data of temperature sensor 1816 * corresponds to a resolution of 12 bits, 1817 * this is the recommended ADC resolution to convert voltage of 1818 * temperature sensor. 1819 * Otherwise, this macro performs the processing to scale 1820 * ADC conversion data to 12 bits. 1821 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1822 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 1823 * temperature sensor (unit: digital value). 1824 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 1825 * sensor voltage has been measured. 1826 * This parameter can be one of the following values: 1827 * @arg @ref ADC_RESOLUTION_12B 1828 * @arg @ref ADC_RESOLUTION_10B 1829 * @arg @ref ADC_RESOLUTION_8B 1830 * @arg @ref ADC_RESOLUTION_6B 1831 * @retval Temperature (unit: degree Celsius) 1832 */ 1833 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 1834 __TEMPSENSOR_ADC_DATA__,\ 1835 __ADC_RESOLUTION__) \ 1836 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ 1837 (__TEMPSENSOR_ADC_DATA__),\ 1838 (__ADC_RESOLUTION__)) 1839 1840 /** 1841 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1842 * from ADC conversion data of internal temperature sensor. 1843 * @note Computation is using temperature sensor typical values 1844 * (refer to device datasheet). 1845 * @note Calculation formula: 1846 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 1847 * / Avg_Slope + CALx_TEMP 1848 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1849 * (unit: digital value) 1850 * Avg_Slope = temperature sensor slope 1851 * (unit: uV/Degree Celsius) 1852 * TS_TYP_CALx_VOLT = temperature sensor digital value at 1853 * temperature CALx_TEMP (unit: mV) 1854 * Caution: Calculation relevancy under reserve the temperature sensor 1855 * of the current device has characteristics in line with 1856 * datasheet typical values. 1857 * If temperature sensor calibration values are available on 1858 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 1859 * temperature calculation will be more accurate using 1860 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 1861 * @note As calculation input, the analog reference voltage (Vref+) must be 1862 * defined as it impacts the ADC LSB equivalent voltage. 1863 * @note Analog reference voltage (Vref+) must be either known from 1864 * user board environment or can be calculated using ADC measurement 1865 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1866 * @note ADC measurement data must correspond to a resolution of 12bits 1867 * (full scale digital value 4095). If not the case, the data must be 1868 * preliminarily rescaled to an equivalent resolution of 12 bits. 1869 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value 1870 (unit: uV/DegCelsius). 1871 * On this STM32 series, refer to device datasheet parameter "Avg_Slope". 1872 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at 1873 temperature and Vref+ defined in parameters below) (unit: mV). 1874 * On this STM32 series, refer to device datasheet parameter "V30" 1875 * (corresponding to TS_CAL1). 1876 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see 1877 parameter above) is corresponding (unit: mV) 1878 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 1879 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 1880 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 1881 * This parameter can be one of the following values: 1882 * @arg @ref ADC_RESOLUTION_12B 1883 * @arg @ref ADC_RESOLUTION_10B 1884 * @arg @ref ADC_RESOLUTION_8B 1885 * @arg @ref ADC_RESOLUTION_6B 1886 * @retval Temperature (unit: degree Celsius) 1887 */ 1888 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 1889 __TEMPSENSOR_TYP_CALX_V__,\ 1890 __TEMPSENSOR_CALX_TEMP__,\ 1891 __VREFANALOG_VOLTAGE__,\ 1892 __TEMPSENSOR_ADC_DATA__,\ 1893 __ADC_RESOLUTION__) \ 1894 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ 1895 (__TEMPSENSOR_TYP_CALX_V__),\ 1896 (__TEMPSENSOR_CALX_TEMP__),\ 1897 (__VREFANALOG_VOLTAGE__),\ 1898 (__TEMPSENSOR_ADC_DATA__),\ 1899 (__ADC_RESOLUTION__)) 1900 1901 /** 1902 * @} 1903 */ 1904 1905 /** 1906 * @} 1907 */ 1908 1909 /* Include ADC HAL Extended module */ 1910 #include "stm32h5xx_hal_adc_ex.h" 1911 1912 /* Exported functions --------------------------------------------------------*/ 1913 /** @addtogroup ADC_Exported_Functions 1914 * @{ 1915 */ 1916 1917 /** @addtogroup ADC_Exported_Functions_Group1 1918 * @brief Initialization and Configuration functions 1919 * @{ 1920 */ 1921 /* Initialization and de-initialization functions ****************************/ 1922 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); 1923 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1924 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); 1925 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); 1926 1927 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1928 /* Callbacks Register/UnRegister functions ***********************************/ 1929 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, 1930 pADC_CallbackTypeDef pCallback); 1931 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 1932 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1933 /** 1934 * @} 1935 */ 1936 1937 /** @addtogroup ADC_Exported_Functions_Group2 1938 * @brief IO operation functions 1939 * @{ 1940 */ 1941 /* IO operation functions *****************************************************/ 1942 1943 /* Blocking mode: Polling */ 1944 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); 1945 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); 1946 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1947 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); 1948 1949 /* Non-blocking mode: Interruption */ 1950 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); 1951 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); 1952 1953 /* Non-blocking mode: DMA */ 1954 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1955 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); 1956 1957 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1958 uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); 1959 1960 /* ADC sampling control */ 1961 HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc); 1962 HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc); 1963 1964 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 1965 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); 1966 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); 1967 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); 1968 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); 1969 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 1970 /** 1971 * @} 1972 */ 1973 1974 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 1975 * @brief Peripheral Control functions 1976 * @{ 1977 */ 1978 /* Peripheral Control functions ***********************************************/ 1979 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig); 1980 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, 1981 const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); 1982 1983 /** 1984 * @} 1985 */ 1986 1987 /* Peripheral State functions *************************************************/ 1988 /** @addtogroup ADC_Exported_Functions_Group4 1989 * @{ 1990 */ 1991 uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); 1992 uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); 1993 1994 /** 1995 * @} 1996 */ 1997 1998 /** 1999 * @} 2000 */ 2001 2002 /* Private functions ---------------------------------------------------------*/ 2003 /** @addtogroup ADC_Private_Functions ADC Private Functions 2004 * @{ 2005 */ 2006 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); 2007 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); 2008 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); 2009 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 2010 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 2011 void ADC_DMAError(DMA_HandleTypeDef *hdma); 2012 2013 /** 2014 * @} 2015 */ 2016 2017 /** 2018 * @} 2019 */ 2020 2021 /** 2022 * @} 2023 */ 2024 2025 #ifdef __cplusplus 2026 } 2027 #endif 2028 2029 2030 #endif /* STM32H5xx_HAL_ADC_H */ 2031
