1 /** 2 ****************************************************************************** 3 * @file stm32_hal_legacy.h 4 * @author MCD Application Team 5 * @brief This file contains aliases definition for the STM32Cube HAL constants 6 * macros and functions maintained for legacy purpose. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32_HAL_LEGACY 22 #define STM32_HAL_LEGACY 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 /* Exported types ------------------------------------------------------------*/ 30 /* Exported constants --------------------------------------------------------*/ 31 32 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose 33 * @{ 34 */ 35 #define AES_FLAG_RDERR CRYP_FLAG_RDERR 36 #define AES_FLAG_WRERR CRYP_FLAG_WRERR 37 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF 38 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR 39 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR 40 #if defined(STM32H7) || defined(STM32MP1) 41 #define CRYP_DATATYPE_32B CRYP_NO_SWAP 42 #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP 43 #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP 44 #define CRYP_DATATYPE_1B CRYP_BIT_SWAP 45 #endif /* STM32H7 || STM32MP1 */ 46 /** 47 * @} 48 */ 49 50 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose 51 * @{ 52 */ 53 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B 54 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B 55 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B 56 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B 57 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN 58 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED 59 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV 60 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV 61 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV 62 #define REGULAR_GROUP ADC_REGULAR_GROUP 63 #define INJECTED_GROUP ADC_INJECTED_GROUP 64 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP 65 #define AWD_EVENT ADC_AWD_EVENT 66 #define AWD1_EVENT ADC_AWD1_EVENT 67 #define AWD2_EVENT ADC_AWD2_EVENT 68 #define AWD3_EVENT ADC_AWD3_EVENT 69 #define OVR_EVENT ADC_OVR_EVENT 70 #define JQOVF_EVENT ADC_JQOVF_EVENT 71 #define ALL_CHANNELS ADC_ALL_CHANNELS 72 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS 73 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS 74 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR 75 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT 76 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 77 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 78 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 79 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 80 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 81 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO 82 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 83 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO 84 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 85 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO 86 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 87 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 88 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE 89 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING 90 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING 91 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING 92 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 93 94 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY 95 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY 96 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC 97 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC 98 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL 99 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL 100 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 101 102 #if defined(STM32H7) 103 #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT 104 #endif /* STM32H7 */ 105 106 #if defined(STM32U5) 107 #define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES 108 #define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES 109 #define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 110 #endif /* STM32U5 */ 111 112 #if defined(STM32H5) 113 #define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE 114 #endif /* STM32H5 */ 115 /** 116 * @} 117 */ 118 119 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose 120 * @{ 121 */ 122 123 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 124 125 /** 126 * @} 127 */ 128 129 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose 130 * @{ 131 */ 132 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE 133 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE 134 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 135 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 136 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 137 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 138 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 139 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 140 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 141 #if defined(STM32L0) 142 #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM 143 input 1 for COMP1, LPTIM input 2 for COMP2 */ 144 #endif 145 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR 146 #if defined(STM32F373xC) || defined(STM32F378xx) 147 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 148 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR 149 #endif /* STM32F373xC || STM32F378xx */ 150 151 #if defined(STM32L0) || defined(STM32L4) 152 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON 153 154 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 155 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 156 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 157 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 158 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 159 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 160 161 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT 162 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT 163 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT 164 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT 165 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 166 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 167 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 168 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 169 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 170 #if defined(STM32L0) 171 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ 172 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ 173 /* to the second dedicated IO (only for COMP2). */ 174 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 175 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 176 #else 177 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 178 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 179 #endif 180 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 181 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 182 183 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW 184 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH 185 186 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ 187 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ 188 #if defined(COMP_CSR_LOCK) 189 #define COMP_FLAG_LOCK COMP_CSR_LOCK 190 #elif defined(COMP_CSR_COMP1LOCK) 191 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK 192 #elif defined(COMP_CSR_COMPxLOCK) 193 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK 194 #endif 195 196 #if defined(STM32L4) 197 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 198 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 199 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 200 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 201 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 202 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 203 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE 204 #endif 205 206 #if defined(STM32L0) 207 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED 208 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER 209 #else 210 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED 211 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED 212 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER 213 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER 214 #endif 215 216 #endif 217 218 #if defined(STM32U5) 219 #define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG 220 #endif 221 222 /** 223 * @} 224 */ 225 226 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose 227 * @{ 228 */ 229 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig 230 #if defined(STM32U5) 231 #define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE 232 #define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE 233 #define MPU_DEVICE_nGRE MPU_DEVICE_NGRE 234 #endif /* STM32U5 */ 235 /** 236 * @} 237 */ 238 239 /** @defgroup CRC_Aliases CRC API aliases 240 * @{ 241 */ 242 #if defined(STM32H5) || defined(STM32C0) 243 #else 244 #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for 245 inter STM32 series compatibility */ 246 #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for 247 inter STM32 series compatibility */ 248 #endif 249 /** 250 * @} 251 */ 252 253 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose 254 * @{ 255 */ 256 257 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE 258 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE 259 260 /** 261 * @} 262 */ 263 264 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose 265 * @{ 266 */ 267 268 #define DAC1_CHANNEL_1 DAC_CHANNEL_1 269 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 270 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 271 #define DAC_WAVE_NONE 0x00000000U 272 #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 273 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 274 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE 275 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE 276 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE 277 278 #if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5) 279 #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL 280 #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL 281 #endif 282 283 #if defined(STM32U5) 284 #define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 285 #define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 286 #define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 287 #define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 288 #endif 289 290 #if defined(STM32H5) 291 #define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 292 #define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 293 #endif 294 295 #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) 296 #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID 297 #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID 298 #endif 299 300 /** 301 * @} 302 */ 303 304 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose 305 * @{ 306 */ 307 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 308 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 309 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 310 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 311 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 312 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 313 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 314 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 315 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 316 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 317 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 318 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 319 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 320 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 321 322 #define IS_HAL_REMAPDMA IS_DMA_REMAP 323 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE 324 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE 325 326 #if defined(STM32L4) 327 328 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 329 #define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 330 #define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 331 #define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 332 #define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 333 #define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 334 #define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 335 #define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 336 #define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 337 #define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 338 #define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 339 #define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 340 #define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 341 #define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 342 #define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 343 #define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 344 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 345 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 346 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 347 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 348 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 349 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 350 #define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE 351 #define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT 352 #define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 353 #define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT 354 355 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 356 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 357 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 358 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 359 360 #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 361 #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI 362 #endif 363 364 #endif /* STM32L4 */ 365 366 #if defined(STM32G0) 367 #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 368 #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 369 #define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM 370 #define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM 371 372 #define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM 373 #define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM 374 #endif 375 376 #if defined(STM32H7) 377 378 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 379 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 380 381 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX 382 #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX 383 384 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 385 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 386 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 387 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 388 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 389 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 390 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 391 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 392 393 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 394 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 395 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 396 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 397 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 398 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 399 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 400 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 401 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 402 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 403 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 404 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 405 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 406 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 407 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 408 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 409 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 410 #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT 411 #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT 412 #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP 413 #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 414 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 415 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 416 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT 417 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 418 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 419 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT 420 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 421 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 422 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 423 424 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 425 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 426 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 427 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 428 429 #define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT 430 #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT 431 #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT 432 433 #define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT 434 #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT 435 436 #endif /* STM32H7 */ 437 438 #if defined(STM32U5) 439 #define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI 440 #endif /* STM32U5 */ 441 /** 442 * @} 443 */ 444 445 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose 446 * @{ 447 */ 448 449 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE 450 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD 451 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD 452 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD 453 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS 454 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES 455 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES 456 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE 457 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE 458 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE 459 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE 460 #define OBEX_PCROP OPTIONBYTE_PCROP 461 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG 462 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE 463 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE 464 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE 465 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD 466 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD 467 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE 468 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD 469 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD 470 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE 471 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD 472 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD 473 #define PAGESIZE FLASH_PAGE_SIZE 474 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE 475 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD 476 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD 477 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 478 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 479 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 480 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 481 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST 482 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST 483 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA 484 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB 485 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA 486 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB 487 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE 488 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN 489 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE 490 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN 491 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE 492 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD 493 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG 494 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS 495 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP 496 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV 497 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR 498 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG 499 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION 500 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA 501 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE 502 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE 503 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS 504 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS 505 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST 506 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR 507 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO 508 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION 509 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS 510 #define OB_WDG_SW OB_IWDG_SW 511 #define OB_WDG_HW OB_IWDG_HW 512 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET 513 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET 514 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET 515 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET 516 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR 517 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 518 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 519 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 520 #if defined(STM32G0) 521 #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE 522 #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH 523 #else 524 #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE 525 #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE 526 #endif 527 #if defined(STM32H7) 528 #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 529 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 530 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 531 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 532 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 533 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 534 #define FLASH_FLAG_WDW FLASH_FLAG_WBNE 535 #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL 536 #endif /* STM32H7 */ 537 #if defined(STM32U5) 538 #define OB_USER_nRST_STOP OB_USER_NRST_STOP 539 #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY 540 #define OB_USER_nRST_SHDW OB_USER_NRST_SHDW 541 #define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 542 #define OB_USER_nBOOT0 OB_USER_NBOOT0 543 #define OB_nBOOT0_RESET OB_NBOOT0_RESET 544 #define OB_nBOOT0_SET OB_NBOOT0_SET 545 #define OB_USER_SRAM134_RST OB_USER_SRAM_RST 546 #define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE 547 #define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE 548 #endif /* STM32U5 */ 549 550 /** 551 * @} 552 */ 553 554 /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose 555 * @{ 556 */ 557 558 #if defined(STM32H7) 559 #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE 560 #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE 561 #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET 562 #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET 563 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE 564 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE 565 #endif /* STM32H7 */ 566 567 /** 568 * @} 569 */ 570 571 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose 572 * @{ 573 */ 574 575 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 576 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 577 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 578 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 579 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 580 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 581 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 582 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 583 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 584 #if defined(STM32G4) 585 586 #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster 587 #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster 588 #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD 589 #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD 590 #endif /* STM32G4 */ 591 592 #if defined(STM32H5) 593 #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC 594 #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC 595 #define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC 596 #define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC 597 #define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC 598 #define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC 599 600 #define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC 601 #define SYSCFG_BREAK_PVD SBS_BREAK_PVD 602 #define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC 603 #define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP 604 605 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 606 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 607 #define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 608 #define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 609 610 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE 611 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE 612 613 #define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 614 #define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 615 #define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 616 #define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 617 618 #define SYSCFG_ETH_MII SBS_ETH_MII 619 #define SYSCFG_ETH_RMII SBS_ETH_RMII 620 #define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG 621 622 #define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE 623 #define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR 624 #define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG 625 626 #define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG 627 628 #define SYSCFG_MPU_NSEC SBS_MPU_NSEC 629 #define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC 630 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 631 #define SYSCFG_SAU SBS_SAU 632 #define SYSCFG_MPU_SEC SBS_MPU_SEC 633 #define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC 634 #define SYSCFG_LOCK_ALL SBS_LOCK_ALL 635 #else 636 #define SYSCFG_LOCK_ALL SBS_LOCK_ALL 637 #endif /* __ARM_FEATURE_CMSE */ 638 639 #define SYSCFG_CLK SBS_CLK 640 #define SYSCFG_CLASSB SBS_CLASSB 641 #define SYSCFG_FPU SBS_FPU 642 #define SYSCFG_ALL SBS_ALL 643 644 #define SYSCFG_SEC SBS_SEC 645 #define SYSCFG_NSEC SBS_NSEC 646 647 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE 648 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE 649 650 #define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK 651 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK 652 #define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK 653 #define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK 654 655 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE 656 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE 657 658 #define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS 659 #define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS 660 661 #define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT 662 #define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG 663 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE 664 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE 665 #define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING 666 #define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS 667 #define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES 668 #define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES 669 #define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS 670 671 #define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig 672 #define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig 673 #define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig 674 #define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF 675 #define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF 676 677 #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster 678 #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster 679 #define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect 680 681 #define HAL_SYSCFG_Lock HAL_SBS_Lock 682 #define HAL_SYSCFG_GetLock HAL_SBS_GetLock 683 684 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 685 #define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes 686 #define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes 687 #endif /* __ARM_FEATURE_CMSE */ 688 689 #endif /* STM32H5 */ 690 691 692 /** 693 * @} 694 */ 695 696 697 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose 698 * @{ 699 */ 700 #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) 701 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE 702 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE 703 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 704 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 705 #elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) 706 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE 707 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE 708 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 709 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 710 #endif 711 /** 712 * @} 713 */ 714 715 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose 716 * @{ 717 */ 718 719 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef 720 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef 721 /** 722 * @} 723 */ 724 725 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose 726 * @{ 727 */ 728 #define GET_GPIO_SOURCE GPIO_GET_INDEX 729 #define GET_GPIO_INDEX GPIO_GET_INDEX 730 731 #if defined(STM32F4) 732 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO 733 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO 734 #endif 735 736 #if defined(STM32F7) 737 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 738 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 739 #endif 740 741 #if defined(STM32L4) 742 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 743 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 744 #endif 745 746 #if defined(STM32H7) 747 #define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 748 #define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 749 #define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 750 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 751 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 752 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 753 754 #if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ 755 defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) 756 #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS 757 #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS 758 #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS 759 #endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ 760 #endif /* STM32H7 */ 761 762 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 763 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 764 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 765 766 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) 767 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 768 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 769 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH 770 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 771 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ 772 773 #if defined(STM32L1) 774 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW 775 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM 776 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH 777 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 778 #endif /* STM32L1 */ 779 780 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) 781 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 782 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 783 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH 784 #endif /* STM32F0 || STM32F3 || STM32F1 */ 785 786 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 787 788 #if defined(STM32U5) || defined(STM32H5) 789 #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ 790 #endif /* STM32U5 || STM32H5 */ 791 #if defined(STM32U5) 792 #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP 793 #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 794 #endif /* STM32U5 */ 795 /** 796 * @} 797 */ 798 799 /** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose 800 * @{ 801 */ 802 #if defined(STM32U5) 803 #define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI 804 #define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB 805 #endif /* STM32U5 */ 806 #if defined(STM32H5) 807 #define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 808 #define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC 809 #endif /* STM32H5 */ 810 /** 811 * @} 812 */ 813 814 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose 815 * @{ 816 */ 817 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED 818 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 819 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 820 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 821 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 822 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 823 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 824 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 825 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 826 827 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER 828 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER 829 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD 830 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD 831 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER 832 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER 833 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE 834 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE 835 836 #if defined(STM32G4) 837 #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig 838 #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable 839 #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable 840 #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset 841 #define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A 842 #define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B 843 #define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL 844 #define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL 845 #endif /* STM32G4 */ 846 847 #if defined(STM32H7) 848 #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 849 #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 850 #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 851 #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 852 #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 853 #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 854 #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 855 #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 856 #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 857 #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 858 #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 859 #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 860 #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 861 #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 862 #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 863 #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 864 #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 865 #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 866 #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 867 #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 868 #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 869 #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 870 #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 871 #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 872 #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 873 #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 874 #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 875 #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 876 #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 877 #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 878 #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 879 #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 880 #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 881 #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 882 #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 883 #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 884 #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 885 #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 886 #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 887 #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 888 #define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 889 #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 890 #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 891 #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 892 #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 893 #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 894 #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 895 #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 896 #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 897 #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 898 #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 899 #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 900 #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 901 #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 902 903 #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 904 #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 905 #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 906 #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 907 #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 908 #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 909 #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 910 #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 911 #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 912 #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 913 #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 914 #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 915 #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 916 #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 917 #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 918 #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 919 #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 920 #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 921 #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 922 #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 923 #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 924 #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 925 #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 926 #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 927 #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 928 #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 929 #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 930 #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 931 #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 932 #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 933 #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 934 #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 935 #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 936 #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 937 #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 938 #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 939 #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 940 #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 941 #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 942 #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 943 #define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 944 #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 945 #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 946 #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 947 #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 948 #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 949 #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 950 #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 951 #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 952 #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 953 #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 954 #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 955 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 956 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 957 #endif /* STM32H7 */ 958 959 #if defined(STM32F3) 960 /** @brief Constants defining available sources associated to external events. 961 */ 962 #define HRTIM_EVENTSRC_1 (0x00000000U) 963 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) 964 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) 965 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) 966 967 /** @brief Constants defining the DLL calibration periods (in micro seconds) 968 */ 969 #define HRTIM_CALIBRATIONRATE_7300 0x00000000U 970 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) 971 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) 972 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) 973 974 #endif /* STM32F3 */ 975 /** 976 * @} 977 */ 978 979 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose 980 * @{ 981 */ 982 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE 983 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE 984 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE 985 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE 986 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE 987 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE 988 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE 989 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE 990 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) 991 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX 992 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX 993 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX 994 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX 995 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX 996 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX 997 #endif 998 /** 999 * @} 1000 */ 1001 1002 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose 1003 * @{ 1004 */ 1005 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE 1006 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE 1007 1008 /** 1009 * @} 1010 */ 1011 1012 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose 1013 * @{ 1014 */ 1015 #define KR_KEY_RELOAD IWDG_KEY_RELOAD 1016 #define KR_KEY_ENABLE IWDG_KEY_ENABLE 1017 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE 1018 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE 1019 /** 1020 * @} 1021 */ 1022 1023 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 1024 * @{ 1025 */ 1026 1027 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 1028 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS 1029 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS 1030 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS 1031 1032 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING 1033 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING 1034 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING 1035 1036 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 1037 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS 1038 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS 1039 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS 1040 1041 /* The following 3 definition have also been present in a temporary version of lptim.h */ 1042 /* They need to be renamed also to the right name, just in case */ 1043 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS 1044 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS 1045 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS 1046 1047 1048 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 1049 * @{ 1050 */ 1051 #define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue 1052 /** 1053 * @} 1054 */ 1055 1056 #if defined(STM32U5) 1057 #define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF 1058 #define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF 1059 #define LPTIM_CHANNEL_ALL 0x00000000U 1060 #endif /* STM32U5 */ 1061 /** 1062 * @} 1063 */ 1064 1065 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose 1066 * @{ 1067 */ 1068 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b 1069 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b 1070 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b 1071 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b 1072 1073 #define NAND_AddressTypedef NAND_AddressTypeDef 1074 1075 #define __ARRAY_ADDRESS ARRAY_ADDRESS 1076 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE 1077 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE 1078 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE 1079 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE 1080 /** 1081 * @} 1082 */ 1083 1084 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose 1085 * @{ 1086 */ 1087 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef 1088 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS 1089 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING 1090 #define NOR_ERROR HAL_NOR_STATUS_ERROR 1091 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT 1092 1093 #define __NOR_WRITE NOR_WRITE 1094 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT 1095 /** 1096 * @} 1097 */ 1098 1099 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose 1100 * @{ 1101 */ 1102 1103 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 1104 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 1105 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 1106 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 1107 1108 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 1109 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 1110 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 1111 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 1112 1113 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 1114 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 1115 1116 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 1117 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 1118 1119 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 1120 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 1121 1122 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 1123 1124 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO 1125 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 1126 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 1127 1128 #if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) 1129 #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID 1130 #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID 1131 #endif 1132 1133 #if defined(STM32L4) || defined(STM32L5) 1134 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER 1135 #elif defined(STM32G4) 1136 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED 1137 #endif 1138 1139 /** 1140 * @} 1141 */ 1142 1143 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose 1144 * @{ 1145 */ 1146 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS 1147 1148 #if defined(STM32H7) 1149 #define I2S_IT_TXE I2S_IT_TXP 1150 #define I2S_IT_RXNE I2S_IT_RXP 1151 1152 #define I2S_FLAG_TXE I2S_FLAG_TXP 1153 #define I2S_FLAG_RXNE I2S_FLAG_RXP 1154 #endif 1155 1156 #if defined(STM32F7) 1157 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL 1158 #endif 1159 /** 1160 * @} 1161 */ 1162 1163 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose 1164 * @{ 1165 */ 1166 1167 /* Compact Flash-ATA registers description */ 1168 #define CF_DATA ATA_DATA 1169 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT 1170 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER 1171 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW 1172 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH 1173 #define CF_CARD_HEAD ATA_CARD_HEAD 1174 #define CF_STATUS_CMD ATA_STATUS_CMD 1175 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE 1176 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA 1177 1178 /* Compact Flash-ATA commands */ 1179 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD 1180 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD 1181 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD 1182 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD 1183 1184 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef 1185 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS 1186 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING 1187 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR 1188 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT 1189 /** 1190 * @} 1191 */ 1192 1193 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose 1194 * @{ 1195 */ 1196 1197 #define FORMAT_BIN RTC_FORMAT_BIN 1198 #define FORMAT_BCD RTC_FORMAT_BCD 1199 1200 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE 1201 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE 1202 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1203 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1204 1205 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1206 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1207 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE 1208 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1209 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1210 1211 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT 1212 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 1213 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 1214 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 1215 1216 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE 1217 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 1218 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 1219 1220 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 1221 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 1222 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 1223 1224 #if defined(STM32F7) 1225 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK 1226 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK 1227 #endif /* STM32F7 */ 1228 1229 #if defined(STM32H7) 1230 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X 1231 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT 1232 #endif /* STM32H7 */ 1233 1234 #if defined(STM32F7) || defined(STM32H7) 1235 #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 1236 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 1237 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 1238 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP 1239 #endif /* STM32F7 || STM32H7 */ 1240 1241 /** 1242 * @} 1243 */ 1244 1245 1246 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose 1247 * @{ 1248 */ 1249 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE 1250 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE 1251 1252 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1253 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1254 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1255 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1256 1257 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE 1258 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE 1259 1260 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE 1261 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE 1262 /** 1263 * @} 1264 */ 1265 1266 1267 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose 1268 * @{ 1269 */ 1270 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE 1271 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE 1272 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE 1273 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE 1274 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE 1275 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE 1276 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE 1277 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE 1278 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE 1279 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE 1280 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN 1281 /** 1282 * @} 1283 */ 1284 1285 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose 1286 * @{ 1287 */ 1288 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE 1289 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE 1290 1291 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE 1292 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE 1293 1294 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE 1295 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE 1296 1297 #if defined(STM32H7) 1298 1299 #define SPI_FLAG_TXE SPI_FLAG_TXP 1300 #define SPI_FLAG_RXNE SPI_FLAG_RXP 1301 1302 #define SPI_IT_TXE SPI_IT_TXP 1303 #define SPI_IT_RXNE SPI_IT_RXP 1304 1305 #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET 1306 #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET 1307 #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET 1308 #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET 1309 1310 #endif /* STM32H7 */ 1311 1312 /** 1313 * @} 1314 */ 1315 1316 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose 1317 * @{ 1318 */ 1319 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK 1320 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK 1321 1322 #define TIM_DMABase_CR1 TIM_DMABASE_CR1 1323 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 1324 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR 1325 #define TIM_DMABase_DIER TIM_DMABASE_DIER 1326 #define TIM_DMABase_SR TIM_DMABASE_SR 1327 #define TIM_DMABase_EGR TIM_DMABASE_EGR 1328 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 1329 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 1330 #define TIM_DMABase_CCER TIM_DMABASE_CCER 1331 #define TIM_DMABase_CNT TIM_DMABASE_CNT 1332 #define TIM_DMABase_PSC TIM_DMABASE_PSC 1333 #define TIM_DMABase_ARR TIM_DMABASE_ARR 1334 #define TIM_DMABase_RCR TIM_DMABASE_RCR 1335 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 1336 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 1337 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 1338 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 1339 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR 1340 #define TIM_DMABase_DCR TIM_DMABASE_DCR 1341 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR 1342 #define TIM_DMABase_OR1 TIM_DMABASE_OR1 1343 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 1344 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 1345 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 1346 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 1347 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 1348 #define TIM_DMABase_OR TIM_DMABASE_OR 1349 1350 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE 1351 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 1352 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 1353 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 1354 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 1355 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM 1356 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER 1357 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK 1358 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 1359 1360 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER 1361 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS 1362 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS 1363 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS 1364 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS 1365 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS 1366 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS 1367 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS 1368 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS 1369 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS 1370 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS 1371 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS 1372 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS 1373 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS 1374 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS 1375 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS 1376 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS 1377 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS 1378 1379 #if defined(STM32L0) 1380 #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO 1381 #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO 1382 #endif 1383 1384 #if defined(STM32F3) 1385 #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE 1386 #endif 1387 1388 #if defined(STM32H7) 1389 #define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 1390 #define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 1391 #define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 1392 #define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 1393 #define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 1394 #define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 1395 #define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 1396 #define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 1397 #define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 1398 #define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 1399 #define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 1400 #define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 1401 #define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 1402 #define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 1403 #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 1404 #endif 1405 1406 #if defined(STM32U5) || defined(STM32MP2) 1407 #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS 1408 #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK 1409 #endif 1410 /** 1411 * @} 1412 */ 1413 1414 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose 1415 * @{ 1416 */ 1417 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING 1418 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING 1419 /** 1420 * @} 1421 */ 1422 1423 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose 1424 * @{ 1425 */ 1426 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1427 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1428 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1429 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1430 1431 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE 1432 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE 1433 1434 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 1435 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 1436 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 1437 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 1438 1439 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 1440 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 1441 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 1442 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 1443 1444 #define __DIV_LPUART UART_DIV_LPUART 1445 1446 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE 1447 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK 1448 1449 /** 1450 * @} 1451 */ 1452 1453 1454 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose 1455 * @{ 1456 */ 1457 1458 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE 1459 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE 1460 1461 #define USARTNACK_ENABLED USART_NACK_ENABLE 1462 #define USARTNACK_DISABLED USART_NACK_DISABLE 1463 /** 1464 * @} 1465 */ 1466 1467 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose 1468 * @{ 1469 */ 1470 #define CFR_BASE WWDG_CFR_BASE 1471 1472 /** 1473 * @} 1474 */ 1475 1476 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose 1477 * @{ 1478 */ 1479 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 1480 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 1481 #define CAN_IT_RQCP0 CAN_IT_TME 1482 #define CAN_IT_RQCP1 CAN_IT_TME 1483 #define CAN_IT_RQCP2 CAN_IT_TME 1484 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE 1485 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE 1486 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) 1487 #define CAN_TXSTATUS_OK ((uint8_t)0x01U) 1488 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) 1489 1490 /** 1491 * @} 1492 */ 1493 1494 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose 1495 * @{ 1496 */ 1497 1498 #define VLAN_TAG ETH_VLAN_TAG 1499 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD 1500 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD 1501 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD 1502 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK 1503 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK 1504 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK 1505 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK 1506 1507 #define ETH_MMCCR 0x00000100U 1508 #define ETH_MMCRIR 0x00000104U 1509 #define ETH_MMCTIR 0x00000108U 1510 #define ETH_MMCRIMR 0x0000010CU 1511 #define ETH_MMCTIMR 0x00000110U 1512 #define ETH_MMCTGFSCCR 0x0000014CU 1513 #define ETH_MMCTGFMSCCR 0x00000150U 1514 #define ETH_MMCTGFCR 0x00000168U 1515 #define ETH_MMCRFCECR 0x00000194U 1516 #define ETH_MMCRFAECR 0x00000198U 1517 #define ETH_MMCRGUFCR 0x000001C4U 1518 1519 #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ 1520 #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ 1521 #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ 1522 #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ 1523 #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to 1524 the MAC transmitter) */ 1525 #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from 1526 MAC transmitter */ 1527 #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus 1528 or flushing the TxFIFO */ 1529 #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ 1530 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ 1531 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status 1532 of previous frame or IFG/backoff period to be over */ 1533 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and 1534 transmitting a Pause control frame (in full duplex mode) */ 1535 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input 1536 frame for transmission */ 1537 #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ 1538 #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ 1539 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control 1540 de-activate threshold */ 1541 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control 1542 activate threshold */ 1543 #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ 1544 #if defined(STM32F1) 1545 #else 1546 #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ 1547 #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ 1548 #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status 1549 (or time-stamp) */ 1550 #endif 1551 #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and 1552 status */ 1553 #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ 1554 #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ 1555 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ 1556 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ 1557 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ 1558 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ 1559 1560 /** 1561 * @} 1562 */ 1563 1564 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose 1565 * @{ 1566 */ 1567 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR 1568 #define DCMI_IT_OVF DCMI_IT_OVR 1569 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI 1570 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI 1571 1572 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop 1573 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop 1574 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop 1575 1576 /** 1577 * @} 1578 */ 1579 1580 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1581 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1582 || defined(STM32H7) 1583 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose 1584 * @{ 1585 */ 1586 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 1587 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 1588 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 1589 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 1590 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 1591 1592 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 1593 #define CM_RGB888 DMA2D_INPUT_RGB888 1594 #define CM_RGB565 DMA2D_INPUT_RGB565 1595 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 1596 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 1597 #define CM_L8 DMA2D_INPUT_L8 1598 #define CM_AL44 DMA2D_INPUT_AL44 1599 #define CM_AL88 DMA2D_INPUT_AL88 1600 #define CM_L4 DMA2D_INPUT_L4 1601 #define CM_A8 DMA2D_INPUT_A8 1602 #define CM_A4 DMA2D_INPUT_A4 1603 /** 1604 * @} 1605 */ 1606 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ 1607 1608 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1609 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1610 || defined(STM32H7) || defined(STM32U5) 1611 /** @defgroup DMA2D_Aliases DMA2D API Aliases 1612 * @{ 1613 */ 1614 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort 1615 for compatibility with legacy code */ 1616 /** 1617 * @} 1618 */ 1619 1620 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ 1621 1622 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose 1623 * @{ 1624 */ 1625 1626 /** 1627 * @} 1628 */ 1629 1630 /* Exported functions --------------------------------------------------------*/ 1631 1632 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose 1633 * @{ 1634 */ 1635 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback 1636 /** 1637 * @} 1638 */ 1639 1640 /** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose 1641 * @{ 1642 */ 1643 1644 #if defined(STM32U5) 1645 #define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr 1646 #define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT 1647 #endif /* STM32U5 */ 1648 1649 /** 1650 * @} 1651 */ 1652 1653 #if !defined(STM32F2) 1654 /** @defgroup HASH_alias HASH API alias 1655 * @{ 1656 */ 1657 #define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ 1658 /** 1659 * 1660 * @} 1661 */ 1662 #endif /* STM32F2 */ 1663 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose 1664 * @{ 1665 */ 1666 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef 1667 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef 1668 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish 1669 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish 1670 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish 1671 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish 1672 1673 /*HASH Algorithm Selection*/ 1674 1675 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 1676 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 1677 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 1678 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 1679 1680 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH 1681 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC 1682 1683 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY 1684 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY 1685 1686 #if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) 1687 1688 #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt 1689 #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End 1690 #define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT 1691 #define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT 1692 1693 #define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt 1694 #define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End 1695 #define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT 1696 #define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT 1697 1698 #define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt 1699 #define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End 1700 #define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT 1701 #define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT 1702 1703 #define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt 1704 #define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End 1705 #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT 1706 #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT 1707 1708 #endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ 1709 /** 1710 * @} 1711 */ 1712 1713 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose 1714 * @{ 1715 */ 1716 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode 1717 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode 1718 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode 1719 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode 1720 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode 1721 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode 1722 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ 1723 )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) 1724 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect 1725 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) 1726 #if defined(STM32L0) 1727 #else 1728 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) 1729 #endif 1730 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) 1731 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ 1732 )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) 1733 #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) 1734 #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode 1735 #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode 1736 #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode 1737 #define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode 1738 #endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ 1739 1740 /** 1741 * @} 1742 */ 1743 1744 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose 1745 * @{ 1746 */ 1747 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram 1748 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown 1749 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown 1750 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock 1751 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock 1752 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase 1753 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program 1754 1755 /** 1756 * @} 1757 */ 1758 1759 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose 1760 * @{ 1761 */ 1762 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter 1763 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter 1764 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter 1765 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter 1766 1767 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ 1768 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) 1769 1770 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) 1771 #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT 1772 #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT 1773 #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT 1774 #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT 1775 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1776 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) 1777 #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA 1778 #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA 1779 #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA 1780 #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA 1781 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1782 1783 #if defined(STM32F4) 1784 #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT 1785 #define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT 1786 #define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT 1787 #define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT 1788 #define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA 1789 #define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA 1790 #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA 1791 #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA 1792 #endif /* STM32F4 */ 1793 /** 1794 * @} 1795 */ 1796 1797 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose 1798 * @{ 1799 */ 1800 1801 #if defined(STM32G0) 1802 #define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD 1803 #define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD 1804 #define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD 1805 #define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler 1806 #endif 1807 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD 1808 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg 1809 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown 1810 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor 1811 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg 1812 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown 1813 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor 1814 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler 1815 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD 1816 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler 1817 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback 1818 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive 1819 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive 1820 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC 1821 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC 1822 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM 1823 1824 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL 1825 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING 1826 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING 1827 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING 1828 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING 1829 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING 1830 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING 1831 1832 #define CR_OFFSET_BB PWR_CR_OFFSET_BB 1833 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB 1834 #define PMODE_BIT_NUMBER VOS_BIT_NUMBER 1835 #define CR_PMODE_BB CR_VOS_BB 1836 1837 #define DBP_BitNumber DBP_BIT_NUMBER 1838 #define PVDE_BitNumber PVDE_BIT_NUMBER 1839 #define PMODE_BitNumber PMODE_BIT_NUMBER 1840 #define EWUP_BitNumber EWUP_BIT_NUMBER 1841 #define FPDS_BitNumber FPDS_BIT_NUMBER 1842 #define ODEN_BitNumber ODEN_BIT_NUMBER 1843 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER 1844 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER 1845 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER 1846 #define BRE_BitNumber BRE_BIT_NUMBER 1847 1848 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL 1849 1850 #if defined (STM32U5) 1851 #define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP 1852 #define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP 1853 #define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP 1854 #define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP 1855 #define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP 1856 #define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP 1857 #define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP 1858 #define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP 1859 #define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP 1860 #define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP 1861 #define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP 1862 #define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP 1863 #define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP 1864 1865 #define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP 1866 #define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP 1867 #define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP 1868 1869 #define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP 1870 #define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP 1871 #define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP 1872 #define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP 1873 #define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP 1874 #define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP 1875 #define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP 1876 #define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP 1877 #define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP 1878 #define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP 1879 #define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP 1880 #define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP 1881 #define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP 1882 #define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP 1883 1884 #define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP 1885 1886 #define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP 1887 #define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP 1888 #define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP 1889 #define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP 1890 #define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP 1891 #define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP 1892 #define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP 1893 #define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP 1894 #define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP 1895 #define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP 1896 #define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP 1897 #define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP 1898 #define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP 1899 #define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP 1900 1901 #define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP 1902 #define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP 1903 #define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP 1904 #define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP 1905 #define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP 1906 #define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP 1907 #define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP 1908 #define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP 1909 1910 #define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY 1911 #define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY 1912 #define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY 1913 1914 #define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN 1915 #define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN 1916 #define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN 1917 #define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN 1918 #define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN 1919 1920 #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK 1921 #endif 1922 1923 /** 1924 * @} 1925 */ 1926 1927 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose 1928 * @{ 1929 */ 1930 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT 1931 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback 1932 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback 1933 /** 1934 * @} 1935 */ 1936 1937 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose 1938 * @{ 1939 */ 1940 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo 1941 /** 1942 * @} 1943 */ 1944 1945 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose 1946 * @{ 1947 */ 1948 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt 1949 #define HAL_TIM_DMAError TIM_DMAError 1950 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt 1951 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt 1952 #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) 1953 #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro 1954 #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT 1955 #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback 1956 #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent 1957 #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT 1958 #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA 1959 #endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ 1960 /** 1961 * @} 1962 */ 1963 1964 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose 1965 * @{ 1966 */ 1967 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback 1968 /** 1969 * @} 1970 */ 1971 1972 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose 1973 * @{ 1974 */ 1975 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback 1976 #define HAL_LTDC_Relaod HAL_LTDC_Reload 1977 #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig 1978 #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig 1979 /** 1980 * @} 1981 */ 1982 1983 1984 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose 1985 * @{ 1986 */ 1987 1988 /** 1989 * @} 1990 */ 1991 1992 /* Exported macros ------------------------------------------------------------*/ 1993 1994 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose 1995 * @{ 1996 */ 1997 #define AES_IT_CC CRYP_IT_CC 1998 #define AES_IT_ERR CRYP_IT_ERR 1999 #define AES_FLAG_CCF CRYP_FLAG_CCF 2000 /** 2001 * @} 2002 */ 2003 2004 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 2005 * @{ 2006 */ 2007 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE 2008 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH 2009 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH 2010 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM 2011 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC 2012 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 2013 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC 2014 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI 2015 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK 2016 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG 2017 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG 2018 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE 2019 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE 2020 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE 2021 2022 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY 2023 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 2024 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS 2025 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER 2026 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER 2027 2028 /** 2029 * @} 2030 */ 2031 2032 2033 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose 2034 * @{ 2035 */ 2036 #define __ADC_ENABLE __HAL_ADC_ENABLE 2037 #define __ADC_DISABLE __HAL_ADC_DISABLE 2038 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS 2039 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS 2040 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE 2041 #define __ADC_IS_ENABLED ADC_IS_ENABLE 2042 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR 2043 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED 2044 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED 2045 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR 2046 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED 2047 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING 2048 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE 2049 2050 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION 2051 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK 2052 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT 2053 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR 2054 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION 2055 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE 2056 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS 2057 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS 2058 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM 2059 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT 2060 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS 2061 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN 2062 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ 2063 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET 2064 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET 2065 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL 2066 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL 2067 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET 2068 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET 2069 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD 2070 2071 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION 2072 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION 2073 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION 2074 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER 2075 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI 2076 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 2077 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 2078 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER 2079 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER 2080 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE 2081 2082 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT 2083 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT 2084 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL 2085 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM 2086 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET 2087 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE 2088 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE 2089 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER 2090 2091 #define __HAL_ADC_SQR1 ADC_SQR1 2092 #define __HAL_ADC_SMPR1 ADC_SMPR1 2093 #define __HAL_ADC_SMPR2 ADC_SMPR2 2094 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK 2095 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK 2096 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK 2097 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS 2098 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS 2099 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV 2100 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection 2101 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq 2102 #define __HAL_ADC_JSQR ADC_JSQR 2103 2104 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL 2105 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS 2106 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF 2107 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT 2108 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS 2109 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN 2110 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR 2111 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ 2112 2113 /** 2114 * @} 2115 */ 2116 2117 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 2118 * @{ 2119 */ 2120 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT 2121 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT 2122 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT 2123 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE 2124 2125 /** 2126 * @} 2127 */ 2128 2129 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose 2130 * @{ 2131 */ 2132 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 2133 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 2134 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 2135 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 2136 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 2137 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 2138 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 2139 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 2140 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 2141 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 2142 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 2143 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 2144 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 2145 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 2146 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 2147 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 2148 2149 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 2150 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 2151 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 2152 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 2153 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 2154 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 2155 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 2156 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 2157 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 2158 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 2159 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 2160 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 2161 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 2162 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 2163 2164 2165 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 2166 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 2167 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 2168 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 2169 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 2170 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 2171 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC 2172 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC 2173 #if defined(STM32H7) 2174 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 2175 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 2176 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 2177 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 2178 #else 2179 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG 2180 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG 2181 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG 2182 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG 2183 #endif /* STM32H7 */ 2184 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT 2185 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT 2186 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT 2187 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT 2188 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT 2189 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT 2190 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 2191 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 2192 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 2193 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 2194 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 2195 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 2196 2197 /** 2198 * @} 2199 */ 2200 2201 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose 2202 * @{ 2203 */ 2204 #if defined(STM32F3) 2205 #define COMP_START __HAL_COMP_ENABLE 2206 #define COMP_STOP __HAL_COMP_DISABLE 2207 #define COMP_LOCK __HAL_COMP_LOCK 2208 2209 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2210 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2211 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2212 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 2213 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2214 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2215 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 2216 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2217 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2218 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 2219 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2220 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2221 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 2222 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2223 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2224 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 2225 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2226 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2227 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 2228 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2229 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2230 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 2231 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2232 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2233 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 2234 # endif 2235 # if defined(STM32F302xE) || defined(STM32F302xC) 2236 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2237 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2238 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2239 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 2240 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2241 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2242 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2243 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 2244 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2245 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2246 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2247 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 2248 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2249 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2250 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2251 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 2252 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2253 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2254 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2255 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 2256 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2257 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2258 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2259 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 2260 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2261 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2262 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2263 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 2264 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2265 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2266 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2267 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 2268 # endif 2269 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) 2270 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2271 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2272 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ 2273 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2274 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ 2275 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ 2276 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) 2277 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2278 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2279 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ 2280 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2281 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ 2282 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ 2283 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) 2284 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2285 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2286 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ 2287 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2288 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ 2289 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ 2290 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) 2291 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2292 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2293 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ 2294 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2295 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ 2296 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ 2297 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) 2298 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2299 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2300 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ 2301 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2302 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ 2303 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ 2304 __HAL_COMP_COMP7_EXTI_ENABLE_IT()) 2305 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2306 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2307 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ 2308 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2309 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ 2310 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ 2311 __HAL_COMP_COMP7_EXTI_DISABLE_IT()) 2312 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2313 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2314 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ 2315 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2316 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ 2317 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ 2318 __HAL_COMP_COMP7_EXTI_GET_FLAG()) 2319 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2320 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2321 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ 2322 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2323 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ 2324 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ 2325 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) 2326 # endif 2327 # if defined(STM32F373xC) ||defined(STM32F378xx) 2328 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2329 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2330 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2331 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2332 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2333 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2334 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2335 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2336 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2337 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2338 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2339 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2340 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2341 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2342 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2343 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2344 # endif 2345 #else 2346 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2347 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2348 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2349 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2350 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2351 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2352 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2353 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2354 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2355 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2356 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2357 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2358 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2359 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2360 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2361 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2362 #endif 2363 2364 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE 2365 2366 #if defined(STM32L0) || defined(STM32L4) 2367 /* Note: On these STM32 families, the only argument of this macro */ 2368 /* is COMP_FLAG_LOCK. */ 2369 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ 2370 /* argument. */ 2371 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) 2372 #endif 2373 /** 2374 * @} 2375 */ 2376 2377 #if defined(STM32L0) || defined(STM32L4) 2378 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose 2379 * @{ 2380 */ 2381 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is 2382 done into HAL_COMP_Init() */ 2383 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is 2384 done into HAL_COMP_Init() */ 2385 /** 2386 * @} 2387 */ 2388 #endif 2389 2390 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 2391 * @{ 2392 */ 2393 2394 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ 2395 ((WAVE) == DAC_WAVE_NOISE)|| \ 2396 ((WAVE) == DAC_WAVE_TRIANGLE)) 2397 2398 /** 2399 * @} 2400 */ 2401 2402 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose 2403 * @{ 2404 */ 2405 2406 #define IS_WRPAREA IS_OB_WRPAREA 2407 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM 2408 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM 2409 #define IS_TYPEERASE IS_FLASH_TYPEERASE 2410 #define IS_NBSECTORS IS_FLASH_NBSECTORS 2411 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE 2412 2413 /** 2414 * @} 2415 */ 2416 2417 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose 2418 * @{ 2419 */ 2420 2421 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 2422 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START 2423 #if defined(STM32F1) 2424 #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE 2425 #else 2426 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE 2427 #endif /* STM32F1 */ 2428 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME 2429 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD 2430 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST 2431 #define __HAL_I2C_SPEED I2C_SPEED 2432 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE 2433 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ 2434 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS 2435 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE 2436 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ 2437 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB 2438 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB 2439 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE 2440 /** 2441 * @} 2442 */ 2443 2444 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose 2445 * @{ 2446 */ 2447 2448 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE 2449 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT 2450 2451 #if defined(STM32H7) 2452 #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG 2453 #endif 2454 2455 /** 2456 * @} 2457 */ 2458 2459 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose 2460 * @{ 2461 */ 2462 2463 #define __IRDA_DISABLE __HAL_IRDA_DISABLE 2464 #define __IRDA_ENABLE __HAL_IRDA_ENABLE 2465 2466 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2467 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2468 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2469 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2470 2471 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE 2472 2473 2474 /** 2475 * @} 2476 */ 2477 2478 2479 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose 2480 * @{ 2481 */ 2482 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS 2483 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS 2484 /** 2485 * @} 2486 */ 2487 2488 2489 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose 2490 * @{ 2491 */ 2492 2493 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT 2494 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT 2495 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE 2496 2497 /** 2498 * @} 2499 */ 2500 2501 2502 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose 2503 * @{ 2504 */ 2505 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD 2506 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX 2507 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX 2508 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX 2509 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX 2510 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L 2511 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H 2512 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM 2513 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES 2514 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX 2515 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT 2516 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION 2517 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET 2518 2519 /** 2520 * @} 2521 */ 2522 2523 2524 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose 2525 * @{ 2526 */ 2527 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2528 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2529 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2530 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2531 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2532 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2533 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE 2534 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE 2535 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE 2536 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE 2537 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE 2538 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE 2539 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine 2540 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine 2541 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig 2542 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig 2543 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) 2544 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2545 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2546 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2547 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2548 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2549 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2550 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2551 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2552 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) 2553 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) 2554 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention 2555 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention 2556 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 2557 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 2558 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE 2559 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE 2560 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB 2561 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB 2562 2563 #if defined (STM32F4) 2564 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() 2565 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() 2566 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() 2567 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() 2568 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() 2569 #else 2570 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG 2571 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT 2572 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT 2573 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT 2574 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG 2575 #endif /* STM32F4 */ 2576 /** 2577 * @} 2578 */ 2579 2580 2581 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose 2582 * @{ 2583 */ 2584 2585 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI 2586 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI 2587 2588 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback 2589 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ 2590 )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) 2591 2592 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE 2593 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE 2594 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE 2595 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE 2596 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET 2597 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET 2598 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE 2599 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE 2600 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET 2601 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET 2602 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE 2603 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE 2604 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE 2605 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE 2606 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET 2607 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET 2608 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE 2609 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE 2610 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET 2611 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET 2612 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 2613 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 2614 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 2615 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 2616 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 2617 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 2618 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE 2619 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE 2620 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE 2621 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE 2622 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET 2623 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET 2624 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 2625 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 2626 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 2627 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 2628 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET 2629 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET 2630 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET 2631 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET 2632 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET 2633 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET 2634 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET 2635 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET 2636 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET 2637 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET 2638 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET 2639 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET 2640 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE 2641 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE 2642 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET 2643 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET 2644 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2645 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2646 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE 2647 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE 2648 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2649 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2650 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2651 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2652 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2653 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2654 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE 2655 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE 2656 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET 2657 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET 2658 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE 2659 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE 2660 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE 2661 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE 2662 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET 2663 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET 2664 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE 2665 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE 2666 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET 2667 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET 2668 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE 2669 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE 2670 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE 2671 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE 2672 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET 2673 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET 2674 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE 2675 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE 2676 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET 2677 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET 2678 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE 2679 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE 2680 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE 2681 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE 2682 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET 2683 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET 2684 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE 2685 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE 2686 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET 2687 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET 2688 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE 2689 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE 2690 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE 2691 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE 2692 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET 2693 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET 2694 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE 2695 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE 2696 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE 2697 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE 2698 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET 2699 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET 2700 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE 2701 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE 2702 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE 2703 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE 2704 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET 2705 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET 2706 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE 2707 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE 2708 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET 2709 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET 2710 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE 2711 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE 2712 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE 2713 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE 2714 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE 2715 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE 2716 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE 2717 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE 2718 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE 2719 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE 2720 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET 2721 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET 2722 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE 2723 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE 2724 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET 2725 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET 2726 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE 2727 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE 2728 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE 2729 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE 2730 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE 2731 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE 2732 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET 2733 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET 2734 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE 2735 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE 2736 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE 2737 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE 2738 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE 2739 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE 2740 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET 2741 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET 2742 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE 2743 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE 2744 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE 2745 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE 2746 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET 2747 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET 2748 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE 2749 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE 2750 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE 2751 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE 2752 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET 2753 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET 2754 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE 2755 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE 2756 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE 2757 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE 2758 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET 2759 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET 2760 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE 2761 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE 2762 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE 2763 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE 2764 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET 2765 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET 2766 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE 2767 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE 2768 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE 2769 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE 2770 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET 2771 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET 2772 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE 2773 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE 2774 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE 2775 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE 2776 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET 2777 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET 2778 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE 2779 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE 2780 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE 2781 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE 2782 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET 2783 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET 2784 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE 2785 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE 2786 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE 2787 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE 2788 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET 2789 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET 2790 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE 2791 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE 2792 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE 2793 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE 2794 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET 2795 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET 2796 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE 2797 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE 2798 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE 2799 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE 2800 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET 2801 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET 2802 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE 2803 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE 2804 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE 2805 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE 2806 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET 2807 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET 2808 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE 2809 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE 2810 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE 2811 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE 2812 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET 2813 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET 2814 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE 2815 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE 2816 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE 2817 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE 2818 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET 2819 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET 2820 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE 2821 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE 2822 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE 2823 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE 2824 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET 2825 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET 2826 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE 2827 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE 2828 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE 2829 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE 2830 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET 2831 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET 2832 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE 2833 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE 2834 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE 2835 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE 2836 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET 2837 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET 2838 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE 2839 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE 2840 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE 2841 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE 2842 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET 2843 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET 2844 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE 2845 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE 2846 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE 2847 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE 2848 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET 2849 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET 2850 2851 #if defined(STM32WB) 2852 #define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE 2853 #define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE 2854 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE 2855 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE 2856 #define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET 2857 #define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET 2858 #define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED 2859 #define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED 2860 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED 2861 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED 2862 #define QSPI_IRQHandler QUADSPI_IRQHandler 2863 #endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ 2864 2865 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE 2866 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE 2867 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE 2868 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE 2869 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET 2870 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET 2871 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE 2872 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE 2873 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE 2874 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE 2875 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET 2876 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET 2877 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE 2878 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE 2879 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE 2880 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE 2881 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET 2882 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET 2883 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 2884 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 2885 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE 2886 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE 2887 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE 2888 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE 2889 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET 2890 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET 2891 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE 2892 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE 2893 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE 2894 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE 2895 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET 2896 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET 2897 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE 2898 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE 2899 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE 2900 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE 2901 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET 2902 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET 2903 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE 2904 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE 2905 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE 2906 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE 2907 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET 2908 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET 2909 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE 2910 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE 2911 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE 2912 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE 2913 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE 2914 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE 2915 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE 2916 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE 2917 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE 2918 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE 2919 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET 2920 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET 2921 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE 2922 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE 2923 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE 2924 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE 2925 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET 2926 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET 2927 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE 2928 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE 2929 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE 2930 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE 2931 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET 2932 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET 2933 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE 2934 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE 2935 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET 2936 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET 2937 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE 2938 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE 2939 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET 2940 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET 2941 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE 2942 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE 2943 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET 2944 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET 2945 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE 2946 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE 2947 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET 2948 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET 2949 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE 2950 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE 2951 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET 2952 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET 2953 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE 2954 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE 2955 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE 2956 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE 2957 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET 2958 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET 2959 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE 2960 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE 2961 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE 2962 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE 2963 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET 2964 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET 2965 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE 2966 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE 2967 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE 2968 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE 2969 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET 2970 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET 2971 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE 2972 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE 2973 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE 2974 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE 2975 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET 2976 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET 2977 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE 2978 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE 2979 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE 2980 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE 2981 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET 2982 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET 2983 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE 2984 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE 2985 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE 2986 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE 2987 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET 2988 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET 2989 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE 2990 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE 2991 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE 2992 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE 2993 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET 2994 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET 2995 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE 2996 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE 2997 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE 2998 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE 2999 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET 3000 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET 3001 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE 3002 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE 3003 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE 3004 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE 3005 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET 3006 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET 3007 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE 3008 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE 3009 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE 3010 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE 3011 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET 3012 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET 3013 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE 3014 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE 3015 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET 3016 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET 3017 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE 3018 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE 3019 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE 3020 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE 3021 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET 3022 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET 3023 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 3024 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 3025 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 3026 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 3027 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 3028 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 3029 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 3030 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 3031 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 3032 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 3033 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 3034 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 3035 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE 3036 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE 3037 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE 3038 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE 3039 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET 3040 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET 3041 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE 3042 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE 3043 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE 3044 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE 3045 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET 3046 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET 3047 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE 3048 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE 3049 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE 3050 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE 3051 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET 3052 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET 3053 #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 3054 #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 3055 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 3056 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 3057 #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 3058 #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 3059 #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 3060 #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 3061 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 3062 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 3063 #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 3064 #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 3065 #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 3066 #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 3067 #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 3068 #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 3069 #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 3070 #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 3071 #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 3072 #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 3073 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE 3074 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE 3075 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET 3076 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE 3077 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE 3078 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE 3079 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE 3080 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET 3081 3082 #if defined(STM32H7) 3083 #define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE 3084 #define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE 3085 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE 3086 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE 3087 3088 #define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ 3089 #define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ 3090 3091 3092 #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED 3093 #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED 3094 #define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 3095 #define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 3096 #define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 3097 #define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 3098 #define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 3099 #endif 3100 3101 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE 3102 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE 3103 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE 3104 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE 3105 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET 3106 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET 3107 3108 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE 3109 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE 3110 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET 3111 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET 3112 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE 3113 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE 3114 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE 3115 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE 3116 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET 3117 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET 3118 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE 3119 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE 3120 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE 3121 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE 3122 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE 3123 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE 3124 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET 3125 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET 3126 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE 3127 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE 3128 3129 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 3130 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 3131 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE 3132 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE 3133 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE 3134 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE 3135 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE 3136 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE 3137 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE 3138 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE 3139 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE 3140 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE 3141 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE 3142 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE 3143 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE 3144 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE 3145 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE 3146 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE 3147 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE 3148 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET 3149 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET 3150 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE 3151 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE 3152 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE 3153 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE 3154 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE 3155 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET 3156 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET 3157 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE 3158 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE 3159 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE 3160 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE 3161 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET 3162 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET 3163 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE 3164 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE 3165 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE 3166 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE 3167 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET 3168 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET 3169 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE 3170 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE 3171 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE 3172 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE 3173 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE 3174 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE 3175 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE 3176 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE 3177 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE 3178 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE 3179 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE 3180 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE 3181 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE 3182 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE 3183 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE 3184 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE 3185 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE 3186 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE 3187 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE 3188 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE 3189 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE 3190 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET 3191 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET 3192 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE 3193 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE 3194 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE 3195 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE 3196 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET 3197 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET 3198 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE 3199 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE 3200 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE 3201 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE 3202 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET 3203 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET 3204 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE 3205 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE 3206 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE 3207 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE 3208 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET 3209 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET 3210 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE 3211 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE 3212 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE 3213 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE 3214 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET 3215 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE 3216 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE 3217 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE 3218 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE 3219 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE 3220 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE 3221 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET 3222 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET 3223 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE 3224 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE 3225 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 3226 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 3227 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 3228 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 3229 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE 3230 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE 3231 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 3232 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 3233 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 3234 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 3235 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE 3236 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE 3237 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 3238 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 3239 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 3240 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 3241 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 3242 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 3243 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 3244 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 3245 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED 3246 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED 3247 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 3248 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 3249 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 3250 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 3251 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED 3252 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED 3253 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE 3254 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE 3255 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE 3256 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE 3257 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE 3258 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE 3259 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE 3260 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE 3261 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE 3262 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET 3263 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET 3264 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE 3265 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE 3266 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3267 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3268 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3269 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3270 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE 3271 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE 3272 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET 3273 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET 3274 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE 3275 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE 3276 3277 /* alias define maintained for legacy */ 3278 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 3279 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 3280 3281 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 3282 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 3283 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE 3284 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE 3285 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE 3286 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE 3287 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE 3288 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE 3289 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE 3290 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE 3291 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE 3292 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE 3293 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE 3294 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE 3295 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE 3296 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE 3297 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE 3298 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE 3299 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE 3300 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE 3301 3302 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 3303 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 3304 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET 3305 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET 3306 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET 3307 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET 3308 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET 3309 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET 3310 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET 3311 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET 3312 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET 3313 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET 3314 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET 3315 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET 3316 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET 3317 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET 3318 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET 3319 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET 3320 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET 3321 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET 3322 3323 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED 3324 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED 3325 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3326 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3327 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED 3328 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED 3329 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED 3330 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED 3331 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED 3332 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED 3333 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED 3334 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED 3335 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED 3336 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED 3337 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED 3338 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED 3339 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED 3340 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED 3341 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED 3342 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED 3343 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED 3344 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED 3345 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED 3346 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED 3347 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED 3348 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED 3349 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED 3350 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED 3351 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED 3352 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED 3353 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED 3354 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED 3355 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED 3356 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED 3357 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED 3358 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED 3359 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED 3360 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED 3361 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED 3362 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED 3363 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED 3364 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED 3365 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED 3366 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED 3367 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED 3368 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED 3369 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED 3370 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED 3371 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED 3372 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED 3373 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED 3374 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED 3375 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED 3376 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED 3377 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED 3378 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED 3379 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED 3380 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED 3381 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED 3382 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED 3383 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED 3384 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED 3385 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED 3386 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED 3387 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED 3388 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED 3389 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED 3390 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED 3391 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED 3392 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED 3393 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED 3394 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED 3395 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED 3396 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED 3397 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED 3398 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED 3399 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED 3400 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED 3401 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED 3402 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED 3403 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED 3404 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED 3405 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED 3406 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED 3407 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED 3408 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED 3409 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED 3410 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED 3411 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED 3412 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED 3413 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED 3414 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED 3415 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED 3416 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED 3417 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED 3418 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED 3419 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED 3420 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED 3421 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED 3422 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED 3423 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED 3424 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED 3425 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED 3426 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED 3427 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED 3428 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED 3429 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED 3430 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED 3431 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED 3432 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED 3433 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED 3434 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED 3435 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED 3436 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED 3437 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED 3438 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED 3439 3440 #if defined(STM32L1) 3441 #define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 3442 #define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 3443 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 3444 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 3445 #define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 3446 #define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 3447 #endif /* STM32L1 */ 3448 3449 #if defined(STM32F4) 3450 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3451 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3452 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3453 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3454 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 3455 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 3456 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED 3457 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED 3458 #define Sdmmc1ClockSelection SdioClockSelection 3459 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO 3460 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 3461 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK 3462 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG 3463 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE 3464 #endif 3465 3466 #if defined(STM32F7) || defined(STM32L4) 3467 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET 3468 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET 3469 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE 3470 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE 3471 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE 3472 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE 3473 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED 3474 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED 3475 #define SdioClockSelection Sdmmc1ClockSelection 3476 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 3477 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG 3478 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE 3479 #endif 3480 3481 #if defined(STM32F7) 3482 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 3483 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK 3484 #endif 3485 3486 #if defined(STM32H7) 3487 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() 3488 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() 3489 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() 3490 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() 3491 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() 3492 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() 3493 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() 3494 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() 3495 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() 3496 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() 3497 3498 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() 3499 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() 3500 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() 3501 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() 3502 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() 3503 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() 3504 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() 3505 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() 3506 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() 3507 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() 3508 #endif 3509 3510 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG 3511 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG 3512 3513 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE 3514 3515 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE 3516 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE 3517 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK 3518 #define IS_RCC_HCLK_DIV IS_RCC_PCLK 3519 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK 3520 3521 #define RCC_IT_HSI14 RCC_IT_HSI14RDY 3522 3523 #define RCC_IT_CSSLSE RCC_IT_LSECSS 3524 #define RCC_IT_CSSHSE RCC_IT_CSS 3525 3526 #define RCC_PLLMUL_3 RCC_PLL_MUL3 3527 #define RCC_PLLMUL_4 RCC_PLL_MUL4 3528 #define RCC_PLLMUL_6 RCC_PLL_MUL6 3529 #define RCC_PLLMUL_8 RCC_PLL_MUL8 3530 #define RCC_PLLMUL_12 RCC_PLL_MUL12 3531 #define RCC_PLLMUL_16 RCC_PLL_MUL16 3532 #define RCC_PLLMUL_24 RCC_PLL_MUL24 3533 #define RCC_PLLMUL_32 RCC_PLL_MUL32 3534 #define RCC_PLLMUL_48 RCC_PLL_MUL48 3535 3536 #define RCC_PLLDIV_2 RCC_PLL_DIV2 3537 #define RCC_PLLDIV_3 RCC_PLL_DIV3 3538 #define RCC_PLLDIV_4 RCC_PLL_DIV4 3539 3540 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE 3541 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG 3542 #define RCC_MCO_NODIV RCC_MCODIV_1 3543 #define RCC_MCO_DIV1 RCC_MCODIV_1 3544 #define RCC_MCO_DIV2 RCC_MCODIV_2 3545 #define RCC_MCO_DIV4 RCC_MCODIV_4 3546 #define RCC_MCO_DIV8 RCC_MCODIV_8 3547 #define RCC_MCO_DIV16 RCC_MCODIV_16 3548 #define RCC_MCO_DIV32 RCC_MCODIV_32 3549 #define RCC_MCO_DIV64 RCC_MCODIV_64 3550 #define RCC_MCO_DIV128 RCC_MCODIV_128 3551 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK 3552 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI 3553 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE 3554 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK 3555 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI 3556 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 3557 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 3558 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE 3559 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK 3560 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK 3561 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 3562 3563 #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) 3564 #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE 3565 #else 3566 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK 3567 #endif 3568 3569 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 3570 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL 3571 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI 3572 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL 3573 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL 3574 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 3575 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 3576 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 3577 3578 #define HSION_BitNumber RCC_HSION_BIT_NUMBER 3579 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER 3580 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER 3581 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER 3582 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER 3583 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER 3584 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER 3585 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER 3586 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER 3587 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER 3588 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER 3589 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER 3590 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER 3591 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER 3592 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER 3593 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER 3594 #define LSION_BitNumber RCC_LSION_BIT_NUMBER 3595 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER 3596 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER 3597 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER 3598 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER 3599 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER 3600 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER 3601 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER 3602 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER 3603 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER 3604 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS 3605 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS 3606 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS 3607 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS 3608 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE 3609 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE 3610 3611 #define CR_HSION_BB RCC_CR_HSION_BB 3612 #define CR_CSSON_BB RCC_CR_CSSON_BB 3613 #define CR_PLLON_BB RCC_CR_PLLON_BB 3614 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB 3615 #define CR_MSION_BB RCC_CR_MSION_BB 3616 #define CSR_LSION_BB RCC_CSR_LSION_BB 3617 #define CSR_LSEON_BB RCC_CSR_LSEON_BB 3618 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB 3619 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB 3620 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB 3621 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB 3622 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB 3623 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB 3624 #define CR_HSEON_BB RCC_CR_HSEON_BB 3625 #define CSR_RMVF_BB RCC_CSR_RMVF_BB 3626 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB 3627 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB 3628 3629 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE 3630 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE 3631 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE 3632 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE 3633 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE 3634 3635 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT 3636 3637 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN 3638 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF 3639 3640 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 3641 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ 3642 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP 3643 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ 3644 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE 3645 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 3646 3647 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE 3648 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE 3649 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED 3650 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED 3651 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET 3652 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET 3653 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE 3654 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE 3655 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED 3656 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED 3657 #define DfsdmClockSelection Dfsdm1ClockSelection 3658 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 3659 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3660 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK 3661 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG 3662 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE 3663 #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3664 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 3665 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 3666 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 3667 3668 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 3669 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 3670 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 3671 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 3672 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 3673 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 3674 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 3675 #if defined(STM32U5) 3676 #define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL 3677 #define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL 3678 #define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE 3679 #define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE 3680 #define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE 3681 #define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE 3682 #define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE 3683 #define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE 3684 #define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE 3685 #define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE 3686 #define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE 3687 #define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT 3688 #define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK 3689 #define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 3690 #define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 3691 #define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 3692 #define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK 3693 #define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 3694 #define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 3695 #define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3696 #define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3697 #define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 3698 #define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 3699 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE 3700 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE 3701 #define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE 3702 #define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE 3703 #define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE 3704 #define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG 3705 #define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE 3706 #endif /* STM32U5 */ 3707 3708 #if defined(STM32H5) 3709 #define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE 3710 #define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE 3711 #define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG 3712 #define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE 3713 3714 #define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE 3715 #define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI 3716 #define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI 3717 #define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE 3718 #define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 3719 #define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 3720 #define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 3721 #define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 3722 #define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE 3723 #define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM 3724 3725 #define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE 3726 #define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE 3727 #define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE 3728 #define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE 3729 #define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE 3730 #define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE 3731 #define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE 3732 #define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE 3733 #define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE 3734 #define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE 3735 3736 #define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE 3737 #define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE 3738 #define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE 3739 #define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE 3740 #define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG 3741 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG 3742 #define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG 3743 #define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG 3744 #define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE 3745 #define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE 3746 #define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE 3747 #define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE 3748 #define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE 3749 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG 3750 3751 #define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE 3752 #define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE 3753 #define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE 3754 #define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE 3755 #define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG 3756 #define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG 3757 3758 #define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE 3759 #define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE 3760 #define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE 3761 #define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE 3762 #define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG 3763 #define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG 3764 3765 #define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 3766 #define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 3767 #define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 3768 #define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 3769 3770 #define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE 3771 #define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM 3772 3773 #define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE 3774 #define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI 3775 #define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI 3776 #define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE 3777 3778 #define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 3779 #define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 3780 #define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 3781 #define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 3782 3783 #define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE 3784 #define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM 3785 3786 #define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE 3787 #define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI 3788 #define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI 3789 #define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE 3790 3791 3792 #endif /* STM32H5 */ 3793 3794 /** 3795 * @} 3796 */ 3797 3798 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose 3799 * @{ 3800 */ 3801 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) 3802 3803 /** 3804 * @} 3805 */ 3806 3807 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose 3808 * @{ 3809 */ 3810 #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \ 3811 defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ 3812 defined (STM32H5) 3813 #else 3814 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG 3815 #endif 3816 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT 3817 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT 3818 3819 #if defined (STM32F1) 3820 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() 3821 3822 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() 3823 3824 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() 3825 3826 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() 3827 3828 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() 3829 #else 3830 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ 3831 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ 3832 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) 3833 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ 3834 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ 3835 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) 3836 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ 3837 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ 3838 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) 3839 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ 3840 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ 3841 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) 3842 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ 3843 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ 3844 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) 3845 #endif /* STM32F1 */ 3846 3847 #if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ 3848 defined (STM32H7) || \ 3849 defined (STM32L0) || defined (STM32L1) 3850 #define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG 3851 #endif 3852 3853 #define IS_ALARM IS_RTC_ALARM 3854 #define IS_ALARM_MASK IS_RTC_ALARM_MASK 3855 #define IS_TAMPER IS_RTC_TAMPER 3856 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE 3857 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER 3858 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT 3859 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE 3860 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION 3861 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE 3862 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ 3863 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION 3864 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER 3865 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK 3866 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER 3867 3868 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE 3869 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE 3870 3871 #if defined (STM32H5) 3872 #define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE 3873 #define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE 3874 #endif /* STM32H5 */ 3875 3876 /** 3877 * @} 3878 */ 3879 3880 /** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose 3881 * @{ 3882 */ 3883 3884 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE 3885 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS 3886 3887 #if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) 3888 #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE 3889 #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE 3890 #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE 3891 3892 #define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV 3893 #define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV 3894 #endif 3895 3896 #if defined(STM32F4) || defined(STM32F2) 3897 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED 3898 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY 3899 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED 3900 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION 3901 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND 3902 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT 3903 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED 3904 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE 3905 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE 3906 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE 3907 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL 3908 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT 3909 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT 3910 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG 3911 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG 3912 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT 3913 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT 3914 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS 3915 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT 3916 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND 3917 /* alias CMSIS */ 3918 #define SDMMC1_IRQn SDIO_IRQn 3919 #define SDMMC1_IRQHandler SDIO_IRQHandler 3920 #endif 3921 3922 #if defined(STM32F7) || defined(STM32L4) 3923 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED 3924 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY 3925 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED 3926 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION 3927 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND 3928 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT 3929 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED 3930 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE 3931 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE 3932 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE 3933 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE 3934 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT 3935 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT 3936 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG 3937 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG 3938 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT 3939 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT 3940 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS 3941 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT 3942 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND 3943 /* alias CMSIS for compatibilities */ 3944 #define SDIO_IRQn SDMMC1_IRQn 3945 #define SDIO_IRQHandler SDMMC1_IRQHandler 3946 #endif 3947 3948 #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) 3949 #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef 3950 #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef 3951 #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef 3952 #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef 3953 #endif 3954 3955 #if defined(STM32H7) || defined(STM32L5) 3956 #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback 3957 #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback 3958 #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback 3959 #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback 3960 #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback 3961 #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback 3962 #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback 3963 #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback 3964 #define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback 3965 #endif 3966 /** 3967 * @} 3968 */ 3969 3970 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose 3971 * @{ 3972 */ 3973 3974 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT 3975 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT 3976 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE 3977 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE 3978 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE 3979 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE 3980 3981 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3982 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3983 3984 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE 3985 3986 /** 3987 * @} 3988 */ 3989 3990 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose 3991 * @{ 3992 */ 3993 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 3994 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 3995 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START 3996 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH 3997 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR 3998 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE 3999 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE 4000 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED 4001 /** 4002 * @} 4003 */ 4004 4005 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose 4006 * @{ 4007 */ 4008 4009 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX 4010 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX 4011 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC 4012 4013 /** 4014 * @} 4015 */ 4016 4017 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose 4018 * @{ 4019 */ 4020 4021 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 4022 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION 4023 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 4024 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION 4025 4026 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD 4027 4028 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE 4029 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE 4030 4031 /** 4032 * @} 4033 */ 4034 4035 4036 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose 4037 * @{ 4038 */ 4039 4040 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT 4041 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT 4042 #define __USART_ENABLE __HAL_USART_ENABLE 4043 #define __USART_DISABLE __HAL_USART_DISABLE 4044 4045 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 4046 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 4047 4048 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) 4049 #define USART_OVERSAMPLING_16 0x00000000U 4050 #define USART_OVERSAMPLING_8 USART_CR1_OVER8 4051 4052 #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ 4053 ((__SAMPLING__) == USART_OVERSAMPLING_8)) 4054 #endif /* STM32F0 || STM32F3 || STM32F7 */ 4055 /** 4056 * @} 4057 */ 4058 4059 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose 4060 * @{ 4061 */ 4062 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE 4063 4064 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 4065 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 4066 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 4067 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE 4068 4069 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 4070 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 4071 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 4072 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE 4073 4074 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT 4075 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT 4076 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG 4077 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG 4078 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE 4079 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE 4080 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 4081 4082 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT 4083 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT 4084 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG 4085 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG 4086 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE 4087 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 4088 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 4089 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT 4090 4091 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT 4092 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT 4093 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG 4094 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG 4095 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE 4096 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 4097 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 4098 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT 4099 4100 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup 4101 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup 4102 4103 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo 4104 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo 4105 /** 4106 * @} 4107 */ 4108 4109 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose 4110 * @{ 4111 */ 4112 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE 4113 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE 4114 4115 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 4116 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT 4117 4118 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 4119 4120 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN 4121 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER 4122 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER 4123 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER 4124 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD 4125 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD 4126 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION 4127 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION 4128 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER 4129 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER 4130 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE 4131 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE 4132 4133 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 4134 /** 4135 * @} 4136 */ 4137 4138 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose 4139 * @{ 4140 */ 4141 4142 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT 4143 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT 4144 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG 4145 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG 4146 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER 4147 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER 4148 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER 4149 4150 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE 4151 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE 4152 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE 4153 /** 4154 * @} 4155 */ 4156 4157 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose 4158 * @{ 4159 */ 4160 #define __HAL_LTDC_LAYER LTDC_LAYER 4161 #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG 4162 /** 4163 * @} 4164 */ 4165 4166 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose 4167 * @{ 4168 */ 4169 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE 4170 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE 4171 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE 4172 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE 4173 #define SAI_STREOMODE SAI_STEREOMODE 4174 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY 4175 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL 4176 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL 4177 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL 4178 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL 4179 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL 4180 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE 4181 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 4182 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE 4183 /** 4184 * @} 4185 */ 4186 4187 /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose 4188 * @{ 4189 */ 4190 #if defined(STM32H7) 4191 #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow 4192 #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT 4193 #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA 4194 #endif 4195 /** 4196 * @} 4197 */ 4198 4199 /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose 4200 * @{ 4201 */ 4202 #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) 4203 #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT 4204 #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA 4205 #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart 4206 #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT 4207 #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA 4208 #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop 4209 #endif 4210 /** 4211 * @} 4212 */ 4213 4214 /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose 4215 * @{ 4216 */ 4217 #if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) 4218 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE 4219 #endif /* STM32L4 || STM32F4 || STM32F7 */ 4220 /** 4221 * @} 4222 */ 4223 4224 /** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 4225 * @{ 4226 */ 4227 #if defined (STM32F7) 4228 #define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE 4229 #endif /* STM32F7 */ 4230 /** 4231 * @} 4232 */ 4233 4234 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose 4235 * @{ 4236 */ 4237 4238 /** 4239 * @} 4240 */ 4241 4242 #ifdef __cplusplus 4243 } 4244 #endif 4245 4246 #endif /* STM32_HAL_LEGACY */ 4247
