1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_utils.c
4 * @author MCD Application Team
5 * @brief UTILS LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Includes ------------------------------------------------------------------*/
20 #include "stm32g4xx_ll_utils.h"
21 #include "stm32g4xx_ll_rcc.h"
22 #include "stm32g4xx_ll_system.h"
23 #include "stm32g4xx_ll_pwr.h"
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32G4xx_LL_Driver
31 * @{
32 */
33
34 /** @addtogroup UTILS_LL
35 * @{
36 */
37
38 /* Private types -------------------------------------------------------------*/
39 /* Private variables ---------------------------------------------------------*/
40 /* Private constants ---------------------------------------------------------*/
41 /** @addtogroup UTILS_LL_Private_Constants
42 * @{
43 */
44 #define UTILS_MAX_FREQUENCY_SCALE1 170000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
45 #define UTILS_MAX_FREQUENCY_SCALE2 26000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
46
47 /* Defines used for PLL range */
48 #define UTILS_PLLVCO_INPUT_MIN 2660000U /*!< Frequency min for PLLVCO input, in Hz */
49 #define UTILS_PLLVCO_INPUT_MAX 8000000U /*!< Frequency max for PLLVCO input, in Hz */
50 #define UTILS_PLLVCO_OUTPUT_MIN 64000000U /*!< Frequency min for PLLVCO output, in Hz */
51 #define UTILS_PLLVCO_OUTPUT_MAX 344000000U /*!< Frequency max for PLLVCO output, in Hz */
52
53 /* Defines used for HSE range */
54 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
55 #define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */
56
57 /* Defines used for FLASH latency according to HCLK Frequency */
58 #define UTILS_SCALE1_LATENCY1_FREQ 20000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
59 #define UTILS_SCALE1_LATENCY2_FREQ 40000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
60 #define UTILS_SCALE1_LATENCY3_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
61 #define UTILS_SCALE1_LATENCY4_FREQ 80000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
62 #define UTILS_SCALE1_LATENCY5_FREQ 100000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
63 #define UTILS_SCALE1_LATENCY6_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 6 in power scale 1 */
64 #define UTILS_SCALE1_LATENCY7_FREQ 140000000U /*!< HCLK frequency to set FLASH latency 7 in power scale 1 */
65 #define UTILS_SCALE1_LATENCY8_FREQ 160000000U /*!< HCLK frequency to set FLASH latency 8 in power scale 1 */
66 #define UTILS_SCALE1_LATENCY9_FREQ 170000000U /*!< HCLK frequency to set FLASH latency 9 in power scale 1 */
67 #define UTILS_SCALE2_LATENCY1_FREQ 8000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
68 #define UTILS_SCALE2_LATENCY2_FREQ 16000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
69 #define UTILS_SCALE2_LATENCY3_FREQ 26000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
70 /**
71 * @}
72 */
73
74 /* Private macros ------------------------------------------------------------*/
75 /** @addtogroup UTILS_LL_Private_Macros
76 * @{
77 */
78 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
79 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
80 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
81 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
82 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
83 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
84 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
85 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
86 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
87
88 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
89 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
90 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
91 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
92 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
93
94 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
95 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
96 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
97 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
98 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
99
100 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_1) \
101 || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \
102 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
103 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
104 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
105 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
106 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
107 || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
108 || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
109 || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
110 || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
111 || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
112 || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
113 || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
114 || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
115 || ((__VALUE__) == LL_RCC_PLLM_DIV_16))
116
117 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U))
118
119 #define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \
120 || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \
121 || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \
122 || ((__VALUE__) == LL_RCC_PLLR_DIV_8))
123
124 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
125
126 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
127
128 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
129 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))
130
131 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
132 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
133
134 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
135 /**
136 * @}
137 */
138 /* Private function prototypes -----------------------------------------------*/
139 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
140 * @{
141 */
142 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
143 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
144 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
145 static ErrorStatus UTILS_PLL_IsBusy(void);
146 /**
147 * @}
148 */
149
150 /* Exported functions --------------------------------------------------------*/
151 /** @addtogroup UTILS_LL_Exported_Functions
152 * @{
153 */
154
155 /** @addtogroup UTILS_LL_EF_DELAY
156 * @{
157 */
158
159 /**
160 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
161 * @note When a RTOS is used, it is recommended to avoid changing the Systick
162 * configuration by calling this function, for a delay use rather osDelay RTOS service.
163 * @param HCLKFrequency HCLK frequency in Hz
164 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
165 * @retval None
166 */
LL_Init1msTick(uint32_t HCLKFrequency)167 void LL_Init1msTick(uint32_t HCLKFrequency)
168 {
169 /* Use frequency provided in argument */
170 LL_InitTick(HCLKFrequency, 1000U);
171 }
172
173 /**
174 * @brief This function provides accurate delay (in milliseconds) based
175 * on SysTick counter flag
176 * @note When a RTOS is used, it is recommended to avoid using blocking delay
177 * and use rather osDelay service.
178 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
179 * will configure Systick to 1ms
180 * @param Delay specifies the delay time length, in milliseconds.
181 * @retval None
182 */
LL_mDelay(uint32_t Delay)183 void LL_mDelay(uint32_t Delay)
184 {
185 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
186 uint32_t tmpDelay; /* MISRAC2012-Rule-17.8 */
187 /* Add this code to indicate that local variable is not used */
188 ((void)tmp);
189 tmpDelay = Delay;
190 /* Add a period to guaranty minimum wait */
191 if(tmpDelay < LL_MAX_DELAY)
192 {
193 tmpDelay++;
194 }
195
196 while (tmpDelay != 0U)
197 {
198 if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
199 {
200 tmpDelay--;
201 }
202 }
203 }
204
205 /**
206 * @}
207 */
208
209 /** @addtogroup UTILS_EF_SYSTEM
210 * @brief System Configuration functions
211 *
212 @verbatim
213 ===============================================================================
214 ##### System Configuration functions #####
215 ===============================================================================
216 [..]
217 System, AHB and APB buses clocks configuration
218
219 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is
220 170000000 Hz for STM32G4xx.
221 @endverbatim
222 @internal
223 Depending on the device voltage range, the maximum frequency should be
224 adapted accordingly:
225
226 (++) Table 1. HCLK clock frequency for STM32G4xx devices
227 (++) +--------------------------------------------------------+
228 (++) | Latency | HCLK clock frequency (MHz) |
229 (++) | |--------------------------------------|
230 (++) | | voltage range 1 | voltage range 2 |
231 (++) | | 1.2 V | 1.0 V |
232 (++) |-----------------|-------------------|------------------|
233 (++) |0WS(1 CPU cycles)| 0 < HCLK <= 20 | 0 < HCLK <= 8 |
234 (++) |-----------------|-------------------|------------------|
235 (++) |1WS(2 CPU cycles)| 20 < HCLK <= 40 | 8 < HCLK <= 16 |
236 (++) |-----------------|-------------------|------------------|
237 (++) |2WS(3 CPU cycles)| 40 < HCLK <= 60 | 16 < HCLK <= 26 |
238 (++) |-----------------|-------------------|------------------|
239 (++) |3WS(4 CPU cycles)| 60 < HCLK <= 80 | 16 < HCLK <= 26 |
240 (++) |-----------------|-------------------|------------------|
241 (++) |4WS(5 CPU cycles)| 80 < HCLK <= 100 | 16 < HCLK <= 26 |
242 (++) |-----------------|-------------------|------------------|
243 (++) |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26 |
244 (++) |-----------------|-------------------|------------------|
245 (++) |6WS(7 CPU cycles)| 120 < HCLK <= 140 | 16 < HCLK <= 26 |
246 (++) |-----------------|-------------------|------------------|
247 (++) |7WS(8 CPU cycles)| 140 < HCLK <= 160 | 16 < HCLK <= 26 |
248 (++) |-----------------|-------------------|------------------|
249 (++) |8WS(9 CPU cycles)| 160 < HCLK <= 170 | 16 < HCLK <= 26 |
250 (++) +--------------------------------------------------------+
251
252
253 @endinternal
254 * @{
255 */
256
257 /**
258 * @brief This function sets directly SystemCoreClock CMSIS variable.
259 * @note Variable can be calculated also through SystemCoreClockUpdate function.
260 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
261 * @retval None
262 */
LL_SetSystemCoreClock(uint32_t HCLKFrequency)263 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
264 {
265 /* HCLK clock frequency */
266 SystemCoreClock = HCLKFrequency;
267 }
268
269 /**
270 * @brief Update number of Flash wait states in line with new frequency and current
271 voltage range.
272 * @param HCLKFrequency HCLK frequency
273 * @retval An ErrorStatus enumeration value:
274 * - SUCCESS: Latency has been modified
275 * - ERROR: Latency cannot be modified
276 */
LL_SetFlashLatency(uint32_t HCLKFrequency)277 ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency)
278 {
279 uint32_t timeout;
280 uint32_t getlatency;
281 ErrorStatus status = SUCCESS;
282
283 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
284
285 /* Frequency cannot be equal to 0 or greater than max clock */
286 if((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_SCALE1_LATENCY9_FREQ))
287 {
288 status = ERROR;
289 }
290 else
291 {
292 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
293 {
294 if(HCLKFrequency > UTILS_SCALE1_LATENCY8_FREQ)
295 {
296 /* 160 < HCLK <= 170 => 8WS (9 CPU cycles) */
297 latency = LL_FLASH_LATENCY_8;
298 }
299 else if(HCLKFrequency > UTILS_SCALE1_LATENCY7_FREQ)
300 {
301 /* 140 < HCLK <= 160 => 7WS (8 CPU cycles) */
302 latency = LL_FLASH_LATENCY_7;
303 }
304 else if(HCLKFrequency > UTILS_SCALE1_LATENCY6_FREQ)
305 {
306 /* 120 < HCLK <= 140 => 6WS (7 CPU cycles) */
307 latency = LL_FLASH_LATENCY_6;
308 }
309 else if(HCLKFrequency > UTILS_SCALE1_LATENCY5_FREQ)
310 {
311 /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */
312 latency = LL_FLASH_LATENCY_5;
313 }
314 else if(HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ)
315 {
316 /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */
317 latency = LL_FLASH_LATENCY_4;
318 }
319 else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ)
320 {
321 /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */
322 latency = LL_FLASH_LATENCY_3;
323 }
324 else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ)
325 {
326 /* 40 < HCLK <= 60 => 2WS (3 CPU cycles) */
327 latency = LL_FLASH_LATENCY_2;
328 }
329 else
330 {
331 if(HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ)
332 {
333 /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */
334 latency = LL_FLASH_LATENCY_1;
335 }
336 /* else HCLKFrequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */
337 }
338 }
339 else /* SCALE2 */
340 {
341 if(HCLKFrequency > UTILS_SCALE2_LATENCY2_FREQ)
342 {
343 /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */
344 latency = LL_FLASH_LATENCY_2;
345 }
346 else
347 {
348 if(HCLKFrequency > UTILS_SCALE2_LATENCY1_FREQ)
349 {
350 /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */
351 latency = LL_FLASH_LATENCY_1;
352 }
353 /* else HCLKFrequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */
354 }
355 }
356
357 if (status != ERROR)
358 {
359 LL_FLASH_SetLatency(latency);
360
361 /* Check that the new number of wait states is taken into account to access the Flash
362 memory by reading the FLASH_ACR register */
363 timeout = 2U;
364 do
365 {
366 /* Wait for Flash latency to be updated */
367 getlatency = LL_FLASH_GetLatency();
368 timeout--;
369 } while ((getlatency != latency) && (timeout > 0U));
370
371 if(getlatency != latency)
372 {
373 status = ERROR;
374 }
375 }
376 }
377
378 return status;
379 }
380
381 /**
382 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
383 * @note The application need to ensure that PLL is disabled.
384 * @note Function is based on the following formula:
385 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
386 * - PLLM: ensure that the VCO input frequency ranges from 2.66 to 8 MHz (PLLVCO_input = HSI frequency / PLLM)
387 * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
388 * - PLLR: ensure that max frequency at 170000000 Hz is reach (PLLVCO_output / PLLR)
389 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
390 * the configuration information for the PLL.
391 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
392 * the configuration information for the BUS prescalers.
393 * @retval An ErrorStatus enumeration value:
394 * - SUCCESS: Max frequency configuration done
395 * - ERROR: Max frequency configuration not done
396 */
LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)397 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
398 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
399 {
400 ErrorStatus status;
401 uint32_t pllfreq;
402 uint32_t hpre = LL_RCC_SYSCLK_DIV_1;
403
404 /* Check if one of the PLL is enabled */
405 if(UTILS_PLL_IsBusy() == SUCCESS)
406 {
407 /* Calculate the new PLL output frequency */
408 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
409
410 /* Enable HSI if not enabled */
411 if(LL_RCC_HSI_IsReady() != 1U)
412 {
413 LL_RCC_HSI_Enable();
414 while (LL_RCC_HSI_IsReady() != 1U)
415 {
416 /* Wait for HSI ready */
417 }
418 }
419
420 /* Configure PLL */
421 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
422 UTILS_PLLInitStruct->PLLR);
423
424 /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
425 if(pllfreq > 80000000U)
426 {
427 if (UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1)
428 {
429 UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
430 hpre = LL_RCC_SYSCLK_DIV_2;
431 }
432 }
433
434 /* Enable PLL and switch system clock to PLL */
435 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
436
437 /* Apply definitive AHB prescaler value if necessary */
438 if ((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1))
439 {
440 /* Set FLASH latency to highest latency */
441 status = LL_SetFlashLatency(pllfreq);
442 if (status == SUCCESS)
443 {
444 UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
445 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
446 LL_SetSystemCoreClock(pllfreq);
447 }
448 }
449 }
450 else
451 {
452 /* Current PLL configuration cannot be modified */
453 status = ERROR;
454 }
455
456 return status;
457 }
458
459 /**
460 * @brief This function configures system clock with HSE as clock source of the PLL
461 * @note The application need to ensure that PLL is disabled.
462 * @note Function is based on the following formula:
463 * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
464 * - PLLM: ensure that the VCO input frequency ranges from 2.66 to 8 MHz (PLLVCO_input = HSE frequency / PLLM)
465 * - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
466 * - PLLR: ensure that max frequency at 170000000 Hz is reached (PLLVCO_output / PLLR)
467 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
468 * @param HSEBypass This parameter can be one of the following values:
469 * @arg @ref LL_UTILS_HSEBYPASS_ON
470 * @arg @ref LL_UTILS_HSEBYPASS_OFF
471 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
472 * the configuration information for the PLL.
473 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
474 * the configuration information for the BUS prescalers.
475 * @retval An ErrorStatus enumeration value:
476 * - SUCCESS: Max frequency configuration done
477 * - ERROR: Max frequency configuration not done
478 */
LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,uint32_t HSEBypass,LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)479 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
480 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
481 {
482 ErrorStatus status;
483 uint32_t pllfreq;
484 uint32_t hpre = LL_RCC_SYSCLK_DIV_1;
485
486 /* Check the parameters */
487 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
488 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
489
490 /* Check if one of the PLL is enabled */
491 if(UTILS_PLL_IsBusy() == SUCCESS)
492 {
493 /* Calculate the new PLL output frequency */
494 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
495
496 /* Enable HSE if not enabled */
497 if(LL_RCC_HSE_IsReady() != 1U)
498 {
499 /* Check if need to enable HSE bypass feature or not */
500 if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
501 {
502 LL_RCC_HSE_EnableBypass();
503 }
504 else
505 {
506 LL_RCC_HSE_DisableBypass();
507 }
508
509 /* Enable HSE */
510 LL_RCC_HSE_Enable();
511 while (LL_RCC_HSE_IsReady() != 1U)
512 {
513 /* Wait for HSE ready */
514 }
515 }
516
517 /* Configure PLL */
518 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
519 UTILS_PLLInitStruct->PLLR);
520
521 /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
522 if(pllfreq > 80000000U)
523 {
524 if (UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1)
525 {
526 UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
527 hpre = LL_RCC_SYSCLK_DIV_2;
528 }
529 }
530
531 /* Enable PLL and switch system clock to PLL */
532 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
533
534 /* Apply definitive AHB prescaler value if necessary */
535 if ((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1))
536 {
537 /* Set FLASH latency to highest latency */
538 status = LL_SetFlashLatency(pllfreq);
539 if (status == SUCCESS)
540 {
541 UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
542 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
543 LL_SetSystemCoreClock(pllfreq);
544 }
545 }
546 }
547 else
548 {
549 /* Current PLL configuration cannot be modified */
550 status = ERROR;
551 }
552
553 return status;
554 }
555
556 /**
557 * @}
558 */
559
560 /**
561 * @}
562 */
563
564 /** @addtogroup UTILS_LL_Private_Functions
565 * @{
566 */
567
568 /**
569 * @brief Function to check that PLL can be modified
570 * @param PLL_InputFrequency PLL input frequency (in Hz)
571 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
572 * the configuration information for the PLL.
573 * @retval PLL output frequency (in Hz)
574 */
UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct)575 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
576 {
577 uint32_t pllfreq;
578
579 /* Check the parameters */
580 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
581 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
582 assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR));
583
584 /* Check different PLL parameters according to RM */
585 /* - PLLM: ensure that the VCO input frequency ranges from 2.66 to 8 MHz. */
586 pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1U));
587 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
588
589 /* - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz.*/
590 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
591 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
592
593 /* - PLLR: ensure that max frequency at 170000000 Hz is reached */
594 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U);
595 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
596
597 return pllfreq;
598 }
599
600 /**
601 * @brief Function to check that PLL can be modified
602 * @retval An ErrorStatus enumeration value:
603 * - SUCCESS: PLL modification can be done
604 * - ERROR: PLL is busy
605 */
UTILS_PLL_IsBusy(void)606 static ErrorStatus UTILS_PLL_IsBusy(void)
607 {
608 ErrorStatus status = SUCCESS;
609
610 /* Check if PLL is busy*/
611 if(LL_RCC_PLL_IsReady() != 0U)
612 {
613 /* PLL configuration cannot be modified */
614 status = ERROR;
615 }
616
617 return status;
618 }
619
620 /**
621 * @brief Function to enable PLL and switch system clock to PLL
622 * @param SYSCLK_Frequency SYSCLK frequency
623 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
624 * the configuration information for the BUS prescalers.
625 * @retval An ErrorStatus enumeration value:
626 * - SUCCESS: No problem to switch system to PLL
627 * - ERROR: Problem to switch system to PLL
628 */
UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)629 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
630 {
631 ErrorStatus status = SUCCESS;
632 uint32_t hclk_frequency;
633
634 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
635 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
636 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
637
638 /* Calculate HCLK frequency */
639 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
640
641 /* Increasing the number of wait states because of higher CPU frequency */
642 if(SystemCoreClock < hclk_frequency)
643 {
644 /* Set FLASH latency to highest latency */
645 status = LL_SetFlashLatency(hclk_frequency);
646 }
647
648 /* Update system clock configuration */
649 if(status == SUCCESS)
650 {
651 /* Enable PLL */
652 LL_RCC_PLL_Enable();
653 LL_RCC_PLL_EnableDomain_SYS();
654 while (LL_RCC_PLL_IsReady() != 1U)
655 {
656 /* Wait for PLL ready */
657 }
658
659 /* Sysclk activation on the main PLL */
660 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
661 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
662 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
663 {
664 /* Wait for system clock switch to PLL */
665 }
666
667 /* Set APB1 & APB2 prescaler*/
668 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
669 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
670 }
671
672 /* Decreasing the number of wait states because of lower CPU frequency */
673 if(SystemCoreClock > hclk_frequency)
674 {
675 /* Set FLASH latency to lowest latency */
676 status = LL_SetFlashLatency(hclk_frequency);
677 }
678
679 /* Update SystemCoreClock variable */
680 if(status == SUCCESS)
681 {
682 LL_SetSystemCoreClock(hclk_frequency);
683 }
684
685 return status;
686 }
687
688 /**
689 * @}
690 */
691
692 /**
693 * @}
694 */
695
696 /**
697 * @}
698 */
699
700
