1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17 #if defined(USE_FULL_LL_DRIVER)
18
19 /* Includes ------------------------------------------------------------------*/
20 #include "stm32g4xx_ll_rcc.h"
21 #ifdef USE_FULL_ASSERT
22 #include "stm32_assert.h"
23 #else
24 #define assert_param(expr) ((void)0U)
25 #endif
26 /** @addtogroup STM32G4xx_LL_Driver
27 * @{
28 */
29
30 /** @addtogroup RCC_LL
31 * @{
32 */
33
34 /* Private types -------------------------------------------------------------*/
35 /* Private variables ---------------------------------------------------------*/
36 /* Private constants ---------------------------------------------------------*/
37 /* Private macros ------------------------------------------------------------*/
38 /** @addtogroup RCC_LL_Private_Macros
39 * @{
40 */
41 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
42 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
43 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
44 #if defined(RCC_CCIPR_UART5SEL)
45 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
46 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
47 #elif defined(RCC_CCIPR_UART4SEL)
48 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
49 #endif /* RCC_CCIPR_UART5SEL*/
50
51 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
52
53 #if defined(RCC_CCIPR2_I2C4SEL)
54 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
55 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
56 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
57 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
58
59 #else
60 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
61 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
62 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
63 #endif /* RCC_CCIPR2_I2C4SEL */
64 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
65
66 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
67
68 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
69
70 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
71
72 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
73
74 #if defined(ADC345_COMMON)
75 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE) \
76 || ((__VALUE__) == LL_RCC_ADC345_CLKSOURCE))
77 #else
78 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE))
79 #endif /* ADC345_COMMON */
80
81 #if defined(QUADSPI)
82 #define IS_LL_RCC_QUADSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_QUADSPI_CLKSOURCE))
83 #endif /* QUADSPI */
84
85 #if defined(FDCAN1)
86 #define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE))
87 #endif /* FDCAN1 */
88
89 /**
90 * @}
91 */
92
93 /* Private function prototypes -----------------------------------------------*/
94 /** @defgroup RCC_LL_Private_Functions RCC Private functions
95 * @{
96 */
97 static uint32_t RCC_GetSystemClockFreq(void);
98 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
99 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
100 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
101 static uint32_t RCC_PLL_GetFreqDomain_SYS(void);
102 static uint32_t RCC_PLL_GetFreqDomain_ADC(void);
103 static uint32_t RCC_PLL_GetFreqDomain_48M(void);
104 /**
105 * @}
106 */
107
108
109 /* Exported functions --------------------------------------------------------*/
110 /** @addtogroup RCC_LL_Exported_Functions
111 * @{
112 */
113
114 /** @addtogroup RCC_LL_EF_Init
115 * @{
116 */
117
118 /**
119 * @brief Reset the RCC clock configuration to the default reset state.
120 * @note The default reset state of the clock configuration is given below:
121 * - HSI ON and used as system clock source
122 * - HSE and PLL OFF
123 * - AHB, APB1 and APB2 prescaler set to 1.
124 * - CSS, MCO OFF
125 * - All interrupts disabled
126 * @note This function doesn't modify the configuration of the
127 * - Peripheral clocks
128 * - LSI, LSE and RTC clocks
129 * @retval An ErrorStatus enumeration value:
130 * - SUCCESS: RCC registers are de-initialized
131 * - ERROR: not applicable
132 */
LL_RCC_DeInit(void)133 ErrorStatus LL_RCC_DeInit(void)
134 {
135 uint32_t vl_mask;
136
137 /* Set HSION bit and wait for HSI READY bit */
138 LL_RCC_HSI_Enable();
139 while (LL_RCC_HSI_IsReady() == 0U)
140 {}
141
142 /* Set HSITRIM bits to reset value*/
143 LL_RCC_HSI_SetCalibTrimming(0x40U);
144
145 /* Reset whole CFGR register but keep HSI as system clock source */
146 LL_RCC_WriteReg(CFGR, LL_RCC_SYS_CLKSOURCE_HSI);
147 while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {};
148
149 /* Reset whole CR register but HSI in 2 steps in case HSEBYP is set */
150 LL_RCC_WriteReg(CR, RCC_CR_HSION);
151 LL_RCC_WriteReg(CR, RCC_CR_HSION);
152
153 /* Wait for PLL READY bit to be reset */
154 while (LL_RCC_PLL_IsReady() != 0U)
155 {}
156
157 /* Reset PLLCFGR register */
158 LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos);
159
160 /* Disable all interrupts */
161 LL_RCC_WriteReg(CIER, 0x00000000U);
162
163 /* Clear all interrupt flags */
164 vl_mask = RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \
165 RCC_CICR_HSI48RDYC | RCC_CICR_CSSC | RCC_CICR_LSECSSC;
166
167 LL_RCC_WriteReg(CICR, vl_mask);
168
169 /* Clear reset flags */
170 LL_RCC_ClearResetFlags();
171
172 return SUCCESS;
173 }
174
175 /**
176 * @}
177 */
178
179 /** @addtogroup RCC_LL_EF_Get_Freq
180 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
181 * and different peripheral clocks available on the device.
182 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
183 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
184 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
185 * or HSI_VALUE(**) multiplied/divided by the PLL factors.
186 * @note (**) HSI_VALUE is a constant defined in this file (default value
187 * 16 MHz) but the real value may vary depending on the variations
188 * in voltage and temperature.
189 * @note (***) HSE_VALUE is a constant defined in this file (default value
190 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
191 * frequency of the crystal used. Otherwise, this function may
192 * have wrong result.
193 * @note The result of this function could be incorrect when using fractional
194 * value for HSE crystal.
195 * @note This function can be used by the user application to compute the
196 * baud-rate for the communication peripherals or configure other parameters.
197 * @{
198 */
199
200 /**
201 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
202 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
203 * must be called to update structure fields. Otherwise, any
204 * configuration based on this function will be incorrect.
205 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
206 * @retval None
207 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)208 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
209 {
210 /* Get SYSCLK frequency */
211 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
212
213 /* HCLK clock frequency */
214 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
215
216 /* PCLK1 clock frequency */
217 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
218
219 /* PCLK2 clock frequency */
220 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
221 }
222
223 /**
224 * @brief Return USARTx clock frequency
225 * @param USARTxSource This parameter can be one of the following values:
226 * @arg @ref LL_RCC_USART1_CLKSOURCE
227 * @arg @ref LL_RCC_USART2_CLKSOURCE
228 * @arg @ref LL_RCC_USART3_CLKSOURCE
229 *
230 * @retval USART clock frequency (in Hz)
231 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
232 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)233 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
234 {
235 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
236
237 /* Check parameter */
238 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
239
240 if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
241 {
242 /* USART1CLK clock frequency */
243 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
244 {
245 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
246 usart_frequency = RCC_GetSystemClockFreq();
247 break;
248
249 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
250 if (LL_RCC_HSI_IsReady() != 0U)
251 {
252 usart_frequency = HSI_VALUE;
253 }
254 break;
255
256 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
257 if (LL_RCC_LSE_IsReady() != 0U)
258 {
259 usart_frequency = LSE_VALUE;
260 }
261 break;
262
263 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
264 default:
265 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
266 break;
267 }
268 }
269 else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
270 {
271 /* USART2CLK clock frequency */
272 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
273 {
274 case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
275 usart_frequency = RCC_GetSystemClockFreq();
276 break;
277
278 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
279 if (LL_RCC_HSI_IsReady() != 0U)
280 {
281 usart_frequency = HSI_VALUE;
282 }
283 break;
284
285 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
286 if (LL_RCC_LSE_IsReady() != 0U)
287 {
288 usart_frequency = LSE_VALUE;
289 }
290 break;
291
292 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
293 default:
294 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
295 break;
296 }
297 }
298 else
299 {
300 if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
301 {
302 /* USART3CLK clock frequency */
303 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
304 {
305 case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
306 usart_frequency = RCC_GetSystemClockFreq();
307 break;
308
309 case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
310 if (LL_RCC_HSI_IsReady() != 0U)
311 {
312 usart_frequency = HSI_VALUE;
313 }
314 break;
315
316 case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
317 if (LL_RCC_LSE_IsReady() != 0U)
318 {
319 usart_frequency = LSE_VALUE;
320 }
321 break;
322
323 case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
324 default:
325 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
326 break;
327 }
328 }
329 }
330 return usart_frequency;
331 }
332
333 #if defined(RCC_CCIPR_UART4SEL)
334 /**
335 * @brief Return UARTx clock frequency
336 * @param UARTxSource This parameter can be one of the following values:
337 * @arg @ref LL_RCC_UART4_CLKSOURCE (*)
338 * @arg @ref LL_RCC_UART5_CLKSOURCE (*)
339 *
340 * (*) value not defined in all devices.
341 * @retval UART clock frequency (in Hz)
342 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
343 */
LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)344 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
345 {
346 uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
347
348 /* Check parameter */
349 assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
350
351 if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
352 {
353 /* UART4CLK clock frequency */
354 switch (LL_RCC_GetUARTClockSource(UARTxSource))
355 {
356 case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
357 uart_frequency = RCC_GetSystemClockFreq();
358 break;
359
360 case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
361 if (LL_RCC_HSI_IsReady() != 0U)
362 {
363 uart_frequency = HSI_VALUE;
364 }
365 break;
366
367 case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
368 if (LL_RCC_LSE_IsReady() != 0U)
369 {
370 uart_frequency = LSE_VALUE;
371 }
372 break;
373
374 case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
375 default:
376 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
377 break;
378 }
379 }
380
381 #if defined(RCC_CCIPR_UART5SEL)
382 if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
383 {
384 /* UART5CLK clock frequency */
385 switch (LL_RCC_GetUARTClockSource(UARTxSource))
386 {
387 case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
388 uart_frequency = RCC_GetSystemClockFreq();
389 break;
390
391 case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
392 if (LL_RCC_HSI_IsReady() != 0U)
393 {
394 uart_frequency = HSI_VALUE;
395 }
396 break;
397
398 case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
399 if (LL_RCC_LSE_IsReady() != 0U)
400 {
401 uart_frequency = LSE_VALUE;
402 }
403 break;
404
405 case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
406 default:
407 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
408 break;
409 }
410 }
411 #endif /* RCC_CCIPR_UART5SEL */
412
413 return uart_frequency;
414 }
415 #endif /* RCC_CCIPR_UART4SEL */
416
417 /**
418 * @brief Return I2Cx clock frequency
419 * @param I2CxSource This parameter can be one of the following values:
420 * @arg @ref LL_RCC_I2C1_CLKSOURCE
421 * @arg @ref LL_RCC_I2C2_CLKSOURCE
422 * @arg @ref LL_RCC_I2C3_CLKSOURCE
423 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
424 *
425 * (*) value not defined in all devices.
426 * @retval I2C clock frequency (in Hz)
427 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
428 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)429 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
430 {
431 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
432
433 /* Check parameter */
434 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
435
436 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
437 {
438 /* I2C1 CLK clock frequency */
439 switch (LL_RCC_GetI2CClockSource(I2CxSource))
440 {
441 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
442 i2c_frequency = RCC_GetSystemClockFreq();
443 break;
444
445 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
446 if (LL_RCC_HSI_IsReady() != 0U)
447 {
448 i2c_frequency = HSI_VALUE;
449 }
450 break;
451
452 case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
453 default:
454 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
455 break;
456 }
457 }
458 else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
459 {
460 /* I2C2 CLK clock frequency */
461 switch (LL_RCC_GetI2CClockSource(I2CxSource))
462 {
463 case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
464 i2c_frequency = RCC_GetSystemClockFreq();
465 break;
466
467 case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
468 if (LL_RCC_HSI_IsReady() != 0U)
469 {
470 i2c_frequency = HSI_VALUE;
471 }
472 break;
473
474 case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
475 default:
476 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
477 break;
478 }
479 }
480 else
481 {
482 if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
483 {
484 /* I2C3 CLK clock frequency */
485 switch (LL_RCC_GetI2CClockSource(I2CxSource))
486 {
487 case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
488 i2c_frequency = RCC_GetSystemClockFreq();
489 break;
490
491 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
492 if (LL_RCC_HSI_IsReady() != 0U)
493 {
494 i2c_frequency = HSI_VALUE;
495 }
496 break;
497
498 case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */
499 default:
500 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
501 break;
502 }
503 }
504 #if defined(RCC_CCIPR2_I2C4SEL)
505 else
506 {
507 if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
508 {
509 /* I2C4 CLK clock frequency */
510 switch (LL_RCC_GetI2CClockSource(I2CxSource))
511 {
512 case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
513 i2c_frequency = RCC_GetSystemClockFreq();
514 break;
515
516 case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */
517 if (LL_RCC_HSI_IsReady() != 0U)
518 {
519 i2c_frequency = HSI_VALUE;
520 }
521 break;
522
523 case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */
524 default:
525 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
526 break;
527 }
528 }
529 }
530 #endif /*RCC_CCIPR2_I2C4SEL*/
531 }
532
533 return i2c_frequency;
534 }
535
536
537 /**
538 * @brief Return LPUARTx clock frequency
539 * @param LPUARTxSource This parameter can be one of the following values:
540 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
541 * @retval LPUART clock frequency (in Hz)
542 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
543 */
LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)544 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
545 {
546 uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
547
548 /* Check parameter */
549 assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
550
551 /* LPUART1CLK clock frequency */
552 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
553 {
554 case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
555 lpuart_frequency = RCC_GetSystemClockFreq();
556 break;
557
558 case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
559 if (LL_RCC_HSI_IsReady() != 0U)
560 {
561 lpuart_frequency = HSI_VALUE;
562 }
563 break;
564
565 case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
566 if (LL_RCC_LSE_IsReady() != 0U)
567 {
568 lpuart_frequency = LSE_VALUE;
569 }
570 break;
571
572 case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */
573 default:
574 lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
575 break;
576 }
577
578 return lpuart_frequency;
579 }
580
581 /**
582 * @brief Return LPTIMx clock frequency
583 * @param LPTIMxSource This parameter can be one of the following values:
584 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
585 * @retval LPTIM clock frequency (in Hz)
586 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
587 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)588 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
589 {
590 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
591
592 /* Check parameter */
593 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
594
595 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
596 {
597 /* LPTIM1CLK clock frequency */
598 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
599 {
600 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
601 if (LL_RCC_LSI_IsReady() != 0U)
602 {
603 lptim_frequency = LSI_VALUE;
604 }
605 break;
606
607 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
608 if (LL_RCC_HSI_IsReady() != 0U)
609 {
610 lptim_frequency = HSI_VALUE;
611 }
612 break;
613
614 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
615 if (LL_RCC_LSE_IsReady() != 0U)
616 {
617 lptim_frequency = LSE_VALUE;
618 }
619 break;
620
621 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
622 default:
623 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
624 break;
625 }
626 }
627
628 return lptim_frequency;
629 }
630
631 /**
632 * @brief Return SAIx clock frequency
633 * @param SAIxSource This parameter can be one of the following values:
634 * @arg @ref LL_RCC_SAI1_CLKSOURCE
635 *
636 * @retval SAI clock frequency (in Hz)
637 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
638 */
LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)639 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
640 {
641 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
642
643 /* Check parameter */
644 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
645
646 if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
647 {
648 /* SAI1CLK clock frequency */
649 switch (LL_RCC_GetSAIClockSource(SAIxSource))
650 {
651 case LL_RCC_SAI1_CLKSOURCE_SYSCLK: /* System clock used as SAI1 clock source */
652 sai_frequency = RCC_GetSystemClockFreq();
653 break;
654
655 case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
656 if (LL_RCC_PLL_IsReady() != 0U)
657 {
658 if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
659 {
660 sai_frequency = RCC_PLL_GetFreqDomain_48M();
661 }
662 }
663 break;
664
665 case LL_RCC_SAI1_CLKSOURCE_PIN: /* SAI1 Clock is External clock */
666 sai_frequency = EXTERNAL_CLOCK_VALUE;
667 break;
668
669 case LL_RCC_SAI1_CLKSOURCE_HSI: /* HSI clock used as SAI1 clock source */
670 default:
671 if (LL_RCC_HSI_IsReady() != 0U)
672 {
673 sai_frequency = HSI_VALUE;
674 }
675 break;
676
677 }
678 }
679
680 return sai_frequency;
681 }
682
683 /**
684 * @brief Return I2Sx clock frequency
685 * @param I2SxSource This parameter can be one of the following values:
686 * @arg @ref LL_RCC_I2S_CLKSOURCE
687 * @retval I2S clock frequency (in Hz)
688 * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
689 */
LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)690 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
691 {
692 uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
693
694 /* Check parameter */
695 assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
696
697 if (I2SxSource == LL_RCC_I2S_CLKSOURCE)
698 {
699 /* I2S CLK clock frequency */
700 switch (LL_RCC_GetI2SClockSource(I2SxSource))
701 {
702 case LL_RCC_I2S_CLKSOURCE_SYSCLK: /* I2S Clock is System Clock */
703 i2s_frequency = RCC_GetSystemClockFreq();
704 break;
705
706 case LL_RCC_I2S_CLKSOURCE_PLL: /* I2S Clock is PLL"Q" */
707 if (LL_RCC_PLL_IsReady() != 0U)
708 {
709 if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
710 {
711 i2s_frequency = RCC_PLL_GetFreqDomain_48M();
712 }
713 }
714 break;
715
716 case LL_RCC_I2S_CLKSOURCE_PIN: /* I2S Clock is External clock */
717 i2s_frequency = EXTERNAL_CLOCK_VALUE;
718 break;
719
720 case LL_RCC_I2S_CLKSOURCE_HSI: /* I2S Clock is HSI */
721 default:
722 if (LL_RCC_HSI_IsReady() != 0U)
723 {
724 i2s_frequency = HSI_VALUE;
725 }
726 break;
727 }
728 }
729
730 return i2s_frequency;
731 }
732
733 #if defined(FDCAN1)
734 /**
735 * @brief Return FDCAN kernel clock frequency
736 * @param FDCANxSource This parameter can be one of the following values:
737 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
738 * @retval FDCAN kernel clock frequency (in Hz)
739 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
740 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
741 */
LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)742 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
743 {
744 uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
745
746 /* Check parameter */
747 assert_param(IS_LL_RCC_FDCAN_CLKSOURCE(FDCANxSource));
748
749 /* FDCAN kernel clock frequency */
750 switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
751 {
752 case LL_RCC_FDCAN_CLKSOURCE_HSE: /* HSE clock used as FDCAN kernel clock */
753 if (LL_RCC_HSE_IsReady() != 0U)
754 {
755 fdcan_frequency = HSE_VALUE;
756 }
757 break;
758
759 case LL_RCC_FDCAN_CLKSOURCE_PLL: /* PLL clock used as FDCAN kernel clock */
760 if (LL_RCC_PLL_IsReady() != 0U)
761 {
762 if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
763 {
764 fdcan_frequency = RCC_PLL_GetFreqDomain_48M();
765 }
766 }
767 break;
768
769 case LL_RCC_FDCAN_CLKSOURCE_PCLK1: /* PCLK1 clock used as FDCAN kernel clock */
770 fdcan_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
771 break;
772
773 default:
774 fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
775 break;
776 }
777 return fdcan_frequency;
778 }
779 #endif /* FDCAN1 */
780
781 /**
782 * @brief Return RNGx clock frequency
783 * @param RNGxSource This parameter can be one of the following values:
784 * @arg @ref LL_RCC_RNG_CLKSOURCE
785 * @retval RNG clock frequency (in Hz)
786 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
787 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
788 */
LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)789 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
790 {
791 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
792
793 /* Check parameter */
794 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
795
796 /* RNGCLK clock frequency */
797 switch (LL_RCC_GetRNGClockSource(RNGxSource))
798 {
799 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
800 if (LL_RCC_PLL_IsReady() != 0U)
801 {
802 if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
803 {
804 rng_frequency = RCC_PLL_GetFreqDomain_48M();
805 }
806 }
807 break;
808
809 case LL_RCC_RNG_CLKSOURCE_HSI48: /* HSI48 used as RNG clock source */
810 if (LL_RCC_HSI48_IsReady() != 0U)
811 {
812 rng_frequency = HSI48_VALUE;
813 }
814 break;
815
816 default:
817 rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
818 break;
819
820 }
821
822 return rng_frequency;
823 }
824
825 /**
826 * @brief Return USBx clock frequency
827 * @param USBxSource This parameter can be one of the following values:
828 * @arg @ref LL_RCC_USB_CLKSOURCE
829 * @retval USB clock frequency (in Hz)
830 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
831 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
832 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)833 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
834 {
835 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
836
837 /* Check parameter */
838 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
839
840 /* USBCLK clock frequency */
841 switch (LL_RCC_GetUSBClockSource(USBxSource))
842 {
843 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
844 if (LL_RCC_PLL_IsReady() != 0U)
845 {
846 if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
847 {
848 usb_frequency = RCC_PLL_GetFreqDomain_48M();
849 }
850 }
851 break;
852
853 case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 used as USB clock source */
854 if (LL_RCC_HSI48_IsReady() != 0U)
855 {
856 usb_frequency = HSI48_VALUE;
857 }
858 break;
859
860 default:
861 usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
862 break;
863 }
864
865 return usb_frequency;
866 }
867
868 /**
869 * @brief Return ADCx clock frequency
870 * @param ADCxSource This parameter can be one of the following values:
871 * @arg @ref LL_RCC_ADC12_CLKSOURCE
872 * @arg @ref LL_RCC_ADC345_CLKSOURCE (*)
873 *
874 * (*) value not defined in all devices.
875 * @retval ADC clock frequency (in Hz)
876 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
877 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
878 */
LL_RCC_GetADCClockFreq(uint32_t ADCxSource)879 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
880 {
881 uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
882
883 /* Check parameter */
884 assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
885
886 if (ADCxSource == LL_RCC_ADC12_CLKSOURCE)
887 {
888 /* ADC12CLK clock frequency */
889 switch (LL_RCC_GetADCClockSource(ADCxSource))
890 {
891 case LL_RCC_ADC12_CLKSOURCE_PLL: /* PLL clock used as ADC12 clock source */
892 if (LL_RCC_PLL_IsReady() != 0U)
893 {
894 if (LL_RCC_PLL_IsEnabledDomain_ADC() != 0U)
895 {
896 adc_frequency = RCC_PLL_GetFreqDomain_ADC();
897 }
898 }
899 break;
900
901 case LL_RCC_ADC12_CLKSOURCE_SYSCLK: /* System clock used as ADC12 clock source */
902 adc_frequency = RCC_GetSystemClockFreq();
903 break;
904
905 case LL_RCC_ADC12_CLKSOURCE_NONE: /* No clock used as ADC12 clock source */
906 default:
907 adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
908 break;
909 }
910 }
911 #if defined(ADC345_COMMON)
912 else
913 {
914 /* ADC345CLK clock frequency */
915 switch (LL_RCC_GetADCClockSource(ADCxSource))
916 {
917 case LL_RCC_ADC345_CLKSOURCE_PLL: /* PLL clock used as ADC345 clock source */
918 if (LL_RCC_PLL_IsReady() != 0U)
919 {
920 if (LL_RCC_PLL_IsEnabledDomain_ADC() != 0U)
921 {
922 adc_frequency = RCC_PLL_GetFreqDomain_ADC();
923 }
924 }
925 break;
926
927 case LL_RCC_ADC345_CLKSOURCE_SYSCLK: /* System clock used as ADC345 clock source */
928 adc_frequency = RCC_GetSystemClockFreq();
929 break;
930
931 case LL_RCC_ADC345_CLKSOURCE_NONE: /* No clock used as ADC345 clock source */
932 default:
933 adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
934 break;
935 }
936 }
937 #endif /* ADC345_COMMON */
938
939 return adc_frequency;
940 }
941
942 #if defined(QUADSPI)
943 /**
944 * @brief Return QUADSPI clock frequency
945 * @param QUADSPIxSource This parameter can be one of the following values:
946 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE
947 * @retval QUADSPI clock frequency (in Hz)
948 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that no clock is configured
949 */
LL_RCC_GetQUADSPIClockFreq(uint32_t QUADSPIxSource)950 uint32_t LL_RCC_GetQUADSPIClockFreq(uint32_t QUADSPIxSource)
951 {
952 uint32_t quadspi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
953
954 /* Check parameter */
955 assert_param(IS_LL_RCC_QUADSPI_CLKSOURCE(QUADSPIxSource));
956
957 /* QUADSPI clock frequency */
958 switch (LL_RCC_GetQUADSPIClockSource(QUADSPIxSource))
959 {
960 case LL_RCC_QUADSPI_CLKSOURCE_SYSCLK: /* SYSCLK used as QUADSPI source */
961 quadspi_frequency = RCC_GetSystemClockFreq();
962 break;
963
964 case LL_RCC_QUADSPI_CLKSOURCE_HSI: /* HSI clock used as QUADSPI source */
965 if (LL_RCC_HSI_IsReady() != 0U)
966 {
967 quadspi_frequency = HSI_VALUE;
968 }
969 break;
970
971 case LL_RCC_QUADSPI_CLKSOURCE_PLL: /* PLL clock used as QUADSPI source */
972 if (LL_RCC_PLL_IsReady() != 0U)
973 {
974 if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
975 {
976 quadspi_frequency = RCC_PLL_GetFreqDomain_48M();
977 }
978 }
979 break;
980
981 default:
982 /* Nothing to do: quadspi frequency already initilalized to LL_RCC_PERIPH_FREQUENCY_NO */
983 break;
984 }
985
986 return quadspi_frequency;
987 }
988 #endif /* QUADSPI */
989
990 /**
991 * @}
992 */
993
994 /**
995 * @}
996 */
997
998 /** @addtogroup RCC_LL_Private_Functions
999 * @{
1000 */
1001
1002 /**
1003 * @brief Return SYSTEM clock frequency
1004 * @retval SYSTEM clock frequency (in Hz)
1005 */
RCC_GetSystemClockFreq(void)1006 static uint32_t RCC_GetSystemClockFreq(void)
1007 {
1008 uint32_t frequency;
1009
1010 /* Get SYSCLK source -------------------------------------------------------*/
1011 switch (LL_RCC_GetSysClkSource())
1012 {
1013 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1014 frequency = HSI_VALUE;
1015 break;
1016
1017 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
1018 frequency = HSE_VALUE;
1019 break;
1020
1021 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
1022 frequency = RCC_PLL_GetFreqDomain_SYS();
1023 break;
1024
1025 default:
1026 frequency = HSI_VALUE;
1027 break;
1028 }
1029
1030 return frequency;
1031 }
1032
1033 /**
1034 * @brief Return HCLK clock frequency
1035 * @param SYSCLK_Frequency SYSCLK clock frequency
1036 * @retval HCLK clock frequency (in Hz)
1037 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)1038 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1039 {
1040 /* HCLK clock frequency */
1041 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1042 }
1043
1044 /**
1045 * @brief Return PCLK1 clock frequency
1046 * @param HCLK_Frequency HCLK clock frequency
1047 * @retval PCLK1 clock frequency (in Hz)
1048 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)1049 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1050 {
1051 /* PCLK1 clock frequency */
1052 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1053 }
1054
1055 /**
1056 * @brief Return PCLK2 clock frequency
1057 * @param HCLK_Frequency HCLK clock frequency
1058 * @retval PCLK2 clock frequency (in Hz)
1059 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)1060 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1061 {
1062 /* PCLK2 clock frequency */
1063 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1064 }
1065
1066 /**
1067 * @brief Return PLL clock frequency used for system domain
1068 * @retval PLL clock frequency (in Hz)
1069 */
RCC_PLL_GetFreqDomain_SYS(void)1070 static uint32_t RCC_PLL_GetFreqDomain_SYS(void)
1071 {
1072 uint32_t pllinputfreq, pllsource;
1073
1074 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1075 SYSCLK = PLL_VCO / PLLR
1076 */
1077 pllsource = LL_RCC_PLL_GetMainSource();
1078
1079 switch (pllsource)
1080 {
1081 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1082 pllinputfreq = HSI_VALUE;
1083 break;
1084
1085 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1086 pllinputfreq = HSE_VALUE;
1087 break;
1088
1089 default:
1090 pllinputfreq = HSI_VALUE;
1091 break;
1092 }
1093 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1094 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1095 }
1096
1097 /**
1098 * @brief Return PLL clock frequency used for ADC domain
1099 * @retval PLL clock frequency (in Hz)
1100 */
RCC_PLL_GetFreqDomain_ADC(void)1101 static uint32_t RCC_PLL_GetFreqDomain_ADC(void)
1102 {
1103 uint32_t pllinputfreq, pllsource;
1104
1105 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1106 ADC Domain clock = PLL_VCO / PLLP
1107 */
1108 pllsource = LL_RCC_PLL_GetMainSource();
1109
1110 switch (pllsource)
1111 {
1112 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1113 pllinputfreq = HSI_VALUE;
1114 break;
1115
1116 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1117 pllinputfreq = HSE_VALUE;
1118 break;
1119
1120 default:
1121 pllinputfreq = HSI_VALUE;
1122 break;
1123 }
1124 return __LL_RCC_CALC_PLLCLK_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1125 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
1126 }
1127
1128 /**
1129 * @brief Return PLL clock frequency used for 48 MHz domain
1130 * @retval PLL clock frequency (in Hz)
1131 */
RCC_PLL_GetFreqDomain_48M(void)1132 static uint32_t RCC_PLL_GetFreqDomain_48M(void)
1133 {
1134 uint32_t pllinputfreq, pllsource;
1135
1136 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1137 48M Domain clock = PLL_VCO / PLLQ
1138 */
1139 pllsource = LL_RCC_PLL_GetMainSource();
1140
1141 switch (pllsource)
1142 {
1143 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1144 pllinputfreq = HSI_VALUE;
1145 break;
1146
1147 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1148 pllinputfreq = HSE_VALUE;
1149 break;
1150
1151 default:
1152 pllinputfreq = HSI_VALUE;
1153 break;
1154 }
1155 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1156 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
1157 }
1158
1159 /**
1160 * @}
1161 */
1162
1163 /**
1164 * @}
1165 */
1166
1167 /**
1168 * @}
1169 */
1170
1171 #endif /* USE_FULL_LL_DRIVER */
1172
1173
