1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32g4xx_ll_adc.h"
22 #include "stm32g4xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif
29
30 /** @addtogroup STM32G4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 /* Definitions of ADC hardware constraints delays */
48 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49 /* not timeout values: */
50 /* Timeout values for ADC operations are dependent to device clock */
51 /* configuration (system clock versus ADC clock), */
52 /* and therefore must be defined in user application. */
53 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54 /* values definition. */
55 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
56 /* of device clock setting. */
57 /* In user application, ADC timeout values should be defined with */
58 /* temporal values, in function of device clock settings. */
59 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
60 /* - ADC clock from synchronous clock with AHB prescaler 512, */
61 /* ADC prescaler 4. */
62 /* Ratio max = 512 *4 = 2048 */
63 /* - ADC clock from asynchronous clock (PLLP) with prescaler 256. */
64 /* Highest CPU clock PLL (PLLR). */
65 /* Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256 */
66 /* = 3968 */
67 /* Unit: CPU cycles. */
68 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (3968UL)
69 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
70 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
71
72 /**
73 * @}
74 */
75
76 /* Private macros ------------------------------------------------------------*/
77
78 /** @addtogroup ADC_LL_Private_Macros
79 * @{
80 */
81
82 /* Check of parameters for configuration of ADC hierarchical scope: */
83 /* common to several ADC instances. */
84 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
85 (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
86 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
87 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
93 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
94 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
97 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
98 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
99 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
100 )
101
102 /* Check of parameters for configuration of ADC hierarchical scope: */
103 /* ADC instance. */
104 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
105 (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
106 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
107 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
108 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
109 )
110
111 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
112 (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
113 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
114 )
115
116 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
117 (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
118 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
119 )
120
121 /* Check of parameters for configuration of ADC hierarchical scope: */
122 /* ADC group regular */
123 #if defined(STM32G474xx) || defined(STM32G484xx)
124 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
125 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
126 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
127 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
128 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
129 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
130 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
131 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
132 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
133 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \
134 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
135 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
136 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
137 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) \
138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) \
139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) \
140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) \
141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) \
142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) \
143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) \
144 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) \
145 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) \
146 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) \
147 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) \
148 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \
149 || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
150 && ( \
151 ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
152 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
153 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
154 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
155 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
156 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) \
157 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) \
158 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
159 ) \
160 ) \
161 || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
162 && ( \
163 ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \
164 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
165 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
166 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \
167 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
168 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \
169 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) \
170 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG4) \
171 ) \
172 ) \
173 )
174 #elif defined(STM32G473xx) || defined(STM32G483xx)
175 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
176 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
177 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
178 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
179 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
180 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
181 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
182 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
183 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
184 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
185 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \
186 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
187 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
188 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
189 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) \
190 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) \
191 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) \
192 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \
193 || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
194 && ( \
195 ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
196 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
197 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
198 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
199 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
200 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) \
201 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) \
202 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
203 ) \
204 ) \
205 || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
206 && ( \
207 ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \
208 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
209 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
210 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \
211 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
212 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \
213 ) \
214 ) \
215 )
216 #elif defined(STM32G471xx)
217 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
218 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
219 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
220 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
221 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
222 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
223 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
224 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
225 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
226 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
227 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \
228 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
229 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
230 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
231 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \
232 || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
233 && ( \
234 ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
235 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
236 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
237 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
238 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
239 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
240 ) \
241 ) \
242 || (((__ADC_INSTANCE__) == ADC3) \
243 && ( \
244 ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \
245 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
246 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
247 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \
248 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
249 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \
250 ) \
251 ) \
252 )
253 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
254 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
255 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
256 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
257 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
258 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
259 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
260 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
261 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
262 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
263 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
264 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
265 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
266 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
267 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
268 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \
269 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
270 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
271 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
272 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \
273 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
274 )
275 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
276 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
277 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
278 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
279 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
280 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
281 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
282 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
283 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
284 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
285 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \
286 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
287 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
288 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
289 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) \
290 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) \
291 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) \
292 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \
293 || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
294 && ( \
295 ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
296 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
297 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
298 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
299 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
300 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) \
301 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) \
302 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
303 ) \
304 ) \
305 || (((__ADC_INSTANCE__) == ADC3) \
306 && ( \
307 ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \
308 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
309 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
310 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \
311 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
312 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \
313 ) \
314 ) \
315 )
316 #endif
317
318 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
319 (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
320 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
321 )
322
323 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
324 (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
325 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
326 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
327 )
328
329 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
330 (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
331 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
332 )
333
334 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
335 (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
336 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
337 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
338 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
339 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
340 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
341 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
342 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
343 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
344 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
345 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
346 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
347 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
348 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
349 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
350 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
351 )
352
353 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
354 (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
355 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
356 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
357 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
358 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
359 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
360 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
361 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
362 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
363 )
364
365 /* Check of parameters for configuration of ADC hierarchical scope: */
366 /* ADC group injected */
367 #if defined(STM32G474xx) || defined(STM32G484xx)
368 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
369 (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
370 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
371 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
372 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
373 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
374 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
375 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
376 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
377 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \
378 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
379 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
380 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
381 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
382 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) \
383 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) \
384 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) \
385 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) \
386 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5) \
387 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6) \
388 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7) \
389 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8) \
390 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9) \
391 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10) \
392 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \
393 || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
394 && ( \
395 ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
396 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
397 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
398 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
399 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \
400 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) \
401 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
402 ) \
403 ) \
404 || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
405 && ( \
406 ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \
407 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
408 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \
409 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
410 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \
411 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1) \
412 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3) \
413 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \
414 ) \
415 ) \
416 )
417 #elif defined(STM32G473xx) || defined(STM32G483xx)
418 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
419 (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
420 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
421 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
422 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
423 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
424 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
425 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
426 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
427 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \
428 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
429 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
430 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
431 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
432 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) \
433 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) \
434 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \
435 || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
436 && ( \
437 ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
438 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
439 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
440 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
441 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \
442 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) \
443 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
444 ) \
445 ) \
446 || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
447 && ( \
448 ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \
449 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
450 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \
451 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
452 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \
453 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \
454 ) \
455 ) \
456 )
457 #elif defined(STM32G471xx)
458 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
459 (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
460 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
461 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
462 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
463 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
464 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
465 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
466 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
467 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \
468 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
469 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
470 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
471 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
472 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \
473 || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
474 && ( \
475 ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
476 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
477 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
478 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
479 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \
480 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
481 ) \
482 ) \
483 || ((((__ADC_INSTANCE__) == ADC3)) \
484 && ( \
485 ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \
486 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
487 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \
488 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
489 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \
490 ) \
491 ) \
492 )
493 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
494 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
495 (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
496 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
497 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
498 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
499 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
500 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
501 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
502 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
503 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
504 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
505 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
506 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
507 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \
508 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
509 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
510 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
511 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
512 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \
513 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \
514 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
515 )
516 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
517 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
518 (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
519 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
520 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
521 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
522 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
523 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
524 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
525 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
526 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \
527 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
528 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
529 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
530 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
531 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) \
532 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) \
533 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \
534 || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
535 && ( \
536 ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
537 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
538 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
539 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
540 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \
541 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) \
542 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
543 ) \
544 ) \
545 || ((((__ADC_INSTANCE__) == ADC3)) \
546 && ( \
547 ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \
548 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
549 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \
550 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
551 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \
552 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \
553 ) \
554 ) \
555 )
556 #endif
557
558 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
559 (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
560 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
561 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
562 )
563
564 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
565 (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
566 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
567 )
568
569 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
570 (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
571 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
572 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
573 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
574 )
575
576 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
577 (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
578 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
579 )
580
581 #if defined(ADC_MULTIMODE_SUPPORT)
582 /* Check of parameters for configuration of ADC hierarchical scope: */
583 /* multimode. */
584 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
585 (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
586 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
587 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
588 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
589 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
590 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
591 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
592 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
593 )
594
595 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
596 (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
597 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \
598 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \
599 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \
600 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \
601 )
602
603 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
604 (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
605 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \
606 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \
607 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \
608 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
609 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
610 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
611 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
612 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
613 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
614 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
615 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
616 )
617
618 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
619 (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
620 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
621 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
622 )
623
624 #endif /* ADC_MULTIMODE_SUPPORT */
625 /**
626 * @}
627 */
628
629
630 /* Private function prototypes -----------------------------------------------*/
631
632 /* Exported functions --------------------------------------------------------*/
633 /** @addtogroup ADC_LL_Exported_Functions
634 * @{
635 */
636
637 /** @addtogroup ADC_LL_EF_Init
638 * @{
639 */
640
641 /**
642 * @brief De-initialize registers of all ADC instances belonging to
643 * the same ADC common instance to their default reset values.
644 * @note This function is performing a hard reset, using high level
645 * clock source RCC ADC reset.
646 * Caution: On this STM32 series, if several ADC instances are available
647 * on the selected device, RCC ADC reset will reset
648 * all ADC instances belonging to the common ADC instance.
649 * To de-initialize only 1 ADC instance, use
650 * function @ref LL_ADC_DeInit().
651 * @param ADCxy_COMMON ADC common instance
652 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
653 * @retval An ErrorStatus enumeration value:
654 * - SUCCESS: ADC common registers are de-initialized
655 * - ERROR: not applicable
656 */
LL_ADC_CommonDeInit(ADC_Common_TypeDef * ADCxy_COMMON)657 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
658 {
659 /* Check the parameters */
660 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
661
662 if (ADCxy_COMMON == ADC12_COMMON)
663 {
664 /* Force reset of ADC clock (core clock) */
665 LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC12);
666
667 /* Release reset of ADC clock (core clock) */
668 LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC12);
669 }
670 #if defined(ADC345_COMMON)
671 else
672 {
673 /* Force reset of ADC clock (core clock) */
674 LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC345);
675
676 /* Release reset of ADC clock (core clock) */
677 LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC345);
678 }
679 #endif
680
681 return SUCCESS;
682 }
683
684 /**
685 * @brief Initialize some features of ADC common parameters
686 * (all ADC instances belonging to the same ADC common instance)
687 * and multimode (for devices with several ADC instances available).
688 * @note The setting of ADC common parameters is conditioned to
689 * ADC instances state:
690 * All ADC instances belonging to the same ADC common instance
691 * must be disabled.
692 * @param ADCxy_COMMON ADC common instance
693 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
694 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
695 * @retval An ErrorStatus enumeration value:
696 * - SUCCESS: ADC common registers are initialized
697 * - ERROR: ADC common registers are not initialized
698 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)699 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
700 {
701 ErrorStatus status = SUCCESS;
702
703 /* Check the parameters */
704 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
705 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
706
707 #if defined(ADC_MULTIMODE_SUPPORT)
708 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
709 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
710 {
711 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
712 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
713 }
714 #endif /* ADC_MULTIMODE_SUPPORT */
715
716 /* Note: Hardware constraint (refer to description of functions */
717 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
718 /* On this STM32 series, setting of these features is conditioned to */
719 /* ADC state: */
720 /* All ADC instances of the ADC common group must be disabled. */
721 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
722 {
723 /* Configuration of ADC hierarchical scope: */
724 /* - common to several ADC */
725 /* (all ADC instances belonging to the same ADC common instance) */
726 /* - Set ADC clock (conversion clock) */
727 /* - multimode (if several ADC instances available on the */
728 /* selected device) */
729 /* - Set ADC multimode configuration */
730 /* - Set ADC multimode DMA transfer */
731 /* - Set ADC multimode: delay between 2 sampling phases */
732 #if defined(ADC_MULTIMODE_SUPPORT)
733 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
734 {
735 MODIFY_REG(ADCxy_COMMON->CCR,
736 ADC_CCR_CKMODE
737 | ADC_CCR_PRESC
738 | ADC_CCR_DUAL
739 | ADC_CCR_MDMA
740 | ADC_CCR_DELAY
741 ,
742 ADC_CommonInitStruct->CommonClock
743 | ADC_CommonInitStruct->Multimode
744 | ADC_CommonInitStruct->MultiDMATransfer
745 | ADC_CommonInitStruct->MultiTwoSamplingDelay
746 );
747 }
748 else
749 {
750 MODIFY_REG(ADCxy_COMMON->CCR,
751 ADC_CCR_CKMODE
752 | ADC_CCR_PRESC
753 | ADC_CCR_DUAL
754 | ADC_CCR_MDMA
755 | ADC_CCR_DELAY
756 ,
757 ADC_CommonInitStruct->CommonClock
758 | LL_ADC_MULTI_INDEPENDENT
759 );
760 }
761 #else
762 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
763 #endif
764 }
765 else
766 {
767 /* Initialization error: One or several ADC instances belonging to */
768 /* the same ADC common instance are not disabled. */
769 status = ERROR;
770 }
771
772 return status;
773 }
774
775 /**
776 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
777 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
778 * whose fields will be set to default values.
779 * @retval None
780 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct)781 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
782 {
783 /* Set ADC_CommonInitStruct fields to default values */
784 /* Set fields of ADC common */
785 /* (all ADC instances belonging to the same ADC common instance) */
786 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
787
788 #if defined(ADC_MULTIMODE_SUPPORT)
789 /* Set fields of ADC multimode */
790 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
791 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
792 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
793 #endif /* ADC_MULTIMODE_SUPPORT */
794 }
795
796 /**
797 * @brief De-initialize registers of the selected ADC instance
798 * to their default reset values.
799 * @note To reset all ADC instances quickly (perform a hard reset),
800 * use function @ref LL_ADC_CommonDeInit().
801 * @note If this functions returns error status, it means that ADC instance
802 * is in an unknown state.
803 * In this case, perform a hard reset using high level
804 * clock source RCC ADC reset.
805 * Caution: On this STM32 series, if several ADC instances are available
806 * on the selected device, RCC ADC reset will reset
807 * all ADC instances belonging to the common ADC instance.
808 * Refer to function @ref LL_ADC_CommonDeInit().
809 * @param ADCx ADC instance
810 * @retval An ErrorStatus enumeration value:
811 * - SUCCESS: ADC registers are de-initialized
812 * - ERROR: ADC registers are not de-initialized
813 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)814 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
815 {
816 ErrorStatus status = SUCCESS;
817
818 __IO uint32_t timeout_cpu_cycles = 0UL;
819
820 /* Check the parameters */
821 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
822
823 /* Disable ADC instance if not already disabled. */
824 if (LL_ADC_IsEnabled(ADCx) == 1UL)
825 {
826 /* Set ADC group regular trigger source to SW start to ensure to not */
827 /* have an external trigger event occurring during the conversion stop */
828 /* ADC disable process. */
829 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
830
831 /* Stop potential ADC conversion on going on ADC group regular. */
832 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
833 {
834 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
835 {
836 LL_ADC_REG_StopConversion(ADCx);
837 }
838 }
839
840 /* Set ADC group injected trigger source to SW start to ensure to not */
841 /* have an external trigger event occurring during the conversion stop */
842 /* ADC disable process. */
843 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
844
845 /* Stop potential ADC conversion on going on ADC group injected. */
846 if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
847 {
848 if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
849 {
850 LL_ADC_INJ_StopConversion(ADCx);
851 }
852 }
853
854 /* Wait for ADC conversions are effectively stopped */
855 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
856 while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
857 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
858 {
859 timeout_cpu_cycles--;
860 if (timeout_cpu_cycles == 0UL)
861 {
862 /* Time-out error */
863 status = ERROR;
864 break;
865 }
866 }
867
868 /* Flush group injected contexts queue (register JSQR): */
869 /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
870 /* contexts queue is maintained with the last active context). */
871 LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
872
873 /* Disable the ADC instance */
874 LL_ADC_Disable(ADCx);
875
876 /* Wait for ADC instance is effectively disabled */
877 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
878 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
879 {
880 timeout_cpu_cycles--;
881 if (timeout_cpu_cycles == 0UL)
882 {
883 /* Time-out error */
884 status = ERROR;
885 break;
886 }
887 }
888 }
889
890 /* Check whether ADC state is compliant with expected state */
891 if (READ_BIT(ADCx->CR,
892 (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
893 | ADC_CR_ADDIS | ADC_CR_ADEN)
894 )
895 == 0UL)
896 {
897 /* ========== Reset ADC registers ========== */
898 /* Reset register IER */
899 CLEAR_BIT(ADCx->IER,
900 (LL_ADC_IT_ADRDY
901 | LL_ADC_IT_EOC
902 | LL_ADC_IT_EOS
903 | LL_ADC_IT_OVR
904 | LL_ADC_IT_EOSMP
905 | LL_ADC_IT_JEOC
906 | LL_ADC_IT_JEOS
907 | LL_ADC_IT_JQOVF
908 | LL_ADC_IT_AWD1
909 | LL_ADC_IT_AWD2
910 | LL_ADC_IT_AWD3
911 )
912 );
913
914 /* Reset register ISR */
915 SET_BIT(ADCx->ISR,
916 (LL_ADC_FLAG_ADRDY
917 | LL_ADC_FLAG_EOC
918 | LL_ADC_FLAG_EOS
919 | LL_ADC_FLAG_OVR
920 | LL_ADC_FLAG_EOSMP
921 | LL_ADC_FLAG_JEOC
922 | LL_ADC_FLAG_JEOS
923 | LL_ADC_FLAG_JQOVF
924 | LL_ADC_FLAG_AWD1
925 | LL_ADC_FLAG_AWD2
926 | LL_ADC_FLAG_AWD3
927 )
928 );
929
930 /* Reset register CR */
931 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
932 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
933 /* access mode "read-set": no direct reset applicable. */
934 /* - Reset Calibration mode to default setting (single ended). */
935 /* - Disable ADC internal voltage regulator. */
936 /* - Enable ADC deep power down. */
937 /* Note: ADC internal voltage regulator disable and ADC deep power */
938 /* down enable are conditioned to ADC state disabled: */
939 /* already done above. */
940 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
941 SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
942
943 /* Reset register CFGR */
944 MODIFY_REG(ADCx->CFGR,
945 (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
946 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
947 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
948 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
949 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN
950 | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN),
951 ADC_CFGR_JQDIS
952 );
953
954 /* Reset register CFGR2 */
955 CLEAR_BIT(ADCx->CFGR2,
956 (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
957 | ADC_CFGR2_SWTRIG | ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG
958 | ADC_CFGR2_GCOMP
959 | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
960 );
961
962 /* Reset register SMPR1 */
963 CLEAR_BIT(ADCx->SMPR1,
964 (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
965 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
966 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
967 );
968
969 /* Reset register SMPR2 */
970 CLEAR_BIT(ADCx->SMPR2,
971 (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
972 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
973 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
974 );
975
976 /* Reset register TR1 */
977 MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT | ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
978
979 /* Reset register TR2 */
980 MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
981
982 /* Reset register TR3 */
983 MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
984
985 /* Reset register SQR1 */
986 CLEAR_BIT(ADCx->SQR1,
987 (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
988 | ADC_SQR1_SQ1 | ADC_SQR1_L)
989 );
990
991 /* Reset register SQR2 */
992 CLEAR_BIT(ADCx->SQR2,
993 (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
994 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
995 );
996
997 /* Reset register SQR3 */
998 CLEAR_BIT(ADCx->SQR3,
999 (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
1000 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
1001 );
1002
1003 /* Reset register SQR4 */
1004 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
1005
1006 /* Reset register JSQR */
1007 CLEAR_BIT(ADCx->JSQR,
1008 (ADC_JSQR_JL
1009 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
1010 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
1011 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1)
1012 );
1013
1014 /* Reset register DR */
1015 /* Note: bits in access mode read only, no direct reset applicable */
1016
1017 /* Reset register OFR1 */
1018 CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 | ADC_OFR1_SATEN | ADC_OFR1_OFFSETPOS);
1019 /* Reset register OFR2 */
1020 CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 | ADC_OFR2_SATEN | ADC_OFR2_OFFSETPOS);
1021 /* Reset register OFR3 */
1022 CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN | ADC_OFR3_OFFSETPOS);
1023 /* Reset register OFR4 */
1024 CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN | ADC_OFR4_OFFSETPOS);
1025
1026 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
1027 /* Note: bits in access mode read only, no direct reset applicable */
1028
1029 /* Reset register AWD2CR */
1030 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
1031
1032 /* Reset register AWD3CR */
1033 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
1034
1035 /* Reset register DIFSEL */
1036 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
1037
1038 /* Reset register CALFACT */
1039 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
1040
1041 /* Reset register GCOMP */
1042 CLEAR_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF);
1043 }
1044 else
1045 {
1046 /* ADC instance is in an unknown state */
1047 /* Need to performing a hard reset of ADC instance, using high level */
1048 /* clock source RCC ADC reset. */
1049 /* Caution: On this STM32 series, if several ADC instances are available */
1050 /* on the selected device, RCC ADC reset will reset */
1051 /* all ADC instances belonging to the common ADC instance. */
1052 /* Caution: On this STM32 series, if several ADC instances are available */
1053 /* on the selected device, RCC ADC reset will reset */
1054 /* all ADC instances belonging to the common ADC instance. */
1055 status = ERROR;
1056 }
1057
1058 return status;
1059 }
1060
1061 /**
1062 * @brief Initialize some features of ADC instance.
1063 * @note These parameters have an impact on ADC scope: ADC instance.
1064 * Affects both group regular and group injected (availability
1065 * of ADC group injected depends on STM32 families).
1066 * Refer to corresponding unitary functions into
1067 * @ref ADC_LL_EF_Configuration_ADC_Instance .
1068 * @note The setting of these parameters by function @ref LL_ADC_Init()
1069 * is conditioned to ADC state:
1070 * ADC instance must be disabled.
1071 * This condition is applied to all ADC features, for efficiency
1072 * and compatibility over all STM32 families. However, the different
1073 * features can be set under different ADC state conditions
1074 * (setting possible with ADC enabled without conversion on going,
1075 * ADC enabled with conversion on going, ...)
1076 * Each feature can be updated afterwards with a unitary function
1077 * and potentially with ADC in a different state than disabled,
1078 * refer to description of each function for setting
1079 * conditioned to ADC state.
1080 * @note After using this function, some other features must be configured
1081 * using LL unitary functions.
1082 * The minimum configuration remaining to be done is:
1083 * - Set ADC group regular or group injected sequencer:
1084 * map channel on the selected sequencer rank.
1085 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
1086 * - Set ADC channel sampling time
1087 * Refer to function LL_ADC_SetChannelSamplingTime();
1088 * @param ADCx ADC instance
1089 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1090 * @retval An ErrorStatus enumeration value:
1091 * - SUCCESS: ADC registers are initialized
1092 * - ERROR: ADC registers are not initialized
1093 */
LL_ADC_Init(ADC_TypeDef * ADCx,LL_ADC_InitTypeDef * ADC_InitStruct)1094 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
1095 {
1096 ErrorStatus status = SUCCESS;
1097
1098 /* Check the parameters */
1099 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1100
1101 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
1102 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
1103 assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
1104
1105 /* Note: Hardware constraint (refer to description of this function): */
1106 /* ADC instance must be disabled. */
1107 if (LL_ADC_IsEnabled(ADCx) == 0UL)
1108 {
1109 /* Configuration of ADC hierarchical scope: */
1110 /* - ADC instance */
1111 /* - Set ADC data resolution */
1112 /* - Set ADC conversion data alignment */
1113 /* - Set ADC low power mode */
1114 MODIFY_REG(ADCx->CFGR,
1115 ADC_CFGR_RES
1116 | ADC_CFGR_ALIGN
1117 | ADC_CFGR_AUTDLY
1118 ,
1119 ADC_InitStruct->Resolution
1120 | ADC_InitStruct->DataAlignment
1121 | ADC_InitStruct->LowPowerMode
1122 );
1123
1124 }
1125 else
1126 {
1127 /* Initialization error: ADC instance is not disabled. */
1128 status = ERROR;
1129 }
1130
1131 return status;
1132 }
1133
1134 /**
1135 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
1136 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
1137 * whose fields will be set to default values.
1138 * @retval None
1139 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * ADC_InitStruct)1140 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
1141 {
1142 /* Set ADC_InitStruct fields to default values */
1143 /* Set fields of ADC instance */
1144 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
1145 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
1146 ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
1147
1148 }
1149
1150 /**
1151 * @brief Initialize some features of ADC group regular.
1152 * @note These parameters have an impact on ADC scope: ADC group regular.
1153 * Refer to corresponding unitary functions into
1154 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
1155 * (functions with prefix "REG").
1156 * @note The setting of these parameters by function @ref LL_ADC_Init()
1157 * is conditioned to ADC state:
1158 * ADC instance must be disabled.
1159 * This condition is applied to all ADC features, for efficiency
1160 * and compatibility over all STM32 families. However, the different
1161 * features can be set under different ADC state conditions
1162 * (setting possible with ADC enabled without conversion on going,
1163 * ADC enabled with conversion on going, ...)
1164 * Each feature can be updated afterwards with a unitary function
1165 * and potentially with ADC in a different state than disabled,
1166 * refer to description of each function for setting
1167 * conditioned to ADC state.
1168 * @note After using this function, other features must be configured
1169 * using LL unitary functions.
1170 * The minimum configuration remaining to be done is:
1171 * - Set ADC group regular or group injected sequencer:
1172 * map channel on the selected sequencer rank.
1173 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
1174 * - Set ADC channel sampling time
1175 * Refer to function LL_ADC_SetChannelSamplingTime();
1176 * @param ADCx ADC instance
1177 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1178 * @retval An ErrorStatus enumeration value:
1179 * - SUCCESS: ADC registers are initialized
1180 * - ERROR: ADC registers are not initialized
1181 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)1182 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
1183 {
1184 ErrorStatus status = SUCCESS;
1185
1186 /* Check the parameters */
1187 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1188 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource));
1189 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
1190 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1191 {
1192 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
1193
1194 /* ADC group regular continuous mode and discontinuous mode */
1195 /* can not be enabled simultenaeously */
1196 assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
1197 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
1198 }
1199 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
1200 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
1201 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
1202
1203 /* Note: Hardware constraint (refer to description of this function): */
1204 /* ADC instance must be disabled. */
1205 if (LL_ADC_IsEnabled(ADCx) == 0UL)
1206 {
1207 /* Configuration of ADC hierarchical scope: */
1208 /* - ADC group regular */
1209 /* - Set ADC group regular trigger source */
1210 /* - Set ADC group regular sequencer length */
1211 /* - Set ADC group regular sequencer discontinuous mode */
1212 /* - Set ADC group regular continuous mode */
1213 /* - Set ADC group regular conversion data transfer: no transfer or */
1214 /* transfer by DMA, and DMA requests mode */
1215 /* - Set ADC group regular overrun behavior */
1216 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
1217 /* setting of trigger source to SW start. */
1218 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1219 {
1220 MODIFY_REG(ADCx->CFGR,
1221 ADC_CFGR_EXTSEL
1222 | ADC_CFGR_EXTEN
1223 | ADC_CFGR_DISCEN
1224 | ADC_CFGR_DISCNUM
1225 | ADC_CFGR_CONT
1226 | ADC_CFGR_DMAEN
1227 | ADC_CFGR_DMACFG
1228 | ADC_CFGR_OVRMOD
1229 ,
1230 ADC_REG_InitStruct->TriggerSource
1231 | ADC_REG_InitStruct->SequencerDiscont
1232 | ADC_REG_InitStruct->ContinuousMode
1233 | ADC_REG_InitStruct->DMATransfer
1234 | ADC_REG_InitStruct->Overrun
1235 );
1236 }
1237 else
1238 {
1239 MODIFY_REG(ADCx->CFGR,
1240 ADC_CFGR_EXTSEL
1241 | ADC_CFGR_EXTEN
1242 | ADC_CFGR_DISCEN
1243 | ADC_CFGR_DISCNUM
1244 | ADC_CFGR_CONT
1245 | ADC_CFGR_DMAEN
1246 | ADC_CFGR_DMACFG
1247 | ADC_CFGR_OVRMOD
1248 ,
1249 ADC_REG_InitStruct->TriggerSource
1250 | LL_ADC_REG_SEQ_DISCONT_DISABLE
1251 | ADC_REG_InitStruct->ContinuousMode
1252 | ADC_REG_InitStruct->DMATransfer
1253 | ADC_REG_InitStruct->Overrun
1254 );
1255 }
1256
1257 /* Set ADC group regular sequencer length and scan direction */
1258 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
1259 }
1260 else
1261 {
1262 /* Initialization error: ADC instance is not disabled. */
1263 status = ERROR;
1264 }
1265 return status;
1266 }
1267
1268 /**
1269 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
1270 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1271 * whose fields will be set to default values.
1272 * @retval None
1273 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct)1274 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
1275 {
1276 /* Set ADC_REG_InitStruct fields to default values */
1277 /* Set fields of ADC group regular */
1278 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
1279 /* setting of trigger source to SW start. */
1280 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
1281 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
1282 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
1283 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
1284 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
1285 ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
1286 }
1287
1288 /**
1289 * @brief Initialize some features of ADC group injected.
1290 * @note These parameters have an impact on ADC scope: ADC group injected.
1291 * Refer to corresponding unitary functions into
1292 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
1293 * (functions with prefix "INJ").
1294 * @note The setting of these parameters by function @ref LL_ADC_Init()
1295 * is conditioned to ADC state:
1296 * ADC instance must be disabled.
1297 * This condition is applied to all ADC features, for efficiency
1298 * and compatibility over all STM32 families. However, the different
1299 * features can be set under different ADC state conditions
1300 * (setting possible with ADC enabled without conversion on going,
1301 * ADC enabled with conversion on going, ...)
1302 * Each feature can be updated afterwards with a unitary function
1303 * and potentially with ADC in a different state than disabled,
1304 * refer to description of each function for setting
1305 * conditioned to ADC state.
1306 * @note After using this function, other features must be configured
1307 * using LL unitary functions.
1308 * The minimum configuration remaining to be done is:
1309 * - Set ADC group injected sequencer:
1310 * map channel on the selected sequencer rank.
1311 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
1312 * - Set ADC channel sampling time
1313 * Refer to function LL_ADC_SetChannelSamplingTime();
1314 * @note Caution if feature ADC group injected contexts queue is enabled
1315 * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
1316 * using successively several times this function will appear as
1317 * having no effect.
1318 * To set several features of ADC group injected, use
1319 * function @ref LL_ADC_INJ_ConfigQueueContext().
1320 * @param ADCx ADC instance
1321 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1322 * @retval An ErrorStatus enumeration value:
1323 * - SUCCESS: ADC registers are initialized
1324 * - ERROR: ADC registers are not initialized
1325 */
LL_ADC_INJ_Init(ADC_TypeDef * ADCx,LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)1326 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1327 {
1328 ErrorStatus status = SUCCESS;
1329
1330 /* Check the parameters */
1331 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1332 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource));
1333 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
1334 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
1335 {
1336 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
1337 }
1338 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
1339
1340 /* Note: Hardware constraint (refer to description of this function): */
1341 /* ADC instance must be disabled. */
1342 if (LL_ADC_IsEnabled(ADCx) == 0UL)
1343 {
1344 /* Configuration of ADC hierarchical scope: */
1345 /* - ADC group injected */
1346 /* - Set ADC group injected trigger source */
1347 /* - Set ADC group injected sequencer length */
1348 /* - Set ADC group injected sequencer discontinuous mode */
1349 /* - Set ADC group injected conversion trigger: independent or */
1350 /* from ADC group regular */
1351 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
1352 /* setting of trigger source to SW start. */
1353 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1354 {
1355 MODIFY_REG(ADCx->CFGR,
1356 ADC_CFGR_JDISCEN
1357 | ADC_CFGR_JAUTO
1358 ,
1359 ADC_INJ_InitStruct->SequencerDiscont
1360 | ADC_INJ_InitStruct->TrigAuto
1361 );
1362 }
1363 else
1364 {
1365 MODIFY_REG(ADCx->CFGR,
1366 ADC_CFGR_JDISCEN
1367 | ADC_CFGR_JAUTO
1368 ,
1369 LL_ADC_REG_SEQ_DISCONT_DISABLE
1370 | ADC_INJ_InitStruct->TrigAuto
1371 );
1372 }
1373
1374 MODIFY_REG(ADCx->JSQR,
1375 ADC_JSQR_JEXTSEL
1376 | ADC_JSQR_JEXTEN
1377 | ADC_JSQR_JL
1378 ,
1379 ADC_INJ_InitStruct->TriggerSource
1380 | ADC_INJ_InitStruct->SequencerLength
1381 );
1382 }
1383 else
1384 {
1385 /* Initialization error: ADC instance is not disabled. */
1386 status = ERROR;
1387 }
1388 return status;
1389 }
1390
1391 /**
1392 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1393 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1394 * whose fields will be set to default values.
1395 * @retval None
1396 */
LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct)1397 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1398 {
1399 /* Set ADC_INJ_InitStruct fields to default values */
1400 /* Set fields of ADC group injected */
1401 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1402 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1403 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1404 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1405 }
1406
1407 /**
1408 * @}
1409 */
1410
1411 /**
1412 * @}
1413 */
1414
1415 /**
1416 * @}
1417 */
1418
1419 #endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */
1420
1421 /**
1422 * @}
1423 */
1424
1425 #endif /* USE_FULL_LL_DRIVER */
1426
