1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization/de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2019 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 */
23
24 /* Includes ------------------------------------------------------------------*/
25 #include "stm32g4xx_hal.h"
26
27 /** @addtogroup STM32G4xx_HAL_Driver
28 * @{
29 */
30
31 /** @defgroup PWR PWR
32 * @brief PWR HAL module driver
33 * @{
34 */
35
36 #ifdef HAL_PWR_MODULE_ENABLED
37
38 /* Private typedef -----------------------------------------------------------*/
39 /* Private define ------------------------------------------------------------*/
40
41 /** @defgroup PWR_Private_Defines PWR Private Defines
42 * @{
43 */
44
45 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
46 * @{
47 */
48 #define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */
49 #define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */
50 #define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */
51 #define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */
52 /**
53 * @}
54 */
55
56 /**
57 * @}
58 */
59
60 /* Private macro -------------------------------------------------------------*/
61 /* Private variables ---------------------------------------------------------*/
62 /* Private function prototypes -----------------------------------------------*/
63 /* Exported functions --------------------------------------------------------*/
64
65 /** @defgroup PWR_Exported_Functions PWR Exported Functions
66 * @{
67 */
68
69 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
70 * @brief Initialization and de-initialization functions
71 *
72 @verbatim
73 ===============================================================================
74 ##### Initialization and de-initialization functions #####
75 ===============================================================================
76 [..]
77
78 @endverbatim
79 * @{
80 */
81
82 /**
83 * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
84 * @retval None
85 */
HAL_PWR_DeInit(void)86 void HAL_PWR_DeInit(void)
87 {
88 __HAL_RCC_PWR_FORCE_RESET();
89 __HAL_RCC_PWR_RELEASE_RESET();
90 }
91
92 /**
93 * @brief Enable access to the backup domain
94 * (RTC registers, RTC backup data registers).
95 * @note After reset, the backup domain is protected against
96 * possible unwanted write accesses.
97 * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
98 * In order to set or modify the RTC clock, the backup domain access must be
99 * disabled.
100 * @note LSEON bit that switches on and off the LSE crystal belongs as well to the
101 * back-up domain.
102 * @retval None
103 */
HAL_PWR_EnableBkUpAccess(void)104 void HAL_PWR_EnableBkUpAccess(void)
105 {
106 SET_BIT(PWR->CR1, PWR_CR1_DBP);
107 }
108
109 /**
110 * @brief Disable access to the backup domain
111 * (RTC registers, RTC backup data registers).
112 * @retval None
113 */
HAL_PWR_DisableBkUpAccess(void)114 void HAL_PWR_DisableBkUpAccess(void)
115 {
116 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
117 }
118
119
120
121
122 /**
123 * @}
124 */
125
126
127
128 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
129 * @brief Low Power modes configuration functions
130 *
131 @verbatim
132
133 ===============================================================================
134 ##### Peripheral Control functions #####
135 ===============================================================================
136
137 [..]
138 *** PVD configuration ***
139 =========================
140 [..]
141 (+) The PVD is used to monitor the VDD power supply by comparing it to a
142 threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
143
144 (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
145 than the PVD threshold. This event is internally connected to the EXTI
146 line16 and can generate an interrupt if enabled. This is done through
147 __HAL_PVD_EXTI_ENABLE_IT() macro.
148 (+) The PVD is stopped in Standby mode.
149
150
151 *** WakeUp pin configuration ***
152 ================================
153 [..]
154 (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
155 The polarity of these pins can be set to configure event detection on high
156 level (rising edge) or low level (falling edge).
157
158
159
160 *** Low Power modes configuration ***
161 =====================================
162 [..]
163 The devices feature 8 low-power modes:
164 (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
165 (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
166 (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
167 (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
168 (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
169 (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
170 (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
171 (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
172
173
174 *** Low-power run mode ***
175 ==========================
176 [..]
177 (+) Entry: (from main run mode)
178 (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
179
180 (+) Exit:
181 (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
182 then can the system clock frequency be increased above 2 MHz.
183
184
185 *** Sleep mode / Low-power sleep mode ***
186 =========================================
187 [..]
188 (+) Entry:
189 The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
190 in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
191 (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
192 (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
193 In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
194 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
195 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
196
197 (+) WFI Exit:
198 (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
199 controller (NVIC) or any wake-up event.
200
201 (+) WFE Exit:
202 (++) Any wake-up event such as an EXTI line configured in event mode.
203
204 [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
205 the MCU is in Low-power Run mode.
206
207 *** Stop 0, Stop 1 modes ***
208 ===============================
209 [..]
210 (+) Entry:
211 The Stop 0, Stop 1 modes are entered through the following API's:
212 (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
213 (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
214 (++) PWR_MAINREGULATOR_ON
215 (++) PWR_LOWPOWERREGULATOR_ON
216 (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
217 (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
218 (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
219
220 (+) WFI Exit:
221 (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
222 (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
223 when programmed in wakeup mode.
224 (+) WFE Exit:
225 (++) Any EXTI Line (Internal or External) configured in Event mode.
226
227 [..]
228 When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
229 depending on the LPR bit setting.
230
231 *** Standby mode ***
232 ====================
233 [..]
234 The Standby mode offers two options:
235 (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
236 SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
237 and Standby circuitry.
238 (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
239 SRAM and register contents are lost except for the RTC registers, RTC backup registers
240 and Standby circuitry.
241
242 (++) Entry:
243 (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
244 SRAM1 and register contents are lost except for registers in the Backup domain and
245 Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
246 To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
247 to set RRS bit.
248
249 (++) Exit:
250 (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
251 external reset in NRST pin, IWDG reset.
252
253 [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.
254
255
256 *** Shutdown mode ***
257 ======================
258 [..]
259 In Shutdown mode,
260 voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
261 SRAM and registers contents are lost except for backup domain registers.
262
263 (+) Entry:
264 The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
265
266 (+) Exit:
267 (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
268 external reset in NRST pin.
269
270 [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
271
272
273 *** Auto-wakeup (AWU) from low-power mode ***
274 =============================================
275 [..]
276 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
277 Wakeup event, a tamper event or a time-stamp event, without depending on
278 an external interrupt (Auto-wakeup mode).
279
280 (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
281
282
283 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
284 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
285
286 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
287 is necessary to configure the RTC to detect the tamper or time stamp event using the
288 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
289
290 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
291 configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
292
293 @endverbatim
294 * @{
295 */
296
297
298
299 /**
300 * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
301 * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD
302 * configuration information.
303 * @note Refer to the electrical characteristics of your device datasheet for
304 * more details about the voltage thresholds corresponding to each
305 * detection level.
306 * @retval None
307 */
HAL_PWR_ConfigPVD(PWR_PVDTypeDef * sConfigPVD)308 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
309 {
310 /* Check the parameters */
311 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
312 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
313
314 /* Set PLS bits according to PVDLevel value */
315 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
316
317 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
318 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
319 __HAL_PWR_PVD_EXTI_DISABLE_IT();
320 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
321 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
322
323 /* Configure interrupt mode */
324 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
325 {
326 __HAL_PWR_PVD_EXTI_ENABLE_IT();
327 }
328
329 /* Configure event mode */
330 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
331 {
332 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
333 }
334
335 /* Configure the edge */
336 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
337 {
338 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
339 }
340
341 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
342 {
343 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
344 }
345
346 return HAL_OK;
347 }
348
349
350 /**
351 * @brief Enable the Power Voltage Detector (PVD).
352 * @retval None
353 */
HAL_PWR_EnablePVD(void)354 void HAL_PWR_EnablePVD(void)
355 {
356 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
357 }
358
359 /**
360 * @brief Disable the Power Voltage Detector (PVD).
361 * @retval None
362 */
HAL_PWR_DisablePVD(void)363 void HAL_PWR_DisablePVD(void)
364 {
365 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
366 }
367
368
369
370
371 /**
372 * @brief Enable the WakeUp PINx functionality.
373 * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
374 * This parameter can be one of the following legacy values which set the default polarity
375 * i.e. detection on high level (rising edge):
376 * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
377 *
378 * or one of the following value where the user can explicitly specify the enabled pin and
379 * the chosen polarity:
380 * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
381 * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
382 * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
383 * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
384 * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
385 * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
386 * @retval None
387 */
HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)388 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
389 {
390 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
391
392 /* Specifies the Wake-Up pin polarity for the event detection
393 (rising or falling edge) */
394 MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
395
396 /* Enable wake-up pin */
397 SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
398
399
400 }
401
402 /**
403 * @brief Disable the WakeUp PINx functionality.
404 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
405 * This parameter can be one of the following values:
406 * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
407 * @retval None
408 */
HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)409 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
410 {
411 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
412
413 CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
414 }
415
416
417 /**
418 * @brief Enter Sleep or Low-power Sleep mode.
419 * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
420 * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
421 * This parameter can be one of the following values:
422 * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
423 * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
424 * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
425 * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
426 * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
427 * Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
428 * Additionally, the clock frequency must be reduced below 2 MHz.
429 * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
430 * be done before calling HAL_PWR_EnterSLEEPMode() API.
431 * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
432 * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
433 * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
434 * This parameter can be one of the following values:
435 * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
436 * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
437 * @note When WFI entry is used, tick interrupt have to be disabled if not desired as
438 * the interrupt wake up source.
439 * @retval None
440 */
HAL_PWR_EnterSLEEPMode(uint32_t Regulator,uint8_t SLEEPEntry)441 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
442 {
443 /* Check the parameters */
444 assert_param(IS_PWR_REGULATOR(Regulator));
445 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
446
447 /* Set Regulator parameter */
448 if (Regulator == PWR_MAINREGULATOR_ON)
449 {
450 /* If in low-power run mode at this point, exit it */
451 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
452 {
453 (void)HAL_PWREx_DisableLowPowerRunMode();
454 }
455 /* Regulator now in main mode. */
456 }
457 else
458 {
459 /* If in run mode, first move to low-power run mode.
460 The system clock frequency must be below 2 MHz at this point. */
461 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == 0U)
462 {
463 HAL_PWREx_EnableLowPowerRunMode();
464 }
465 }
466
467 /* Clear SLEEPDEEP bit of Cortex System Control Register */
468 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
469
470 /* Select SLEEP mode entry -------------------------------------------------*/
471 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
472 {
473 /* Request Wait For Interrupt */
474 __WFI();
475 }
476 else
477 {
478 /* Request Wait For Event */
479 __SEV();
480 __WFE();
481 __WFE();
482 }
483
484 }
485
486
487 /**
488 * @brief Enter Stop mode
489 * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
490 * on devices where only "Stop mode" is mentioned with main or low power regulator ON.
491 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
492 * @note All clocks in the VCORE domain are stopped; the PLL,
493 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
494 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
495 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
496 * only to the peripheral requesting it.
497 * SRAM1, SRAM2 and register contents are preserved.
498 * The BOR is available.
499 * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
500 * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
501 * the HSI RC oscillator is selected as system clock.
502 * @note When the voltage regulator operates in low power mode (Stop 1), an additional
503 * startup delay is incurred when waking up.
504 * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
505 * is higher although the startup time is reduced.
506 * @param Regulator: Specifies the regulator state in Stop mode.
507 * This parameter can be one of the following values:
508 * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
509 * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
510 * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
511 * This parameter can be one of the following values:
512 * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
513 * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
514 * @retval None
515 */
HAL_PWR_EnterSTOPMode(uint32_t Regulator,uint8_t STOPEntry)516 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
517 {
518 /* Check the parameters */
519 assert_param(IS_PWR_REGULATOR(Regulator));
520
521 if(Regulator == PWR_LOWPOWERREGULATOR_ON)
522 {
523 HAL_PWREx_EnterSTOP1Mode(STOPEntry);
524 }
525 else
526 {
527 HAL_PWREx_EnterSTOP0Mode(STOPEntry);
528 }
529 }
530
531 /**
532 * @brief Enter Standby mode.
533 * @note In Standby mode, the PLL, the HSI and the HSE oscillators are switched
534 * off. The voltage regulator is disabled, except when SRAM2 content is preserved
535 * in which case the regulator is in low-power mode.
536 * SRAM1 and register contents are lost except for registers in the Backup domain and
537 * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
538 * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
539 * to set RRS bit.
540 * The BOR is available.
541 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
542 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
543 * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
544 * same.
545 * These states are effective in Standby mode only if APC bit is set through
546 * HAL_PWREx_EnablePullUpPullDownConfig() API.
547 * @retval None
548 */
HAL_PWR_EnterSTANDBYMode(void)549 void HAL_PWR_EnterSTANDBYMode(void)
550 {
551 /* Set Stand-by mode */
552 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
553
554 /* Set SLEEPDEEP bit of Cortex System Control Register */
555 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
556
557 /* This option is used to ensure that store operations are completed */
558 #if defined ( __CC_ARM)
559 __force_stores();
560 #endif
561 /* Request Wait For Interrupt */
562 __WFI();
563 }
564
565
566
567 /**
568 * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
569 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
570 * re-enters SLEEP mode when an interruption handling is over.
571 * Setting this bit is useful when the processor is expected to run only on
572 * interruptions handling.
573 * @retval None
574 */
HAL_PWR_EnableSleepOnExit(void)575 void HAL_PWR_EnableSleepOnExit(void)
576 {
577 /* Set SLEEPONEXIT bit of Cortex System Control Register */
578 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
579 }
580
581
582 /**
583 * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
584 * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
585 * re-enters SLEEP mode when an interruption handling is over.
586 * @retval None
587 */
HAL_PWR_DisableSleepOnExit(void)588 void HAL_PWR_DisableSleepOnExit(void)
589 {
590 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
591 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
592 }
593
594
595
596 /**
597 * @brief Enable CORTEX M4 SEVONPEND bit.
598 * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
599 * WFE to wake up when an interrupt moves from inactive to pended.
600 * @retval None
601 */
HAL_PWR_EnableSEVOnPend(void)602 void HAL_PWR_EnableSEVOnPend(void)
603 {
604 /* Set SEVONPEND bit of Cortex System Control Register */
605 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
606 }
607
608
609 /**
610 * @brief Disable CORTEX M4 SEVONPEND bit.
611 * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
612 * WFE to wake up when an interrupt moves from inactive to pended.
613 * @retval None
614 */
HAL_PWR_DisableSEVOnPend(void)615 void HAL_PWR_DisableSEVOnPend(void)
616 {
617 /* Clear SEVONPEND bit of Cortex System Control Register */
618 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
619 }
620
621
622
623
624
625 /**
626 * @brief PWR PVD interrupt callback
627 * @retval None
628 */
HAL_PWR_PVDCallback(void)629 __weak void HAL_PWR_PVDCallback(void)
630 {
631 /* NOTE : This function should not be modified; when the callback is needed,
632 the HAL_PWR_PVDCallback can be implemented in the user file
633 */
634 }
635
636 /**
637 * @}
638 */
639
640 /**
641 * @}
642 */
643
644 #endif /* HAL_PWR_MODULE_ENABLED */
645 /**
646 * @}
647 */
648
649 /**
650 * @}
651 */
652
653
