1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_dac.c
4 * @author MCD Application Team
5 * @brief DAC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Digital to Analog Converter (DAC) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State and Errors functions
12 *
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2019 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### DAC Peripheral features #####
28 ==============================================================================
29 [..]
30 *** DAC Channels ***
31 ====================
32 [..]
33 STM32G4 devices integrate up to seven 12-bit Digital Analog Converters,
34 up to six of them grouped by pair forming a DAC instance.
35
36 The 2 converters of an single instance (i.e. channel1 & channel2)
37 can be used independently or simultaneously (dual mode):
38 (#) DAC channel1 with DAC_OUT1 as output (not for all) or connected to on-chip
39 peripherals (ex. comparators, operational amplifier).
40 (#) DAC channel2 with DAC_OUT2 as output (not for all) or connected to on-chip
41 peripherals (ex. comparators, operational amplifier).
42 Note: when an instance only includes one converter, only independent mode is
43 supported by this converter.
44
45 STM32G4 instances & converters availability and output PIO mapping (DAC_OUTx):
46 ----------------------------------------------------------------------------
47 | DAC1 | DAC2 | DAC3 | DAC4 |
48 ----------------------------------------------------------------------------
49 Channel 1 | | YES | YES | YES | YES
50 | DAC_OUT1 | PA4 | PA6 | - | -
51 ----------------------------------------------------------------------------
52 Channel 2 | | YES | NO | YES | YES
53 | DAC_OUT2 | PA5 | - | - | -
54 ----------------------------------------------------------------------------
55 Note: On this STM32 series, all devices do not include each DAC instances listed
56 above. Refer to device datasheet for DACx instance availability.
57
58 *** DAC Triggers ***
59 ====================
60 [..]
61 Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
62 and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
63 [..]
64 Digital to Analog conversion can be triggered by:
65 (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
66 The used pin (GPIOx_PIN_9) must be configured in input mode.
67
68 (#) Timers TRGO: TIM1, TIM2, TIM3, TIM4, TIM6, TIM7, TIM8 and TIM15
69 (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...)
70
71 (#) Software using DAC_TRIGGER_SOFTWARE
72
73 (#) HRTimer TRGO: HRTIM1 (1)
74 (DAC_TRIGGER_HRTIM_TRG01, DAC_TRIGGER_HRTIM_TRG02...)
75
76 [..]
77 Specific triggers for sawtooth generation:
78 (#) External event: EXTI Line 10 (any GPIOx_PIN_10) using DAC_TRIGGER_EXT_IT10.
79 The used pin (GPIOx_PIN_10) must be configured in input mode.
80
81 (#) HRTimer Step & Reset: HRTIM1 (1)
82 (DAC_TRIGGER_HRTIM_RST_TRG1, DAC_TRIGGER_HRTIM_STEP_TRG1...)
83
84 Note: On this STM32 series, parameter only available if HRTIM feature is
85 supported (refer to device datasheet for supported features list)
86
87 *** DAC Buffer mode feature ***
88 ===============================
89 [..]
90 Each DAC channel integrates an output buffer that can be used to
91 reduce the output impedance, and to drive external loads directly
92 without having to add an external operational amplifier.
93 To enable, the output buffer use
94 sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
95 [..]
96 (@) Refer to the device datasheet for more details about output
97 impedance value with and without output buffer.
98
99 *** DAC connect feature ***
100 ===============================
101 [..]
102 Each DAC channel can be connected internally.
103 To connect, use
104 sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL;
105 or
106 sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_BOTH;
107
108 *** GPIO configurations guidelines ***
109 =====================
110 [..]
111 When a DAC channel is used (ex channel1 on PA4) and the other is not
112 (ex channel2 on PA5 is configured in Analog and disabled).
113 Channel1 may disturb channel2 as coupling effect.
114 Note that there is no coupling on channel2 as soon as channel2 is turned on.
115 Coupling on adjacent channel could be avoided as follows:
116 when unused PA5 is configured as INPUT PULL-UP or DOWN.
117 PA5 is configured in ANALOG just before it is turned on.
118
119 *** DAC Sample and Hold feature ***
120 ========================
121 [..]
122 For each converter, 2 modes are supported: normal mode and
123 "sample and hold" mode (i.e. low power mode).
124 In the sample and hold mode, the DAC core converts data, then holds the
125 converted voltage on a capacitor. When not converting, the DAC cores and
126 buffer are completely turned off between samples and the DAC output is
127 tri-stated, therefore reducing the overall power consumption. A new
128 stabilization period is needed before each new conversion.
129
130 The sample and hold allow setting internal or external voltage @
131 low power consumption cost (output value can be at any given rate either
132 by CPU or DMA).
133
134 The Sample and hold block and registers uses either LSI & run in
135 several power modes: run mode, sleep mode, low power run, low power sleep
136 mode & stop1 mode.
137
138 Low power stop1 mode allows only static conversion.
139
140 To enable Sample and Hold mode
141 Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI &
142 RCC_LSI_ON parameters.
143
144 Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE;
145 & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
146 DAC_HoldTime & DAC_RefreshTime;
147
148 *** DAC calibration feature ***
149 ===================================
150 [..]
151 (#) The 2 converters (channel1 & channel2) provide calibration capabilities.
152 (++) Calibration aims at correcting some offset of output buffer.
153 (++) The DAC uses either factory calibration settings OR user defined
154 calibration (trimming) settings (i.e. trimming mode).
155 (++) The user defined settings can be figured out using self calibration
156 handled by HAL_DACEx_SelfCalibrate.
157 (++) HAL_DACEx_SelfCalibrate:
158 (+++) Runs automatically the calibration.
159 (+++) Enables the user trimming mode
160 (+++) Updates a structure with trimming values with fresh calibration
161 results.
162 The user may store the calibration results for larger
163 (ex monitoring the trimming as a function of temperature
164 for instance)
165
166 *** DAC wave generation feature ***
167 ===================================
168 [..]
169 Both DAC channels can be used to generate
170 (#) Noise wave
171 (#) Triangle wave
172 (#) Sawtooth wave
173
174 *** DAC data format ***
175 =======================
176 [..]
177 The DAC data format can be:
178 (#) 8-bit right alignment using DAC_ALIGN_8B_R
179 (#) 12-bit left alignment using DAC_ALIGN_12B_L
180 (#) 12-bit right alignment using DAC_ALIGN_12B_R
181
182 *** DAC data value to voltage correspondence ***
183 ================================================
184 [..]
185 The analog output voltage on each DAC channel pin is determined
186 by the following equation:
187 [..]
188 DAC_OUTx = VREF+ * DOR / 4095
189 (+) with DOR is the Data Output Register
190 [..]
191 VREF+ is the input voltage reference (refer to the device datasheet)
192 [..]
193 e.g. To set DAC_OUT1 to 0.7V, use
194 (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
195
196 *** DMA requests ***
197 =====================
198 [..]
199 A DMAMUX request can be generated when an external trigger (but not a software trigger)
200 occurs if DMAMUX requests are enabled using HAL_DAC_Start_DMA().
201 DMAMUX requests are mapped as following:
202 ----------------------------------------------------------------------------
203 | DAC1 | DAC2 | DAC3 | DAC4 |
204 ----------------------------------------------------------------------------
205 Channel 1 | | 6 | 41 | 102 | 104
206 ----------------------------------------------------------------------------
207 Channel 2 | | 7 | - | 103 | 105
208 ----------------------------------------------------------------------------
209 Note: On this STM32 series, all devices do not include each DAC instances listed
210 above. Refer to device datasheet for DACx instance availability.
211
212 *** High frequency interface mode ***
213 =====================================
214 [..]
215 The high frequency interface informs DAC instance about the bus frequency in use.
216 It is mandatory information for DAC (as internal timing of DAC is bus frequency dependent)
217 provided thanks to parameter DAC_HighFrequency handled in HAL_DAC_ConfigChannel () function.
218 Use of DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC value of DAC_HighFrequency is recommended
219 function figured out the correct setting.
220 The high frequency mode is same for all converters of a same DAC instance. Either same
221 parameter DAC_HighFrequency is used for all DAC converters or again self
222 DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC detection parameter.
223
224 [..]
225 (@) For Dual mode and specific signal (Sawtooth, triangle and noise) generation
226 please refer to Extended Features Driver description
227
228 ##### How to use this driver #####
229 ==============================================================================
230 [..]
231 (+) DAC APB clock must be enabled to get write access to DAC
232 registers using HAL_DAC_Init()
233 (+) If available & needed, configure DAC_OUTx (DAC_OUT1, DAC_OUT2) in analog mode.
234 (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
235 (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
236
237 *** Calibration mode IO operation ***
238 ======================================
239 [..]
240 (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
241 (+) Run the calibration using HAL_DACEx_SelfCalibrate()
242 (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()
243
244 *** Polling mode IO operation ***
245 =================================
246 [..]
247 (+) Start the DAC peripheral using HAL_DAC_Start()
248 (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
249 (+) Stop the DAC peripheral using HAL_DAC_Stop()
250
251 *** DMA mode IO operation ***
252 ==============================
253 [..]
254 (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
255 of data to be transferred at each end of conversion
256 First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue().
257 (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
258 function is executed and user can add his own code by customization of function pointer
259 HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
260 (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
261 function is executed and user can add his own code by customization of function pointer
262 HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
263 (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
264 add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
265 (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
266 HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
267 function is executed and user can add his own code by customization of function pointer
268 HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
269 add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
270 (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
271
272 *** Callback registration ***
273 =============================================
274 [..]
275 The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
276 allows the user to configure dynamically the driver callbacks.
277
278 Use Functions HAL_DAC_RegisterCallback() to register a user callback,
279 it allows to register following callbacks:
280 (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
281 (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
282 (+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
283 (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
284 (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
285 (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
286 (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
287 (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
288 (+) MspInitCallback : DAC MspInit.
289 (+) MspDeInitCallback : DAC MspdeInit.
290 This function takes as parameters the HAL peripheral handle, the Callback ID
291 and a pointer to the user callback function.
292
293 Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
294 weak (surcharged) function. It allows to reset following callbacks:
295 (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
296 (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
297 (+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
298 (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
299 (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
300 (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
301 (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
302 (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
303 (+) MspInitCallback : DAC MspInit.
304 (+) MspDeInitCallback : DAC MspdeInit.
305 (+) All Callbacks
306 This function) takes as parameters the HAL peripheral handle and the Callback ID.
307
308 By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
309 all callbacks are reset to the corresponding legacy weak (surcharged) functions.
310 Exception done for MspInit and MspDeInit callbacks that are respectively
311 reset to the legacy weak (surcharged) functions in the HAL_DAC_Init
312 and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
313 If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
314 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
315
316 Callbacks can be registered/unregistered in READY state only.
317 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
318 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
319 during the Init/DeInit.
320 In that case first register the MspInit/MspDeInit user callbacks
321 using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit
322 or HAL_DAC_Init function.
323
324 When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
325 not defined, the callback registering feature is not available
326 and weak (surcharged) callbacks are used.
327
328 *** DAC HAL driver macros list ***
329 =============================================
330 [..]
331 Below the list of most used macros in DAC HAL driver.
332
333 (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
334 (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
335 (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
336 (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
337
338 [..]
339 (@) You can refer to the DAC HAL driver header file for more useful macros
340
341 @endverbatim
342 ******************************************************************************
343 */
344
345 /* Includes ------------------------------------------------------------------*/
346 #include "stm32g4xx_hal.h"
347
348 /** @addtogroup STM32G4xx_HAL_Driver
349 * @{
350 */
351
352 #ifdef HAL_DAC_MODULE_ENABLED
353 #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
354
355 /** @defgroup DAC DAC
356 * @brief DAC driver modules
357 * @{
358 */
359
360 /* Private typedef -----------------------------------------------------------*/
361 /* Private define ------------------------------------------------------------*/
362 /* Private constants ---------------------------------------------------------*/
363 /** @addtogroup DAC_Private_Constants DAC Private Constants
364 * @{
365 */
366 #define TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */
367 #define HFSEL_ENABLE_THRESHOLD_80MHZ 80000000U /* 80 MHz */
368 #define HFSEL_ENABLE_THRESHOLD_160MHZ 160000000U /* 160 MHz */
369
370 /**
371 * @}
372 */
373
374 /* Private macro -------------------------------------------------------------*/
375 /* Private variables ---------------------------------------------------------*/
376 /* Private function prototypes -----------------------------------------------*/
377 /* Exported functions -------------------------------------------------------*/
378
379 /** @defgroup DAC_Exported_Functions DAC Exported Functions
380 * @{
381 */
382
383 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
384 * @brief Initialization and Configuration functions
385 *
386 @verbatim
387 ==============================================================================
388 ##### Initialization and de-initialization functions #####
389 ==============================================================================
390 [..] This section provides functions allowing to:
391 (+) Initialize and configure the DAC.
392 (+) De-initialize the DAC.
393
394 @endverbatim
395 * @{
396 */
397
398 /**
399 * @brief Initialize the DAC peripheral according to the specified parameters
400 * in the DAC_InitStruct and initialize the associated handle.
401 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
402 * the configuration information for the specified DAC.
403 * @retval HAL status
404 */
HAL_DAC_Init(DAC_HandleTypeDef * hdac)405 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
406 {
407 /* Check DAC handle */
408 if (hdac == NULL)
409 {
410 return HAL_ERROR;
411 }
412 /* Check the parameters */
413 assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
414
415 if (hdac->State == HAL_DAC_STATE_RESET)
416 {
417 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
418 /* Init the DAC Callback settings */
419 hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
420 hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
421 hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
422 hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
423
424 hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
425 hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
426 hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
427 hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
428
429 if (hdac->MspInitCallback == NULL)
430 {
431 hdac->MspInitCallback = HAL_DAC_MspInit;
432 }
433 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
434
435 /* Allocate lock resource and initialize it */
436 hdac->Lock = HAL_UNLOCKED;
437
438 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
439 /* Init the low level hardware */
440 hdac->MspInitCallback(hdac);
441 #else
442 /* Init the low level hardware */
443 HAL_DAC_MspInit(hdac);
444 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
445 }
446
447 /* Initialize the DAC state*/
448 hdac->State = HAL_DAC_STATE_BUSY;
449
450 /* Set DAC error code to none */
451 hdac->ErrorCode = HAL_DAC_ERROR_NONE;
452
453 /* Initialize the DAC state*/
454 hdac->State = HAL_DAC_STATE_READY;
455
456 /* Return function status */
457 return HAL_OK;
458 }
459
460 /**
461 * @brief Deinitialize the DAC peripheral registers to their default reset values.
462 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
463 * the configuration information for the specified DAC.
464 * @retval HAL status
465 */
HAL_DAC_DeInit(DAC_HandleTypeDef * hdac)466 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
467 {
468 /* Check DAC handle */
469 if (hdac == NULL)
470 {
471 return HAL_ERROR;
472 }
473
474 /* Check the parameters */
475 assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
476
477 /* Change DAC state */
478 hdac->State = HAL_DAC_STATE_BUSY;
479
480 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
481 if (hdac->MspDeInitCallback == NULL)
482 {
483 hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
484 }
485 /* DeInit the low level hardware */
486 hdac->MspDeInitCallback(hdac);
487 #else
488 /* DeInit the low level hardware */
489 HAL_DAC_MspDeInit(hdac);
490 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
491
492 /* Set DAC error code to none */
493 hdac->ErrorCode = HAL_DAC_ERROR_NONE;
494
495 /* Change DAC state */
496 hdac->State = HAL_DAC_STATE_RESET;
497
498 /* Release Lock */
499 __HAL_UNLOCK(hdac);
500
501 /* Return function status */
502 return HAL_OK;
503 }
504
505 /**
506 * @brief Initialize the DAC MSP.
507 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
508 * the configuration information for the specified DAC.
509 * @retval None
510 */
HAL_DAC_MspInit(DAC_HandleTypeDef * hdac)511 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac)
512 {
513 /* Prevent unused argument(s) compilation warning */
514 UNUSED(hdac);
515
516 /* NOTE : This function should not be modified, when the callback is needed,
517 the HAL_DAC_MspInit could be implemented in the user file
518 */
519 }
520
521 /**
522 * @brief DeInitialize the DAC MSP.
523 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
524 * the configuration information for the specified DAC.
525 * @retval None
526 */
HAL_DAC_MspDeInit(DAC_HandleTypeDef * hdac)527 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
528 {
529 /* Prevent unused argument(s) compilation warning */
530 UNUSED(hdac);
531
532 /* NOTE : This function should not be modified, when the callback is needed,
533 the HAL_DAC_MspDeInit could be implemented in the user file
534 */
535 }
536
537 /**
538 * @}
539 */
540
541 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions
542 * @brief IO operation functions
543 *
544 @verbatim
545 ==============================================================================
546 ##### IO operation functions #####
547 ==============================================================================
548 [..] This section provides functions allowing to:
549 (+) Start conversion.
550 (+) Stop conversion.
551 (+) Start conversion and enable DMA transfer.
552 (+) Stop conversion and disable DMA transfer.
553 (+) Get result of conversion.
554
555 @endverbatim
556 * @{
557 */
558
559 /**
560 * @brief Enables DAC and starts conversion of channel.
561 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
562 * the configuration information for the specified DAC.
563 * @param Channel The selected DAC channel.
564 * This parameter can be one of the following values:
565 * @arg DAC_CHANNEL_1: DAC Channel1 selected
566 * @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
567 *
568 * (1) On this STM32 series, parameter not available on all instances.
569 * Refer to device datasheet for channels availability.
570 * @retval HAL status
571 */
HAL_DAC_Start(DAC_HandleTypeDef * hdac,uint32_t Channel)572 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
573 {
574 /* Check the parameters */
575 assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
576
577 /* Process locked */
578 __HAL_LOCK(hdac);
579
580 /* Change DAC state */
581 hdac->State = HAL_DAC_STATE_BUSY;
582
583 /* Enable the Peripheral */
584 __HAL_DAC_ENABLE(hdac, Channel);
585 /* Ensure minimum wait before using peripheral after enabling it */
586 HAL_Delay(1);
587
588 if (Channel == DAC_CHANNEL_1)
589 {
590 /* Check if software trigger enabled */
591 if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
592 {
593 /* Enable the selected DAC software conversion */
594 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
595 }
596 }
597
598 else
599 {
600 /* Check if software trigger enabled */
601 if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
602 {
603 /* Enable the selected DAC software conversion*/
604 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
605 }
606 }
607
608
609 /* Change DAC state */
610 hdac->State = HAL_DAC_STATE_READY;
611
612 /* Process unlocked */
613 __HAL_UNLOCK(hdac);
614
615 /* Return function status */
616 return HAL_OK;
617 }
618
619 /**
620 * @brief Disables DAC and stop conversion of channel.
621 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
622 * the configuration information for the specified DAC.
623 * @param Channel The selected DAC channel.
624 * This parameter can be one of the following values:
625 * @arg DAC_CHANNEL_1: DAC Channel1 selected
626 * @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
627 *
628 * (1) On this STM32 series, parameter not available on all instances.
629 * Refer to device datasheet for channels availability.
630 * @retval HAL status
631 */
HAL_DAC_Stop(DAC_HandleTypeDef * hdac,uint32_t Channel)632 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
633 {
634 /* Check the parameters */
635 assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
636
637 /* Disable the Peripheral */
638 __HAL_DAC_DISABLE(hdac, Channel);
639 /* Ensure minimum wait before enabling peripheral after disabling it */
640 HAL_Delay(1);
641
642 /* Change DAC state */
643 hdac->State = HAL_DAC_STATE_READY;
644
645 /* Return function status */
646 return HAL_OK;
647 }
648
649 /**
650 * @brief Enables DAC and starts conversion of channel.
651 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
652 * the configuration information for the specified DAC.
653 * @param Channel The selected DAC channel.
654 * This parameter can be one of the following values:
655 * @arg DAC_CHANNEL_1: DAC Channel1 selected
656 * @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
657 *
658 * (1) On this STM32 series, parameter not available on all instances.
659 * Refer to device datasheet for channels availability.
660 * @param pData The source Buffer address.
661 * @param Length The length of data to be transferred from memory to DAC peripheral
662 * @param Alignment Specifies the data alignment for DAC channel.
663 * This parameter can be one of the following values:
664 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
665 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
666 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
667 * @retval HAL status
668 */
HAL_DAC_Start_DMA(DAC_HandleTypeDef * hdac,uint32_t Channel,uint32_t * pData,uint32_t Length,uint32_t Alignment)669 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
670 uint32_t Alignment)
671 {
672 HAL_StatusTypeDef status;
673 uint32_t tmpreg = 0U;
674
675 /* Check the parameters */
676 assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
677 assert_param(IS_DAC_ALIGN(Alignment));
678
679 /* Process locked */
680 __HAL_LOCK(hdac);
681
682 /* Change DAC state */
683 hdac->State = HAL_DAC_STATE_BUSY;
684
685 if (Channel == DAC_CHANNEL_1)
686 {
687 /* Set the DMA transfer complete callback for channel1 */
688 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
689
690 /* Set the DMA half transfer complete callback for channel1 */
691 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
692
693 /* Set the DMA error callback for channel1 */
694 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
695
696 /* Enable the selected DAC channel1 DMA request */
697 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
698
699 /* Case of use of channel 1 */
700 switch (Alignment)
701 {
702 case DAC_ALIGN_12B_R:
703 /* Get DHR12R1 address */
704 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
705 break;
706 case DAC_ALIGN_12B_L:
707 /* Get DHR12L1 address */
708 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
709 break;
710 case DAC_ALIGN_8B_R:
711 /* Get DHR8R1 address */
712 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
713 break;
714 default:
715 break;
716 }
717 }
718
719 else
720 {
721 /* Set the DMA transfer complete callback for channel2 */
722 hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
723
724 /* Set the DMA half transfer complete callback for channel2 */
725 hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
726
727 /* Set the DMA error callback for channel2 */
728 hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
729
730 /* Enable the selected DAC channel2 DMA request */
731 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
732
733 /* Case of use of channel 2 */
734 switch (Alignment)
735 {
736 case DAC_ALIGN_12B_R:
737 /* Get DHR12R2 address */
738 tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
739 break;
740 case DAC_ALIGN_12B_L:
741 /* Get DHR12L2 address */
742 tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
743 break;
744 case DAC_ALIGN_8B_R:
745 /* Get DHR8R2 address */
746 tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
747 break;
748 default:
749 break;
750 }
751 }
752
753
754 /* Enable the DMA channel */
755 if (Channel == DAC_CHANNEL_1)
756 {
757 /* Enable the DAC DMA underrun interrupt */
758 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
759
760 /* Enable the DMA channel */
761 status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
762 }
763
764 else
765 {
766 /* Enable the DAC DMA underrun interrupt */
767 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
768
769 /* Enable the DMA channel */
770 status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
771 }
772
773
774 /* Process Unlocked */
775 __HAL_UNLOCK(hdac);
776
777 if (status == HAL_OK)
778 {
779 /* Enable the Peripheral */
780 __HAL_DAC_ENABLE(hdac, Channel);
781 /* Ensure minimum wait before using peripheral after enabling it */
782 HAL_Delay(1);
783 }
784 else
785 {
786 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
787 }
788
789 /* Return function status */
790 return status;
791 }
792
793 /**
794 * @brief Disables DAC and stop conversion of channel.
795 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
796 * the configuration information for the specified DAC.
797 * @param Channel The selected DAC channel.
798 * This parameter can be one of the following values:
799 * @arg DAC_CHANNEL_1: DAC Channel1 selected
800 * @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
801 *
802 * (1) On this STM32 series, parameter not available on all instances.
803 * Refer to device datasheet for channels availability.
804 * @retval HAL status
805 */
HAL_DAC_Stop_DMA(DAC_HandleTypeDef * hdac,uint32_t Channel)806 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
807 {
808 /* Check the parameters */
809 assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
810
811 /* Disable the selected DAC channel DMA request */
812 hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL));
813
814 /* Disable the Peripheral */
815 __HAL_DAC_DISABLE(hdac, Channel);
816 /* Ensure minimum wait before enabling peripheral after disabling it */
817 HAL_Delay(1);
818
819 /* Disable the DMA channel */
820
821 /* Channel1 is used */
822 if (Channel == DAC_CHANNEL_1)
823 {
824 /* Disable the DMA channel */
825 (void)HAL_DMA_Abort(hdac->DMA_Handle1);
826
827 /* Disable the DAC DMA underrun interrupt */
828 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
829 }
830
831 else /* Channel2 is used for */
832 {
833 /* Disable the DMA channel */
834 (void)HAL_DMA_Abort(hdac->DMA_Handle2);
835
836 /* Disable the DAC DMA underrun interrupt */
837 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
838 }
839
840
841 /* Change DAC state */
842 hdac->State = HAL_DAC_STATE_READY;
843
844 /* Return function status */
845 return HAL_OK;
846 }
847
848 /**
849 * @brief Handles DAC interrupt request
850 * This function uses the interruption of DMA
851 * underrun.
852 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
853 * the configuration information for the specified DAC.
854 * @retval None
855 */
HAL_DAC_IRQHandler(DAC_HandleTypeDef * hdac)856 void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
857 {
858 if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
859 {
860 /* Check underrun flag of DAC channel 1 */
861 if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
862 {
863 /* Change DAC state to error state */
864 hdac->State = HAL_DAC_STATE_ERROR;
865
866 /* Set DAC error code to channel1 DMA underrun error */
867 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
868
869 /* Clear the underrun flag */
870 __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
871
872 /* Disable the selected DAC channel1 DMA request */
873 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
874
875 /* Error callback */
876 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
877 hdac->DMAUnderrunCallbackCh1(hdac);
878 #else
879 HAL_DAC_DMAUnderrunCallbackCh1(hdac);
880 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
881 }
882 }
883
884
885 if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
886 {
887 /* Check underrun flag of DAC channel 2 */
888 if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
889 {
890 /* Change DAC state to error state */
891 hdac->State = HAL_DAC_STATE_ERROR;
892
893 /* Set DAC error code to channel2 DMA underrun error */
894 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
895
896 /* Clear the underrun flag */
897 __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
898
899 /* Disable the selected DAC channel2 DMA request */
900 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
901
902 /* Error callback */
903 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
904 hdac->DMAUnderrunCallbackCh2(hdac);
905 #else
906 HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
907 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
908 }
909 }
910
911 }
912
913 /**
914 * @brief Set the specified data holding register value for DAC channel.
915 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
916 * the configuration information for the specified DAC.
917 * @param Channel The selected DAC channel.
918 * This parameter can be one of the following values:
919 * @arg DAC_CHANNEL_1: DAC Channel1 selected
920 * @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
921 *
922 * (1) On this STM32 series, parameter not available on all instances.
923 * Refer to device datasheet for channels availability.
924 * @param Alignment Specifies the data alignment.
925 * This parameter can be one of the following values:
926 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
927 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
928 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
929 * @param Data Data to be loaded in the selected data holding register.
930 * @retval HAL status
931 */
HAL_DAC_SetValue(DAC_HandleTypeDef * hdac,uint32_t Channel,uint32_t Alignment,uint32_t Data)932 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
933 {
934 __IO uint32_t tmp = 0UL;
935
936 /* Check the parameters */
937 assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
938 assert_param(IS_DAC_ALIGN(Alignment));
939 /* In case DMA Double data mode is activated, DATA range is almost full uin32_t one: no check */
940 if ((hdac->Instance->MCR & (DAC_MCR_DMADOUBLE1 << (Channel & 0x10UL))) == 0UL)
941 {
942 assert_param(IS_DAC_DATA(Data));
943 }
944
945 tmp = (uint32_t)hdac->Instance;
946 if (Channel == DAC_CHANNEL_1)
947 {
948 tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
949 }
950
951 else
952 {
953 tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
954 }
955
956
957 /* Set the DAC channel selected data holding register */
958 *(__IO uint32_t *) tmp = Data;
959
960 /* Return function status */
961 return HAL_OK;
962 }
963
964 /**
965 * @brief Conversion complete callback in non-blocking mode for Channel1
966 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
967 * the configuration information for the specified DAC.
968 * @retval None
969 */
HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef * hdac)970 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac)
971 {
972 /* Prevent unused argument(s) compilation warning */
973 UNUSED(hdac);
974
975 /* NOTE : This function should not be modified, when the callback is needed,
976 the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
977 */
978 }
979
980 /**
981 * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1
982 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
983 * the configuration information for the specified DAC.
984 * @retval None
985 */
HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef * hdac)986 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac)
987 {
988 /* Prevent unused argument(s) compilation warning */
989 UNUSED(hdac);
990
991 /* NOTE : This function should not be modified, when the callback is needed,
992 the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
993 */
994 }
995
996 /**
997 * @brief Error DAC callback for Channel1.
998 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
999 * the configuration information for the specified DAC.
1000 * @retval None
1001 */
HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef * hdac)1002 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
1003 {
1004 /* Prevent unused argument(s) compilation warning */
1005 UNUSED(hdac);
1006
1007 /* NOTE : This function should not be modified, when the callback is needed,
1008 the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
1009 */
1010 }
1011
1012 /**
1013 * @brief DMA underrun DAC callback for channel1.
1014 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1015 * the configuration information for the specified DAC.
1016 * @retval None
1017 */
HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef * hdac)1018 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
1019 {
1020 /* Prevent unused argument(s) compilation warning */
1021 UNUSED(hdac);
1022
1023 /* NOTE : This function should not be modified, when the callback is needed,
1024 the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
1025 */
1026 }
1027
1028 /**
1029 * @}
1030 */
1031
1032 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
1033 * @brief Peripheral Control functions
1034 *
1035 @verbatim
1036 ==============================================================================
1037 ##### Peripheral Control functions #####
1038 ==============================================================================
1039 [..] This section provides functions allowing to:
1040 (+) Configure channels.
1041 (+) Set the specified data holding register value for DAC channel.
1042
1043 @endverbatim
1044 * @{
1045 */
1046
1047 /**
1048 * @brief Returns the last data output value of the selected DAC channel.
1049 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1050 * the configuration information for the specified DAC.
1051 * @param Channel The selected DAC channel.
1052 * This parameter can be one of the following values:
1053 * @arg DAC_CHANNEL_1: DAC Channel1 selected
1054 * @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
1055 *
1056 * (1) On this STM32 series, parameter not available on all instances.
1057 * Refer to device datasheet for channels availability.
1058 * @retval The selected DAC channel data output value.
1059 */
HAL_DAC_GetValue(DAC_HandleTypeDef * hdac,uint32_t Channel)1060 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
1061 {
1062 uint32_t result;
1063
1064 /* Check the parameters */
1065 assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
1066
1067 if (Channel == DAC_CHANNEL_1)
1068 {
1069 result = hdac->Instance->DOR1;
1070 }
1071
1072 else
1073 {
1074 result = hdac->Instance->DOR2;
1075 }
1076
1077 /* Returns the DAC channel data output register value */
1078 return result;
1079 }
1080
1081 /**
1082 * @brief Configures the selected DAC channel.
1083 * @note By calling this function, the high frequency interface mode (HFSEL bits)
1084 * will be set. This parameter scope is the DAC instance. As the function
1085 * is called for each channel, the @ref DAC_HighFrequency of @arg sConfig
1086 * must be the same at each call.
1087 * (or DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC self detect).
1088 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1089 * the configuration information for the specified DAC.
1090 * @param sConfig DAC configuration structure.
1091 * @param Channel The selected DAC channel.
1092 * This parameter can be one of the following values:
1093 * @arg DAC_CHANNEL_1: DAC Channel1 selected
1094 * @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
1095 *
1096 * (1) On this STM32 series, parameter not available on all instances.
1097 * Refer to device datasheet for channels availability.
1098 * @retval HAL status
1099 */
HAL_DAC_ConfigChannel(DAC_HandleTypeDef * hdac,DAC_ChannelConfTypeDef * sConfig,uint32_t Channel)1100 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
1101 {
1102 uint32_t tmpreg1;
1103 uint32_t tmpreg2;
1104 uint32_t tickstart;
1105 uint32_t hclkfreq;
1106 uint32_t connectOnChip;
1107
1108 /* Check the DAC parameters */
1109 assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency));
1110 assert_param(IS_DAC_TRIGGER(hdac->Instance, sConfig->DAC_Trigger));
1111 assert_param(IS_DAC_TRIGGER(hdac->Instance, sConfig->DAC_Trigger2));
1112 assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
1113 assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
1114 assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming));
1115 if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
1116 {
1117 assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));
1118 }
1119 assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
1120 if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
1121 {
1122 assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime));
1123 assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime));
1124 assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime));
1125 }
1126 assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
1127 assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode));
1128 assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat));
1129
1130 /* Process locked */
1131 __HAL_LOCK(hdac);
1132
1133 /* Change DAC state */
1134 hdac->State = HAL_DAC_STATE_BUSY;
1135
1136 /* Sample and hold configuration */
1137 if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
1138 {
1139 /* Get timeout */
1140 tickstart = HAL_GetTick();
1141
1142 if (Channel == DAC_CHANNEL_1)
1143 {
1144 /* SHSR1 can be written when BWST1 is cleared */
1145 while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
1146 {
1147 /* Check for the Timeout */
1148 if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
1149 {
1150 /* Update error code */
1151 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
1152
1153 /* Change the DMA state */
1154 hdac->State = HAL_DAC_STATE_TIMEOUT;
1155
1156 return HAL_TIMEOUT;
1157 }
1158 }
1159 HAL_Delay(1);
1160 hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
1161 }
1162
1163 else /* Channel 2 */
1164 {
1165 /* SHSR2 can be written when BWST2 is cleared */
1166 while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
1167 {
1168 /* Check for the Timeout */
1169 if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
1170 {
1171 /* Update error code */
1172 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
1173
1174 /* Change the DMA state */
1175 hdac->State = HAL_DAC_STATE_TIMEOUT;
1176
1177 return HAL_TIMEOUT;
1178 }
1179 }
1180 HAL_Delay(1U);
1181 hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
1182 }
1183
1184
1185 /* HoldTime */
1186 MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
1187 (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
1188 /* RefreshTime */
1189 MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL),
1190 (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
1191 }
1192
1193 if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
1194 /* USER TRIMMING */
1195 {
1196 /* Get the DAC CCR value */
1197 tmpreg1 = hdac->Instance->CCR;
1198 /* Clear trimming value */
1199 tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL));
1200 /* Configure for the selected trimming offset */
1201 tmpreg2 = sConfig->DAC_TrimmingValue;
1202 /* Calculate CCR register value depending on DAC_Channel */
1203 tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
1204 /* Write to DAC CCR */
1205 hdac->Instance->CCR = tmpreg1;
1206 }
1207 /* else factory trimming is used (factory setting are available at reset)*/
1208 /* SW Nothing has nothing to do */
1209
1210 /* Get the DAC MCR value */
1211 tmpreg1 = hdac->Instance->MCR;
1212 /* Clear DAC_MCR_MODEx bits */
1213 tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
1214 /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
1215 if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
1216 {
1217 connectOnChip = 0x00000000UL;
1218 }
1219 else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL)
1220 {
1221 connectOnChip = DAC_MCR_MODE1_0;
1222 }
1223 else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */
1224 {
1225 if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE)
1226 {
1227 connectOnChip = DAC_MCR_MODE1_0;
1228 }
1229 else
1230 {
1231 connectOnChip = 0x00000000UL;
1232 }
1233 }
1234 tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip);
1235 /* Clear DAC_MCR_DMADOUBLEx */
1236 tmpreg1 &= ~(((uint32_t)(DAC_MCR_DMADOUBLE1)) << (Channel & 0x10UL));
1237 /* Configure for the selected DAC channel: DMA double data mode */
1238 tmpreg2 |= (sConfig->DAC_DMADoubleDataMode == ENABLE) ? DAC_MCR_DMADOUBLE1 : 0UL;
1239 /* Clear DAC_MCR_SINFORMATx */
1240 tmpreg1 &= ~(((uint32_t)(DAC_MCR_SINFORMAT1)) << (Channel & 0x10UL));
1241 /* Configure for the selected DAC channel: Signed format */
1242 tmpreg2 |= (sConfig->DAC_SignedFormat == ENABLE) ? DAC_MCR_SINFORMAT1 : 0UL;
1243 /* Clear DAC_MCR_HFSEL bits */
1244 tmpreg1 &= ~(DAC_MCR_HFSEL);
1245 /* Configure for both DAC channels: high frequency mode */
1246 if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC == sConfig->DAC_HighFrequency)
1247 {
1248 hclkfreq = HAL_RCC_GetHCLKFreq();
1249 if (hclkfreq > HFSEL_ENABLE_THRESHOLD_160MHZ)
1250 {
1251 tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ;
1252 }
1253 else if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ)
1254 {
1255 tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ;
1256 }
1257 else
1258 {
1259 tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE;
1260 }
1261 }
1262 else
1263 {
1264 tmpreg1 |= sConfig->DAC_HighFrequency;
1265 }
1266 /* Calculate MCR register value depending on DAC_Channel */
1267 tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
1268 /* Write to DAC MCR */
1269 hdac->Instance->MCR = tmpreg1;
1270
1271 /* DAC in normal operating mode hence clear DAC_CR_CENx bit */
1272 CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL));
1273
1274 /* Get the DAC CR value */
1275 tmpreg1 = hdac->Instance->CR;
1276 /* Clear TENx, TSELx, WAVEx and MAMPx bits */
1277 tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL));
1278 /* Configure for the selected DAC channel: trigger */
1279 /* Set TSELx and TENx bits according to DAC_Trigger value */
1280 tmpreg2 = sConfig->DAC_Trigger;
1281 /* Calculate CR register value depending on DAC_Channel */
1282 tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
1283 /* Write to DAC CR */
1284 hdac->Instance->CR = tmpreg1;
1285 /* Disable wave generation */
1286 CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
1287
1288 /* Set STRSTTRIGSELx and STINCTRIGSELx bits according to DAC_Trigger & DAC_Trigger2 values */
1289 tmpreg2 = ((sConfig->DAC_Trigger & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos;
1290 tmpreg2 |= ((sConfig->DAC_Trigger2 & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos;
1291 /* Modify STMODR register value depending on DAC_Channel */
1292 MODIFY_REG(hdac->Instance->STMODR, (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1) << (Channel & 0x10UL), tmpreg2 << (Channel & 0x10UL));
1293 /* Change DAC state */
1294 hdac->State = HAL_DAC_STATE_READY;
1295
1296 /* Process unlocked */
1297 __HAL_UNLOCK(hdac);
1298
1299 /* Return function status */
1300 return HAL_OK;
1301 }
1302
1303 /**
1304 * @}
1305 */
1306
1307 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
1308 * @brief Peripheral State and Errors functions
1309 *
1310 @verbatim
1311 ==============================================================================
1312 ##### Peripheral State and Errors functions #####
1313 ==============================================================================
1314 [..]
1315 This subsection provides functions allowing to
1316 (+) Check the DAC state.
1317 (+) Check the DAC Errors.
1318
1319 @endverbatim
1320 * @{
1321 */
1322
1323 /**
1324 * @brief return the DAC handle state
1325 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1326 * the configuration information for the specified DAC.
1327 * @retval HAL state
1328 */
HAL_DAC_GetState(DAC_HandleTypeDef * hdac)1329 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
1330 {
1331 /* Return DAC handle state */
1332 return hdac->State;
1333 }
1334
1335
1336 /**
1337 * @brief Return the DAC error code
1338 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1339 * the configuration information for the specified DAC.
1340 * @retval DAC Error Code
1341 */
HAL_DAC_GetError(DAC_HandleTypeDef * hdac)1342 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
1343 {
1344 return hdac->ErrorCode;
1345 }
1346
1347 /**
1348 * @}
1349 */
1350
1351 /**
1352 * @}
1353 */
1354
1355 /** @addtogroup DAC_Exported_Functions
1356 * @{
1357 */
1358
1359 /** @addtogroup DAC_Exported_Functions_Group1
1360 * @{
1361 */
1362 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1363 /**
1364 * @brief Register a User DAC Callback
1365 * To be used instead of the weak (surcharged) predefined callback
1366 * @param hdac DAC handle
1367 * @param CallbackID ID of the callback to be registered
1368 * This parameter can be one of the following values:
1369 * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID
1370 * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID
1371 * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
1372 * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
1373 * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
1374 * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
1375 * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
1376 * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
1377 * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
1378 * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
1379 * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
1380 *
1381 * @param pCallback pointer to the Callback function
1382 * @retval status
1383 */
HAL_DAC_RegisterCallback(DAC_HandleTypeDef * hdac,HAL_DAC_CallbackIDTypeDef CallbackID,pDAC_CallbackTypeDef pCallback)1384 HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
1385 pDAC_CallbackTypeDef pCallback)
1386 {
1387 HAL_StatusTypeDef status = HAL_OK;
1388
1389 if (pCallback == NULL)
1390 {
1391 /* Update the error code */
1392 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1393 return HAL_ERROR;
1394 }
1395
1396 /* Process locked */
1397 __HAL_LOCK(hdac);
1398
1399 if (hdac->State == HAL_DAC_STATE_READY)
1400 {
1401 switch (CallbackID)
1402 {
1403 case HAL_DAC_CH1_COMPLETE_CB_ID :
1404 hdac->ConvCpltCallbackCh1 = pCallback;
1405 break;
1406 case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
1407 hdac->ConvHalfCpltCallbackCh1 = pCallback;
1408 break;
1409 case HAL_DAC_CH1_ERROR_ID :
1410 hdac->ErrorCallbackCh1 = pCallback;
1411 break;
1412 case HAL_DAC_CH1_UNDERRUN_CB_ID :
1413 hdac->DMAUnderrunCallbackCh1 = pCallback;
1414 break;
1415
1416 case HAL_DAC_CH2_COMPLETE_CB_ID :
1417 hdac->ConvCpltCallbackCh2 = pCallback;
1418 break;
1419 case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
1420 hdac->ConvHalfCpltCallbackCh2 = pCallback;
1421 break;
1422 case HAL_DAC_CH2_ERROR_ID :
1423 hdac->ErrorCallbackCh2 = pCallback;
1424 break;
1425 case HAL_DAC_CH2_UNDERRUN_CB_ID :
1426 hdac->DMAUnderrunCallbackCh2 = pCallback;
1427 break;
1428
1429 case HAL_DAC_MSPINIT_CB_ID :
1430 hdac->MspInitCallback = pCallback;
1431 break;
1432 case HAL_DAC_MSPDEINIT_CB_ID :
1433 hdac->MspDeInitCallback = pCallback;
1434 break;
1435 default :
1436 /* Update the error code */
1437 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1438 /* update return status */
1439 status = HAL_ERROR;
1440 break;
1441 }
1442 }
1443 else if (hdac->State == HAL_DAC_STATE_RESET)
1444 {
1445 switch (CallbackID)
1446 {
1447 case HAL_DAC_MSPINIT_CB_ID :
1448 hdac->MspInitCallback = pCallback;
1449 break;
1450 case HAL_DAC_MSPDEINIT_CB_ID :
1451 hdac->MspDeInitCallback = pCallback;
1452 break;
1453 default :
1454 /* Update the error code */
1455 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1456 /* update return status */
1457 status = HAL_ERROR;
1458 break;
1459 }
1460 }
1461 else
1462 {
1463 /* Update the error code */
1464 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1465 /* update return status */
1466 status = HAL_ERROR;
1467 }
1468
1469 /* Release Lock */
1470 __HAL_UNLOCK(hdac);
1471 return status;
1472 }
1473
1474 /**
1475 * @brief Unregister a User DAC Callback
1476 * DAC Callback is redirected to the weak (surcharged) predefined callback
1477 * @param hdac DAC handle
1478 * @param CallbackID ID of the callback to be unregistered
1479 * This parameter can be one of the following values:
1480 * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID
1481 * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
1482 * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
1483 * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
1484 * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
1485 * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
1486 * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
1487 * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
1488 * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
1489 * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
1490 * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks
1491 * @retval status
1492 */
HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef * hdac,HAL_DAC_CallbackIDTypeDef CallbackID)1493 HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
1494 {
1495 HAL_StatusTypeDef status = HAL_OK;
1496
1497 /* Process locked */
1498 __HAL_LOCK(hdac);
1499
1500 if (hdac->State == HAL_DAC_STATE_READY)
1501 {
1502 switch (CallbackID)
1503 {
1504 case HAL_DAC_CH1_COMPLETE_CB_ID :
1505 hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
1506 break;
1507 case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
1508 hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
1509 break;
1510 case HAL_DAC_CH1_ERROR_ID :
1511 hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
1512 break;
1513 case HAL_DAC_CH1_UNDERRUN_CB_ID :
1514 hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
1515 break;
1516
1517 case HAL_DAC_CH2_COMPLETE_CB_ID :
1518 hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
1519 break;
1520 case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
1521 hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
1522 break;
1523 case HAL_DAC_CH2_ERROR_ID :
1524 hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
1525 break;
1526 case HAL_DAC_CH2_UNDERRUN_CB_ID :
1527 hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
1528 break;
1529
1530 case HAL_DAC_MSPINIT_CB_ID :
1531 hdac->MspInitCallback = HAL_DAC_MspInit;
1532 break;
1533 case HAL_DAC_MSPDEINIT_CB_ID :
1534 hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
1535 break;
1536 case HAL_DAC_ALL_CB_ID :
1537 hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
1538 hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
1539 hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
1540 hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
1541
1542 hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
1543 hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
1544 hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
1545 hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
1546
1547 hdac->MspInitCallback = HAL_DAC_MspInit;
1548 hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
1549 break;
1550 default :
1551 /* Update the error code */
1552 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1553 /* update return status */
1554 status = HAL_ERROR;
1555 break;
1556 }
1557 }
1558 else if (hdac->State == HAL_DAC_STATE_RESET)
1559 {
1560 switch (CallbackID)
1561 {
1562 case HAL_DAC_MSPINIT_CB_ID :
1563 hdac->MspInitCallback = HAL_DAC_MspInit;
1564 break;
1565 case HAL_DAC_MSPDEINIT_CB_ID :
1566 hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
1567 break;
1568 default :
1569 /* Update the error code */
1570 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1571 /* update return status */
1572 status = HAL_ERROR;
1573 break;
1574 }
1575 }
1576 else
1577 {
1578 /* Update the error code */
1579 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1580 /* update return status */
1581 status = HAL_ERROR;
1582 }
1583
1584 /* Release Lock */
1585 __HAL_UNLOCK(hdac);
1586 return status;
1587 }
1588 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1589
1590 /**
1591 * @}
1592 */
1593
1594 /**
1595 * @}
1596 */
1597
1598 /** @addtogroup DAC_Private_Functions
1599 * @{
1600 */
1601
1602 /**
1603 * @brief DMA conversion complete callback.
1604 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1605 * the configuration information for the specified DMA module.
1606 * @retval None
1607 */
DAC_DMAConvCpltCh1(DMA_HandleTypeDef * hdma)1608 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
1609 {
1610 DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1611
1612 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1613 hdac->ConvCpltCallbackCh1(hdac);
1614 #else
1615 HAL_DAC_ConvCpltCallbackCh1(hdac);
1616 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1617
1618 hdac->State = HAL_DAC_STATE_READY;
1619 }
1620
1621 /**
1622 * @brief DMA half transfer complete callback.
1623 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1624 * the configuration information for the specified DMA module.
1625 * @retval None
1626 */
DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef * hdma)1627 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
1628 {
1629 DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1630 /* Conversion complete callback */
1631 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1632 hdac->ConvHalfCpltCallbackCh1(hdac);
1633 #else
1634 HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
1635 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1636 }
1637
1638 /**
1639 * @brief DMA error callback
1640 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1641 * the configuration information for the specified DMA module.
1642 * @retval None
1643 */
DAC_DMAErrorCh1(DMA_HandleTypeDef * hdma)1644 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
1645 {
1646 DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1647
1648 /* Set DAC error code to DMA error */
1649 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
1650
1651 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1652 hdac->ErrorCallbackCh1(hdac);
1653 #else
1654 HAL_DAC_ErrorCallbackCh1(hdac);
1655 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1656
1657 hdac->State = HAL_DAC_STATE_READY;
1658 }
1659
1660 /**
1661 * @}
1662 */
1663
1664 /**
1665 * @}
1666 */
1667
1668 #endif /* DAC1 || DAC2 || DAC3 || DAC4 */
1669
1670 #endif /* HAL_DAC_MODULE_ENABLED */
1671
1672 /**
1673 * @}
1674 */
1675
1676
