1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_adc_ex.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Converter (ADC)
7 * peripheral:
8 * + Peripheral Control functions
9 * Other functions (generic functions) are available in file
10 * "stm32g4xx_hal_adc.c".
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2019 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 [..]
25 (@) Sections "ADC peripheral features" and "How to use this driver" are
26 available in file of generic functions "stm32g4xx_hal_adc.c".
27 [..]
28 @endverbatim
29 ******************************************************************************
30 */
31
32 /* Includes ------------------------------------------------------------------*/
33 #include "stm32g4xx_hal.h"
34
35 /** @addtogroup STM32G4xx_HAL_Driver
36 * @{
37 */
38
39 /** @defgroup ADCEx ADCEx
40 * @brief ADC Extended HAL module driver
41 * @{
42 */
43
44 #ifdef HAL_ADC_MODULE_ENABLED
45
46 /* Private typedef -----------------------------------------------------------*/
47 /* Private define ------------------------------------------------------------*/
48
49 /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
50 * @{
51 */
52
53 #define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
54 ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
55 ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */
56
57 /* Fixed timeout value for ADC calibration. */
58 /* Values defined to be higher than worst cases: low clock frequency, */
59 /* maximum prescalers. */
60 /* Ex of profile low frequency : f_ADC at f_CPU/3968 (minimum value */
61 /* considering both possible ADC clocking scheme: */
62 /* - ADC clock from synchronous clock with AHB prescaler 512, */
63 /* ADC prescaler 4. */
64 /* Ratio max = 512 *4 = 2048 */
65 /* - ADC clock from asynchronous clock (PLLP) with prescaler 256. */
66 /* Highest CPU clock PLL (PLLR). */
67 /* Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256 */
68 /* = 3968 ) */
69 /* Calibration_time MAX = 81 / f_ADC */
70 /* = 81 / (f_CPU/3938) = 318978 CPU cycles */
71 #define ADC_CALIBRATION_TIMEOUT (318978UL) /*!< ADC calibration time-out value (unit: CPU cycles) */
72
73 /**
74 * @}
75 */
76
77 /* Private macro -------------------------------------------------------------*/
78 /* Private variables ---------------------------------------------------------*/
79 /* Private function prototypes -----------------------------------------------*/
80 /* Exported functions --------------------------------------------------------*/
81
82 /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
83 * @{
84 */
85
86 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
87 * @brief Extended IO operation functions
88 *
89 @verbatim
90 ===============================================================================
91 ##### IO operation functions #####
92 ===============================================================================
93 [..] This section provides functions allowing to:
94
95 (+) Perform the ADC self-calibration for single or differential ending.
96 (+) Get calibration factors for single or differential ending.
97 (+) Set calibration factors for single or differential ending.
98
99 (+) Start conversion of ADC group injected.
100 (+) Stop conversion of ADC group injected.
101 (+) Poll for conversion complete on ADC group injected.
102 (+) Get result of ADC group injected channel conversion.
103 (+) Start conversion of ADC group injected and enable interruptions.
104 (+) Stop conversion of ADC group injected and disable interruptions.
105
106 (+) When multimode feature is available, start multimode and enable DMA transfer.
107 (+) Stop multimode and disable ADC DMA transfer.
108 (+) Get result of multimode conversion.
109
110 @endverbatim
111 * @{
112 */
113
114 /**
115 * @brief Perform an ADC automatic self-calibration
116 * Calibration prerequisite: ADC must be disabled (execute this
117 * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
118 * @param hadc ADC handle
119 * @param SingleDiff Selection of single-ended or differential input
120 * This parameter can be one of the following values:
121 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
122 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
123 * @retval HAL status
124 */
HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef * hadc,uint32_t SingleDiff)125 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
126 {
127 HAL_StatusTypeDef tmp_hal_status;
128 __IO uint32_t wait_loop_index = 0UL;
129
130 /* Check the parameters */
131 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
132 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
133
134 /* Process locked */
135 __HAL_LOCK(hadc);
136
137 /* Calibration prerequisite: ADC must be disabled. */
138
139 /* Disable the ADC (if not already disabled) */
140 tmp_hal_status = ADC_Disable(hadc);
141
142 /* Check if ADC is effectively disabled */
143 if (tmp_hal_status == HAL_OK)
144 {
145 /* Set ADC state */
146 ADC_STATE_CLR_SET(hadc->State,
147 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
148 HAL_ADC_STATE_BUSY_INTERNAL);
149
150 /* Start ADC calibration in mode single-ended or differential */
151 LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
152
153 /* Wait for calibration completion */
154 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
155 {
156 wait_loop_index++;
157 if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
158 {
159 /* Update ADC state machine to error */
160 ADC_STATE_CLR_SET(hadc->State,
161 HAL_ADC_STATE_BUSY_INTERNAL,
162 HAL_ADC_STATE_ERROR_INTERNAL);
163
164 /* Process unlocked */
165 __HAL_UNLOCK(hadc);
166
167 return HAL_ERROR;
168 }
169 }
170
171 /* Set ADC state */
172 ADC_STATE_CLR_SET(hadc->State,
173 HAL_ADC_STATE_BUSY_INTERNAL,
174 HAL_ADC_STATE_READY);
175 }
176 else
177 {
178 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
179
180 /* Note: No need to update variable "tmp_hal_status" here: already set */
181 /* to state "HAL_ERROR" by function disabling the ADC. */
182 }
183
184 /* Process unlocked */
185 __HAL_UNLOCK(hadc);
186
187 /* Return function status */
188 return tmp_hal_status;
189 }
190
191 /**
192 * @brief Get the calibration factor.
193 * @param hadc ADC handle.
194 * @param SingleDiff This parameter can be only:
195 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
196 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
197 * @retval Calibration value.
198 */
HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef * hadc,uint32_t SingleDiff)199 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
200 {
201 /* Check the parameters */
202 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
203 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
204
205 /* Return the selected ADC calibration value */
206 return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff);
207 }
208
209 /**
210 * @brief Set the calibration factor to overwrite automatic conversion result.
211 * ADC must be enabled and no conversion is ongoing.
212 * @param hadc ADC handle
213 * @param SingleDiff This parameter can be only:
214 * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
215 * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
216 * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
217 * @retval HAL state
218 */
HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef * hadc,uint32_t SingleDiff,uint32_t CalibrationFactor)219 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
220 uint32_t CalibrationFactor)
221 {
222 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
223 uint32_t tmp_adc_is_conversion_on_going_regular;
224 uint32_t tmp_adc_is_conversion_on_going_injected;
225
226 /* Check the parameters */
227 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
228 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
229 assert_param(IS_ADC_CALFACT(CalibrationFactor));
230
231 /* Process locked */
232 __HAL_LOCK(hadc);
233
234 /* Verification of hardware constraints before modifying the calibration */
235 /* factors register: ADC must be enabled, no conversion on going. */
236 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
237 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
238
239 if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
240 && (tmp_adc_is_conversion_on_going_regular == 0UL)
241 && (tmp_adc_is_conversion_on_going_injected == 0UL)
242 )
243 {
244 /* Set the selected ADC calibration value */
245 LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor);
246 }
247 else
248 {
249 /* Update ADC state machine */
250 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
251 /* Update ADC error code */
252 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
253
254 /* Update ADC state machine to error */
255 tmp_hal_status = HAL_ERROR;
256 }
257
258 /* Process unlocked */
259 __HAL_UNLOCK(hadc);
260
261 /* Return function status */
262 return tmp_hal_status;
263 }
264
265 /**
266 * @brief Enable ADC, start conversion of injected group.
267 * @note Interruptions enabled in this function: None.
268 * @note Case of multimode enabled when multimode feature is available:
269 * HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
270 * then for ADC master.
271 * For ADC slave, ADC is enabled only (conversion is not started).
272 * For ADC master, ADC is enabled and multimode conversion is started.
273 * @param hadc ADC handle.
274 * @retval HAL status
275 */
HAL_ADCEx_InjectedStart(ADC_HandleTypeDef * hadc)276 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
277 {
278 HAL_StatusTypeDef tmp_hal_status;
279 uint32_t tmp_config_injected_queue;
280 #if defined(ADC_MULTIMODE_SUPPORT)
281 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
282 #endif
283
284 /* Check the parameters */
285 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
286
287 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
288 {
289 return HAL_BUSY;
290 }
291 else
292 {
293 /* In case of software trigger detection enabled, JQDIS must be set
294 (which can be done only if ADSTART and JADSTART are both cleared).
295 If JQDIS is not set at that point, returns an error
296 - since software trigger detection is disabled. User needs to
297 resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
298 - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
299 the queue is empty */
300 tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
301
302 if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
303 && (tmp_config_injected_queue == 0UL)
304 )
305 {
306 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
307 return HAL_ERROR;
308 }
309
310 /* Process locked */
311 __HAL_LOCK(hadc);
312
313 /* Enable the ADC peripheral */
314 tmp_hal_status = ADC_Enable(hadc);
315
316 /* Start conversion if ADC is effectively enabled */
317 if (tmp_hal_status == HAL_OK)
318 {
319 /* Check if a regular conversion is ongoing */
320 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
321 {
322 /* Reset ADC error code field related to injected conversions only */
323 CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
324 }
325 else
326 {
327 /* Set ADC error code to none */
328 ADC_CLEAR_ERRORCODE(hadc);
329 }
330
331 /* Set ADC state */
332 /* - Clear state bitfield related to injected group conversion results */
333 /* - Set state bitfield related to injected operation */
334 ADC_STATE_CLR_SET(hadc->State,
335 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
336 HAL_ADC_STATE_INJ_BUSY);
337
338 #if defined(ADC_MULTIMODE_SUPPORT)
339 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
340 - if ADC instance is master or if multimode feature is not available
341 - if multimode setting is disabled (ADC instance slave in independent mode) */
342 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
343 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
344 )
345 {
346 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
347 }
348 #endif
349
350 /* Clear ADC group injected group conversion flag */
351 /* (To ensure of no unknown state from potential previous ADC operations) */
352 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
353
354 /* Process unlocked */
355 /* Unlock before starting ADC conversions: in case of potential */
356 /* interruption, to let the process to ADC IRQ Handler. */
357 __HAL_UNLOCK(hadc);
358
359 /* Enable conversion of injected group, if automatic injected conversion */
360 /* is disabled. */
361 /* If software start has been selected, conversion starts immediately. */
362 /* If external trigger has been selected, conversion will start at next */
363 /* trigger event. */
364 /* Case of multimode enabled (when multimode feature is available): */
365 /* if ADC is slave, */
366 /* - ADC is enabled only (conversion is not started), */
367 /* - if multimode only concerns regular conversion, ADC is enabled */
368 /* and conversion is started. */
369 /* If ADC is master or independent, */
370 /* - ADC is enabled and conversion is started. */
371 #if defined(ADC_MULTIMODE_SUPPORT)
372 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
373 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
374 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
375 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
376 )
377 {
378 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
379 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
380 {
381 LL_ADC_INJ_StartConversion(hadc->Instance);
382 }
383 }
384 else
385 {
386 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
387 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
388 }
389 #else
390 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
391 {
392 /* Start ADC group injected conversion */
393 LL_ADC_INJ_StartConversion(hadc->Instance);
394 }
395 #endif
396
397 }
398 else
399 {
400 /* Process unlocked */
401 __HAL_UNLOCK(hadc);
402 }
403
404 /* Return function status */
405 return tmp_hal_status;
406 }
407 }
408
409 /**
410 * @brief Stop conversion of injected channels. Disable ADC peripheral if
411 * no regular conversion is on going.
412 * @note If ADC must be disabled and if conversion is on going on
413 * regular group, function HAL_ADC_Stop must be used to stop both
414 * injected and regular groups, and disable the ADC.
415 * @note If injected group mode auto-injection is enabled,
416 * function HAL_ADC_Stop must be used.
417 * @note In case of multimode enabled (when multimode feature is available),
418 * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
419 * For ADC master, conversion is stopped and ADC is disabled.
420 * For ADC slave, ADC is disabled only (conversion stop of ADC master
421 * has already stopped conversion of ADC slave).
422 * @param hadc ADC handle.
423 * @retval HAL status
424 */
HAL_ADCEx_InjectedStop(ADC_HandleTypeDef * hadc)425 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
426 {
427 HAL_StatusTypeDef tmp_hal_status;
428
429 /* Check the parameters */
430 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
431
432 /* Process locked */
433 __HAL_LOCK(hadc);
434
435 /* 1. Stop potential conversion on going on injected group only. */
436 tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
437
438 /* Disable ADC peripheral if injected conversions are effectively stopped */
439 /* and if no conversion on regular group is on-going */
440 if (tmp_hal_status == HAL_OK)
441 {
442 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
443 {
444 /* 2. Disable the ADC peripheral */
445 tmp_hal_status = ADC_Disable(hadc);
446
447 /* Check if ADC is effectively disabled */
448 if (tmp_hal_status == HAL_OK)
449 {
450 /* Set ADC state */
451 ADC_STATE_CLR_SET(hadc->State,
452 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
453 HAL_ADC_STATE_READY);
454 }
455 }
456 /* Conversion on injected group is stopped, but ADC not disabled since */
457 /* conversion on regular group is still running. */
458 else
459 {
460 /* Set ADC state */
461 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
462 }
463 }
464
465 /* Process unlocked */
466 __HAL_UNLOCK(hadc);
467
468 /* Return function status */
469 return tmp_hal_status;
470 }
471
472 /**
473 * @brief Wait for injected group conversion to be completed.
474 * @param hadc ADC handle
475 * @param Timeout Timeout value in millisecond.
476 * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is
477 * checked and cleared depending on AUTDLY bit status.
478 * @retval HAL status
479 */
HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)480 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
481 {
482 uint32_t tickstart;
483 uint32_t tmp_Flag_End;
484 uint32_t tmp_adc_inj_is_trigger_source_sw_start;
485 uint32_t tmp_adc_reg_is_trigger_source_sw_start;
486 uint32_t tmp_cfgr;
487 #if defined(ADC_MULTIMODE_SUPPORT)
488 const ADC_TypeDef *tmpADC_Master;
489 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
490 #endif
491
492 /* Check the parameters */
493 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
494
495 /* If end of sequence selected */
496 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
497 {
498 tmp_Flag_End = ADC_FLAG_JEOS;
499 }
500 else /* end of conversion selected */
501 {
502 tmp_Flag_End = ADC_FLAG_JEOC;
503 }
504
505 /* Get timeout */
506 tickstart = HAL_GetTick();
507
508 /* Wait until End of Conversion or Sequence flag is raised */
509 while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
510 {
511 /* Check if timeout is disabled (set to infinite wait) */
512 if (Timeout != HAL_MAX_DELAY)
513 {
514 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
515 {
516 /* New check to avoid false timeout detection in case of preemption */
517 if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
518 {
519 /* Update ADC state machine to timeout */
520 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
521
522 /* Process unlocked */
523 __HAL_UNLOCK(hadc);
524
525 return HAL_TIMEOUT;
526 }
527 }
528 }
529 }
530
531 /* Retrieve ADC configuration */
532 tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
533 tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
534 /* Get relevant register CFGR in ADC instance of ADC master or slave */
535 /* in function of multimode state (for devices with multimode */
536 /* available). */
537 #if defined(ADC_MULTIMODE_SUPPORT)
538 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
539 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
540 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
541 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
542 )
543 {
544 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
545 }
546 else
547 {
548 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
549 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
550 }
551 #else
552 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
553 #endif
554
555 /* Update ADC state machine */
556 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
557
558 /* Determine whether any further conversion upcoming on group injected */
559 /* by external trigger or by automatic injected conversion */
560 /* from group regular. */
561 if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
562 ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) &&
563 ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
564 (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
565 {
566 /* Check whether end of sequence is reached */
567 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
568 {
569 /* Particular case if injected contexts queue is enabled: */
570 /* when the last context has been fully processed, JSQR is reset */
571 /* by the hardware. Even if no injected conversion is planned to come */
572 /* (queue empty, triggers are ignored), it can start again */
573 /* immediately after setting a new context (JADSTART is still set). */
574 /* Therefore, state of HAL ADC injected group is kept to busy. */
575 if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
576 {
577 /* Set ADC state */
578 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
579
580 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
581 {
582 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
583 }
584 }
585 }
586 }
587
588 /* Clear polled flag */
589 if (tmp_Flag_End == ADC_FLAG_JEOS)
590 {
591 /* Clear end of sequence JEOS flag of injected group if low power feature */
592 /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
593 /* For injected groups, no new conversion will start before JEOS is */
594 /* cleared. */
595 if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
596 {
597 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
598 }
599 }
600 else
601 {
602 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
603 }
604
605 /* Return API HAL status */
606 return HAL_OK;
607 }
608
609 /**
610 * @brief Enable ADC, start conversion of injected group with interruption.
611 * @note Interruptions enabled in this function according to initialization
612 * setting : JEOC (end of conversion) or JEOS (end of sequence)
613 * @note Case of multimode enabled (when multimode feature is enabled):
614 * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
615 * then for ADC master.
616 * For ADC slave, ADC is enabled only (conversion is not started).
617 * For ADC master, ADC is enabled and multimode conversion is started.
618 * @param hadc ADC handle.
619 * @retval HAL status.
620 */
HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef * hadc)621 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
622 {
623 HAL_StatusTypeDef tmp_hal_status;
624 uint32_t tmp_config_injected_queue;
625 #if defined(ADC_MULTIMODE_SUPPORT)
626 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
627 #endif
628
629 /* Check the parameters */
630 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
631
632 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
633 {
634 return HAL_BUSY;
635 }
636 else
637 {
638 /* In case of software trigger detection enabled, JQDIS must be set
639 (which can be done only if ADSTART and JADSTART are both cleared).
640 If JQDIS is not set at that point, returns an error
641 - since software trigger detection is disabled. User needs to
642 resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
643 - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
644 the queue is empty */
645 tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
646
647 if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
648 && (tmp_config_injected_queue == 0UL)
649 )
650 {
651 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
652 return HAL_ERROR;
653 }
654
655 /* Process locked */
656 __HAL_LOCK(hadc);
657
658 /* Enable the ADC peripheral */
659 tmp_hal_status = ADC_Enable(hadc);
660
661 /* Start conversion if ADC is effectively enabled */
662 if (tmp_hal_status == HAL_OK)
663 {
664 /* Check if a regular conversion is ongoing */
665 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
666 {
667 /* Reset ADC error code field related to injected conversions only */
668 CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
669 }
670 else
671 {
672 /* Set ADC error code to none */
673 ADC_CLEAR_ERRORCODE(hadc);
674 }
675
676 /* Set ADC state */
677 /* - Clear state bitfield related to injected group conversion results */
678 /* - Set state bitfield related to injected operation */
679 ADC_STATE_CLR_SET(hadc->State,
680 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
681 HAL_ADC_STATE_INJ_BUSY);
682
683 #if defined(ADC_MULTIMODE_SUPPORT)
684 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
685 - if ADC instance is master or if multimode feature is not available
686 - if multimode setting is disabled (ADC instance slave in independent mode) */
687 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
688 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
689 )
690 {
691 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
692 }
693 #endif
694
695 /* Clear ADC group injected group conversion flag */
696 /* (To ensure of no unknown state from potential previous ADC operations) */
697 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
698
699 /* Process unlocked */
700 /* Unlock before starting ADC conversions: in case of potential */
701 /* interruption, to let the process to ADC IRQ Handler. */
702 __HAL_UNLOCK(hadc);
703
704 /* Enable ADC Injected context queue overflow interrupt if this feature */
705 /* is enabled. */
706 if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL)
707 {
708 __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
709 }
710
711 /* Enable ADC end of conversion interrupt */
712 switch (hadc->Init.EOCSelection)
713 {
714 case ADC_EOC_SEQ_CONV:
715 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
716 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
717 break;
718 /* case ADC_EOC_SINGLE_CONV */
719 default:
720 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
721 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
722 break;
723 }
724
725 /* Enable conversion of injected group, if automatic injected conversion */
726 /* is disabled. */
727 /* If software start has been selected, conversion starts immediately. */
728 /* If external trigger has been selected, conversion will start at next */
729 /* trigger event. */
730 /* Case of multimode enabled (when multimode feature is available): */
731 /* if ADC is slave, */
732 /* - ADC is enabled only (conversion is not started), */
733 /* - if multimode only concerns regular conversion, ADC is enabled */
734 /* and conversion is started. */
735 /* If ADC is master or independent, */
736 /* - ADC is enabled and conversion is started. */
737 #if defined(ADC_MULTIMODE_SUPPORT)
738 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
739 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
740 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
741 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
742 )
743 {
744 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
745 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
746 {
747 LL_ADC_INJ_StartConversion(hadc->Instance);
748 }
749 }
750 else
751 {
752 /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
753 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
754 }
755 #else
756 if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
757 {
758 /* Start ADC group injected conversion */
759 LL_ADC_INJ_StartConversion(hadc->Instance);
760 }
761 #endif
762
763 }
764 else
765 {
766 /* Process unlocked */
767 __HAL_UNLOCK(hadc);
768 }
769
770 /* Return function status */
771 return tmp_hal_status;
772 }
773 }
774
775 /**
776 * @brief Stop conversion of injected channels, disable interruption of
777 * end-of-conversion. Disable ADC peripheral if no regular conversion
778 * is on going.
779 * @note If ADC must be disabled and if conversion is on going on
780 * regular group, function HAL_ADC_Stop must be used to stop both
781 * injected and regular groups, and disable the ADC.
782 * @note If injected group mode auto-injection is enabled,
783 * function HAL_ADC_Stop must be used.
784 * @note Case of multimode enabled (when multimode feature is available):
785 * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
786 * then for ADC slave.
787 * For ADC master, conversion is stopped and ADC is disabled.
788 * For ADC slave, ADC is disabled only (conversion stop of ADC master
789 * has already stopped conversion of ADC slave).
790 * @note In case of auto-injection mode, HAL_ADC_Stop() must be used.
791 * @param hadc ADC handle
792 * @retval HAL status
793 */
HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef * hadc)794 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
795 {
796 HAL_StatusTypeDef tmp_hal_status;
797
798 /* Check the parameters */
799 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
800
801 /* Process locked */
802 __HAL_LOCK(hadc);
803
804 /* 1. Stop potential conversion on going on injected group only. */
805 tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
806
807 /* Disable ADC peripheral if injected conversions are effectively stopped */
808 /* and if no conversion on the other group (regular group) is intended to */
809 /* continue. */
810 if (tmp_hal_status == HAL_OK)
811 {
812 /* Disable ADC end of conversion interrupt for injected channels */
813 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
814
815 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
816 {
817 /* 2. Disable the ADC peripheral */
818 tmp_hal_status = ADC_Disable(hadc);
819
820 /* Check if ADC is effectively disabled */
821 if (tmp_hal_status == HAL_OK)
822 {
823 /* Set ADC state */
824 ADC_STATE_CLR_SET(hadc->State,
825 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
826 HAL_ADC_STATE_READY);
827 }
828 }
829 /* Conversion on injected group is stopped, but ADC not disabled since */
830 /* conversion on regular group is still running. */
831 else
832 {
833 /* Set ADC state */
834 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
835 }
836 }
837
838 /* Process unlocked */
839 __HAL_UNLOCK(hadc);
840
841 /* Return function status */
842 return tmp_hal_status;
843 }
844
845 #if defined(ADC_MULTIMODE_SUPPORT)
846 /**
847 * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
848 * @note Multimode must have been previously configured using
849 * HAL_ADCEx_MultiModeConfigChannel() function.
850 * Interruptions enabled in this function:
851 * overrun, DMA half transfer, DMA transfer complete.
852 * Each of these interruptions has its dedicated callback function.
853 * @note State field of Slave ADC handle is not updated in this configuration:
854 * user should not rely on it for information related to Slave regular
855 * conversions.
856 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
857 * @param pData Destination Buffer address.
858 * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
859 * @retval HAL status
860 */
HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)861 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
862 {
863 HAL_StatusTypeDef tmp_hal_status;
864 ADC_HandleTypeDef tmphadcSlave;
865 ADC_Common_TypeDef *tmpADC_Common;
866
867 /* Check the parameters */
868 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
869 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
870 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
871 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
872
873 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
874 {
875 return HAL_BUSY;
876 }
877 else
878 {
879 /* Process locked */
880 __HAL_LOCK(hadc);
881
882 /* Temporary handle minimum initialization */
883 __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
884 ADC_CLEAR_ERRORCODE(&tmphadcSlave);
885
886 /* Set a temporary handle of the ADC slave associated to the ADC master */
887 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
888
889 if (tmphadcSlave.Instance == NULL)
890 {
891 /* Set ADC state */
892 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
893
894 /* Process unlocked */
895 __HAL_UNLOCK(hadc);
896
897 return HAL_ERROR;
898 }
899
900 /* Enable the ADC peripherals: master and slave (in case if not already */
901 /* enabled previously) */
902 tmp_hal_status = ADC_Enable(hadc);
903 if (tmp_hal_status == HAL_OK)
904 {
905 tmp_hal_status = ADC_Enable(&tmphadcSlave);
906 }
907
908 /* Start multimode conversion of ADCs pair */
909 if (tmp_hal_status == HAL_OK)
910 {
911 /* Set ADC state */
912 ADC_STATE_CLR_SET(hadc->State,
913 (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP),
914 HAL_ADC_STATE_REG_BUSY);
915
916 /* Set ADC error code to none */
917 ADC_CLEAR_ERRORCODE(hadc);
918
919 /* Set the DMA transfer complete callback */
920 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
921
922 /* Set the DMA half transfer complete callback */
923 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
924
925 /* Set the DMA error callback */
926 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
927
928 /* Pointer to the common control register */
929 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
930
931 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
932 /* start (in case of SW start): */
933
934 /* Clear regular group conversion flag and overrun flag */
935 /* (To ensure of no unknown state from potential previous ADC operations) */
936 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
937
938 /* Process unlocked */
939 /* Unlock before starting ADC conversions: in case of potential */
940 /* interruption, to let the process to ADC IRQ Handler. */
941 __HAL_UNLOCK(hadc);
942
943 /* Enable ADC overrun interrupt */
944 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
945
946 /* Start the DMA channel */
947 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
948
949 /* Enable conversion of regular group. */
950 /* If software start has been selected, conversion starts immediately. */
951 /* If external trigger has been selected, conversion will start at next */
952 /* trigger event. */
953 /* Start ADC group regular conversion */
954 LL_ADC_REG_StartConversion(hadc->Instance);
955 }
956 else
957 {
958 /* Process unlocked */
959 __HAL_UNLOCK(hadc);
960 }
961
962 /* Return function status */
963 return tmp_hal_status;
964 }
965 }
966
967 /**
968 * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
969 * @note Multimode is kept enabled after this function. MultiMode DMA bits
970 * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
971 * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
972 * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
973 * resort to HAL_ADCEx_DisableMultiMode() API.
974 * @note In case of DMA configured in circular mode, function
975 * HAL_ADC_Stop_DMA() must be called after this function with handle of
976 * ADC slave, to properly disable the DMA channel.
977 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
978 * @retval HAL status
979 */
HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef * hadc)980 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
981 {
982 HAL_StatusTypeDef tmp_hal_status;
983 uint32_t tickstart;
984 ADC_HandleTypeDef tmphadcSlave;
985 uint32_t tmphadcSlave_conversion_on_going;
986 HAL_StatusTypeDef tmphadcSlave_disable_status;
987
988 /* Check the parameters */
989 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
990
991 /* Process locked */
992 __HAL_LOCK(hadc);
993
994
995 /* 1. Stop potential multimode conversion on going, on regular and injected groups */
996 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
997
998 /* Disable ADC peripheral if conversions are effectively stopped */
999 if (tmp_hal_status == HAL_OK)
1000 {
1001 /* Temporary handle minimum initialization */
1002 __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
1003 ADC_CLEAR_ERRORCODE(&tmphadcSlave);
1004
1005 /* Set a temporary handle of the ADC slave associated to the ADC master */
1006 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
1007
1008 if (tmphadcSlave.Instance == NULL)
1009 {
1010 /* Update ADC state machine to error */
1011 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1012
1013 /* Process unlocked */
1014 __HAL_UNLOCK(hadc);
1015
1016 return HAL_ERROR;
1017 }
1018
1019 /* Procedure to disable the ADC peripheral: wait for conversions */
1020 /* effectively stopped (ADC master and ADC slave), then disable ADC */
1021
1022 /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
1023 tickstart = HAL_GetTick();
1024
1025 tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
1026 while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1027 || (tmphadcSlave_conversion_on_going == 1UL)
1028 )
1029 {
1030 if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
1031 {
1032 /* New check to avoid false timeout detection in case of preemption */
1033 tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
1034 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1035 || (tmphadcSlave_conversion_on_going == 1UL)
1036 )
1037 {
1038 /* Update ADC state machine to error */
1039 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1040
1041 /* Process unlocked */
1042 __HAL_UNLOCK(hadc);
1043
1044 return HAL_ERROR;
1045 }
1046 }
1047
1048 tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
1049 }
1050
1051 /* Disable the DMA channel (in case of DMA in circular mode or stop */
1052 /* while DMA transfer is on going) */
1053 /* Note: DMA channel of ADC slave should be stopped after this function */
1054 /* with HAL_ADC_Stop_DMA() API. */
1055 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1056
1057 /* Check if DMA channel effectively disabled */
1058 if (tmp_hal_status == HAL_ERROR)
1059 {
1060 /* Update ADC state machine to error */
1061 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1062 }
1063
1064 /* Disable ADC overrun interrupt */
1065 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1066
1067 /* 2. Disable the ADC peripherals: master and slave */
1068 /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
1069 /* memory a potential failing status. */
1070 if (tmp_hal_status == HAL_OK)
1071 {
1072 tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave);
1073 if ((ADC_Disable(hadc) == HAL_OK) &&
1074 (tmphadcSlave_disable_status == HAL_OK))
1075 {
1076 tmp_hal_status = HAL_OK;
1077 }
1078 }
1079 else
1080 {
1081 /* In case of error, attempt to disable ADC master and slave without status assert */
1082 (void) ADC_Disable(hadc);
1083 (void) ADC_Disable(&tmphadcSlave);
1084 }
1085
1086 /* Set ADC state (ADC master) */
1087 ADC_STATE_CLR_SET(hadc->State,
1088 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1089 HAL_ADC_STATE_READY);
1090 }
1091
1092 /* Process unlocked */
1093 __HAL_UNLOCK(hadc);
1094
1095 /* Return function status */
1096 return tmp_hal_status;
1097 }
1098
1099 /**
1100 * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration.
1101 * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
1102 * @retval The converted data values.
1103 */
HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef * hadc)1104 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
1105 {
1106 const ADC_Common_TypeDef *tmpADC_Common;
1107
1108 /* Check the parameters */
1109 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1110
1111 /* Prevent unused argument(s) compilation warning if no assert_param check */
1112 /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */
1113 UNUSED(hadc);
1114
1115 /* Pointer to the common control register */
1116 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
1117
1118 /* Return the multi mode conversion value */
1119 return tmpADC_Common->CDR;
1120 }
1121 #endif /* ADC_MULTIMODE_SUPPORT */
1122
1123 /**
1124 * @brief Get ADC injected group conversion result.
1125 * @note Reading register JDRx automatically clears ADC flag JEOC
1126 * (ADC group injected end of unitary conversion).
1127 * @note This function does not clear ADC flag JEOS
1128 * (ADC group injected end of sequence conversion)
1129 * Occurrence of flag JEOS rising:
1130 * - If sequencer is composed of 1 rank, flag JEOS is equivalent
1131 * to flag JEOC.
1132 * - If sequencer is composed of several ranks, during the scan
1133 * sequence flag JEOC only is raised, at the end of the scan sequence
1134 * both flags JEOC and EOS are raised.
1135 * Flag JEOS must not be cleared by this function because
1136 * it would not be compliant with low power features
1137 * (feature low power auto-wait, not available on all STM32 families).
1138 * To clear this flag, either use function:
1139 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
1140 * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
1141 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
1142 * @param hadc ADC handle
1143 * @param InjectedRank the converted ADC injected rank.
1144 * This parameter can be one of the following values:
1145 * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
1146 * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
1147 * @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
1148 * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
1149 * @retval ADC group injected conversion data
1150 */
HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef * hadc,uint32_t InjectedRank)1151 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
1152 {
1153 uint32_t tmp_jdr;
1154
1155 /* Check the parameters */
1156 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1157 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
1158
1159 /* Get ADC converted value */
1160 switch (InjectedRank)
1161 {
1162 case ADC_INJECTED_RANK_4:
1163 tmp_jdr = hadc->Instance->JDR4;
1164 break;
1165 case ADC_INJECTED_RANK_3:
1166 tmp_jdr = hadc->Instance->JDR3;
1167 break;
1168 case ADC_INJECTED_RANK_2:
1169 tmp_jdr = hadc->Instance->JDR2;
1170 break;
1171 case ADC_INJECTED_RANK_1:
1172 default:
1173 tmp_jdr = hadc->Instance->JDR1;
1174 break;
1175 }
1176
1177 /* Return ADC converted value */
1178 return tmp_jdr;
1179 }
1180
1181 /**
1182 * @brief Injected conversion complete callback in non-blocking mode.
1183 * @param hadc ADC handle
1184 * @retval None
1185 */
HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef * hadc)1186 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
1187 {
1188 /* Prevent unused argument(s) compilation warning */
1189 UNUSED(hadc);
1190
1191 /* NOTE : This function should not be modified. When the callback is needed,
1192 function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
1193 */
1194 }
1195
1196 /**
1197 * @brief Injected context queue overflow callback.
1198 * @note This callback is called if injected context queue is enabled
1199 (parameter "QueueInjectedContext" in injected channel configuration)
1200 and if a new injected context is set when queue is full (maximum 2
1201 contexts).
1202 * @param hadc ADC handle
1203 * @retval None
1204 */
HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef * hadc)1205 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
1206 {
1207 /* Prevent unused argument(s) compilation warning */
1208 UNUSED(hadc);
1209
1210 /* NOTE : This function should not be modified. When the callback is needed,
1211 function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
1212 */
1213 }
1214
1215 /**
1216 * @brief Analog watchdog 2 callback in non-blocking mode.
1217 * @param hadc ADC handle
1218 * @retval None
1219 */
HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef * hadc)1220 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
1221 {
1222 /* Prevent unused argument(s) compilation warning */
1223 UNUSED(hadc);
1224
1225 /* NOTE : This function should not be modified. When the callback is needed,
1226 function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
1227 */
1228 }
1229
1230 /**
1231 * @brief Analog watchdog 3 callback in non-blocking mode.
1232 * @param hadc ADC handle
1233 * @retval None
1234 */
HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef * hadc)1235 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
1236 {
1237 /* Prevent unused argument(s) compilation warning */
1238 UNUSED(hadc);
1239
1240 /* NOTE : This function should not be modified. When the callback is needed,
1241 function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
1242 */
1243 }
1244
1245
1246 /**
1247 * @brief End Of Sampling callback in non-blocking mode.
1248 * @param hadc ADC handle
1249 * @retval None
1250 */
HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef * hadc)1251 __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
1252 {
1253 /* Prevent unused argument(s) compilation warning */
1254 UNUSED(hadc);
1255
1256 /* NOTE : This function should not be modified. When the callback is needed,
1257 function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
1258 */
1259 }
1260
1261 /**
1262 * @brief Stop ADC conversion of regular group (and injected channels in
1263 * case of auto_injection mode), disable ADC peripheral if no
1264 * conversion is on going on injected group.
1265 * @param hadc ADC handle
1266 * @retval HAL status.
1267 */
HAL_ADCEx_RegularStop(ADC_HandleTypeDef * hadc)1268 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
1269 {
1270 HAL_StatusTypeDef tmp_hal_status;
1271
1272 /* Check the parameters */
1273 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1274
1275 /* Process locked */
1276 __HAL_LOCK(hadc);
1277
1278 /* 1. Stop potential regular conversion on going */
1279 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1280
1281 /* Disable ADC peripheral if regular conversions are effectively stopped
1282 and if no injected conversions are on-going */
1283 if (tmp_hal_status == HAL_OK)
1284 {
1285 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1286 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1287
1288 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1289 {
1290 /* 2. Disable the ADC peripheral */
1291 tmp_hal_status = ADC_Disable(hadc);
1292
1293 /* Check if ADC is effectively disabled */
1294 if (tmp_hal_status == HAL_OK)
1295 {
1296 /* Set ADC state */
1297 ADC_STATE_CLR_SET(hadc->State,
1298 HAL_ADC_STATE_INJ_BUSY,
1299 HAL_ADC_STATE_READY);
1300 }
1301 }
1302 /* Conversion on injected group is stopped, but ADC not disabled since */
1303 /* conversion on regular group is still running. */
1304 else
1305 {
1306 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1307 }
1308 }
1309
1310 /* Process unlocked */
1311 __HAL_UNLOCK(hadc);
1312
1313 /* Return function status */
1314 return tmp_hal_status;
1315 }
1316
1317
1318 /**
1319 * @brief Stop ADC conversion of ADC groups regular and injected,
1320 * disable interrution of end-of-conversion,
1321 * disable ADC peripheral if no conversion is on going
1322 * on injected group.
1323 * @param hadc ADC handle
1324 * @retval HAL status.
1325 */
HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef * hadc)1326 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
1327 {
1328 HAL_StatusTypeDef tmp_hal_status;
1329
1330 /* Check the parameters */
1331 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1332
1333 /* Process locked */
1334 __HAL_LOCK(hadc);
1335
1336 /* 1. Stop potential regular conversion on going */
1337 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1338
1339 /* Disable ADC peripheral if conversions are effectively stopped
1340 and if no injected conversion is on-going */
1341 if (tmp_hal_status == HAL_OK)
1342 {
1343 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1344 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1345
1346 /* Disable all regular-related interrupts */
1347 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1348
1349 /* 2. Disable ADC peripheral if no injected conversions are on-going */
1350 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1351 {
1352 tmp_hal_status = ADC_Disable(hadc);
1353 /* if no issue reported */
1354 if (tmp_hal_status == HAL_OK)
1355 {
1356 /* Set ADC state */
1357 ADC_STATE_CLR_SET(hadc->State,
1358 HAL_ADC_STATE_INJ_BUSY,
1359 HAL_ADC_STATE_READY);
1360 }
1361 }
1362 else
1363 {
1364 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1365 }
1366 }
1367
1368 /* Process unlocked */
1369 __HAL_UNLOCK(hadc);
1370
1371 /* Return function status */
1372 return tmp_hal_status;
1373 }
1374
1375 /**
1376 * @brief Stop ADC conversion of regular group (and injected group in
1377 * case of auto_injection mode), disable ADC DMA transfer, disable
1378 * ADC peripheral if no conversion is on going
1379 * on injected group.
1380 * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
1381 * For multimode (when multimode feature is available),
1382 * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
1383 * @param hadc ADC handle
1384 * @retval HAL status.
1385 */
HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef * hadc)1386 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
1387 {
1388 HAL_StatusTypeDef tmp_hal_status;
1389
1390 /* Check the parameters */
1391 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1392
1393 /* Process locked */
1394 __HAL_LOCK(hadc);
1395
1396 /* 1. Stop potential regular conversion on going */
1397 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1398
1399 /* Disable ADC peripheral if conversions are effectively stopped
1400 and if no injected conversion is on-going */
1401 if (tmp_hal_status == HAL_OK)
1402 {
1403 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1404 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1405
1406 /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
1407 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
1408
1409 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
1410 /* while DMA transfer is on going) */
1411 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1412
1413 /* Check if DMA channel effectively disabled */
1414 if (tmp_hal_status != HAL_OK)
1415 {
1416 /* Update ADC state machine to error */
1417 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1418 }
1419
1420 /* Disable ADC overrun interrupt */
1421 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1422
1423 /* 2. Disable the ADC peripheral */
1424 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
1425 /* to keep in memory a potential failing status. */
1426 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1427 {
1428 if (tmp_hal_status == HAL_OK)
1429 {
1430 tmp_hal_status = ADC_Disable(hadc);
1431 }
1432 else
1433 {
1434 (void)ADC_Disable(hadc);
1435 }
1436
1437 /* Check if ADC is effectively disabled */
1438 if (tmp_hal_status == HAL_OK)
1439 {
1440 /* Set ADC state */
1441 ADC_STATE_CLR_SET(hadc->State,
1442 HAL_ADC_STATE_INJ_BUSY,
1443 HAL_ADC_STATE_READY);
1444 }
1445 }
1446 else
1447 {
1448 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
1449 }
1450 }
1451
1452 /* Process unlocked */
1453 __HAL_UNLOCK(hadc);
1454
1455 /* Return function status */
1456 return tmp_hal_status;
1457 }
1458
1459 #if defined(ADC_MULTIMODE_SUPPORT)
1460 /**
1461 * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
1462 * @note Multimode is kept enabled after this function. Multimode DMA bits
1463 * (MDMA and DMACFG bits of common CCR register) are maintained. To disable
1464 * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
1465 * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
1466 * resort to HAL_ADCEx_DisableMultiMode() API.
1467 * @note In case of DMA configured in circular mode, function
1468 * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
1469 * ADC slave, to properly disable the DMA channel.
1470 * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
1471 * @retval HAL status
1472 */
HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef * hadc)1473 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
1474 {
1475 HAL_StatusTypeDef tmp_hal_status;
1476 uint32_t tickstart;
1477 ADC_HandleTypeDef tmphadcSlave;
1478 uint32_t tmphadcSlave_conversion_on_going;
1479
1480 /* Check the parameters */
1481 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1482
1483 /* Process locked */
1484 __HAL_LOCK(hadc);
1485
1486
1487 /* 1. Stop potential multimode conversion on going, on regular groups */
1488 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
1489
1490 /* Disable ADC peripheral if conversions are effectively stopped */
1491 if (tmp_hal_status == HAL_OK)
1492 {
1493 /* Clear HAL_ADC_STATE_REG_BUSY bit */
1494 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1495
1496 /* Temporary handle minimum initialization */
1497 __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
1498 ADC_CLEAR_ERRORCODE(&tmphadcSlave);
1499
1500 /* Set a temporary handle of the ADC slave associated to the ADC master */
1501 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
1502
1503 if (tmphadcSlave.Instance == NULL)
1504 {
1505 /* Update ADC state machine to error */
1506 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1507
1508 /* Process unlocked */
1509 __HAL_UNLOCK(hadc);
1510
1511 return HAL_ERROR;
1512 }
1513
1514 /* Procedure to disable the ADC peripheral: wait for conversions */
1515 /* effectively stopped (ADC master and ADC slave), then disable ADC */
1516
1517 /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
1518 tickstart = HAL_GetTick();
1519
1520 tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
1521 while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1522 || (tmphadcSlave_conversion_on_going == 1UL)
1523 )
1524 {
1525 if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
1526 {
1527 /* New check to avoid false timeout detection in case of preemption */
1528 tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
1529 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
1530 || (tmphadcSlave_conversion_on_going == 1UL)
1531 )
1532 {
1533 /* Update ADC state machine to error */
1534 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
1535
1536 /* Process unlocked */
1537 __HAL_UNLOCK(hadc);
1538
1539 return HAL_ERROR;
1540 }
1541 }
1542
1543 tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
1544 }
1545
1546 /* Disable the DMA channel (in case of DMA in circular mode or stop */
1547 /* while DMA transfer is on going) */
1548 /* Note: DMA channel of ADC slave should be stopped after this function */
1549 /* with HAL_ADCEx_RegularStop_DMA() API. */
1550 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
1551
1552 /* Check if DMA channel effectively disabled */
1553 if (tmp_hal_status != HAL_OK)
1554 {
1555 /* Update ADC state machine to error */
1556 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
1557 }
1558
1559 /* Disable ADC overrun interrupt */
1560 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
1561
1562 /* 2. Disable the ADC peripherals: master and slave if no injected */
1563 /* conversion is on-going. */
1564 /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
1565 /* memory a potential failing status. */
1566 if (tmp_hal_status == HAL_OK)
1567 {
1568 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1569 {
1570 tmp_hal_status = ADC_Disable(hadc);
1571 if (tmp_hal_status == HAL_OK)
1572 {
1573 if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL)
1574 {
1575 tmp_hal_status = ADC_Disable(&tmphadcSlave);
1576 }
1577 }
1578 }
1579
1580 if (tmp_hal_status == HAL_OK)
1581 {
1582 /* Both Master and Slave ADC's could be disabled. Update Master State */
1583 /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
1584 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
1585 }
1586 else
1587 {
1588 /* injected (Master or Slave) conversions are still on-going,
1589 no Master State change */
1590 }
1591 }
1592 }
1593
1594 /* Process unlocked */
1595 __HAL_UNLOCK(hadc);
1596
1597 /* Return function status */
1598 return tmp_hal_status;
1599 }
1600 #endif /* ADC_MULTIMODE_SUPPORT */
1601
1602 /**
1603 * @}
1604 */
1605
1606 /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
1607 * @brief ADC Extended Peripheral Control functions
1608 *
1609 @verbatim
1610 ===============================================================================
1611 ##### Peripheral Control functions #####
1612 ===============================================================================
1613 [..] This section provides functions allowing to:
1614 (+) Configure channels on injected group
1615 (+) Configure multimode when multimode feature is available
1616 (+) Enable or Disable Injected Queue
1617 (+) Disable ADC voltage regulator
1618 (+) Enter ADC deep-power-down mode
1619
1620 @endverbatim
1621 * @{
1622 */
1623
1624 /**
1625 * @brief Configure a channel to be assigned to ADC group injected.
1626 * @note Possibility to update parameters on the fly:
1627 * This function initializes injected group, following calls to this
1628 * function can be used to reconfigure some parameters of structure
1629 * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
1630 * The setting of these parameters is conditioned to ADC state:
1631 * Refer to comments of structure "ADC_InjectionConfTypeDef".
1632 * @note In case of usage of internal measurement channels:
1633 * Vbat/VrefInt/TempSensor.
1634 * These internal paths can be disabled using function
1635 * HAL_ADC_DeInit().
1636 * @note Caution: For Injected Context Queue use, a context must be fully
1637 * defined before start of injected conversion. All channels are configured
1638 * consecutively for the same ADC instance. Therefore, the number of calls to
1639 * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
1640 * InjectedNbrOfConversion for each context.
1641 * - Example 1: If 1 context is intended to be used (or if there is no use of the
1642 * Injected Queue Context feature) and if the context contains 3 injected ranks
1643 * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
1644 * called once for each channel (i.e. 3 times) before starting a conversion.
1645 * This function must not be called to configure a 4th injected channel:
1646 * it would start a new context into context queue.
1647 * - Example 2: If 2 contexts are intended to be used and each of them contains
1648 * 3 injected ranks (InjectedNbrOfConversion = 3),
1649 * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
1650 * for each context (3 channels x 2 contexts = 6 calls). Conversion can
1651 * start once the 1st context is set, that is after the first three
1652 * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
1653 * @param hadc ADC handle
1654 * @param sConfigInjected Structure of ADC injected group and ADC channel for
1655 * injected group.
1656 * @retval HAL status
1657 */
HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef * hadc,ADC_InjectionConfTypeDef * sConfigInjected)1658 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
1659 {
1660 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1661 uint32_t tmpOffsetShifted;
1662 uint32_t tmp_config_internal_channel;
1663 uint32_t tmp_adc_is_conversion_on_going_regular;
1664 uint32_t tmp_adc_is_conversion_on_going_injected;
1665 __IO uint32_t wait_loop_index = 0;
1666
1667 uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U;
1668
1669 /* Check the parameters */
1670 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1671 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
1672 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
1673 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
1674 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
1675 assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
1676 assert_param(IS_ADC_EXTTRIGINJEC(hadc, sConfigInjected->ExternalTrigInjecConv));
1677 assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
1678 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
1679 assert_param(IS_ADC_OFFSET_SIGN(sConfigInjected->InjectedOffsetSign));
1680 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedOffsetSaturation));
1681 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
1682
1683 if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
1684 {
1685 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
1686 assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
1687 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
1688 }
1689
1690
1691 /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
1692 ignored (considered as reset) */
1693 assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE)));
1694
1695 /* JDISCEN and JAUTO bits can't be set at the same time */
1696 assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
1697
1698 /* DISCEN and JAUTO bits can't be set at the same time */
1699 assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
1700
1701 /* Verification of channel number */
1702 if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
1703 {
1704 assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel));
1705 }
1706 else
1707 {
1708 assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel));
1709 }
1710
1711 /* Process locked */
1712 __HAL_LOCK(hadc);
1713
1714 /* Configuration of injected group sequencer: */
1715 /* Hardware constraint: Must fully define injected context register JSQR */
1716 /* before make it entering into injected sequencer queue. */
1717 /* */
1718 /* - if scan mode is disabled: */
1719 /* * Injected channels sequence length is set to 0x00: 1 channel */
1720 /* converted (channel on injected rank 1) */
1721 /* Parameter "InjectedNbrOfConversion" is discarded. */
1722 /* * Injected context register JSQR setting is simple: register is fully */
1723 /* defined on one call of this function (for injected rank 1) and can */
1724 /* be entered into queue directly. */
1725 /* - if scan mode is enabled: */
1726 /* * Injected channels sequence length is set to parameter */
1727 /* "InjectedNbrOfConversion". */
1728 /* * Injected context register JSQR setting more complex: register is */
1729 /* fully defined over successive calls of this function, for each */
1730 /* injected channel rank. It is entered into queue only when all */
1731 /* injected ranks have been set. */
1732 /* Note: Scan mode is not present by hardware on this device, but used */
1733 /* by software for alignment over all STM32 devices. */
1734
1735 if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
1736 (sConfigInjected->InjectedNbrOfConversion == 1U))
1737 {
1738 /* Configuration of context register JSQR: */
1739 /* - number of ranks in injected group sequencer: fixed to 1st rank */
1740 /* (scan mode disabled, only rank 1 used) */
1741 /* - external trigger to start conversion */
1742 /* - external trigger polarity */
1743 /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
1744
1745 if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
1746 {
1747 /* Enable external trigger if trigger selection is different of */
1748 /* software start. */
1749 /* Note: This configuration keeps the hardware feature of parameter */
1750 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
1751 /* software start. */
1752 if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
1753 {
1754 tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
1755 | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
1756 | sConfigInjected->ExternalTrigInjecConvEdge
1757 );
1758 }
1759 else
1760 {
1761 tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
1762 }
1763
1764 MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt);
1765 /* For debug and informative reasons, hadc handle saves JSQR setting */
1766 hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
1767
1768 }
1769 }
1770 else
1771 {
1772 /* Case of scan mode enabled, several channels to set into injected group */
1773 /* sequencer. */
1774 /* */
1775 /* Procedure to define injected context register JSQR over successive */
1776 /* calls of this function, for each injected channel rank: */
1777 /* 1. Start new context and set parameters related to all injected */
1778 /* channels: injected sequence length and trigger. */
1779
1780 /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
1781 /* call of the context under setting */
1782 if (hadc->InjectionConfig.ChannelCount == 0U)
1783 {
1784 /* Initialize number of channels that will be configured on the context */
1785 /* being built */
1786 hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
1787 /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
1788 call, this context will be written in JSQR register at the last call.
1789 At this point, the context is merely reset */
1790 hadc->InjectionConfig.ContextQueue = 0x00000000U;
1791
1792 /* Configuration of context register JSQR: */
1793 /* - number of ranks in injected group sequencer */
1794 /* - external trigger to start conversion */
1795 /* - external trigger polarity */
1796
1797 /* Enable external trigger if trigger selection is different of */
1798 /* software start. */
1799 /* Note: This configuration keeps the hardware feature of parameter */
1800 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
1801 /* software start. */
1802 if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
1803 {
1804 tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U)
1805 | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
1806 | sConfigInjected->ExternalTrigInjecConvEdge
1807 );
1808 }
1809 else
1810 {
1811 tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U));
1812 }
1813
1814 }
1815
1816 /* 2. Continue setting of context under definition with parameter */
1817 /* related to each channel: channel rank sequence */
1818 /* Clear the old JSQx bits for the selected rank */
1819 tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
1820
1821 /* Set the JSQx bits for the selected rank */
1822 tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
1823
1824 /* Decrease channel count */
1825 hadc->InjectionConfig.ChannelCount--;
1826
1827 /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
1828 call, aggregate the setting to those already built during the previous
1829 HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */
1830 hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
1831
1832 /* 4. End of context setting: if this is the last channel set, then write context
1833 into register JSQR and make it enter into queue */
1834 if (hadc->InjectionConfig.ChannelCount == 0U)
1835 {
1836 MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
1837 }
1838 }
1839
1840 /* Parameters update conditioned to ADC state: */
1841 /* Parameters that can be updated when ADC is disabled or enabled without */
1842 /* conversion on going on injected group: */
1843 /* - Injected context queue: Queue disable (active context is kept) or */
1844 /* enable (context decremented, up to 2 contexts queued) */
1845 /* - Injected discontinuous mode: can be enabled only if auto-injected */
1846 /* mode is disabled. */
1847 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
1848 {
1849 /* If auto-injected mode is disabled: no constraint */
1850 if (sConfigInjected->AutoInjectedConv == DISABLE)
1851 {
1852 MODIFY_REG(hadc->Instance->CFGR,
1853 ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
1854 ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) |
1855 ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode));
1856 }
1857 /* If auto-injected mode is enabled: Injected discontinuous setting is */
1858 /* discarded. */
1859 else
1860 {
1861 MODIFY_REG(hadc->Instance->CFGR,
1862 ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
1863 ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext));
1864 }
1865
1866 }
1867
1868 /* Parameters update conditioned to ADC state: */
1869 /* Parameters that can be updated when ADC is disabled or enabled without */
1870 /* conversion on going on regular and injected groups: */
1871 /* - Automatic injected conversion: can be enabled if injected group */
1872 /* external triggers are disabled. */
1873 /* - Channel sampling time */
1874 /* - Channel offset */
1875 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
1876 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
1877
1878 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
1879 && (tmp_adc_is_conversion_on_going_injected == 0UL)
1880 )
1881 {
1882 /* If injected group external triggers are disabled (set to injected */
1883 /* software start): no constraint */
1884 if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
1885 || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
1886 {
1887 if (sConfigInjected->AutoInjectedConv == ENABLE)
1888 {
1889 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
1890 }
1891 else
1892 {
1893 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
1894 }
1895 }
1896 /* If Automatic injected conversion was intended to be set and could not */
1897 /* due to injected group external triggers enabled, error is reported. */
1898 else
1899 {
1900 if (sConfigInjected->AutoInjectedConv == ENABLE)
1901 {
1902 /* Update ADC state machine to error */
1903 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1904
1905 tmp_hal_status = HAL_ERROR;
1906 }
1907 else
1908 {
1909 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
1910 }
1911 }
1912
1913 if (sConfigInjected->InjecOversamplingMode == ENABLE)
1914 {
1915 assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
1916 assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
1917
1918 /* JOVSE must be reset in case of triggered regular mode */
1919 assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
1920
1921 /* Configuration of Injected Oversampler: */
1922 /* - Oversampling Ratio */
1923 /* - Right bit shift */
1924
1925 /* Enable OverSampling mode */
1926 MODIFY_REG(hadc->Instance->CFGR2,
1927 ADC_CFGR2_JOVSE |
1928 ADC_CFGR2_OVSR |
1929 ADC_CFGR2_OVSS,
1930 ADC_CFGR2_JOVSE |
1931 sConfigInjected->InjecOversampling.Ratio |
1932 sConfigInjected->InjecOversampling.RightBitShift
1933 );
1934 }
1935 else
1936 {
1937 /* Disable Regular OverSampling */
1938 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
1939 }
1940
1941 /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
1942 if (sConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5)
1943 {
1944 /* Set sampling time of the selected ADC channel */
1945 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
1946
1947 /* Set ADC sampling time common configuration */
1948 LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
1949 }
1950 else
1951 {
1952 /* Set sampling time of the selected ADC channel */
1953 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime);
1954
1955 /* Set ADC sampling time common configuration */
1956 LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
1957 }
1958
1959 /* Configure the offset: offset enable/disable, channel, offset value */
1960
1961 /* Shift the offset with respect to the selected ADC resolution. */
1962 /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
1963 tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
1964
1965 if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
1966 {
1967 /* Set ADC selected offset number */
1968 LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel,
1969 tmpOffsetShifted);
1970
1971 /* Set ADC selected offset sign & saturation */
1972 LL_ADC_SetOffsetSign(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedOffsetSign);
1973 LL_ADC_SetOffsetSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber,
1974 (sConfigInjected->InjectedOffsetSaturation == ENABLE) ? LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE);
1975 }
1976 else
1977 {
1978 /* Scan each offset register to check if the selected channel is targeted. */
1979 /* If this is the case, the corresponding offset number is disabled. */
1980 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
1981 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
1982 {
1983 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
1984 }
1985 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
1986 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
1987 {
1988 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
1989 }
1990 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
1991 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
1992 {
1993 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
1994 }
1995 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
1996 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
1997 {
1998 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
1999 }
2000 }
2001
2002 }
2003
2004 /* Parameters update conditioned to ADC state: */
2005 /* Parameters that can be updated only when ADC is disabled: */
2006 /* - Single or differential mode */
2007 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2008 {
2009 /* Set mode single-ended or differential input of the selected ADC channel */
2010 LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff);
2011
2012 /* Configuration of differential mode */
2013 /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
2014 if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
2015 {
2016 /* Set sampling time of the selected ADC channel */
2017 LL_ADC_SetChannelSamplingTime(hadc->Instance,
2018 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel)
2019 + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime);
2020 }
2021
2022 }
2023
2024 /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
2025 /* internal measurement paths enable: If internal channel selected, */
2026 /* enable dedicated internal buffers and path. */
2027 /* Note: these internal measurement paths can be disabled using */
2028 /* HAL_ADC_DeInit(). */
2029
2030 if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
2031 {
2032 tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2033
2034 /* If the requested internal measurement path has already been enabled, */
2035 /* bypass the configuration processing. */
2036 if (((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC1)
2037 || (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC5))
2038 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
2039 {
2040 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
2041 {
2042 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2043 LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
2044
2045 /* Delay for temperature sensor stabilization time */
2046 /* Wait loop initialization and execution */
2047 /* Note: Variable divided by 2 to compensate partially */
2048 /* CPU processing cycles, scaling in us split to not */
2049 /* exceed 32 bits register capacity and handle low frequency. */
2050 wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL));
2051 while (wait_loop_index != 0UL)
2052 {
2053 wait_loop_index--;
2054 }
2055 }
2056 }
2057 else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
2058 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
2059 {
2060 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
2061 {
2062 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2063 LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
2064 }
2065 }
2066 else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
2067 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
2068 {
2069 if (ADC_VREFINT_INSTANCE(hadc))
2070 {
2071 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2072 LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
2073 }
2074 }
2075 else
2076 {
2077 /* nothing to do */
2078 }
2079 }
2080
2081 /* Process unlocked */
2082 __HAL_UNLOCK(hadc);
2083
2084 /* Return function status */
2085 return tmp_hal_status;
2086 }
2087
2088 #if defined(ADC_MULTIMODE_SUPPORT)
2089 /**
2090 * @brief Enable ADC multimode and configure multimode parameters
2091 * @note Possibility to update parameters on the fly:
2092 * This function initializes multimode parameters, following
2093 * calls to this function can be used to reconfigure some parameters
2094 * of structure "ADC_MultiModeTypeDef" on the fly, without resetting
2095 * the ADCs.
2096 * The setting of these parameters is conditioned to ADC state.
2097 * For parameters constraints, see comments of structure
2098 * "ADC_MultiModeTypeDef".
2099 * @note To move back configuration from multimode to single mode, ADC must
2100 * be reset (using function HAL_ADC_Init() ).
2101 * @param hadc Master ADC handle
2102 * @param multimode Structure of ADC multimode configuration
2103 * @retval HAL status
2104 */
HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef * hadc,ADC_MultiModeTypeDef * multimode)2105 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
2106 {
2107 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2108 ADC_Common_TypeDef *tmpADC_Common;
2109 ADC_HandleTypeDef tmphadcSlave;
2110 uint32_t tmphadcSlave_conversion_on_going;
2111
2112 /* Check the parameters */
2113 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
2114 assert_param(IS_ADC_MULTIMODE(multimode->Mode));
2115 if (multimode->Mode != ADC_MODE_INDEPENDENT)
2116 {
2117 assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode));
2118 assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
2119 }
2120
2121 /* Process locked */
2122 __HAL_LOCK(hadc);
2123
2124 /* Temporary handle minimum initialization */
2125 __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
2126 ADC_CLEAR_ERRORCODE(&tmphadcSlave);
2127
2128 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
2129
2130 if (tmphadcSlave.Instance == NULL)
2131 {
2132 /* Update ADC state machine to error */
2133 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2134
2135 /* Process unlocked */
2136 __HAL_UNLOCK(hadc);
2137
2138 return HAL_ERROR;
2139 }
2140
2141 /* Parameters update conditioned to ADC state: */
2142 /* Parameters that can be updated when ADC is disabled or enabled without */
2143 /* conversion on going on regular group: */
2144 /* - Multimode DMA configuration */
2145 /* - Multimode DMA mode */
2146 tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
2147 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2148 && (tmphadcSlave_conversion_on_going == 0UL))
2149 {
2150 /* Pointer to the common control register */
2151 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
2152
2153 /* If multimode is selected, configure all multimode parameters. */
2154 /* Otherwise, reset multimode parameters (can be used in case of */
2155 /* transition from multimode to independent mode). */
2156 if (multimode->Mode != ADC_MODE_INDEPENDENT)
2157 {
2158 MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
2159 multimode->DMAAccessMode |
2160 ADC_CCR_MULTI_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
2161
2162 /* Parameters that can be updated only when ADC is disabled: */
2163 /* - Multimode mode selection */
2164 /* - Multimode delay */
2165 /* Note: Delay range depends on selected resolution: */
2166 /* from 1 to 12 clock cycles for 12 bits */
2167 /* from 1 to 10 clock cycles for 10 bits, */
2168 /* from 1 to 8 clock cycles for 8 bits */
2169 /* from 1 to 6 clock cycles for 6 bits */
2170 /* If a higher delay is selected, it will be clipped to maximum delay */
2171 /* range */
2172 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
2173 {
2174 MODIFY_REG(tmpADC_Common->CCR,
2175 ADC_CCR_DUAL |
2176 ADC_CCR_DELAY,
2177 multimode->Mode |
2178 multimode->TwoSamplingDelay
2179 );
2180 }
2181 }
2182 else /* ADC_MODE_INDEPENDENT */
2183 {
2184 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
2185
2186 /* Parameters that can be updated only when ADC is disabled: */
2187 /* - Multimode mode selection */
2188 /* - Multimode delay */
2189 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
2190 {
2191 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
2192 }
2193 }
2194 }
2195 /* If one of the ADC sharing the same common group is enabled, no update */
2196 /* could be done on neither of the multimode structure parameters. */
2197 else
2198 {
2199 /* Update ADC state machine to error */
2200 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2201
2202 tmp_hal_status = HAL_ERROR;
2203 }
2204
2205 /* Process unlocked */
2206 __HAL_UNLOCK(hadc);
2207
2208 /* Return function status */
2209 return tmp_hal_status;
2210 }
2211 #endif /* ADC_MULTIMODE_SUPPORT */
2212
2213 /**
2214 * @brief Enable Injected Queue
2215 * @note This function resets CFGR register JQDIS bit in order to enable the
2216 * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
2217 * are both equal to 0 to ensure that no regular nor injected
2218 * conversion is ongoing.
2219 * @param hadc ADC handle
2220 * @retval HAL status
2221 */
HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef * hadc)2222 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc)
2223 {
2224 HAL_StatusTypeDef tmp_hal_status;
2225 uint32_t tmp_adc_is_conversion_on_going_regular;
2226 uint32_t tmp_adc_is_conversion_on_going_injected;
2227
2228 /* Check the parameters */
2229 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2230
2231 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2232 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2233
2234 /* Parameter can be set only if no conversion is on-going */
2235 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
2236 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2237 )
2238 {
2239 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
2240
2241 /* Update state, clear previous result related to injected queue overflow */
2242 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
2243
2244 tmp_hal_status = HAL_OK;
2245 }
2246 else
2247 {
2248 tmp_hal_status = HAL_ERROR;
2249 }
2250
2251 return tmp_hal_status;
2252 }
2253
2254 /**
2255 * @brief Disable Injected Queue
2256 * @note This function sets CFGR register JQDIS bit in order to disable the
2257 * Injected Queue. JQDIS can be written only when ADSTART and JDSTART
2258 * are both equal to 0 to ensure that no regular nor injected
2259 * conversion is ongoing.
2260 * @param hadc ADC handle
2261 * @retval HAL status
2262 */
HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef * hadc)2263 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc)
2264 {
2265 HAL_StatusTypeDef tmp_hal_status;
2266 uint32_t tmp_adc_is_conversion_on_going_regular;
2267 uint32_t tmp_adc_is_conversion_on_going_injected;
2268
2269 /* Check the parameters */
2270 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2271
2272 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2273 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2274
2275 /* Parameter can be set only if no conversion is on-going */
2276 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
2277 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2278 )
2279 {
2280 LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE);
2281 tmp_hal_status = HAL_OK;
2282 }
2283 else
2284 {
2285 tmp_hal_status = HAL_ERROR;
2286 }
2287
2288 return tmp_hal_status;
2289 }
2290
2291 /**
2292 * @brief Disable ADC voltage regulator.
2293 * @note Disabling voltage regulator allows to save power. This operation can
2294 * be carried out only when ADC is disabled.
2295 * @note To enable again the voltage regulator, the user is expected to
2296 * resort to HAL_ADC_Init() API.
2297 * @param hadc ADC handle
2298 * @retval HAL status
2299 */
HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef * hadc)2300 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
2301 {
2302 HAL_StatusTypeDef tmp_hal_status;
2303
2304 /* Check the parameters */
2305 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2306
2307 /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
2308 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2309 {
2310 LL_ADC_DisableInternalRegulator(hadc->Instance);
2311 tmp_hal_status = HAL_OK;
2312 }
2313 else
2314 {
2315 tmp_hal_status = HAL_ERROR;
2316 }
2317
2318 return tmp_hal_status;
2319 }
2320
2321 /**
2322 * @brief Enter ADC deep-power-down mode
2323 * @note This mode is achieved in setting DEEPPWD bit and allows to save power
2324 * in reducing leakage currents. It is particularly interesting before
2325 * entering stop modes.
2326 * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the
2327 * ADC voltage regulator. This means that this API encompasses
2328 * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
2329 * calibration is lost.
2330 * @note To exit the ADC deep-power-down mode, the user is expected to
2331 * resort to HAL_ADC_Init() API as well as to relaunch a calibration
2332 * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
2333 * saved calibration factor.
2334 * @param hadc ADC handle
2335 * @retval HAL status
2336 */
HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef * hadc)2337 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
2338 {
2339 HAL_StatusTypeDef tmp_hal_status;
2340
2341 /* Check the parameters */
2342 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2343
2344 /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
2345 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2346 {
2347 LL_ADC_EnableDeepPowerDown(hadc->Instance);
2348 tmp_hal_status = HAL_OK;
2349 }
2350 else
2351 {
2352 tmp_hal_status = HAL_ERROR;
2353 }
2354
2355 return tmp_hal_status;
2356 }
2357
2358 /**
2359 * @}
2360 */
2361
2362 /**
2363 * @}
2364 */
2365
2366 #endif /* HAL_ADC_MODULE_ENABLED */
2367 /**
2368 * @}
2369 */
2370
2371 /**
2372 * @}
2373 */
2374
