1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_utils.h
4 * @author MCD Application Team
5 * @brief Header file of UTILS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL UTILS driver contains a set of generic APIs that can be
23 used by user:
24 (+) Device electronic signature
25 (+) Timing functions
26 (+) PLL configuration functions
27
28 @endverbatim
29 */
30
31 /* Define to prevent recursive inclusion -------------------------------------*/
32 #ifndef STM32G4xx_LL_UTILS_H
33 #define STM32G4xx_LL_UTILS_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32g4xx.h"
41
42 /** @addtogroup STM32G4xx_LL_Driver
43 * @{
44 */
45
46 /** @defgroup UTILS_LL UTILS
47 * @{
48 */
49
50 /* Private types -------------------------------------------------------------*/
51 /* Private variables ---------------------------------------------------------*/
52
53 /* Private constants ---------------------------------------------------------*/
54 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
55 * @{
56 */
57
58 /* Max delay can be used in LL_mDelay */
59 #define LL_MAX_DELAY 0xFFFFFFFFU
60
61 /**
62 * @brief Unique device ID register base address
63 */
64 #define UID_BASE_ADDRESS UID_BASE
65
66 /**
67 * @brief Flash size data register base address
68 */
69 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
70
71 /**
72 * @brief Package data register base address
73 */
74 #define PACKAGE_BASE_ADDRESS PACKAGE_BASE
75
76 /**
77 * @}
78 */
79
80 /* Private macros ------------------------------------------------------------*/
81 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
82 * @{
83 */
84 /**
85 * @}
86 */
87 /* Exported types ------------------------------------------------------------*/
88 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
89 * @{
90 */
91 /**
92 * @brief UTILS PLL structure definition
93 */
94 typedef struct
95 {
96 uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
97 This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
98
99 This feature can be modified afterwards using unitary function
100 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
101
102 uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
103 This parameter must be a number between Min_Data = 8 and Max_Data = 86
104
105 This feature can be modified afterwards using unitary function
106 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
107
108 uint32_t PLLR; /*!< Division for the main system clock.
109 This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
110
111 This feature can be modified afterwards using unitary function
112 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
113 } LL_UTILS_PLLInitTypeDef;
114
115 /**
116 * @brief UTILS System, AHB and APB buses clock configuration structure definition
117 */
118 typedef struct
119 {
120 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
121 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
122
123 This feature can be modified afterwards using unitary function
124 @ref LL_RCC_SetAHBPrescaler(). */
125
126 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
127 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
128
129 This feature can be modified afterwards using unitary function
130 @ref LL_RCC_SetAPB1Prescaler(). */
131
132 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
133 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
134
135 This feature can be modified afterwards using unitary function
136 @ref LL_RCC_SetAPB2Prescaler(). */
137
138 } LL_UTILS_ClkInitTypeDef;
139
140 /**
141 * @}
142 */
143
144 /* Exported constants --------------------------------------------------------*/
145 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
146 * @{
147 */
148
149 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
150 * @{
151 */
152 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
153 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
154 /**
155 * @}
156 */
157
158 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
159 * @{
160 */
161 #define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */
162 #define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */
163 #define LL_UTILS_PACKAGETYPE_WLCSP81 0x00000005U /*!< WLCSP81 package type */
164 #define LL_UTILS_PACKAGETYPE_LQFP128 0x00000007U /*!< LQFP128 package type */
165 #define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000008U /*!< UFQFPN32 package type */
166 #define LL_UTILS_PACKAGETYPE_LQFP32 0x00000009U /*!< LQFP32 package type */
167 #define LL_UTILS_PACKAGETYPE_UFQFPN48 0x0000000AU /*!< UFQFPN48 package type */
168 #define LL_UTILS_PACKAGETYPE_LQFP48 0x0000000BU /*!< LQFP48 package type */
169 #define LL_UTILS_PACKAGETYPE_WLCSP49 0x0000000CU /*!< WLCSP49 package type */
170 #define LL_UTILS_PACKAGETYPE_UFBGA64 0x0000000DU /*!< UFBGA64 package type */
171 #define LL_UTILS_PACKAGETYPE_UFBGA100 0x0000000EU /*!< UFBGA100 package type */
172 #define LL_UTILS_PACKAGETYPE_LQFP48_EBIKE 0x00000010U /*!< LQFP48 EBIKE package type */
173
174 /**
175 * @}
176 */
177
178 /**
179 * @}
180 */
181
182 /* Exported macro ------------------------------------------------------------*/
183
184 /* Exported functions --------------------------------------------------------*/
185 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
186 * @{
187 */
188
189 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
190 * @{
191 */
192
193 /**
194 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
195 * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
196 */
LL_GetUID_Word0(void)197 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
198 {
199 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
200 }
201
202 /**
203 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
204 * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
205 */
LL_GetUID_Word1(void)206 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
207 {
208 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
209 }
210
211 /**
212 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
213 * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
214 */
LL_GetUID_Word2(void)215 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
216 {
217 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
218 }
219
220 /**
221 * @brief Get Flash memory size
222 * @note This bitfield indicates the size of the device Flash memory expressed in
223 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
224 * @retval FLASH_SIZE[15:0]: Flash memory size
225 */
LL_GetFlashSize(void)226 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
227 {
228 return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0x0000FFFFUL);
229 }
230
231 /**
232 * @brief Get Package type
233 * @retval Returned value can be one of the following values:
234 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64
235 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
236 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP81
237 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP128
238 * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32
239 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP32
240 * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48
241 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48
242 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP49
243 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64
244 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100
245 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48_EBIKE
246 *
247 */
LL_GetPackageType(void)248 __STATIC_INLINE uint32_t LL_GetPackageType(void)
249 {
250 return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
251 }
252
253 /**
254 * @}
255 */
256
257 /** @defgroup UTILS_LL_EF_DELAY DELAY
258 * @{
259 */
260
261 /**
262 * @brief This function configures the Cortex-M SysTick source of the time base.
263 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
264 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
265 * configuration by calling this function, for a delay use rather osDelay RTOS service.
266 * @param Ticks Number of ticks
267 * @retval None
268 */
LL_InitTick(uint32_t HCLKFrequency,uint32_t Ticks)269 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
270 {
271 /* Configure the SysTick to have interrupt in 1ms time base */
272 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
273 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
274 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
275 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
276 }
277
278 void LL_Init1msTick(uint32_t HCLKFrequency);
279 void LL_mDelay(uint32_t Delay);
280
281 /**
282 * @}
283 */
284
285 /** @defgroup UTILS_EF_SYSTEM SYSTEM
286 * @{
287 */
288
289 void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
290 ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
291 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
292 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
293 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
294 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
295
296 /**
297 * @}
298 */
299
300 /**
301 * @}
302 */
303
304 /**
305 * @}
306 */
307
308 /**
309 * @}
310 */
311
312 #ifdef __cplusplus
313 }
314 #endif
315
316 #endif /* STM32G4xx_LL_UTILS_H */
317
318
