1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL SYSTEM driver contains a set of generic APIs that can be
23 used by user:
24 (+) Some of the FLASH features need to be handled in the SYSTEM file.
25 (+) Access to DBGCMU registers
26 (+) Access to SYSCFG registers
27 (+) Access to VREFBUF registers
28
29 @endverbatim
30 ******************************************************************************
31 */
32
33 /* Define to prevent recursive inclusion -------------------------------------*/
34 #ifndef __STM32G4xx_LL_SYSTEM_H
35 #define __STM32G4xx_LL_SYSTEM_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32g4xx.h"
43
44 /** @addtogroup STM32G4xx_LL_Driver
45 * @{
46 */
47
48 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
49
50 /** @defgroup SYSTEM_LL SYSTEM
51 * @{
52 */
53
54 /* Private types -------------------------------------------------------------*/
55 /* Private variables ---------------------------------------------------------*/
56
57 /* Private constants ---------------------------------------------------------*/
58 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
59 * @{
60 */
61
62 /* Defines used for position in the register */
63 #define DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
64
65 /**
66 * @brief Power-down in Run mode Flash key
67 */
68 #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */
69 #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1
70 to unlock the RUN_PD bit in FLASH_ACR */
71
72 /**
73 * @}
74 */
75
76 /* Private macros ------------------------------------------------------------*/
77
78 /* Exported types ------------------------------------------------------------*/
79 /* Exported constants --------------------------------------------------------*/
80 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
81 * @{
82 */
83
84 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
85 * @{
86 */
87 #define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */
88 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
89 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */
90 #if defined(FMC_Bank1_R)
91 #define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */
92 #endif /* FMC_Bank1_R */
93 #define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000 */
94 /**
95 * @}
96 */
97
98 #if defined(SYSCFG_MEMRMP_FB_MODE)
99 /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
100 * @{
101 */
102 #define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)
103 and Flash Bank2 mapped at 0x08040000 (and aliased at 0x00080000) */
104 #define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
105 and Flash Bank1 mapped at 0x08040000 (and aliased at 0x00080000) */
106 /**
107 * @}
108 */
109
110 #endif /* SYSCFG_MEMRMP_FB_MODE */
111 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
112 * @{
113 */
114 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
115 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
116 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
117 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
118 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
119 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
120 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
121 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
122 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
123 #if defined(I2C2)
124 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
125 #endif /* I2C2 */
126 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
127 #if defined(I2C4)
128 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
129 #endif /* I2C4 */
130 /**
131 * @}
132 */
133
134 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
135 * @{
136 */
137 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
138 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
139 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
140 #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
141 #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
142 #define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */
143 #define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */
144 /**
145 * @}
146 */
147
148 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
149 * @{
150 */
151 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)((0x000FU << 16U) | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */
152 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)((0x00F0U << 16U) | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */
153 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)((0x0F00U << 16U) | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */
154 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)((0xF000U << 16U) | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */
155 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)((0x000FU << 16U) | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */
156 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)((0x00F0U << 16U) | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */
157 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)((0x0F00U << 16U) | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */
158 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)((0xF000U << 16U) | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */
159 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)((0x000FU << 16U) | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */
160 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)((0x00F0U << 16U) | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */
161 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)((0x0F00U << 16U) | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */
162 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)((0xF000U << 16U) | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */
163 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)((0x000FU << 16U) | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */
164 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)((0x00F0U << 16U) | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */
165 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)((0x0F00U << 16U) | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */
166 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)((0xF000U << 16U) | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */
167 /**
168 * @}
169 */
170
171 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
172 * @{
173 */
174 #define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
175 with Break Input of TIM1/8/15/16/17 */
176 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
177 with TIM1/8/15/16/17 Break Input
178 and also the PVDE and PLS bits of the Power Control Interface */
179 #define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal
180 with Break Input of TIM1/8/15/16/17 */
181 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4
182 with Break Input of TIM1/15/16/17 */
183 /**
184 * @}
185 */
186
187 /** @defgroup SYSTEM_LL_EC_CCMSRAMWRP SYSCFG CCMSRAM WRP
188 * @{
189 */
190 #define LL_SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< CCMSRAM Write protection page 0 */
191 #define LL_SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< CCMSRAM Write protection page 1 */
192 #define LL_SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< CCMSRAM Write protection page 2 */
193 #define LL_SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< CCMSRAM Write protection page 3 */
194 #define LL_SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< CCMSRAM Write protection page 4 */
195 #define LL_SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< CCMSRAM Write protection page 5 */
196 #define LL_SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< CCMSRAM Write protection page 6 */
197 #define LL_SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< CCMSRAM Write protection page 7 */
198 #define LL_SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< CCMSRAM Write protection page 8 */
199 #define LL_SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< CCMSRAM Write protection page 9 */
200 #if defined(SYSCFG_SWPR_PAGE10)
201 #define LL_SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */
202 #define LL_SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */
203 #define LL_SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */
204 #define LL_SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */
205 #define LL_SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */
206 #define LL_SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */
207 #define LL_SYSCFG_CCMSRAMWRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */
208 #define LL_SYSCFG_CCMSRAMWRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */
209 #define LL_SYSCFG_CCMSRAMWRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */
210 #define LL_SYSCFG_CCMSRAMWRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */
211 #define LL_SYSCFG_CCMSRAMWRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */
212 #define LL_SYSCFG_CCMSRAMWRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */
213 #define LL_SYSCFG_CCMSRAMWRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */
214 #define LL_SYSCFG_CCMSRAMWRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */
215 #define LL_SYSCFG_CCMSRAMWRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */
216 #define LL_SYSCFG_CCMSRAMWRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */
217 #define LL_SYSCFG_CCMSRAMWRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */
218 #define LL_SYSCFG_CCMSRAMWRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */
219 #define LL_SYSCFG_CCMSRAMWRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */
220 #define LL_SYSCFG_CCMSRAMWRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */
221 #define LL_SYSCFG_CCMSRAMWRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */
222 #define LL_SYSCFG_CCMSRAMWRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */
223 #endif /* SYSCFG_SWPR_PAGE10 */
224 /**
225 * @}
226 */
227
228 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
229 * @{
230 */
231 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
232 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
233 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
234 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
235 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
236 /**
237 * @}
238 */
239
240 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
241 * @{
242 */
243 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/
244 #if defined(TIM3)
245 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/
246 #endif /* TIM3 */
247 #if defined(TIM4)
248 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/
249 #endif /* TIM4 */
250 #if defined(TIM5)
251 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/
252 #endif /* TIM5 */
253 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/
254 #if defined(TIM7)
255 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/
256 #endif /* TIM7 */
257 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted*/
258 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/
259 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/
260 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/
261 #if defined(I2C2)
262 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/
263 #endif /* I2C2 */
264 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen*/
265 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
266 /**
267 * @}
268 */
269
270 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
271 * @{
272 */
273 #if defined(I2C4)
274 #define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/
275 #endif /* I2C4 */
276 /**
277 * @}
278 */
279
280 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
281 * @{
282 */
283 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/
284 #if defined(TIM8)
285 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/
286 #endif /* TIM8 */
287 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/
288 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/
289 #if defined(TIM17)
290 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/
291 #endif /* TIM17 */
292 #if defined(TIM20)
293 #define LL_DBGMCU_APB2_GRP1_TIM20_STOP DBGMCU_APB2FZ_DBG_TIM20_STOP /*!< The counter clock of TIM20 is stopped when the core is halted*/
294 #endif /* TIM20 */
295 #if defined(HRTIM1)
296 #define LL_DBGMCU_APB2_GRP1_HRTIM1_STOP DBGMCU_APB2FZ_DBG_HRTIM1_STOP /*!< The counter clock of HRTIM1 is stopped when the core is halted*/
297 #endif /* HRTIM1 */
298 /**
299 * @}
300 */
301
302 #if defined(VREFBUF)
303 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
304 * @{
305 */
306 #define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */
307 #define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V) */
308 #define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V) */
309 /**
310 * @}
311 */
312 #endif /* VREFBUF */
313
314 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
315 * @{
316 */
317 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
318 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
319 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
320 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
321 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
322 #if defined(FLASH_ACR_LATENCY_5WS)
323 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
324 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
325 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
326 #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */
327 #define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
328 #define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
329 #define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
330 #define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
331 #define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
332 #define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
333 #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
334 #endif /* FLASH_ACR_LATENCY_5WS */
335 /**
336 * @}
337 */
338
339 /**
340 * @}
341 */
342
343 /* Exported macro ------------------------------------------------------------*/
344
345 /* Exported functions --------------------------------------------------------*/
346 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
347 * @{
348 */
349
350 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
351 * @{
352 */
353
354 /**
355 * @brief Set memory mapping at address 0x00000000
356 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
357 * @param Memory This parameter can be one of the following values:
358 * @arg @ref LL_SYSCFG_REMAP_FLASH
359 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
360 * @arg @ref LL_SYSCFG_REMAP_SRAM
361 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
362 * @arg @ref LL_SYSCFG_REMAP_QUADSPI (*)
363 *
364 * (*) value not defined in all devices
365 * @retval None
366 */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)367 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
368 {
369 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
370 }
371
372 /**
373 * @brief Get memory mapping at address 0x00000000
374 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
375 * @retval Returned value can be one of the following values:
376 * @arg @ref LL_SYSCFG_REMAP_FLASH
377 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
378 * @arg @ref LL_SYSCFG_REMAP_SRAM
379 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
380 * @arg @ref LL_SYSCFG_REMAP_QUADSPI (*)
381 *
382 * (*) value not defined in all devices
383 */
LL_SYSCFG_GetRemapMemory(void)384 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
385 {
386 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
387 }
388
389 #if defined(SYSCFG_MEMRMP_FB_MODE)
390 /**
391 * @brief Select Flash bank mode (Bank flashed at 0x08000000)
392 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode
393 * @param Bank This parameter can be one of the following values:
394 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
395 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
396 * @retval None
397 */
LL_SYSCFG_SetFlashBankMode(uint32_t Bank)398 __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
399 {
400 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
401 }
402
403 /**
404 * @brief Get Flash bank mode (Bank flashed at 0x08000000)
405 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode
406 * @retval Returned value can be one of the following values:
407 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
408 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
409 */
LL_SYSCFG_GetFlashBankMode(void)410 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
411 {
412 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
413 }
414 #endif /* SYSCFG_MEMRMP_FB_MODE */
415
416 /**
417 * @brief Enable I/O analog switch voltage booster.
418 * @note When voltage booster is enabled, I/O analog switches are supplied
419 * by a dedicated voltage booster, from VDD power domain. This is
420 * the recommended configuration with low VDDA voltage operation.
421 * @note The I/O analog switch voltage booster is relevant for peripherals
422 * using I/O in analog input: ADC, COMP, OPAMP.
423 * However, COMP and OPAMP inputs have a high impedance and
424 * voltage booster do not impact performance significantly.
425 * Therefore, the voltage booster is mainly intended for
426 * usage with ADC.
427 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
428 * @retval None
429 */
LL_SYSCFG_EnableAnalogBooster(void)430 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
431 {
432 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
433 }
434
435 /**
436 * @brief Disable I/O analog switch voltage booster.
437 * @note When voltage booster is enabled, I/O analog switches are supplied
438 * by a dedicated voltage booster, from VDD power domain. This is
439 * the recommended configuration with low VDDA voltage operation.
440 * @note The I/O analog switch voltage booster is relevant for peripherals
441 * using I/O in analog input: ADC, COMP, OPAMP.
442 * However, COMP and OPAMP inputs have a high impedance and
443 * voltage booster do not impact performance significantly.
444 * Therefore, the voltage booster is mainly intended for
445 * usage with ADC.
446 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
447 * @retval None
448 */
LL_SYSCFG_DisableAnalogBooster(void)449 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
450 {
451 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
452 }
453
454 /**
455 * @brief Enable the I2C fast mode plus driving capability.
456 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
457 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
458 * @param ConfigFastModePlus This parameter can be a combination of the following values:
459 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
460 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
461 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
462 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
463 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
464 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
465 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
466 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
467 *
468 * (*) value not defined in all devices
469 * @retval None
470 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)471 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
472 {
473 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
474 }
475
476 /**
477 * @brief Disable the I2C fast mode plus driving capability.
478 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
479 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
480 * @param ConfigFastModePlus This parameter can be a combination of the following values:
481 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
482 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
483 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
484 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
485 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
486 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
487 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
488 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
489 *
490 * (*) value not defined in all devices
491 * @retval None
492 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)493 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
494 {
495 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
496 }
497
498 /**
499 * @brief Enable Floating Point Unit Invalid operation Interrupt
500 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
501 * @retval None
502 */
LL_SYSCFG_EnableIT_FPU_IOC(void)503 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
504 {
505 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
506 }
507
508 /**
509 * @brief Enable Floating Point Unit Divide-by-zero Interrupt
510 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
511 * @retval None
512 */
LL_SYSCFG_EnableIT_FPU_DZC(void)513 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
514 {
515 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
516 }
517
518 /**
519 * @brief Enable Floating Point Unit Underflow Interrupt
520 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
521 * @retval None
522 */
LL_SYSCFG_EnableIT_FPU_UFC(void)523 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
524 {
525 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
526 }
527
528 /**
529 * @brief Enable Floating Point Unit Overflow Interrupt
530 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
531 * @retval None
532 */
LL_SYSCFG_EnableIT_FPU_OFC(void)533 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
534 {
535 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
536 }
537
538 /**
539 * @brief Enable Floating Point Unit Input denormal Interrupt
540 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
541 * @retval None
542 */
LL_SYSCFG_EnableIT_FPU_IDC(void)543 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
544 {
545 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
546 }
547
548 /**
549 * @brief Enable Floating Point Unit Inexact Interrupt
550 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
551 * @retval None
552 */
LL_SYSCFG_EnableIT_FPU_IXC(void)553 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
554 {
555 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
556 }
557
558 /**
559 * @brief Disable Floating Point Unit Invalid operation Interrupt
560 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
561 * @retval None
562 */
LL_SYSCFG_DisableIT_FPU_IOC(void)563 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
564 {
565 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
566 }
567
568 /**
569 * @brief Disable Floating Point Unit Divide-by-zero Interrupt
570 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
571 * @retval None
572 */
LL_SYSCFG_DisableIT_FPU_DZC(void)573 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
574 {
575 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
576 }
577
578 /**
579 * @brief Disable Floating Point Unit Underflow Interrupt
580 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
581 * @retval None
582 */
LL_SYSCFG_DisableIT_FPU_UFC(void)583 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
584 {
585 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
586 }
587
588 /**
589 * @brief Disable Floating Point Unit Overflow Interrupt
590 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
591 * @retval None
592 */
LL_SYSCFG_DisableIT_FPU_OFC(void)593 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
594 {
595 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
596 }
597
598 /**
599 * @brief Disable Floating Point Unit Input denormal Interrupt
600 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
601 * @retval None
602 */
LL_SYSCFG_DisableIT_FPU_IDC(void)603 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
604 {
605 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
606 }
607
608 /**
609 * @brief Disable Floating Point Unit Inexact Interrupt
610 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
611 * @retval None
612 */
LL_SYSCFG_DisableIT_FPU_IXC(void)613 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
614 {
615 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
616 }
617
618 /**
619 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
620 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
621 * @retval State of bit (1 or 0).
622 */
LL_SYSCFG_IsEnabledIT_FPU_IOC(void)623 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
624 {
625 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0)) ? 1UL : 0UL);
626 }
627
628 /**
629 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
630 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
631 * @retval State of bit (1 or 0).
632 */
LL_SYSCFG_IsEnabledIT_FPU_DZC(void)633 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
634 {
635 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1)) ? 1UL : 0UL);
636 }
637
638 /**
639 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
640 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
641 * @retval State of bit (1 or 0).
642 */
LL_SYSCFG_IsEnabledIT_FPU_UFC(void)643 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
644 {
645 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2)) ? 1UL : 0UL);
646 }
647
648 /**
649 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
650 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
651 * @retval State of bit (1 or 0).
652 */
LL_SYSCFG_IsEnabledIT_FPU_OFC(void)653 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
654 {
655 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3)) ? 1UL : 0UL);
656 }
657
658 /**
659 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
660 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
661 * @retval State of bit (1 or 0).
662 */
LL_SYSCFG_IsEnabledIT_FPU_IDC(void)663 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
664 {
665 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4)) ? 1UL : 0UL);
666 }
667
668 /**
669 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
670 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
671 * @retval State of bit (1 or 0).
672 */
LL_SYSCFG_IsEnabledIT_FPU_IXC(void)673 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
674 {
675 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5)) ? 1UL : 0UL);
676 }
677
678 /**
679 * @brief Configure source input for the EXTI external interrupt.
680 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
681 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
682 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
683 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
684 * @param Port This parameter can be one of the following values:
685 * @arg @ref LL_SYSCFG_EXTI_PORTA
686 * @arg @ref LL_SYSCFG_EXTI_PORTB
687 * @arg @ref LL_SYSCFG_EXTI_PORTC
688 * @arg @ref LL_SYSCFG_EXTI_PORTD
689 * @arg @ref LL_SYSCFG_EXTI_PORTE
690 * @arg @ref LL_SYSCFG_EXTI_PORTF
691 * @arg @ref LL_SYSCFG_EXTI_PORTG
692 *
693 * (*) value not defined in all devices
694 * @param Line This parameter can be one of the following values:
695 * @arg @ref LL_SYSCFG_EXTI_LINE0
696 * @arg @ref LL_SYSCFG_EXTI_LINE1
697 * @arg @ref LL_SYSCFG_EXTI_LINE2
698 * @arg @ref LL_SYSCFG_EXTI_LINE3
699 * @arg @ref LL_SYSCFG_EXTI_LINE4
700 * @arg @ref LL_SYSCFG_EXTI_LINE5
701 * @arg @ref LL_SYSCFG_EXTI_LINE6
702 * @arg @ref LL_SYSCFG_EXTI_LINE7
703 * @arg @ref LL_SYSCFG_EXTI_LINE8
704 * @arg @ref LL_SYSCFG_EXTI_LINE9
705 * @arg @ref LL_SYSCFG_EXTI_LINE10
706 * @arg @ref LL_SYSCFG_EXTI_LINE11
707 * @arg @ref LL_SYSCFG_EXTI_LINE12
708 * @arg @ref LL_SYSCFG_EXTI_LINE13
709 * @arg @ref LL_SYSCFG_EXTI_LINE14
710 * @arg @ref LL_SYSCFG_EXTI_LINE15
711 * @retval None
712 */
LL_SYSCFG_SetEXTISource(uint32_t Port,uint32_t Line)713 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
714 {
715 MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << (POSITION_VAL((Line >> 16U)) & 0x1FU) );
716 }
717
718 /**
719 * @brief Get the configured defined for specific EXTI Line
720 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
721 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
722 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
723 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
724 * @param Line This parameter can be one of the following values:
725 * @arg @ref LL_SYSCFG_EXTI_LINE0
726 * @arg @ref LL_SYSCFG_EXTI_LINE1
727 * @arg @ref LL_SYSCFG_EXTI_LINE2
728 * @arg @ref LL_SYSCFG_EXTI_LINE3
729 * @arg @ref LL_SYSCFG_EXTI_LINE4
730 * @arg @ref LL_SYSCFG_EXTI_LINE5
731 * @arg @ref LL_SYSCFG_EXTI_LINE6
732 * @arg @ref LL_SYSCFG_EXTI_LINE7
733 * @arg @ref LL_SYSCFG_EXTI_LINE8
734 * @arg @ref LL_SYSCFG_EXTI_LINE9
735 * @arg @ref LL_SYSCFG_EXTI_LINE10
736 * @arg @ref LL_SYSCFG_EXTI_LINE11
737 * @arg @ref LL_SYSCFG_EXTI_LINE12
738 * @arg @ref LL_SYSCFG_EXTI_LINE13
739 * @arg @ref LL_SYSCFG_EXTI_LINE14
740 * @arg @ref LL_SYSCFG_EXTI_LINE15
741 * @retval Returned value can be one of the following values:
742 * @arg @ref LL_SYSCFG_EXTI_PORTA
743 * @arg @ref LL_SYSCFG_EXTI_PORTB
744 * @arg @ref LL_SYSCFG_EXTI_PORTC
745 * @arg @ref LL_SYSCFG_EXTI_PORTD
746 * @arg @ref LL_SYSCFG_EXTI_PORTE
747 * @arg @ref LL_SYSCFG_EXTI_PORTF
748 * @arg @ref LL_SYSCFG_EXTI_PORTG
749 *
750 * (*) value not defined in all devices
751 */
LL_SYSCFG_GetEXTISource(uint32_t Line)752 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
753 {
754 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 0x1FU));
755 }
756
757 /**
758 * @brief Enable CCMSRAM Erase (starts a hardware CCMSRAM erase operation. This bit is
759 * automatically cleared at the end of the CCMSRAM erase operation.)
760 * @note This bit is write-protected: setting this bit is possible only after the
761 * correct key sequence is written in the SYSCFG_SKR register as described in
762 * the Reference Manual.
763 * @rmtoll SYSCFG_SCSR CCMER LL_SYSCFG_EnableCCMSRAMErase
764 * @retval None
765 */
LL_SYSCFG_EnableCCMSRAMErase(void)766 __STATIC_INLINE void LL_SYSCFG_EnableCCMSRAMErase(void)
767 {
768 /* Starts a hardware CCMSRAM erase operation*/
769 SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER);
770 }
771
772 /**
773 * @brief Check if CCMSRAM erase operation is on going
774 * @rmtoll SYSCFG_SCSR CCMBSY LL_SYSCFG_IsCCMSRAMEraseOngoing
775 * @retval State of bit (1 or 0).
776 */
LL_SYSCFG_IsCCMSRAMEraseOngoing(void)777 __STATIC_INLINE uint32_t LL_SYSCFG_IsCCMSRAMEraseOngoing(void)
778 {
779 return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMBSY) == (SYSCFG_SCSR_CCMBSY)) ? 1UL : 0UL);
780 }
781
782 /**
783 * @brief Set connections to TIM1/8/15/16/17 Break inputs
784 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
785 * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
786 * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
787 * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
788 * @param Break This parameter can be a combination of the following values:
789 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
790 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
791 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
792 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
793 * @retval None
794 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)795 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
796 {
797 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
798 }
799
800 /**
801 * @brief Get connections to TIM1/8/15/16/17 Break inputs
802 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
803 * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
804 * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
805 * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
806 * @retval Returned value can be can be a combination of the following values:
807 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
808 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
809 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
810 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
811 */
LL_SYSCFG_GetTIMBreakInputs(void)812 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
813 {
814 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
815 }
816
817 /**
818 * @brief Check if SRAM parity error detected
819 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
820 * @retval State of bit (1 or 0).
821 */
LL_SYSCFG_IsActiveFlag_SP(void)822 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
823 {
824 return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)) ? 1UL : 0UL);
825 }
826
827 /**
828 * @brief Clear SRAM parity error flag
829 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
830 * @retval None
831 */
LL_SYSCFG_ClearFlag_SP(void)832 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
833 {
834 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
835 }
836
837 /**
838 * @brief Enable CCMSRAM page write protection
839 * @note Write protection is cleared only by a system reset
840 * @rmtoll SYSCFG_SWPR PAGEx LL_SYSCFG_EnableCCMSRAMPageWRP
841 * @param CCMSRAMWRP This parameter can be a combination of the following values:
842 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE0
843 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE1
844 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE2
845 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE3
846 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE4
847 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE5
848 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE6
849 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE7
850 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE8
851 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE9
852 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE10 (*)
853 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE11 (*)
854 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE12 (*)
855 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE13 (*)
856 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE14 (*)
857 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE15 (*)
858 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE16 (*)
859 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE17 (*)
860 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE18 (*)
861 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE19 (*)
862 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE20 (*)
863 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE21 (*)
864 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE22 (*)
865 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE23 (*)
866 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE24 (*)
867 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE25 (*)
868 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE26 (*)
869 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE27 (*)
870 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE28 (*)
871 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE29 (*)
872 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE30 (*)
873 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE31 (*)
874 *
875 * (*) value not defined in all devices
876 * @retval None
877 */
LL_SYSCFG_EnableCCMSRAMPageWRP(uint32_t CCMSRAMWRP)878 __STATIC_INLINE void LL_SYSCFG_EnableCCMSRAMPageWRP(uint32_t CCMSRAMWRP)
879 {
880 SET_BIT(SYSCFG->SWPR, CCMSRAMWRP);
881 }
882
883 /**
884 * @brief CCMSRAM page write protection lock prior to erase
885 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockCCMSRAMWRP
886 * @retval None
887 */
LL_SYSCFG_LockCCMSRAMWRP(void)888 __STATIC_INLINE void LL_SYSCFG_LockCCMSRAMWRP(void)
889 {
890 /* Writing a wrong key reactivates the write protection */
891 WRITE_REG(SYSCFG->SKR, 0x00);
892 }
893
894 /**
895 * @brief CCMSRAM page write protection unlock prior to erase
896 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockCCMSRAMWRP
897 * @retval None
898 */
LL_SYSCFG_UnlockCCMSRAMWRP(void)899 __STATIC_INLINE void LL_SYSCFG_UnlockCCMSRAMWRP(void)
900 {
901 /* unlock the write protection of the CCMER bit */
902 WRITE_REG(SYSCFG->SKR, 0xCA);
903 WRITE_REG(SYSCFG->SKR, 0x53);
904 }
905
906 /**
907 * @}
908 */
909
910
911 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
912 * @{
913 */
914
915 /**
916 * @brief Return the device identifier
917 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
918 * @retval Values between Min_Data=0x00 and Max_Data=0x0FFF (ex: device ID is 0x6415)
919 */
LL_DBGMCU_GetDeviceID(void)920 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
921 {
922 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
923 }
924
925 /**
926 * @brief Return the device revision identifier
927 * @note This field indicates the revision of the device.
928 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
929 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
930 */
LL_DBGMCU_GetRevisionID(void)931 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
932 {
933 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> (DBGMCU_REVID_POSITION & 0x1FU));
934 }
935
936 /**
937 * @brief Enable the Debug Module during SLEEP mode
938 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
939 * @retval None
940 */
LL_DBGMCU_EnableDBGSleepMode(void)941 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
942 {
943 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
944 }
945
946 /**
947 * @brief Disable the Debug Module during SLEEP mode
948 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
949 * @retval None
950 */
LL_DBGMCU_DisableDBGSleepMode(void)951 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
952 {
953 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
954 }
955
956 /**
957 * @brief Enable the Debug Module during STOP mode
958 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
959 * @retval None
960 */
LL_DBGMCU_EnableDBGStopMode(void)961 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
962 {
963 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
964 }
965
966 /**
967 * @brief Disable the Debug Module during STOP mode
968 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
969 * @retval None
970 */
LL_DBGMCU_DisableDBGStopMode(void)971 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
972 {
973 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
974 }
975
976 /**
977 * @brief Enable the Debug Module during STANDBY mode
978 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
979 * @retval None
980 */
LL_DBGMCU_EnableDBGStandbyMode(void)981 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
982 {
983 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
984 }
985
986 /**
987 * @brief Disable the Debug Module during STANDBY mode
988 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
989 * @retval None
990 */
LL_DBGMCU_DisableDBGStandbyMode(void)991 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
992 {
993 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
994 }
995
996 /**
997 * @brief Set Trace pin assignment control
998 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
999 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
1000 * @param PinAssignment This parameter can be one of the following values:
1001 * @arg @ref LL_DBGMCU_TRACE_NONE
1002 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1003 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1004 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1005 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1006 * @retval None
1007 */
LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)1008 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1009 {
1010 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
1011 }
1012
1013 /**
1014 * @brief Get Trace pin assignment control
1015 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
1016 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
1017 * @retval Returned value can be one of the following values:
1018 * @arg @ref LL_DBGMCU_TRACE_NONE
1019 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1020 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1021 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1022 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1023 */
LL_DBGMCU_GetTracePinAssignment(void)1024 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
1025 {
1026 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
1027 }
1028
1029 /**
1030 * @brief Freeze APB1 peripherals (group1 peripherals)
1031 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
1032 * @param Periphs This parameter can be a combination of the following values:
1033 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1034 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1035 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1036 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
1037 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1038 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1039 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1040 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1041 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1042 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1043 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1044 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1045 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1046 *
1047 * (*) value not defined in all devices.
1048 * @retval None
1049 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1050 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1051 {
1052 SET_BIT(DBGMCU->APB1FZR1, Periphs);
1053 }
1054
1055 /**
1056 * @brief Freeze APB1 peripherals (group2 peripherals)
1057 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
1058 * @param Periphs This parameter can be a combination of the following values:
1059 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
1060 *
1061 * (*) value not defined in all devices.
1062 * @retval None
1063 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1064 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1065 {
1066 SET_BIT(DBGMCU->APB1FZR2, Periphs);
1067 }
1068
1069 /**
1070 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1071 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1072 * @param Periphs This parameter can be a combination of the following values:
1073 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1074 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1075 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1076 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
1077 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1078 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1079 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1080 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1081 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1082 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1083 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1084 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1085 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1086 *
1087 * (*) value not defined in all devices.
1088 * @retval None
1089 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1090 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1091 {
1092 CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
1093 }
1094
1095 /**
1096 * @brief Unfreeze APB1 peripherals (group2 peripherals)
1097 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
1098 * @param Periphs This parameter can be a combination of the following values:
1099 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
1100 *
1101 * (*) value not defined in all devices.
1102 * @retval None
1103 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1104 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1105 {
1106 CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
1107 }
1108
1109 /**
1110 * @brief Freeze APB2 peripherals
1111 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1112 * @param Periphs This parameter can be a combination of the following values:
1113 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1114 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
1115 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1116 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1117 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1118 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
1119 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
1120 *
1121 * (*) value not defined in all devices.
1122 * @retval None
1123 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1124 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1125 {
1126 SET_BIT(DBGMCU->APB2FZ, Periphs);
1127 }
1128
1129 /**
1130 * @brief Unfreeze APB2 peripherals
1131 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1132 * @param Periphs This parameter can be a combination of the following values:
1133 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1134 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
1135 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1136 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1137 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1138 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
1139 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
1140 *
1141 * (*) value not defined in all devices.
1142 * @retval None
1143 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1144 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1145 {
1146 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
1147 }
1148
1149 /**
1150 * @}
1151 */
1152
1153 #if defined(VREFBUF)
1154 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
1155 * @{
1156 */
1157
1158 /**
1159 * @brief Enable Internal voltage reference
1160 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
1161 * @retval None
1162 */
LL_VREFBUF_Enable(void)1163 __STATIC_INLINE void LL_VREFBUF_Enable(void)
1164 {
1165 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1166 }
1167
1168 /**
1169 * @brief Disable Internal voltage reference
1170 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
1171 * @retval None
1172 */
LL_VREFBUF_Disable(void)1173 __STATIC_INLINE void LL_VREFBUF_Disable(void)
1174 {
1175 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1176 }
1177
1178 /**
1179 * @brief Enable high impedance (VREF+pin is high impedance)
1180 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
1181 * @retval None
1182 */
LL_VREFBUF_EnableHIZ(void)1183 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
1184 {
1185 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1186 }
1187
1188 /**
1189 * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
1190 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
1191 * @retval None
1192 */
LL_VREFBUF_DisableHIZ(void)1193 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
1194 {
1195 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1196 }
1197
1198 /**
1199 * @brief Set the Voltage reference scale
1200 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
1201 * @param Scale This parameter can be one of the following values:
1202 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1203 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1204 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
1205 * @retval None
1206 */
LL_VREFBUF_SetVoltageScaling(uint32_t Scale)1207 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
1208 {
1209 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
1210 }
1211
1212 /**
1213 * @brief Get the Voltage reference scale
1214 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
1215 * @retval Returned value can be one of the following values:
1216 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1217 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1218 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
1219 */
LL_VREFBUF_GetVoltageScaling(void)1220 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
1221 {
1222 return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
1223 }
1224
1225 /**
1226 * @brief Check if Voltage reference buffer is ready
1227 * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
1228 * @retval State of bit (1 or 0).
1229 */
LL_VREFBUF_IsVREFReady(void)1230 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
1231 {
1232 return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)) ? 1UL : 0UL);
1233 }
1234
1235 /**
1236 * @brief Get the trimming code for VREFBUF calibration
1237 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
1238 * @retval Between 0 and 0x3F
1239 */
LL_VREFBUF_GetTrimming(void)1240 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
1241 {
1242 return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
1243 }
1244
1245 /**
1246 * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
1247 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
1248 * @param Value Between 0 and 0x3F
1249 * @retval None
1250 */
LL_VREFBUF_SetTrimming(uint32_t Value)1251 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
1252 {
1253 WRITE_REG(VREFBUF->CCR, Value);
1254 }
1255
1256 /**
1257 * @}
1258 */
1259 #endif /* VREFBUF */
1260
1261 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1262 * @{
1263 */
1264
1265 /**
1266 * @brief Set FLASH Latency
1267 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1268 * @param Latency This parameter can be one of the following values:
1269 * @arg @ref LL_FLASH_LATENCY_0
1270 * @arg @ref LL_FLASH_LATENCY_1
1271 * @arg @ref LL_FLASH_LATENCY_2
1272 * @arg @ref LL_FLASH_LATENCY_3
1273 * @arg @ref LL_FLASH_LATENCY_4
1274 * @arg @ref LL_FLASH_LATENCY_5 (*)
1275 * @arg @ref LL_FLASH_LATENCY_6 (*)
1276 * @arg @ref LL_FLASH_LATENCY_7 (*)
1277 * @arg @ref LL_FLASH_LATENCY_8 (*)
1278 * @arg @ref LL_FLASH_LATENCY_9 (*)
1279 * @arg @ref LL_FLASH_LATENCY_10 (*)
1280 * @arg @ref LL_FLASH_LATENCY_11 (*)
1281 * @arg @ref LL_FLASH_LATENCY_12 (*)
1282 * @arg @ref LL_FLASH_LATENCY_13 (*)
1283 * @arg @ref LL_FLASH_LATENCY_14 (*)
1284 * @arg @ref LL_FLASH_LATENCY_15 (*)
1285 *
1286 * (*) value not defined in all devices.
1287 * @retval None
1288 */
LL_FLASH_SetLatency(uint32_t Latency)1289 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1290 {
1291 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1292 }
1293
1294 /**
1295 * @brief Get FLASH Latency
1296 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1297 * @retval Returned value can be one of the following values:
1298 * @arg @ref LL_FLASH_LATENCY_0
1299 * @arg @ref LL_FLASH_LATENCY_1
1300 * @arg @ref LL_FLASH_LATENCY_2
1301 * @arg @ref LL_FLASH_LATENCY_3
1302 * @arg @ref LL_FLASH_LATENCY_4
1303 * @arg @ref LL_FLASH_LATENCY_5 (*)
1304 * @arg @ref LL_FLASH_LATENCY_6 (*)
1305 * @arg @ref LL_FLASH_LATENCY_7 (*)
1306 * @arg @ref LL_FLASH_LATENCY_8 (*)
1307 * @arg @ref LL_FLASH_LATENCY_9 (*)
1308 * @arg @ref LL_FLASH_LATENCY_10 (*)
1309 * @arg @ref LL_FLASH_LATENCY_11 (*)
1310 * @arg @ref LL_FLASH_LATENCY_12 (*)
1311 * @arg @ref LL_FLASH_LATENCY_13 (*)
1312 * @arg @ref LL_FLASH_LATENCY_14 (*)
1313 * @arg @ref LL_FLASH_LATENCY_15 (*)
1314 *
1315 * (*) value not defined in all devices.
1316 */
LL_FLASH_GetLatency(void)1317 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1318 {
1319 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1320 }
1321
1322 /**
1323 * @brief Enable Prefetch
1324 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
1325 * @retval None
1326 */
LL_FLASH_EnablePrefetch(void)1327 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1328 {
1329 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1330 }
1331
1332 /**
1333 * @brief Disable Prefetch
1334 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
1335 * @retval None
1336 */
LL_FLASH_DisablePrefetch(void)1337 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1338 {
1339 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1340 }
1341
1342 /**
1343 * @brief Check if Prefetch buffer is enabled
1344 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
1345 * @retval State of bit (1 or 0).
1346 */
LL_FLASH_IsPrefetchEnabled(void)1347 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1348 {
1349 return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL : 0UL);
1350 }
1351
1352 /**
1353 * @brief Enable Instruction cache
1354 * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
1355 * @retval None
1356 */
LL_FLASH_EnableInstCache(void)1357 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
1358 {
1359 SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1360 }
1361
1362 /**
1363 * @brief Disable Instruction cache
1364 * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
1365 * @retval None
1366 */
LL_FLASH_DisableInstCache(void)1367 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
1368 {
1369 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1370 }
1371
1372 /**
1373 * @brief Enable Data cache
1374 * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
1375 * @retval None
1376 */
LL_FLASH_EnableDataCache(void)1377 __STATIC_INLINE void LL_FLASH_EnableDataCache(void)
1378 {
1379 SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1380 }
1381
1382 /**
1383 * @brief Disable Data cache
1384 * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
1385 * @retval None
1386 */
LL_FLASH_DisableDataCache(void)1387 __STATIC_INLINE void LL_FLASH_DisableDataCache(void)
1388 {
1389 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1390 }
1391
1392 /**
1393 * @brief Enable Instruction cache reset
1394 * @note bit can be written only when the instruction cache is disabled
1395 * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
1396 * @retval None
1397 */
LL_FLASH_EnableInstCacheReset(void)1398 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
1399 {
1400 SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1401 }
1402
1403 /**
1404 * @brief Disable Instruction cache reset
1405 * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
1406 * @retval None
1407 */
LL_FLASH_DisableInstCacheReset(void)1408 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
1409 {
1410 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1411 }
1412
1413 /**
1414 * @brief Enable Data cache reset
1415 * @note bit can be written only when the data cache is disabled
1416 * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
1417 * @retval None
1418 */
LL_FLASH_EnableDataCacheReset(void)1419 __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
1420 {
1421 SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1422 }
1423
1424 /**
1425 * @brief Disable Data cache reset
1426 * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
1427 * @retval None
1428 */
LL_FLASH_DisableDataCacheReset(void)1429 __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
1430 {
1431 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1432 }
1433
1434 /**
1435 * @brief Enable Flash Power-down mode during run mode or Low-power run mode
1436 * @note Flash memory can be put in power-down mode only when the code is executed
1437 * from RAM
1438 * @note Flash must not be accessed when power down is enabled
1439 * @note Flash must not be put in power-down while a program or an erase operation
1440 * is on-going
1441 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
1442 * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n
1443 * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
1444 * @retval None
1445 */
LL_FLASH_EnableRunPowerDown(void)1446 __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
1447 {
1448 /* Following values must be written consecutively to unlock the RUN_PD bit in
1449 FLASH_ACR */
1450 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
1451 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
1452 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
1453 }
1454
1455 /**
1456 * @brief Disable Flash Power-down mode during run mode or Low-power run mode
1457 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n
1458 * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n
1459 * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
1460 * @retval None
1461 */
LL_FLASH_DisableRunPowerDown(void)1462 __STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
1463 {
1464 /* Following values must be written consecutively to unlock the RUN_PD bit in
1465 FLASH_ACR */
1466 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
1467 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
1468 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
1469 }
1470
1471 /**
1472 * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
1473 * @note Flash must not be put in power-down while a program or an erase operation
1474 * is on-going
1475 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
1476 * @retval None
1477 */
LL_FLASH_EnableSleepPowerDown(void)1478 __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
1479 {
1480 SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1481 }
1482
1483 /**
1484 * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
1485 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
1486 * @retval None
1487 */
LL_FLASH_DisableSleepPowerDown(void)1488 __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
1489 {
1490 CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1491 }
1492
1493 /**
1494 * @}
1495 */
1496
1497 /**
1498 * @}
1499 */
1500
1501 /**
1502 * @}
1503 */
1504
1505 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
1506
1507 /**
1508 * @}
1509 */
1510
1511 #ifdef __cplusplus
1512 }
1513 #endif
1514
1515 #endif /* __STM32G4xx_LL_SYSTEM_H */
1516
1517
