1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17
18 /* Define to prevent recursive inclusion -------------------------------------*/
19 #ifndef STM32G4xx_LL_RCC_H
20 #define STM32G4xx_LL_RCC_H
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 /* Includes ------------------------------------------------------------------*/
27 #include "stm32g4xx.h"
28
29 /** @addtogroup STM32G4xx_LL_Driver
30 * @{
31 */
32
33 /** @defgroup RCC_LL RCC
34 * @{
35 */
36
37 /* Private types -------------------------------------------------------------*/
38 /* Private variables ---------------------------------------------------------*/
39 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
40 * @{
41 */
42
43 /**
44 * @}
45 */
46
47 /* Private constants ---------------------------------------------------------*/
48 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
49 * @{
50 */
51 /* Defines used to perform offsets*/
52 /* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */
53 #define RCC_OFFSET_CCIPR 0U
54 #define RCC_OFFSET_CCIPR2 0x14U
55
56 /**
57 * @}
58 */
59
60 /* Private macros ------------------------------------------------------------*/
61 #if defined(USE_FULL_LL_DRIVER)
62 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
63 * @{
64 */
65 /**
66 * @}
67 */
68 #endif /*USE_FULL_LL_DRIVER*/
69
70 /* Exported types ------------------------------------------------------------*/
71 #if defined(USE_FULL_LL_DRIVER)
72 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
73 * @{
74 */
75
76 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
77 * @{
78 */
79
80 /**
81 * @brief RCC Clocks Frequency Structure
82 */
83 typedef struct
84 {
85 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
86 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
87 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
88 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
89 } LL_RCC_ClocksTypeDef;
90
91 /**
92 * @}
93 */
94
95 /**
96 * @}
97 */
98 #endif /* USE_FULL_LL_DRIVER */
99
100 /* Exported constants --------------------------------------------------------*/
101 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
102 * @{
103 */
104
105 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
106 * @brief Defines used to adapt values of different oscillators
107 * @note These values could be modified in the user environment according to
108 * HW set-up.
109 * @{
110 */
111 #if !defined (HSE_VALUE)
112 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
113 #endif /* HSE_VALUE */
114
115 #if !defined (HSI_VALUE)
116 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
117 #endif /* HSI_VALUE */
118
119 #if !defined (LSE_VALUE)
120 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
121 #endif /* LSE_VALUE */
122
123 #if !defined (LSI_VALUE)
124 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
125 #endif /* LSI_VALUE */
126
127 #if !defined (HSI48_VALUE)
128 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
129 #endif /* HSI48_VALUE */
130
131 #if !defined (EXTERNAL_CLOCK_VALUE)
132 #define EXTERNAL_CLOCK_VALUE 48000U /*!< Value of the I2S_CKIN, I2S and SAI1 external clock source in Hz */
133 #endif /* EXTERNAL_CLOCK_VALUE */
134
135 /**
136 * @}
137 */
138
139 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
140 * @brief Flags defines which can be used with LL_RCC_WriteReg function
141 * @{
142 */
143 #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */
144 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
145 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
146 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
147 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
148 #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
149 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
150 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
151 /**
152 * @}
153 */
154
155 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
156 * @brief Flags defines which can be used with LL_RCC_ReadReg function
157 * @{
158 */
159 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
160 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
161 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
162 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
163 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
164 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
165 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
166 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
167 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
168 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
169 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
170 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
171 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
172 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
173 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
174 /**
175 * @}
176 */
177
178 /** @defgroup RCC_LL_EC_IT IT Defines
179 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
180 * @{
181 */
182 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
183 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
184 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
185 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
186 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
187 #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
188 #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */
189 /**
190 * @}
191 */
192
193 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
194 * @{
195 */
196 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
197 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
198 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
199 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
200 /**
201 * @}
202 */
203
204 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
205 * @{
206 */
207 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
208 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
209 /**
210 * @}
211 */
212
213 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
214 * @{
215 */
216 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
217 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
218 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
219 /**
220 * @}
221 */
222
223 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
224 * @{
225 */
226 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
227 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
228 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
229 /**
230 * @}
231 */
232
233 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
234 * @{
235 */
236 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
237 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
238 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
239 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
240 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
241 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
242 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
243 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
244 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
245 /**
246 * @}
247 */
248
249 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
250 * @{
251 */
252 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
253 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
254 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
255 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
256 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
257 /**
258 * @}
259 */
260
261 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
262 * @{
263 */
264 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
265 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
266 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
267 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
268 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
269 /**
270 * @}
271 */
272
273 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
274 * @{
275 */
276 #define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
277 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
278 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
279 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
280 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
281 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
282 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
283 #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
284 /**
285 * @}
286 */
287
288 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
289 * @{
290 */
291 #define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
292 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
293 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
294 #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
295 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
296 /**
297 * @}
298 */
299
300 #if defined(USE_FULL_LL_DRIVER)
301 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
302 * @{
303 */
304 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
305 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
306 /**
307 * @}
308 */
309 #endif /* USE_FULL_LL_DRIVER */
310
311 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
312 * @{
313 */
314 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */
315 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
316 #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
317 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */
318 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */
319 #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
320 #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
321 #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */
322 #define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U) /*!< PCLK1 clock used as USART3 clock source */
323 #define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
324 #define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
325 #define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */
326 /**
327 * @}
328 */
329
330 /** @defgroup RCC_LL_EC_UARTx_CLKSOURCE Peripheral UART clock source selection
331 * @{
332 */
333 #if defined(RCC_CCIPR_UART4SEL)
334 #define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR_UART4SEL << 16U) /*!< PCLK1 clock used as UART4 clock source */
335 #define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */
336 #define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_1) /*!< HSI clock used as UART4 clock source */
337 #define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL) /*!< LSE clock used as UART4 clock source */
338 #endif /* RCC_CCIPR_UART4SEL */
339 #if defined(RCC_CCIPR_UART5SEL)
340 #define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR_UART5SEL << 16U) /*!< PCLK1 clock used as UART5 clock source */
341 #define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */
342 #define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_1) /*!< HSI clock used as UART5 clock source */
343 #define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL) /*!< LSE clock used as UART5 clock source */
344 #endif /* RCC_CCIPR_UART5SEL */
345 /**
346 * @}
347 */
348
349 /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection
350 * @{
351 */
352 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPUART1 clock source */
353 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */
354 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */
355 #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE clock used as LPUART1 clock source */
356 /**
357 * @}
358 */
359
360 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
361 * @{
362 */
363 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
364 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
365 #define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
366 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */
367 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */
368 #define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */
369 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */
370 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
371 #define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
372 #if defined(RCC_CCIPR2_I2C4SEL)
373 #define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */
374 #define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
375 #define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
376 #endif /* RCC_CCIPR2_I2C4SEL */
377 /**
378 * @}
379 */
380
381 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
382 * @{
383 */
384 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock source */
385 #define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 /*!< LSI clock used as LPTIM1 clock source */
386 #define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 /*!< HSI clock used as LPTIM1 clock source */
387 #define LL_RCC_LPTIM1_CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL /*!< LSE clock used as LPTIM1 clock source */
388 /**
389 * @}
390 */
391
392 /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection
393 * @{
394 */
395 #define LL_RCC_SAI1_CLKSOURCE_SYSCLK 0x00000000U /*!< System clock used as SAI1 clock source */
396 #define LL_RCC_SAI1_CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0 /*!< PLL clock used as SAI1 clock source */
397 #define LL_RCC_SAI1_CLKSOURCE_PIN RCC_CCIPR_SAI1SEL_1 /*!< EXT clock used as SAI1 clock source */
398 #define LL_RCC_SAI1_CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_0 | RCC_CCIPR_SAI1SEL_1) /*!< HSI clock used as SAI1 clock source */
399 /**
400 * @}
401 */
402
403 /** @defgroup RCC_LL_EC_I2S_CLKSOURCE Peripheral I2S clock source selection
404 * @{
405 */
406 #define LL_RCC_I2S_CLKSOURCE_SYSCLK 0x00000000U /*!< System clock used as I2S clock source */
407 #define LL_RCC_I2S_CLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0 /*!< PLL clock used as I2S clock source */
408 #define LL_RCC_I2S_CLKSOURCE_PIN RCC_CCIPR_I2S23SEL_1 /*!< EXT clock used as I2S clock source */
409 #define LL_RCC_I2S_CLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_0 | RCC_CCIPR_I2S23SEL_1) /*!< HSI clock used as I2S clock source */
410 /**
411 * @}
412 */
413
414 #if defined(FDCAN1)
415 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection
416 * @{
417 */
418 #define LL_RCC_FDCAN_CLKSOURCE_HSE 0x00000000U /*!< HSE clock used as FDCAN clock source */
419 #define LL_RCC_FDCAN_CLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0 /*!< PLL clock used as FDCAN clock source */
420 #define LL_RCC_FDCAN_CLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1 /*!< PCLK1 clock used as FDCAN clock source */
421 /**
422 * @}
423 */
424 #endif /* FDCAN1 */
425
426 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
427 * @{
428 */
429 #define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */
430 #define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as RNG clock source */
431 /**
432 * @}
433 */
434
435 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
436 * @{
437 */
438 #define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */
439 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as USB clock source */
440 /**
441 * @}
442 */
443
444 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
445 * @{
446 */
447 #define LL_RCC_ADC12_CLKSOURCE_NONE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U)) /*!< No clock used as ADC12 clock source */
448 #define LL_RCC_ADC12_CLKSOURCE_PLL ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_0 >> RCC_CCIPR_ADC12SEL_Pos)) /*!< PLL clock used as ADC12 clock source */
449 #define LL_RCC_ADC12_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_1 >> RCC_CCIPR_ADC12SEL_Pos)) /*!< SYSCLK clock used as ADC12 clock source */
450 #if defined(RCC_CCIPR_ADC345SEL)
451 #define LL_RCC_ADC345_CLKSOURCE_NONE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U)) /*!< No clock used as ADC345 clock source */
452 #define LL_RCC_ADC345_CLKSOURCE_PLL ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL_0 >> RCC_CCIPR_ADC345SEL_Pos)) /*!< PLL clock used as ADC345 clock source */
453 #define LL_RCC_ADC345_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL_1 >> RCC_CCIPR_ADC345SEL_Pos)) /*!< SYSCLK clock used as ADC345 clock source */
454 #endif /* RCC_CCIPR_ADC345SEL */
455 /**
456 * @}
457 */
458
459 /** @defgroup RCC_LL_EC_QUADSPI Peripheral QUADSPI get clock source
460 * @{
461 */
462 #define LL_RCC_QUADSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as QuadSPI clock source */
463 #define LL_RCC_QUADSPI_CLKSOURCE_HSI RCC_CCIPR2_QSPISEL_0 /*!< HSI used as QuadSPI clock source */
464 #define LL_RCC_QUADSPI_CLKSOURCE_PLL RCC_CCIPR2_QSPISEL_1 /*!< PLL used as QuadSPI clock source */
465 /**
466 * @}
467 */
468
469
470 /** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source
471 * @{
472 */
473 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
474 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
475 #define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
476 /**
477 * @}
478 */
479
480 /** @defgroup RCC_LL_EC_UARTx Peripheral UART get clock source
481 * @{
482 */
483 #if defined(RCC_CCIPR_UART4SEL)
484 #define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */
485 #endif /* RCC_CCIPR_UART4SEL */
486 #if defined(RCC_CCIPR_UART5SEL)
487 #define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */
488 #endif /* RCC_CCIPR_UART5SEL */
489 /**
490 * @}
491 */
492
493 /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
494 * @{
495 */
496 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
497 /**
498 * @}
499 */
500
501 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
502 * @{
503 */
504 #define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
505 #define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
506 #define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
507 #if defined(RCC_CCIPR2_I2C4SEL)
508 #define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
509 #endif /* RCC_CCIPR2_I2C4SEL */
510 /**
511 * @}
512 */
513
514 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
515 * @{
516 */
517 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */
518 /**
519 * @}
520 */
521
522 /** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source
523 * @{
524 */
525 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */
526 /**
527 * @}
528 */
529
530 /** @defgroup RCC_LL_EC_I2S Peripheral I2S get clock source
531 * @{
532 */
533 #define LL_RCC_I2S_CLKSOURCE RCC_CCIPR_I2S23SEL /*!< I2S Clock source selection */
534 /**
535 * @}
536 */
537
538 #if defined(FDCAN1)
539 /** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source
540 * @{
541 */
542 #define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR_FDCANSEL /*!< FDCAN Clock source selection */
543 #endif /* FDCAN1 */
544
545 /**
546 * @}
547 */
548
549 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
550 * @{
551 */
552 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */
553 /**
554 * @}
555 */
556
557 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
558 * @{
559 */
560 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */
561 /**
562 * @}
563 */
564
565 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
566 * @{
567 */
568 #define LL_RCC_ADC12_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL >> RCC_CCIPR_ADC12SEL_Pos)) /*!< ADC12 Clock source selection */
569 #if defined(RCC_CCIPR_ADC345SEL_Pos)
570 #define LL_RCC_ADC345_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL >> RCC_CCIPR_ADC345SEL_Pos)) /*!< ADC345 Clock source selection */
571 #endif /* RCC_CCIPR_ADC345SEL_Pos */
572 /**
573 * @}
574 */
575
576 /** @defgroup RCC_LL_EC_QUADSPI Peripheral QUADSPI get clock source
577 * @{
578 */
579 #define LL_RCC_QUADSPI_CLKSOURCE RCC_CCIPR2_QSPISEL /*!< QuadSPI Clock source selection */
580 /**
581 * @}
582 */
583
584 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
585 * @{
586 */
587 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
588 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
589 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
590 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
591 /**
592 * @}
593 */
594
595
596 /** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source
597 * @{
598 */
599 #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
600 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
601 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
602 /**
603 * @}
604 */
605
606 /** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor
607 * @{
608 */
609 #define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL division factor by 1 */
610 #define LL_RCC_PLLM_DIV_2 RCC_PLLCFGR_PLLM_0 /*!< PLL division factor by 2 */
611 #define LL_RCC_PLLM_DIV_3 RCC_PLLCFGR_PLLM_1 /*!< PLL division factor by 3 */
612 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 4 */
613 #define LL_RCC_PLLM_DIV_5 RCC_PLLCFGR_PLLM_2 /*!< PLL division factor by 5 */
614 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 6 */
615 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 7 */
616 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 8 */
617 #define LL_RCC_PLLM_DIV_9 RCC_PLLCFGR_PLLM_3 /*!< PLL division factor by 9 */
618 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 10 */
619 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 11 */
620 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 12 */
621 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL division factor by 13 */
622 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 14 */
623 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 15 */
624 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 16 */
625 /**
626 * @}
627 */
628
629 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
630 * @{
631 */
632 #define LL_RCC_PLLR_DIV_2 0x00000000U /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
633 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
634 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
635 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
636 /**
637 * @}
638 */
639
640 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
641 * @{
642 */
643 #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 2 */
644 #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 3 */
645 #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 4 */
646 #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 5 */
647 #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 6 */
648 #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 7 */
649 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 8 */
650 #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 9 */
651 #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 10 */
652 #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 11 */
653 #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 12 */
654 #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 13 */
655 #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 14 */
656 #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 */
657 #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 16 */
658 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 17 */
659 #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 18 */
660 #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 19 */
661 #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 20 */
662 #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 21 */
663 #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 22 */
664 #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 */
665 #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 24 */
666 #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 25 */
667 #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 26 */
668 #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 */
669 #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 28 */
670 #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 */
671 #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 */
672 #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 */
673 /**
674 * @}
675 */
676
677 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
678 * @{
679 */
680 #define LL_RCC_PLLQ_DIV_2 0x00000000U /*!< Main PLL division factor for PLLQ output by 2 */
681 #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
682 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
683 #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */
684 /**
685 * @}
686 */
687
688 /**
689 * @}
690 */
691
692 /* Exported macro ------------------------------------------------------------*/
693 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
694 * @{
695 */
696
697 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
698 * @{
699 */
700
701 /**
702 * @brief Write a value in RCC register
703 * @param __REG__ Register to be written
704 * @param __VALUE__ Value to be written in the register
705 * @retval None
706 */
707 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, __VALUE__)
708
709 /**
710 * @brief Read a value in RCC register
711 * @param __REG__ Register to be read
712 * @retval Register value
713 */
714 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
715 /**
716 * @}
717 */
718
719 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
720 * @{
721 */
722
723 /**
724 * @brief Helper macro to calculate the PLLCLK frequency on system domain
725 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
726 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
727 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
728 * @param __PLLM__ This parameter can be one of the following values:
729 * @arg @ref LL_RCC_PLLM_DIV_1
730 * @arg @ref LL_RCC_PLLM_DIV_2
731 * @arg @ref LL_RCC_PLLM_DIV_3
732 * @arg @ref LL_RCC_PLLM_DIV_4
733 * @arg @ref LL_RCC_PLLM_DIV_5
734 * @arg @ref LL_RCC_PLLM_DIV_6
735 * @arg @ref LL_RCC_PLLM_DIV_7
736 * @arg @ref LL_RCC_PLLM_DIV_8
737 * @arg @ref LL_RCC_PLLM_DIV_9
738 * @arg @ref LL_RCC_PLLM_DIV_10
739 * @arg @ref LL_RCC_PLLM_DIV_11
740 * @arg @ref LL_RCC_PLLM_DIV_12
741 * @arg @ref LL_RCC_PLLM_DIV_13
742 * @arg @ref LL_RCC_PLLM_DIV_14
743 * @arg @ref LL_RCC_PLLM_DIV_15
744 * @arg @ref LL_RCC_PLLM_DIV_16
745 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 127
746 * @param __PLLR__ This parameter can be one of the following values:
747 * @arg @ref LL_RCC_PLLR_DIV_2
748 * @arg @ref LL_RCC_PLLR_DIV_4
749 * @arg @ref LL_RCC_PLLR_DIV_6
750 * @arg @ref LL_RCC_PLLR_DIV_8
751 * @retval PLL clock frequency (in Hz)
752 */
753 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
754 ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
755
756 /**
757 * @brief Helper macro to calculate the PLLCLK frequency used on ADC domain
758 * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
759 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
760 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
761 * @param __PLLM__ This parameter can be one of the following values:
762 * @arg @ref LL_RCC_PLLM_DIV_1
763 * @arg @ref LL_RCC_PLLM_DIV_2
764 * @arg @ref LL_RCC_PLLM_DIV_3
765 * @arg @ref LL_RCC_PLLM_DIV_4
766 * @arg @ref LL_RCC_PLLM_DIV_5
767 * @arg @ref LL_RCC_PLLM_DIV_6
768 * @arg @ref LL_RCC_PLLM_DIV_7
769 * @arg @ref LL_RCC_PLLM_DIV_8
770 * @arg @ref LL_RCC_PLLM_DIV_9
771 * @arg @ref LL_RCC_PLLM_DIV_10
772 * @arg @ref LL_RCC_PLLM_DIV_11
773 * @arg @ref LL_RCC_PLLM_DIV_12
774 * @arg @ref LL_RCC_PLLM_DIV_13
775 * @arg @ref LL_RCC_PLLM_DIV_14
776 * @arg @ref LL_RCC_PLLM_DIV_15
777 * @arg @ref LL_RCC_PLLM_DIV_16
778
779 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 127
780 * @param __PLLP__ This parameter can be one of the following values:
781 * @arg @ref LL_RCC_PLLP_DIV_2
782 * @arg @ref LL_RCC_PLLP_DIV_3
783 * @arg @ref LL_RCC_PLLP_DIV_4
784 * @arg @ref LL_RCC_PLLP_DIV_5
785 * @arg @ref LL_RCC_PLLP_DIV_6
786 * @arg @ref LL_RCC_PLLP_DIV_7
787 * @arg @ref LL_RCC_PLLP_DIV_8
788 * @arg @ref LL_RCC_PLLP_DIV_9
789 * @arg @ref LL_RCC_PLLP_DIV_10
790 * @arg @ref LL_RCC_PLLP_DIV_11
791 * @arg @ref LL_RCC_PLLP_DIV_12
792 * @arg @ref LL_RCC_PLLP_DIV_13
793 * @arg @ref LL_RCC_PLLP_DIV_14
794 * @arg @ref LL_RCC_PLLP_DIV_15
795 * @arg @ref LL_RCC_PLLP_DIV_16
796 * @arg @ref LL_RCC_PLLP_DIV_17
797 * @arg @ref LL_RCC_PLLP_DIV_18
798 * @arg @ref LL_RCC_PLLP_DIV_19
799 * @arg @ref LL_RCC_PLLP_DIV_20
800 * @arg @ref LL_RCC_PLLP_DIV_21
801 * @arg @ref LL_RCC_PLLP_DIV_22
802 * @arg @ref LL_RCC_PLLP_DIV_23
803 * @arg @ref LL_RCC_PLLP_DIV_24
804 * @arg @ref LL_RCC_PLLP_DIV_25
805 * @arg @ref LL_RCC_PLLP_DIV_26
806 * @arg @ref LL_RCC_PLLP_DIV_27
807 * @arg @ref LL_RCC_PLLP_DIV_28
808 * @arg @ref LL_RCC_PLLP_DIV_29
809 * @arg @ref LL_RCC_PLLP_DIV_30
810 * @arg @ref LL_RCC_PLLP_DIV_31
811 * @retval PLL clock frequency (in Hz)
812 */
813 #define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
814 ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
815
816 /**
817 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
818 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
819 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
820 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
821 * @param __PLLM__ This parameter can be one of the following values:
822 * @arg @ref LL_RCC_PLLM_DIV_1
823 * @arg @ref LL_RCC_PLLM_DIV_2
824 * @arg @ref LL_RCC_PLLM_DIV_3
825 * @arg @ref LL_RCC_PLLM_DIV_4
826 * @arg @ref LL_RCC_PLLM_DIV_5
827 * @arg @ref LL_RCC_PLLM_DIV_6
828 * @arg @ref LL_RCC_PLLM_DIV_7
829 * @arg @ref LL_RCC_PLLM_DIV_8
830 * @arg @ref LL_RCC_PLLM_DIV_9
831 * @arg @ref LL_RCC_PLLM_DIV_10
832 * @arg @ref LL_RCC_PLLM_DIV_11
833 * @arg @ref LL_RCC_PLLM_DIV_12
834 * @arg @ref LL_RCC_PLLM_DIV_13
835 * @arg @ref LL_RCC_PLLM_DIV_14
836 * @arg @ref LL_RCC_PLLM_DIV_15
837 * @arg @ref LL_RCC_PLLM_DIV_16
838 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 127
839 * @param __PLLQ__ This parameter can be one of the following values:
840 * @arg @ref LL_RCC_PLLQ_DIV_2
841 * @arg @ref LL_RCC_PLLQ_DIV_4
842 * @arg @ref LL_RCC_PLLQ_DIV_6
843 * @arg @ref LL_RCC_PLLQ_DIV_8
844 * @retval PLL clock frequency (in Hz)
845 */
846 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
847 ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
848
849 /**
850 * @brief Helper macro to calculate the HCLK frequency
851 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
852 * @param __AHBPRESCALER__ This parameter can be one of the following values:
853 * @arg @ref LL_RCC_SYSCLK_DIV_1
854 * @arg @ref LL_RCC_SYSCLK_DIV_2
855 * @arg @ref LL_RCC_SYSCLK_DIV_4
856 * @arg @ref LL_RCC_SYSCLK_DIV_8
857 * @arg @ref LL_RCC_SYSCLK_DIV_16
858 * @arg @ref LL_RCC_SYSCLK_DIV_64
859 * @arg @ref LL_RCC_SYSCLK_DIV_128
860 * @arg @ref LL_RCC_SYSCLK_DIV_256
861 * @arg @ref LL_RCC_SYSCLK_DIV_512
862 * @retval HCLK clock frequency (in Hz)
863 */
864 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__,__AHBPRESCALER__) ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU))
865
866 /**
867 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
868 * @param __HCLKFREQ__ HCLK frequency
869 * @param __APB1PRESCALER__ This parameter can be one of the following values:
870 * @arg @ref LL_RCC_APB1_DIV_1
871 * @arg @ref LL_RCC_APB1_DIV_2
872 * @arg @ref LL_RCC_APB1_DIV_4
873 * @arg @ref LL_RCC_APB1_DIV_8
874 * @arg @ref LL_RCC_APB1_DIV_16
875 * @retval PCLK1 clock frequency (in Hz)
876 */
877 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos] & 0x1FU))
878
879 /**
880 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
881 * @param __HCLKFREQ__ HCLK frequency
882 * @param __APB2PRESCALER__ This parameter can be one of the following values:
883 * @arg @ref LL_RCC_APB2_DIV_1
884 * @arg @ref LL_RCC_APB2_DIV_2
885 * @arg @ref LL_RCC_APB2_DIV_4
886 * @arg @ref LL_RCC_APB2_DIV_8
887 * @arg @ref LL_RCC_APB2_DIV_16
888 * @retval PCLK2 clock frequency (in Hz)
889 */
890 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos] & 0x1FU))
891
892 /**
893 * @}
894 */
895
896 /**
897 * @}
898 */
899
900 /* Exported functions --------------------------------------------------------*/
901 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
902 * @{
903 */
904
905 /** @defgroup RCC_LL_EF_HSE HSE
906 * @{
907 */
908
909 /**
910 * @brief Enable the Clock Security System.
911 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
912 * @retval None
913 */
LL_RCC_HSE_EnableCSS(void)914 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
915 {
916 SET_BIT(RCC->CR, RCC_CR_CSSON);
917 }
918
919 /**
920 * @brief Enable HSE external oscillator (HSE Bypass)
921 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
922 * @retval None
923 */
LL_RCC_HSE_EnableBypass(void)924 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
925 {
926 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
927 }
928
929 /**
930 * @brief Disable HSE external oscillator (HSE Bypass)
931 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
932 * @retval None
933 */
LL_RCC_HSE_DisableBypass(void)934 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
935 {
936 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
937 }
938
939 /**
940 * @brief Enable HSE crystal oscillator (HSE ON)
941 * @rmtoll CR HSEON LL_RCC_HSE_Enable
942 * @retval None
943 */
LL_RCC_HSE_Enable(void)944 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
945 {
946 SET_BIT(RCC->CR, RCC_CR_HSEON);
947 }
948
949 /**
950 * @brief Disable HSE crystal oscillator (HSE ON)
951 * @rmtoll CR HSEON LL_RCC_HSE_Disable
952 * @retval None
953 */
LL_RCC_HSE_Disable(void)954 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
955 {
956 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
957 }
958
959 /**
960 * @brief Check if HSE oscillator Ready
961 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
962 * @retval State of bit (1 or 0).
963 */
LL_RCC_HSE_IsReady(void)964 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
965 {
966 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
967 }
968
969 /**
970 * @}
971 */
972
973 /** @defgroup RCC_LL_EF_HSI HSI
974 * @{
975 */
976
977 /**
978 * @brief Enable HSI even in stop mode
979 * @note HSI oscillator is forced ON even in Stop mode
980 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
981 * @retval None
982 */
LL_RCC_HSI_EnableInStopMode(void)983 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
984 {
985 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
986 }
987
988 /**
989 * @brief Disable HSI in stop mode
990 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
991 * @retval None
992 */
LL_RCC_HSI_DisableInStopMode(void)993 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
994 {
995 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
996 }
997
998 /**
999 * @brief Enable HSI oscillator
1000 * @rmtoll CR HSION LL_RCC_HSI_Enable
1001 * @retval None
1002 */
LL_RCC_HSI_Enable(void)1003 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1004 {
1005 SET_BIT(RCC->CR, RCC_CR_HSION);
1006 }
1007
1008 /**
1009 * @brief Disable HSI oscillator
1010 * @rmtoll CR HSION LL_RCC_HSI_Disable
1011 * @retval None
1012 */
LL_RCC_HSI_Disable(void)1013 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1014 {
1015 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1016 }
1017
1018 /**
1019 * @brief Check if HSI clock is ready
1020 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1021 * @retval State of bit (1 or 0).
1022 */
LL_RCC_HSI_IsReady(void)1023 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1024 {
1025 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
1026 }
1027
1028 /**
1029 * @brief Get HSI Calibration value
1030 * @note When HSITRIM is written, HSICAL is updated with the sum of
1031 * HSITRIM and the factory trim value
1032 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
1033 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
1034 */
LL_RCC_HSI_GetCalibration(void)1035 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1036 {
1037 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
1038 }
1039
1040 /**
1041 * @brief Set HSI Calibration trimming
1042 * @note user-programmable trimming value that is added to the HSICAL
1043 * @note Default value is 16, which, when added to the HSICAL value,
1044 * should trim the HSI to 16 MHz +/- 1 %
1045 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
1046 * @param Value Between Min_Data = 0 and Max_Data = 127
1047 * @retval None
1048 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1049 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1050 {
1051 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
1052 }
1053
1054 /**
1055 * @brief Get HSI Calibration trimming
1056 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
1057 * @retval Between Min_Data = 0 and Max_Data = 127
1058 */
LL_RCC_HSI_GetCalibTrimming(void)1059 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1060 {
1061 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
1062 }
1063
1064 /**
1065 * @}
1066 */
1067
1068 /** @defgroup RCC_LL_EF_HSI48 HSI48
1069 * @{
1070 */
1071
1072 /**
1073 * @brief Enable HSI48
1074 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
1075 * @retval None
1076 */
LL_RCC_HSI48_Enable(void)1077 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
1078 {
1079 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
1080 }
1081
1082 /**
1083 * @brief Disable HSI48
1084 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
1085 * @retval None
1086 */
LL_RCC_HSI48_Disable(void)1087 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
1088 {
1089 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
1090 }
1091
1092 /**
1093 * @brief Check if HSI48 oscillator Ready
1094 * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
1095 * @retval State of bit (1 or 0).
1096 */
LL_RCC_HSI48_IsReady(void)1097 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
1098 {
1099 return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)) ? 1UL : 0UL);
1100 }
1101
1102 /**
1103 * @brief Get HSI48 Calibration value
1104 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
1105 * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
1106 */
LL_RCC_HSI48_GetCalibration(void)1107 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
1108 {
1109 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
1110 }
1111
1112 /**
1113 * @}
1114 */
1115
1116 /** @defgroup RCC_LL_EF_LSE LSE
1117 * @{
1118 */
1119
1120 /**
1121 * @brief Enable Low Speed External (LSE) crystal.
1122 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
1123 * @retval None
1124 */
LL_RCC_LSE_Enable(void)1125 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1126 {
1127 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1128 }
1129
1130 /**
1131 * @brief Disable Low Speed External (LSE) crystal.
1132 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
1133 * @retval None
1134 */
LL_RCC_LSE_Disable(void)1135 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1136 {
1137 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1138 }
1139
1140 /**
1141 * @brief Enable external clock source (LSE bypass).
1142 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
1143 * @retval None
1144 */
LL_RCC_LSE_EnableBypass(void)1145 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1146 {
1147 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1148 }
1149
1150 /**
1151 * @brief Disable external clock source (LSE bypass).
1152 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
1153 * @retval None
1154 */
LL_RCC_LSE_DisableBypass(void)1155 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1156 {
1157 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1158 }
1159
1160 /**
1161 * @brief Set LSE oscillator drive capability
1162 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1163 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
1164 * @param LSEDrive This parameter can be one of the following values:
1165 * @arg @ref LL_RCC_LSEDRIVE_LOW
1166 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1167 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1168 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1169 * @retval None
1170 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1171 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1172 {
1173 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
1174 }
1175
1176 /**
1177 * @brief Get LSE oscillator drive capability
1178 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
1179 * @retval Returned value can be one of the following values:
1180 * @arg @ref LL_RCC_LSEDRIVE_LOW
1181 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1182 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1183 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1184 */
LL_RCC_LSE_GetDriveCapability(void)1185 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1186 {
1187 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
1188 }
1189
1190 /**
1191 * @brief Enable Clock security system on LSE.
1192 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
1193 * @retval None
1194 */
LL_RCC_LSE_EnableCSS(void)1195 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
1196 {
1197 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1198 }
1199
1200 /**
1201 * @brief Disable Clock security system on LSE.
1202 * @note Clock security system can be disabled only after a LSE
1203 * failure detection. In that case it MUST be disabled by software.
1204 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
1205 * @retval None
1206 */
LL_RCC_LSE_DisableCSS(void)1207 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
1208 {
1209 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1210 }
1211
1212 /**
1213 * @brief Check if LSE oscillator Ready
1214 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
1215 * @retval State of bit (1 or 0).
1216 */
LL_RCC_LSE_IsReady(void)1217 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1218 {
1219 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
1220 }
1221
1222 /**
1223 * @brief Check if CSS on LSE failure Detection
1224 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
1225 * @retval State of bit (1 or 0).
1226 */
LL_RCC_LSE_IsCSSDetected(void)1227 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
1228 {
1229 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);
1230 }
1231
1232 /**
1233 * @}
1234 */
1235
1236 /** @defgroup RCC_LL_EF_LSI LSI
1237 * @{
1238 */
1239
1240 /**
1241 * @brief Enable LSI Oscillator
1242 * @rmtoll CSR LSION LL_RCC_LSI_Enable
1243 * @retval None
1244 */
LL_RCC_LSI_Enable(void)1245 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
1246 {
1247 SET_BIT(RCC->CSR, RCC_CSR_LSION);
1248 }
1249
1250 /**
1251 * @brief Disable LSI Oscillator
1252 * @rmtoll CSR LSION LL_RCC_LSI_Disable
1253 * @retval None
1254 */
LL_RCC_LSI_Disable(void)1255 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
1256 {
1257 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
1258 }
1259
1260 /**
1261 * @brief Check if LSI is Ready
1262 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
1263 * @retval State of bit (1 or 0).
1264 */
LL_RCC_LSI_IsReady(void)1265 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
1266 {
1267 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL);
1268 }
1269
1270 /**
1271 * @}
1272 */
1273
1274 /** @defgroup RCC_LL_EF_LSCO LSCO
1275 * @{
1276 */
1277
1278 /**
1279 * @brief Enable Low speed clock
1280 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
1281 * @retval None
1282 */
LL_RCC_LSCO_Enable(void)1283 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
1284 {
1285 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
1286 }
1287
1288 /**
1289 * @brief Disable Low speed clock
1290 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
1291 * @retval None
1292 */
LL_RCC_LSCO_Disable(void)1293 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
1294 {
1295 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
1296 }
1297
1298 /**
1299 * @brief Configure Low speed clock selection
1300 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
1301 * @param Source This parameter can be one of the following values:
1302 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1303 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1304 * @retval None
1305 */
LL_RCC_LSCO_SetSource(uint32_t Source)1306 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
1307 {
1308 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
1309 }
1310
1311 /**
1312 * @brief Get Low speed clock selection
1313 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
1314 * @retval Returned value can be one of the following values:
1315 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1316 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1317 */
LL_RCC_LSCO_GetSource(void)1318 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
1319 {
1320 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
1321 }
1322
1323 /**
1324 * @}
1325 */
1326
1327 /** @defgroup RCC_LL_EF_System System
1328 * @{
1329 */
1330
1331 /**
1332 * @brief Configure the system clock source
1333 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
1334 * @param Source This parameter can be one of the following values:
1335 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
1336 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
1337 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
1338 * @retval None
1339 */
LL_RCC_SetSysClkSource(uint32_t Source)1340 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1341 {
1342 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
1343 }
1344
1345 /**
1346 * @brief Get the system clock source
1347 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
1348 * @retval Returned value can be one of the following values:
1349 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
1350 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
1351 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
1352 */
LL_RCC_GetSysClkSource(void)1353 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1354 {
1355 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
1356 }
1357
1358 /**
1359 * @brief Set AHB prescaler
1360 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
1361 * @param Prescaler This parameter can be one of the following values:
1362 * @arg @ref LL_RCC_SYSCLK_DIV_1
1363 * @arg @ref LL_RCC_SYSCLK_DIV_2
1364 * @arg @ref LL_RCC_SYSCLK_DIV_4
1365 * @arg @ref LL_RCC_SYSCLK_DIV_8
1366 * @arg @ref LL_RCC_SYSCLK_DIV_16
1367 * @arg @ref LL_RCC_SYSCLK_DIV_64
1368 * @arg @ref LL_RCC_SYSCLK_DIV_128
1369 * @arg @ref LL_RCC_SYSCLK_DIV_256
1370 * @arg @ref LL_RCC_SYSCLK_DIV_512
1371 * @retval None
1372 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)1373 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
1374 {
1375 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
1376 }
1377
1378 /**
1379 * @brief Set APB1 prescaler
1380 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
1381 * @param Prescaler This parameter can be one of the following values:
1382 * @arg @ref LL_RCC_APB1_DIV_1
1383 * @arg @ref LL_RCC_APB1_DIV_2
1384 * @arg @ref LL_RCC_APB1_DIV_4
1385 * @arg @ref LL_RCC_APB1_DIV_8
1386 * @arg @ref LL_RCC_APB1_DIV_16
1387 * @retval None
1388 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)1389 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
1390 {
1391 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
1392 }
1393
1394 /**
1395 * @brief Set APB2 prescaler
1396 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
1397 * @param Prescaler This parameter can be one of the following values:
1398 * @arg @ref LL_RCC_APB2_DIV_1
1399 * @arg @ref LL_RCC_APB2_DIV_2
1400 * @arg @ref LL_RCC_APB2_DIV_4
1401 * @arg @ref LL_RCC_APB2_DIV_8
1402 * @arg @ref LL_RCC_APB2_DIV_16
1403 * @retval None
1404 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)1405 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
1406 {
1407 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
1408 }
1409
1410 /**
1411 * @brief Get AHB prescaler
1412 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
1413 * @retval Returned value can be one of the following values:
1414 * @arg @ref LL_RCC_SYSCLK_DIV_1
1415 * @arg @ref LL_RCC_SYSCLK_DIV_2
1416 * @arg @ref LL_RCC_SYSCLK_DIV_4
1417 * @arg @ref LL_RCC_SYSCLK_DIV_8
1418 * @arg @ref LL_RCC_SYSCLK_DIV_16
1419 * @arg @ref LL_RCC_SYSCLK_DIV_64
1420 * @arg @ref LL_RCC_SYSCLK_DIV_128
1421 * @arg @ref LL_RCC_SYSCLK_DIV_256
1422 * @arg @ref LL_RCC_SYSCLK_DIV_512
1423 */
LL_RCC_GetAHBPrescaler(void)1424 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
1425 {
1426 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
1427 }
1428
1429 /**
1430 * @brief Get APB1 prescaler
1431 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
1432 * @retval Returned value can be one of the following values:
1433 * @arg @ref LL_RCC_APB1_DIV_1
1434 * @arg @ref LL_RCC_APB1_DIV_2
1435 * @arg @ref LL_RCC_APB1_DIV_4
1436 * @arg @ref LL_RCC_APB1_DIV_8
1437 * @arg @ref LL_RCC_APB1_DIV_16
1438 */
LL_RCC_GetAPB1Prescaler(void)1439 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1440 {
1441 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
1442 }
1443
1444 /**
1445 * @brief Get APB2 prescaler
1446 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
1447 * @retval Returned value can be one of the following values:
1448 * @arg @ref LL_RCC_APB2_DIV_1
1449 * @arg @ref LL_RCC_APB2_DIV_2
1450 * @arg @ref LL_RCC_APB2_DIV_4
1451 * @arg @ref LL_RCC_APB2_DIV_8
1452 * @arg @ref LL_RCC_APB2_DIV_16
1453 */
LL_RCC_GetAPB2Prescaler(void)1454 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
1455 {
1456 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
1457 }
1458
1459 /**
1460 * @}
1461 */
1462
1463 /** @defgroup RCC_LL_EF_MCO MCO
1464 * @{
1465 */
1466
1467 /**
1468 * @brief Configure MCOx
1469 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
1470 * CFGR MCOPRE LL_RCC_ConfigMCO
1471 * @param MCOxSource This parameter can be one of the following values:
1472 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
1473 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
1474 * @arg @ref LL_RCC_MCO1SOURCE_HSI
1475 * @arg @ref LL_RCC_MCO1SOURCE_HSE
1476 * @arg @ref LL_RCC_MCO1SOURCE_HSI48
1477 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
1478 * @arg @ref LL_RCC_MCO1SOURCE_LSI
1479 * @arg @ref LL_RCC_MCO1SOURCE_LSE
1480 *
1481 * (*) value not defined in all devices.
1482 * @param MCOxPrescaler This parameter can be one of the following values:
1483 * @arg @ref LL_RCC_MCO1_DIV_1
1484 * @arg @ref LL_RCC_MCO1_DIV_2
1485 * @arg @ref LL_RCC_MCO1_DIV_4
1486 * @arg @ref LL_RCC_MCO1_DIV_8
1487 * @arg @ref LL_RCC_MCO1_DIV_16
1488 * @retval None
1489 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)1490 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1491 {
1492 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
1493 }
1494
1495 /**
1496 * @}
1497 */
1498
1499 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
1500 * @{
1501 */
1502
1503 /**
1504 * @brief Configure USARTx clock source
1505 * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
1506 * @param USARTxSource This parameter can be one of the following values:
1507 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
1508 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1509 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1510 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1511 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
1512 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
1513 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
1514 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
1515 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
1516 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
1517 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
1518 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
1519 * @retval None
1520 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)1521 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
1522 {
1523 MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
1524 }
1525
1526 #if defined(UART4)
1527 /**
1528 * @brief Configure UARTx clock source
1529 * @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource
1530 * @param UARTxSource This parameter can be one of the following values:
1531 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
1532 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK (*)
1533 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
1534 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
1535 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
1536 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK (*)
1537 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
1538 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
1539 *
1540 * (*) value not defined in all devices.
1541 * @retval None
1542 */
LL_RCC_SetUARTClockSource(uint32_t UARTxSource)1543 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
1544 {
1545 MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
1546 }
1547 #endif /* UART4 */
1548
1549 /**
1550 * @brief Configure LPUART1x clock source
1551 * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
1552 * @param LPUARTxSource This parameter can be one of the following values:
1553 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
1554 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
1555 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
1556 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
1557 * @retval None
1558 */
LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)1559 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
1560 {
1561 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
1562 }
1563
1564 /**
1565 * @brief Configure I2Cx clock source
1566 * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
1567 * @param I2CxSource This parameter can be one of the following values:
1568 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1569 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1570 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1571 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
1572 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
1573 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
1574 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
1575 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
1576 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
1577 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
1578 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
1579 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
1580 *
1581 * (*) value not defined in all devices.
1582 * @retval None
1583 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)1584 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
1585 {
1586 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
1587 MODIFY_REG(*reg, 3UL << ((I2CxSource & 0x001F0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x001F0000U) >> 16U)));
1588 }
1589
1590 /**
1591 * @brief Configure LPTIMx clock source
1592 * @rmtoll CCIPR LPTIM1SEL LL_RCC_SetLPTIMClockSource
1593 * @param LPTIMxSource This parameter can be one of the following values:
1594 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
1595 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
1596 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
1597 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
1598 * @retval None
1599 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)1600 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
1601 {
1602 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMxSource);
1603 }
1604
1605 /**
1606 * @brief Configure SAIx clock source
1607 * @rmtoll CCIPR SAI1SEL LL_RCC_SetSAIClockSource
1608 * @param SAIxSource This parameter can be one of the following values:
1609 * @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK
1610 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
1611 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
1612 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
1613 *
1614 * (*) value not defined in all devices.
1615 * @retval None
1616 */
LL_RCC_SetSAIClockSource(uint32_t SAIxSource)1617 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
1618 {
1619 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource);
1620 }
1621
1622 /**
1623 * @brief Configure I2S clock source
1624 * @rmtoll CCIPR I2S23SEL LL_RCC_SetI2SClockSource
1625 * @param I2SxSource This parameter can be one of the following values:
1626 * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
1627 * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
1628 * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
1629 * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
1630 * @retval None
1631 */
LL_RCC_SetI2SClockSource(uint32_t I2SxSource)1632 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
1633 {
1634 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, I2SxSource);
1635 }
1636
1637 #if defined(FDCAN1)
1638 /**
1639 * @brief Configure FDCAN clock source
1640 * @rmtoll CCIPR FDCANSEL LL_RCC_SetFDCANClockSource
1641 * @param FDCANxSource This parameter can be one of the following values:
1642 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
1643 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
1644 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
1645 * @retval None
1646 */
LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)1647 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)
1648 {
1649 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, FDCANxSource);
1650 }
1651 #endif /* FDCAN1 */
1652
1653 /**
1654 * @brief Configure RNG clock source
1655 * @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource
1656 * @param RNGxSource This parameter can be one of the following values:
1657 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
1658 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
1659 * @retval None
1660 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)1661 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
1662 {
1663 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
1664 }
1665
1666 /**
1667 * @brief Configure USB clock source
1668 * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
1669 * @param USBxSource This parameter can be one of the following values:
1670 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
1671 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
1672 * @retval None
1673 */
LL_RCC_SetUSBClockSource(uint32_t USBxSource)1674 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
1675 {
1676 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
1677 }
1678
1679 /**
1680 * @brief Configure ADC clock source
1681 * @rmtoll CCIPR ADC12SEL LL_RCC_SetADCClockSource\n
1682 * CCIPR ADC345SEL LL_RCC_SetADCClockSource
1683 * @param ADCxSource This parameter can be one of the following values:
1684 * @arg @ref LL_RCC_ADC12_CLKSOURCE_NONE
1685 * @arg @ref LL_RCC_ADC12_CLKSOURCE_PLL
1686 * @arg @ref LL_RCC_ADC12_CLKSOURCE_SYSCLK
1687 * @arg @ref LL_RCC_ADC345_CLKSOURCE_NONE (*)
1688 * @arg @ref LL_RCC_ADC345_CLKSOURCE_PLL (*)
1689 * @arg @ref LL_RCC_ADC345_CLKSOURCE_SYSCLK (*)
1690 *
1691 * (*) value not defined in all devices.
1692 * @retval None
1693 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)1694 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
1695 {
1696 MODIFY_REG(RCC->CCIPR, 3U << ((ADCxSource & 0x001F0000U) >> 16U), ((ADCxSource & 0x000000FFU) << ((ADCxSource & 0x001F0000U) >> 16U)));
1697 }
1698
1699 #if defined(QUADSPI)
1700 /**
1701 * @brief Configure QUADSPI clock source
1702 * @rmtoll CCIPR2 QSPISEL LL_RCC_SetQUADSPIClockSource
1703 * @param Source This parameter can be one of the following values:
1704 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_SYSCLK
1705 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_HSI
1706 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_PLL
1707 * @retval None
1708 */
LL_RCC_SetQUADSPIClockSource(uint32_t Source)1709 __STATIC_INLINE void LL_RCC_SetQUADSPIClockSource(uint32_t Source)
1710 {
1711 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, Source);
1712 }
1713 #endif /* QUADSPI */
1714
1715 /**
1716 * @brief Get USARTx clock source
1717 * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
1718 * @param USARTx This parameter can be one of the following values:
1719 * @arg @ref LL_RCC_USART1_CLKSOURCE
1720 * @arg @ref LL_RCC_USART2_CLKSOURCE
1721 * @arg @ref LL_RCC_USART3_CLKSOURCE
1722 * @retval Returned value can be one of the following values:
1723 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
1724 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1725 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1726 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1727 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
1728 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
1729 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
1730 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
1731 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
1732 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
1733 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
1734 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
1735 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)1736 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
1737 {
1738 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
1739 }
1740
1741 #if defined(UART4)
1742 /**
1743 * @brief Get UARTx clock source
1744 * @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource
1745 * @param UARTx This parameter can be one of the following values:
1746 * @arg @ref LL_RCC_UART4_CLKSOURCE (*)
1747 * @arg @ref LL_RCC_UART5_CLKSOURCE (*)
1748 * @retval Returned value can be one of the following values:
1749 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
1750 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK (*)
1751 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
1752 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
1753 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
1754 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK (*)
1755 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
1756 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
1757 *
1758 * (*) value not defined in all devices.
1759 */
LL_RCC_GetUARTClockSource(uint32_t UARTx)1760 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
1761 {
1762 return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16U));
1763 }
1764 #endif /* UART4 */
1765
1766 /**
1767 * @brief Get LPUARTx clock source
1768 * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
1769 * @param LPUARTx This parameter can be one of the following values:
1770 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
1771 * @retval Returned value can be one of the following values:
1772 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
1773 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
1774 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
1775 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
1776 */
LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)1777 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
1778 {
1779 return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
1780 }
1781
1782 /**
1783 * @brief Get I2Cx clock source
1784 * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
1785 * @param I2Cx This parameter can be one of the following values:
1786 * @arg @ref LL_RCC_I2C1_CLKSOURCE
1787 * @arg @ref LL_RCC_I2C2_CLKSOURCE
1788 * @arg @ref LL_RCC_I2C3_CLKSOURCE
1789 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
1790 *
1791 * (*) value not defined in all devices.
1792 * @retval Returned value can be one of the following values:
1793 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1794 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1795 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1796 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
1797 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
1798 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
1799 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
1800 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
1801 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
1802 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
1803 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
1804 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
1805 *
1806 * (*) value not defined in all devices.
1807 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)1808 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
1809 {
1810 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
1811 return (uint32_t)((READ_BIT(*reg, 3UL << ((I2Cx & 0x001F0000U) >> 16U)) >> ((I2Cx & 0x001F0000U) >> 16U)) | (I2Cx & 0xFFFF0000U));
1812 }
1813
1814 /**
1815 * @brief Get LPTIMx clock source
1816 * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
1817 * @param LPTIMx This parameter can be one of the following values:
1818 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
1819 * @retval Returned value can be one of the following values:
1820 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
1821 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
1822 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
1823 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
1824 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)1825 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
1826 {
1827 return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx));
1828 }
1829
1830 /**
1831 * @brief Get SAIx clock source
1832 * @rmtoll CCIPR SAI1SEL LL_RCC_GetSAIClockSource
1833 * @param SAIx This parameter can be one of the following values:
1834 * @arg @ref LL_RCC_SAI1_CLKSOURCE
1835 *
1836 * (*) value not defined in all devices.
1837 * @retval Returned value can be one of the following values:
1838 * @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK
1839 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
1840 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
1841 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
1842 *
1843 * (*) value not defined in all devices.
1844 */
LL_RCC_GetSAIClockSource(uint32_t SAIx)1845 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
1846 {
1847 return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx));
1848 }
1849
1850 /**
1851 * @brief Get I2Sx clock source
1852 * @rmtoll CCIPR I2S23SEL LL_RCC_GetI2SClockSource
1853 * @param I2Sx This parameter can be one of the following values:
1854 * @arg @ref LL_RCC_I2S_CLKSOURCE
1855 * @retval Returned value can be one of the following values:
1856 * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
1857 * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
1858 * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
1859 * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
1860 */
LL_RCC_GetI2SClockSource(uint32_t I2Sx)1861 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
1862 {
1863 return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx));
1864 }
1865
1866 #if defined(FDCAN1)
1867 /**
1868 * @brief Get FDCANx clock source
1869 * @rmtoll CCIPR FDCANSEL LL_RCC_GetFDCANClockSource
1870 * @param FDCANx This parameter can be one of the following values:
1871 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
1872 * @retval Returned value can be one of the following values:
1873 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
1874 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
1875 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
1876 * @retval None
1877 */
LL_RCC_GetFDCANClockSource(uint32_t FDCANx)1878 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx)
1879 {
1880 return (uint32_t)(READ_BIT(RCC->CCIPR, FDCANx));
1881 }
1882 #endif /* FDCAN1 */
1883
1884 /**
1885 * @brief Get RNGx clock source
1886 * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
1887 * @param RNGx This parameter can be one of the following values:
1888 * @arg @ref LL_RCC_RNG_CLKSOURCE
1889 * @retval Returned value can be one of the following values:
1890 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
1891 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
1892 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)1893 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
1894 {
1895 return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
1896 }
1897
1898 /**
1899 * @brief Get USBx clock source
1900 * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
1901 * @param USBx This parameter can be one of the following values:
1902 * @arg @ref LL_RCC_USB_CLKSOURCE
1903 * @retval Returned value can be one of the following values:
1904 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
1905 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
1906 */
LL_RCC_GetUSBClockSource(uint32_t USBx)1907 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
1908 {
1909 return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
1910 }
1911
1912 /**
1913 * @brief Get ADCx clock source
1914 * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
1915 * @param ADCx This parameter can be one of the following values:
1916 * @arg @ref LL_RCC_ADC12_CLKSOURCE
1917 * @arg @ref LL_RCC_ADC345_CLKSOURCE (*)
1918 * @retval Returned value can be one of the following values:
1919 * @arg @ref LL_RCC_ADC12_CLKSOURCE_NONE
1920 * @arg @ref LL_RCC_ADC12_CLKSOURCE_PLL
1921 * @arg @ref LL_RCC_ADC12_CLKSOURCE_SYSCLK
1922 * @arg @ref LL_RCC_ADC345_CLKSOURCE_NONE (*)
1923 * @arg @ref LL_RCC_ADC345_CLKSOURCE_PLL (*)
1924 * @arg @ref LL_RCC_ADC345_CLKSOURCE_SYSCLK (*)
1925 *
1926 * (*) value not defined in all devices.
1927 */
LL_RCC_GetADCClockSource(uint32_t ADCx)1928 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
1929 {
1930 return (uint32_t)((READ_BIT(RCC->CCIPR, 3UL << ((ADCx & 0x001F0000U) >> 16U)) >> ((ADCx & 0x001F0000U) >> 16U)) | (ADCx & 0xFFFF0000U));
1931 }
1932
1933 #if defined(QUADSPI)
1934 /**
1935 * @brief Get QUADSPI clock source
1936 * @rmtoll CCIPR2 QSPISEL LL_RCC_GetQUADSPIClockSource
1937 * @param QUADSPIx This parameter can be one of the following values:
1938 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE
1939 * @retval Returned value can be one of the following values:
1940 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_SYSCLK
1941 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_HSI
1942 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_PLL
1943 */
LL_RCC_GetQUADSPIClockSource(uint32_t QUADSPIx)1944 __STATIC_INLINE uint32_t LL_RCC_GetQUADSPIClockSource(uint32_t QUADSPIx)
1945 {
1946 return (uint32_t)(READ_BIT(RCC->CCIPR2, QUADSPIx));
1947 }
1948 #endif /* QUADSPI */
1949 /**
1950 * @}
1951 */
1952
1953 /** @defgroup RCC_LL_EF_RTC RTC
1954 * @{
1955 */
1956
1957 /**
1958 * @brief Set RTC Clock Source
1959 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
1960 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
1961 * set). The BDRST bit can be used to reset them.
1962 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
1963 * @param Source This parameter can be one of the following values:
1964 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1965 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1966 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1967 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
1968 * @retval None
1969 */
LL_RCC_SetRTCClockSource(uint32_t Source)1970 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
1971 {
1972 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
1973 }
1974
1975 /**
1976 * @brief Get RTC Clock Source
1977 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
1978 * @retval Returned value can be one of the following values:
1979 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1980 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1981 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1982 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
1983 */
LL_RCC_GetRTCClockSource(void)1984 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
1985 {
1986 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
1987 }
1988
1989 /**
1990 * @brief Enable RTC
1991 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
1992 * @retval None
1993 */
LL_RCC_EnableRTC(void)1994 __STATIC_INLINE void LL_RCC_EnableRTC(void)
1995 {
1996 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
1997 }
1998
1999 /**
2000 * @brief Disable RTC
2001 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
2002 * @retval None
2003 */
LL_RCC_DisableRTC(void)2004 __STATIC_INLINE void LL_RCC_DisableRTC(void)
2005 {
2006 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2007 }
2008
2009 /**
2010 * @brief Check if RTC has been enabled or not
2011 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
2012 * @retval State of bit (1 or 0).
2013 */
LL_RCC_IsEnabledRTC(void)2014 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
2015 {
2016 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
2017 }
2018
2019 /**
2020 * @brief Force the Backup domain reset
2021 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
2022 * @retval None
2023 */
LL_RCC_ForceBackupDomainReset(void)2024 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2025 {
2026 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2027 }
2028
2029 /**
2030 * @brief Release the Backup domain reset
2031 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
2032 * @retval None
2033 */
LL_RCC_ReleaseBackupDomainReset(void)2034 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
2035 {
2036 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2037 }
2038
2039 /**
2040 * @}
2041 */
2042
2043
2044 /** @defgroup RCC_LL_EF_PLL PLL
2045 * @{
2046 */
2047
2048 /**
2049 * @brief Enable PLL
2050 * @rmtoll CR PLLON LL_RCC_PLL_Enable
2051 * @retval None
2052 */
LL_RCC_PLL_Enable(void)2053 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
2054 {
2055 SET_BIT(RCC->CR, RCC_CR_PLLON);
2056 }
2057
2058 /**
2059 * @brief Disable PLL
2060 * @note Cannot be disabled if the PLL clock is used as the system clock
2061 * @rmtoll CR PLLON LL_RCC_PLL_Disable
2062 * @retval None
2063 */
LL_RCC_PLL_Disable(void)2064 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
2065 {
2066 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
2067 }
2068
2069 /**
2070 * @brief Check if PLL Ready
2071 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
2072 * @retval State of bit (1 or 0).
2073 */
LL_RCC_PLL_IsReady(void)2074 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
2075 {
2076 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
2077 }
2078
2079 /**
2080 * @brief Configure PLL used for SYSCLK Domain
2081 * @note PLL Source and PLLM Divider can be written only when PLL
2082 * is disabled.
2083 * @note PLLN/PLLR can be written only when PLL is disabled.
2084 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
2085 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
2086 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
2087 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
2088 * @param Source This parameter can be one of the following values:
2089 * @arg @ref LL_RCC_PLLSOURCE_NONE
2090 * @arg @ref LL_RCC_PLLSOURCE_HSI
2091 * @arg @ref LL_RCC_PLLSOURCE_HSE
2092 * @param PLLM This parameter can be one of the following values:
2093 * @arg @ref LL_RCC_PLLM_DIV_1
2094 * @arg @ref LL_RCC_PLLM_DIV_2
2095 * @arg @ref LL_RCC_PLLM_DIV_3
2096 * @arg @ref LL_RCC_PLLM_DIV_4
2097 * @arg @ref LL_RCC_PLLM_DIV_5
2098 * @arg @ref LL_RCC_PLLM_DIV_6
2099 * @arg @ref LL_RCC_PLLM_DIV_7
2100 * @arg @ref LL_RCC_PLLM_DIV_8
2101 * @arg @ref LL_RCC_PLLM_DIV_9
2102 * @arg @ref LL_RCC_PLLM_DIV_10
2103 * @arg @ref LL_RCC_PLLM_DIV_11
2104 * @arg @ref LL_RCC_PLLM_DIV_12
2105 * @arg @ref LL_RCC_PLLM_DIV_13
2106 * @arg @ref LL_RCC_PLLM_DIV_14
2107 * @arg @ref LL_RCC_PLLM_DIV_15
2108 * @arg @ref LL_RCC_PLLM_DIV_16
2109 * @param PLLN Between Min_Data = 8 and Max_Data = 127
2110 * @param PLLR This parameter can be one of the following values:
2111 * @arg @ref LL_RCC_PLLR_DIV_2
2112 * @arg @ref LL_RCC_PLLR_DIV_4
2113 * @arg @ref LL_RCC_PLLR_DIV_6
2114 * @arg @ref LL_RCC_PLLR_DIV_8
2115 * @retval None
2116 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)2117 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
2118 {
2119 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
2120 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
2121 }
2122
2123 /**
2124 * @brief Configure PLL used for ADC domain clock
2125 * @note PLL Source and PLLM Divider can be written only when PLL
2126 * is disabled.
2127 * @note PLLN/PLLP can be written only when PLL is disabled.
2128 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_ADC\n
2129 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_ADC\n
2130 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_ADC\n
2131 * PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_ADC
2132 * @param Source This parameter can be one of the following values:
2133 * @arg @ref LL_RCC_PLLSOURCE_NONE
2134 * @arg @ref LL_RCC_PLLSOURCE_HSI
2135 * @arg @ref LL_RCC_PLLSOURCE_HSE
2136 * @param PLLM This parameter can be one of the following values:
2137 * @arg @ref LL_RCC_PLLM_DIV_1
2138 * @arg @ref LL_RCC_PLLM_DIV_2
2139 * @arg @ref LL_RCC_PLLM_DIV_3
2140 * @arg @ref LL_RCC_PLLM_DIV_4
2141 * @arg @ref LL_RCC_PLLM_DIV_5
2142 * @arg @ref LL_RCC_PLLM_DIV_6
2143 * @arg @ref LL_RCC_PLLM_DIV_7
2144 * @arg @ref LL_RCC_PLLM_DIV_8
2145 * @arg @ref LL_RCC_PLLM_DIV_9
2146 * @arg @ref LL_RCC_PLLM_DIV_10
2147 * @arg @ref LL_RCC_PLLM_DIV_11
2148 * @arg @ref LL_RCC_PLLM_DIV_12
2149 * @arg @ref LL_RCC_PLLM_DIV_13
2150 * @arg @ref LL_RCC_PLLM_DIV_14
2151 * @arg @ref LL_RCC_PLLM_DIV_15
2152 * @arg @ref LL_RCC_PLLM_DIV_16
2153 * @param PLLN Between Min_Data = 8 and Max_Data = 127
2154 * @param PLLP This parameter can be one of the following values:
2155 * @arg @ref LL_RCC_PLLP_DIV_2
2156 * @arg @ref LL_RCC_PLLP_DIV_3
2157 * @arg @ref LL_RCC_PLLP_DIV_4
2158 * @arg @ref LL_RCC_PLLP_DIV_5
2159 * @arg @ref LL_RCC_PLLP_DIV_6
2160 * @arg @ref LL_RCC_PLLP_DIV_7
2161 * @arg @ref LL_RCC_PLLP_DIV_8
2162 * @arg @ref LL_RCC_PLLP_DIV_9
2163 * @arg @ref LL_RCC_PLLP_DIV_10
2164 * @arg @ref LL_RCC_PLLP_DIV_11
2165 * @arg @ref LL_RCC_PLLP_DIV_12
2166 * @arg @ref LL_RCC_PLLP_DIV_13
2167 * @arg @ref LL_RCC_PLLP_DIV_14
2168 * @arg @ref LL_RCC_PLLP_DIV_15
2169 * @arg @ref LL_RCC_PLLP_DIV_16
2170 * @arg @ref LL_RCC_PLLP_DIV_17
2171 * @arg @ref LL_RCC_PLLP_DIV_18
2172 * @arg @ref LL_RCC_PLLP_DIV_19
2173 * @arg @ref LL_RCC_PLLP_DIV_20
2174 * @arg @ref LL_RCC_PLLP_DIV_21
2175 * @arg @ref LL_RCC_PLLP_DIV_22
2176 * @arg @ref LL_RCC_PLLP_DIV_23
2177 * @arg @ref LL_RCC_PLLP_DIV_24
2178 * @arg @ref LL_RCC_PLLP_DIV_25
2179 * @arg @ref LL_RCC_PLLP_DIV_26
2180 * @arg @ref LL_RCC_PLLP_DIV_27
2181 * @arg @ref LL_RCC_PLLP_DIV_28
2182 * @arg @ref LL_RCC_PLLP_DIV_29
2183 * @arg @ref LL_RCC_PLLP_DIV_30
2184 * @arg @ref LL_RCC_PLLP_DIV_31
2185 * @retval None
2186 */
LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)2187 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
2188 {
2189 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV,
2190 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
2191 }
2192
2193 /**
2194 * @brief Configure PLL used for 48Mhz domain clock
2195 * @note PLL Source and PLLM Divider can be written only when PLL,
2196 * is disabled.
2197 * @note PLLN/PLLQ can be written only when PLL is disabled.
2198 * @note This can be selected for USB, RNG
2199 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
2200 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
2201 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
2202 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
2203 * @param Source This parameter can be one of the following values:
2204 * @arg @ref LL_RCC_PLLSOURCE_NONE
2205 * @arg @ref LL_RCC_PLLSOURCE_HSI
2206 * @arg @ref LL_RCC_PLLSOURCE_HSE
2207 * @param PLLM This parameter can be one of the following values:
2208 * @arg @ref LL_RCC_PLLM_DIV_1
2209 * @arg @ref LL_RCC_PLLM_DIV_2
2210 * @arg @ref LL_RCC_PLLM_DIV_3
2211 * @arg @ref LL_RCC_PLLM_DIV_4
2212 * @arg @ref LL_RCC_PLLM_DIV_5
2213 * @arg @ref LL_RCC_PLLM_DIV_6
2214 * @arg @ref LL_RCC_PLLM_DIV_7
2215 * @arg @ref LL_RCC_PLLM_DIV_8
2216 * @arg @ref LL_RCC_PLLM_DIV_9
2217 * @arg @ref LL_RCC_PLLM_DIV_10
2218 * @arg @ref LL_RCC_PLLM_DIV_11
2219 * @arg @ref LL_RCC_PLLM_DIV_12
2220 * @arg @ref LL_RCC_PLLM_DIV_13
2221 * @arg @ref LL_RCC_PLLM_DIV_14
2222 * @arg @ref LL_RCC_PLLM_DIV_15
2223 * @arg @ref LL_RCC_PLLM_DIV_16
2224 * @param PLLN Between Min_Data = 8 and Max_Data = 127
2225 * @param PLLQ This parameter can be one of the following values:
2226 * @arg @ref LL_RCC_PLLQ_DIV_2
2227 * @arg @ref LL_RCC_PLLQ_DIV_4
2228 * @arg @ref LL_RCC_PLLQ_DIV_6
2229 * @arg @ref LL_RCC_PLLQ_DIV_8
2230 * @retval None
2231 */
LL_RCC_PLL_ConfigDomain_48M(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)2232 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2233 {
2234 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
2235 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
2236 }
2237
2238 /**
2239 * @brief Configure PLL clock source
2240 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
2241 * @param PLLSource This parameter can be one of the following values:
2242 * @arg @ref LL_RCC_PLLSOURCE_NONE
2243 * @arg @ref LL_RCC_PLLSOURCE_HSI
2244 * @arg @ref LL_RCC_PLLSOURCE_HSE
2245 * @retval None
2246 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)2247 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
2248 {
2249 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
2250 }
2251
2252 /**
2253 * @brief Get the oscillator used as PLL clock source.
2254 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
2255 * @retval Returned value can be one of the following values:
2256 * @arg @ref LL_RCC_PLLSOURCE_NONE
2257 * @arg @ref LL_RCC_PLLSOURCE_HSI
2258 * @arg @ref LL_RCC_PLLSOURCE_HSE
2259 */
LL_RCC_PLL_GetMainSource(void)2260 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
2261 {
2262 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
2263 }
2264
2265 /**
2266 * @brief Get Main PLL multiplication factor for VCO
2267 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
2268 * @retval Between Min_Data = 8 and Max_Data = 127
2269 */
LL_RCC_PLL_GetN(void)2270 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
2271 {
2272 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
2273 }
2274
2275 /**
2276 * @brief Get Main PLL division factor for PLLP
2277 * @note Used for PLLADCCLK (ADC clock)
2278 * @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP\n
2279 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
2280 * @retval Returned value can be one of the following values:
2281 * @arg @ref LL_RCC_PLLP_DIV_2
2282 * @arg @ref LL_RCC_PLLP_DIV_3
2283 * @arg @ref LL_RCC_PLLP_DIV_4
2284 * @arg @ref LL_RCC_PLLP_DIV_5
2285 * @arg @ref LL_RCC_PLLP_DIV_6
2286 * @arg @ref LL_RCC_PLLP_DIV_7
2287 * @arg @ref LL_RCC_PLLP_DIV_8
2288 * @arg @ref LL_RCC_PLLP_DIV_9
2289 * @arg @ref LL_RCC_PLLP_DIV_10
2290 * @arg @ref LL_RCC_PLLP_DIV_11
2291 * @arg @ref LL_RCC_PLLP_DIV_12
2292 * @arg @ref LL_RCC_PLLP_DIV_13
2293 * @arg @ref LL_RCC_PLLP_DIV_14
2294 * @arg @ref LL_RCC_PLLP_DIV_15
2295 * @arg @ref LL_RCC_PLLP_DIV_16
2296 * @arg @ref LL_RCC_PLLP_DIV_17
2297 * @arg @ref LL_RCC_PLLP_DIV_18
2298 * @arg @ref LL_RCC_PLLP_DIV_19
2299 * @arg @ref LL_RCC_PLLP_DIV_20
2300 * @arg @ref LL_RCC_PLLP_DIV_21
2301 * @arg @ref LL_RCC_PLLP_DIV_22
2302 * @arg @ref LL_RCC_PLLP_DIV_23
2303 * @arg @ref LL_RCC_PLLP_DIV_24
2304 * @arg @ref LL_RCC_PLLP_DIV_25
2305 * @arg @ref LL_RCC_PLLP_DIV_26
2306 * @arg @ref LL_RCC_PLLP_DIV_27
2307 * @arg @ref LL_RCC_PLLP_DIV_28
2308 * @arg @ref LL_RCC_PLLP_DIV_29
2309 * @arg @ref LL_RCC_PLLP_DIV_30
2310 * @arg @ref LL_RCC_PLLP_DIV_31
2311 */
LL_RCC_PLL_GetP(void)2312 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
2313 {
2314 return (uint32_t) ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) != 0U) ? READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) : ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) == RCC_PLLCFGR_PLLP) ? LL_RCC_PLLP_DIV_17 : LL_RCC_PLLP_DIV_7) );
2315 }
2316
2317 /**
2318 * @brief Get Main PLL division factor for PLLQ
2319 * @note Used for PLL48M1CLK selected for USB, RNG (48 MHz clock)
2320 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
2321 * @retval Returned value can be one of the following values:
2322 * @arg @ref LL_RCC_PLLQ_DIV_2
2323 * @arg @ref LL_RCC_PLLQ_DIV_4
2324 * @arg @ref LL_RCC_PLLQ_DIV_6
2325 * @arg @ref LL_RCC_PLLQ_DIV_8
2326 */
LL_RCC_PLL_GetQ(void)2327 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
2328 {
2329 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
2330 }
2331
2332 /**
2333 * @brief Get Main PLL division factor for PLLR
2334 * @note Used for PLLCLK (system clock)
2335 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
2336 * @retval Returned value can be one of the following values:
2337 * @arg @ref LL_RCC_PLLR_DIV_2
2338 * @arg @ref LL_RCC_PLLR_DIV_4
2339 * @arg @ref LL_RCC_PLLR_DIV_6
2340 * @arg @ref LL_RCC_PLLR_DIV_8
2341 */
LL_RCC_PLL_GetR(void)2342 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
2343 {
2344 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
2345 }
2346
2347 /**
2348 * @brief Get Division factor for the main PLL and other PLL
2349 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
2350 * @retval Returned value can be one of the following values:
2351 * @arg @ref LL_RCC_PLLM_DIV_1
2352 * @arg @ref LL_RCC_PLLM_DIV_2
2353 * @arg @ref LL_RCC_PLLM_DIV_3
2354 * @arg @ref LL_RCC_PLLM_DIV_4
2355 * @arg @ref LL_RCC_PLLM_DIV_5
2356 * @arg @ref LL_RCC_PLLM_DIV_6
2357 * @arg @ref LL_RCC_PLLM_DIV_7
2358 * @arg @ref LL_RCC_PLLM_DIV_8
2359 * @arg @ref LL_RCC_PLLM_DIV_9
2360 * @arg @ref LL_RCC_PLLM_DIV_10
2361 * @arg @ref LL_RCC_PLLM_DIV_11
2362 * @arg @ref LL_RCC_PLLM_DIV_12
2363 * @arg @ref LL_RCC_PLLM_DIV_13
2364 * @arg @ref LL_RCC_PLLM_DIV_14
2365 * @arg @ref LL_RCC_PLLM_DIV_15
2366 * @arg @ref LL_RCC_PLLM_DIV_16
2367 */
LL_RCC_PLL_GetDivider(void)2368 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
2369 {
2370 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
2371 }
2372
2373 /**
2374 * @brief Enable PLL output mapped on ADC domain clock
2375 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_ADC
2376 * @retval None
2377 */
LL_RCC_PLL_EnableDomain_ADC(void)2378 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void)
2379 {
2380 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
2381 }
2382
2383 /**
2384 * @brief Disable PLL output mapped on ADC domain clock
2385 * @note Cannot be disabled if the PLL clock is used as the system
2386 * clock
2387 * @note In order to save power, when the PLLCLK of the PLL is
2388 * not used, should be 0
2389 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_ADC
2390 * @retval None
2391 */
LL_RCC_PLL_DisableDomain_ADC(void)2392 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void)
2393 {
2394 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
2395 }
2396
2397 /**
2398 * @brief Check if PLL output mapped on ADC domain clock is enabled
2399 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_ADC
2400 * @retval State of bit (1 or 0).
2401 */
LL_RCC_PLL_IsEnabledDomain_ADC(void)2402 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_ADC(void)
2403 {
2404 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
2405 }
2406
2407 /**
2408 * @brief Enable PLL output mapped on 48MHz domain clock
2409 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
2410 * @retval None
2411 */
LL_RCC_PLL_EnableDomain_48M(void)2412 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
2413 {
2414 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
2415 }
2416
2417 /**
2418 * @brief Disable PLL output mapped on 48MHz domain clock
2419 * @note Cannot be disabled if the PLL clock is used as the system
2420 * clock
2421 * @note In order to save power, when the PLLCLK of the PLL is
2422 * not used, should be 0
2423 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
2424 * @retval None
2425 */
LL_RCC_PLL_DisableDomain_48M(void)2426 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
2427 {
2428 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
2429 }
2430
2431 /**
2432 * @brief Check if PLL output mapped on 48MHz domain clock is enabled
2433 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_48M
2434 * @retval State of bit (1 or 0).
2435 */
LL_RCC_PLL_IsEnabledDomain_48M(void)2436 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_48M(void)
2437 {
2438 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
2439 }
2440
2441 /**
2442 * @brief Enable PLL output mapped on SYSCLK domain
2443 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
2444 * @retval None
2445 */
LL_RCC_PLL_EnableDomain_SYS(void)2446 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
2447 {
2448 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
2449 }
2450
2451 /**
2452 * @brief Disable PLL output mapped on SYSCLK domain
2453 * @note Cannot be disabled if the PLL clock is used as the system
2454 * clock
2455 * @note In order to save power, when the PLLCLK of the PLL is
2456 * not used, Main PLL should be 0
2457 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
2458 * @retval None
2459 */
LL_RCC_PLL_DisableDomain_SYS(void)2460 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
2461 {
2462 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
2463 }
2464
2465 /**
2466 * @brief Check if PLL output mapped on SYSCLK domain clock is enabled
2467 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS
2468 * @retval State of bit (1 or 0).
2469 */
LL_RCC_PLL_IsEnabledDomain_SYS(void)2470 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void)
2471 {
2472 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL);
2473 }
2474
2475 /**
2476 * @}
2477 */
2478
2479 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
2480 * @{
2481 */
2482
2483 /**
2484 * @brief Clear LSI ready interrupt flag
2485 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
2486 * @retval None
2487 */
LL_RCC_ClearFlag_LSIRDY(void)2488 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
2489 {
2490 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
2491 }
2492
2493 /**
2494 * @brief Clear LSE ready interrupt flag
2495 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
2496 * @retval None
2497 */
LL_RCC_ClearFlag_LSERDY(void)2498 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
2499 {
2500 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
2501 }
2502
2503 /**
2504 * @brief Clear HSI ready interrupt flag
2505 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
2506 * @retval None
2507 */
LL_RCC_ClearFlag_HSIRDY(void)2508 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
2509 {
2510 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
2511 }
2512
2513 /**
2514 * @brief Clear HSE ready interrupt flag
2515 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
2516 * @retval None
2517 */
LL_RCC_ClearFlag_HSERDY(void)2518 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
2519 {
2520 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
2521 }
2522
2523 /**
2524 * @brief Clear PLL ready interrupt flag
2525 * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
2526 * @retval None
2527 */
LL_RCC_ClearFlag_PLLRDY(void)2528 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
2529 {
2530 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
2531 }
2532
2533 /**
2534 * @brief Clear HSI48 ready interrupt flag
2535 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
2536 * @retval None
2537 */
LL_RCC_ClearFlag_HSI48RDY(void)2538 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
2539 {
2540 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
2541 }
2542
2543 /**
2544 * @brief Clear Clock security system interrupt flag
2545 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
2546 * @retval None
2547 */
LL_RCC_ClearFlag_HSECSS(void)2548 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
2549 {
2550 SET_BIT(RCC->CICR, RCC_CICR_CSSC);
2551 }
2552
2553 /**
2554 * @brief Clear LSE Clock security system interrupt flag
2555 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
2556 * @retval None
2557 */
LL_RCC_ClearFlag_LSECSS(void)2558 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
2559 {
2560 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
2561 }
2562
2563 /**
2564 * @brief Check if LSI ready interrupt occurred or not
2565 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
2566 * @retval State of bit (1 or 0).
2567 */
LL_RCC_IsActiveFlag_LSIRDY(void)2568 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
2569 {
2570 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);
2571 }
2572
2573 /**
2574 * @brief Check if LSE ready interrupt occurred or not
2575 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
2576 * @retval State of bit (1 or 0).
2577 */
LL_RCC_IsActiveFlag_LSERDY(void)2578 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
2579 {
2580 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
2581 }
2582
2583 /**
2584 * @brief Check if HSI ready interrupt occurred or not
2585 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
2586 * @retval State of bit (1 or 0).
2587 */
LL_RCC_IsActiveFlag_HSIRDY(void)2588 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
2589 {
2590 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
2591 }
2592
2593 /**
2594 * @brief Check if HSE ready interrupt occurred or not
2595 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
2596 * @retval State of bit (1 or 0).
2597 */
LL_RCC_IsActiveFlag_HSERDY(void)2598 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
2599 {
2600 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
2601 }
2602
2603 /**
2604 * @brief Check if PLL ready interrupt occurred or not
2605 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
2606 * @retval State of bit (1 or 0).
2607 */
LL_RCC_IsActiveFlag_PLLRDY(void)2608 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
2609 {
2610 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
2611 }
2612
2613 /**
2614 * @brief Check if HSI48 ready interrupt occurred or not
2615 * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
2616 * @retval State of bit (1 or 0).
2617 */
LL_RCC_IsActiveFlag_HSI48RDY(void)2618 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
2619 {
2620 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
2621 }
2622
2623 /**
2624 * @brief Check if Clock security system interrupt occurred or not
2625 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
2626 * @retval State of bit (1 or 0).
2627 */
LL_RCC_IsActiveFlag_HSECSS(void)2628 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
2629 {
2630 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
2631 }
2632
2633 /**
2634 * @brief Check if LSE Clock security system interrupt occurred or not
2635 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
2636 * @retval State of bit (1 or 0).
2637 */
LL_RCC_IsActiveFlag_LSECSS(void)2638 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
2639 {
2640 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
2641 }
2642
2643 /**
2644 * @brief Check if RCC flag Independent Watchdog reset is set or not.
2645 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
2646 * @retval State of bit (1 or 0).
2647 */
LL_RCC_IsActiveFlag_IWDGRST(void)2648 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
2649 {
2650 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL);
2651 }
2652
2653 /**
2654 * @brief Check if RCC flag Low Power reset is set or not.
2655 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
2656 * @retval State of bit (1 or 0).
2657 */
LL_RCC_IsActiveFlag_LPWRRST(void)2658 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
2659 {
2660 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL);
2661 }
2662
2663 /**
2664 * @brief Check if RCC flag Option byte reset is set or not.
2665 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
2666 * @retval State of bit (1 or 0).
2667 */
LL_RCC_IsActiveFlag_OBLRST(void)2668 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
2669 {
2670 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL);
2671 }
2672
2673 /**
2674 * @brief Check if RCC flag Pin reset is set or not.
2675 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
2676 * @retval State of bit (1 or 0).
2677 */
LL_RCC_IsActiveFlag_PINRST(void)2678 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
2679 {
2680 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL);
2681 }
2682
2683 /**
2684 * @brief Check if RCC flag Software reset is set or not.
2685 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
2686 * @retval State of bit (1 or 0).
2687 */
LL_RCC_IsActiveFlag_SFTRST(void)2688 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
2689 {
2690 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL);
2691 }
2692
2693 /**
2694 * @brief Check if RCC flag Window Watchdog reset is set or not.
2695 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
2696 * @retval State of bit (1 or 0).
2697 */
LL_RCC_IsActiveFlag_WWDGRST(void)2698 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
2699 {
2700 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL);
2701 }
2702
2703 /**
2704 * @brief Check if RCC flag BOR reset is set or not.
2705 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
2706 * @retval State of bit (1 or 0).
2707 */
LL_RCC_IsActiveFlag_BORRST(void)2708 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
2709 {
2710 return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)) ? 1UL : 0UL);
2711 }
2712
2713 /**
2714 * @brief Set RMVF bit to clear the reset flags.
2715 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
2716 * @retval None
2717 */
LL_RCC_ClearResetFlags(void)2718 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
2719 {
2720 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
2721 }
2722
2723 /**
2724 * @}
2725 */
2726
2727 /** @defgroup RCC_LL_EF_IT_Management IT Management
2728 * @{
2729 */
2730
2731 /**
2732 * @brief Enable LSI ready interrupt
2733 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
2734 * @retval None
2735 */
LL_RCC_EnableIT_LSIRDY(void)2736 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
2737 {
2738 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
2739 }
2740
2741 /**
2742 * @brief Enable LSE ready interrupt
2743 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
2744 * @retval None
2745 */
LL_RCC_EnableIT_LSERDY(void)2746 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
2747 {
2748 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
2749 }
2750
2751 /**
2752 * @brief Enable HSI ready interrupt
2753 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
2754 * @retval None
2755 */
LL_RCC_EnableIT_HSIRDY(void)2756 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
2757 {
2758 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
2759 }
2760
2761 /**
2762 * @brief Enable HSE ready interrupt
2763 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
2764 * @retval None
2765 */
LL_RCC_EnableIT_HSERDY(void)2766 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
2767 {
2768 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
2769 }
2770
2771 /**
2772 * @brief Enable PLL ready interrupt
2773 * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
2774 * @retval None
2775 */
LL_RCC_EnableIT_PLLRDY(void)2776 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
2777 {
2778 SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
2779 }
2780
2781 /**
2782 * @brief Enable HSI48 ready interrupt
2783 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
2784 * @retval None
2785 */
LL_RCC_EnableIT_HSI48RDY(void)2786 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
2787 {
2788 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
2789 }
2790
2791 /**
2792 * @brief Enable LSE clock security system interrupt
2793 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
2794 * @retval None
2795 */
LL_RCC_EnableIT_LSECSS(void)2796 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
2797 {
2798 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
2799 }
2800
2801 /**
2802 * @brief Disable LSI ready interrupt
2803 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
2804 * @retval None
2805 */
LL_RCC_DisableIT_LSIRDY(void)2806 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
2807 {
2808 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
2809 }
2810
2811 /**
2812 * @brief Disable LSE ready interrupt
2813 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
2814 * @retval None
2815 */
LL_RCC_DisableIT_LSERDY(void)2816 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
2817 {
2818 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
2819 }
2820
2821 /**
2822 * @brief Disable HSI ready interrupt
2823 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
2824 * @retval None
2825 */
LL_RCC_DisableIT_HSIRDY(void)2826 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
2827 {
2828 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
2829 }
2830
2831 /**
2832 * @brief Disable HSE ready interrupt
2833 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
2834 * @retval None
2835 */
LL_RCC_DisableIT_HSERDY(void)2836 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
2837 {
2838 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
2839 }
2840
2841 /**
2842 * @brief Disable PLL ready interrupt
2843 * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
2844 * @retval None
2845 */
LL_RCC_DisableIT_PLLRDY(void)2846 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
2847 {
2848 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
2849 }
2850
2851 /**
2852 * @brief Disable HSI48 ready interrupt
2853 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
2854 * @retval None
2855 */
LL_RCC_DisableIT_HSI48RDY(void)2856 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
2857 {
2858 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
2859 }
2860
2861 /**
2862 * @brief Disable LSE clock security system interrupt
2863 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
2864 * @retval None
2865 */
LL_RCC_DisableIT_LSECSS(void)2866 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
2867 {
2868 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
2869 }
2870
2871 /**
2872 * @brief Checks if LSI ready interrupt source is enabled or disabled.
2873 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
2874 * @retval State of bit (1 or 0).
2875 */
LL_RCC_IsEnabledIT_LSIRDY(void)2876 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
2877 {
2878 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL);
2879 }
2880
2881 /**
2882 * @brief Checks if LSE ready interrupt source is enabled or disabled.
2883 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
2884 * @retval State of bit (1 or 0).
2885 */
LL_RCC_IsEnabledIT_LSERDY(void)2886 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
2887 {
2888 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
2889 }
2890
2891 /**
2892 * @brief Checks if HSI ready interrupt source is enabled or disabled.
2893 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
2894 * @retval State of bit (1 or 0).
2895 */
LL_RCC_IsEnabledIT_HSIRDY(void)2896 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
2897 {
2898 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
2899 }
2900
2901 /**
2902 * @brief Checks if HSE ready interrupt source is enabled or disabled.
2903 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
2904 * @retval State of bit (1 or 0).
2905 */
LL_RCC_IsEnabledIT_HSERDY(void)2906 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
2907 {
2908 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
2909 }
2910
2911 /**
2912 * @brief Checks if PLL ready interrupt source is enabled or disabled.
2913 * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
2914 * @retval State of bit (1 or 0).
2915 */
LL_RCC_IsEnabledIT_PLLRDY(void)2916 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
2917 {
2918 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL);
2919 }
2920
2921 /**
2922 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
2923 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
2924 * @retval State of bit (1 or 0).
2925 */
LL_RCC_IsEnabledIT_HSI48RDY(void)2926 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
2927 {
2928 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL);
2929 }
2930
2931 /**
2932 * @brief Checks if LSECSS interrupt source is enabled or disabled.
2933 * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
2934 * @retval State of bit (1 or 0).
2935 */
LL_RCC_IsEnabledIT_LSECSS(void)2936 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
2937 {
2938 return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE)) ? 1UL : 0UL);
2939 }
2940
2941 /**
2942 * @}
2943 */
2944
2945 #if defined(USE_FULL_LL_DRIVER)
2946 /** @defgroup RCC_LL_EF_Init De-initialization function
2947 * @{
2948 */
2949 ErrorStatus LL_RCC_DeInit(void);
2950 /**
2951 * @}
2952 */
2953
2954 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
2955 * @{
2956 */
2957 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
2958 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
2959 #if defined(UART4)
2960 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
2961 #endif /* UART4 */
2962 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
2963 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
2964 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
2965 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
2966 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
2967 #if defined(FDCAN1)
2968 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
2969 #endif /* FDCAN1 */
2970 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
2971 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
2972 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
2973 #if defined(QUADSPI)
2974 uint32_t LL_RCC_GetQUADSPIClockFreq(uint32_t QUADSPIxSource);
2975 #endif /* QUADSPI */
2976 /**
2977 * @}
2978 */
2979 #endif /* USE_FULL_LL_DRIVER */
2980
2981 /**
2982 * @}
2983 */
2984
2985 /**
2986 * @}
2987 */
2988
2989 /**
2990 * @}
2991 */
2992
2993 #ifdef __cplusplus
2994 }
2995 #endif
2996
2997 #endif /* STM32G4xx_LL_RCC_H */
2998
2999
