1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32G4xx_LL_LPTIM_H
21 #define STM32G4xx_LL_LPTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g4xx.h"
29
30 /** @addtogroup STM32G4xx_LL_Driver
31 * @{
32 */
33
34
35
36 /** @defgroup LPTIM_LL LPTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44
45 /* Private macros ------------------------------------------------------------*/
46 #if defined(USE_FULL_LL_DRIVER)
47 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
48 * @{
49 */
50 /**
51 * @}
52 */
53 #endif /*USE_FULL_LL_DRIVER*/
54
55 /* Exported types ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
58 * @{
59 */
60
61 /**
62 * @brief LPTIM Init structure definition
63 */
64 typedef struct
65 {
66 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
67 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
68
69 This feature can be modified afterwards using unitary
70 function @ref LL_LPTIM_SetClockSource().*/
71
72 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
73 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
74
75 This feature can be modified afterwards using using unitary
76 function @ref LL_LPTIM_SetPrescaler().*/
77
78 uint32_t Waveform; /*!< Specifies the waveform shape.
79 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
80
81 This feature can be modified afterwards using unitary
82 function @ref LL_LPTIM_ConfigOutput().*/
83
84 uint32_t Polarity; /*!< Specifies waveform polarity.
85 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
86
87 This feature can be modified afterwards using unitary
88 function @ref LL_LPTIM_ConfigOutput().*/
89 } LL_LPTIM_InitTypeDef;
90
91 /**
92 * @}
93 */
94 #endif /* USE_FULL_LL_DRIVER */
95
96 /* Exported constants --------------------------------------------------------*/
97 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
98 * @{
99 */
100
101 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
102 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
103 * @{
104 */
105 #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
106 #define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
107 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
108 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
109 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
110 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
111 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
112 /**
113 * @}
114 */
115
116 /** @defgroup LPTIM_LL_EC_IT IT Defines
117 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
118 * @{
119 */
120 #define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */
121 #define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */
122 #define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */
123 #define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */
124 #define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */
125 #define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */
126 #define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */
127 /**
128 * @}
129 */
130
131 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
132 * @{
133 */
134 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
135 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
136 /**
137 * @}
138 */
139
140 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
141 * @{
142 */
143 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
144 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
145 /**
146 * @}
147 */
148
149 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
150 * @{
151 */
152 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
153 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
154 /**
155 * @}
156 */
157
158 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
159 * @{
160 */
161 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
162 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
163 /**
164 * @}
165 */
166
167 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
168 * @{
169 */
170 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
171 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
172 /**
173 * @}
174 */
175
176 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
177 * @{
178 */
179 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
180 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
181 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
182 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
183 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
184 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
185 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
186 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
187 /**
188 * @}
189 */
190
191 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
192 * @{
193 */
194 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
195 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
196 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
197 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
198 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
199 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
200 #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
201 #define LL_LPTIM_TRIG_SOURCE_COMP2 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to COMP2 output*/
202 #define LL_LPTIM_TRIG_SOURCE_COMP3 LPTIM_CFGR_TRIGSEL_3 /*!<External input trigger is connected to COMP3 output*/
203 #define LL_LPTIM_TRIG_SOURCE_COMP4 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to COMP4 output*/
204 #if defined(COMP5)
205 #define LL_LPTIM_TRIG_SOURCE_COMP5 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP5 output*/
206 #endif /* COMP5 */
207 #if defined(COMP6)
208 #define LL_LPTIM_TRIG_SOURCE_COMP6 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to COMP6 output*/
209 #endif /* COMP6 */
210 #if defined(COMP7)
211 #define LL_LPTIM_TRIG_SOURCE_COMP7 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_2) /*!<External input trigger is connected to COMP7 output*/
212 #endif /* COMP7 */
213 /**
214 * @}
215 */
216
217 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
218 * @{
219 */
220 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
221 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
222 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
223 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
224 /**
225 * @}
226 */
227
228 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
229 * @{
230 */
231 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
232 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
233 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
234 /**
235 * @}
236 */
237
238 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
239 * @{
240 */
241 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
242 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
243 /**
244 * @}
245 */
246
247 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
248 * @{
249 */
250 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
251 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
252 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
253 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
254 /**
255 * @}
256 */
257
258 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
259 * @{
260 */
261 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
262 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
263 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
264 /**
265 * @}
266 */
267
268 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
269 * @{
270 */
271 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
272 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
273 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
274 /**
275 * @}
276 */
277
278 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
279 * @{
280 */
281 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U
282 #define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_IN1_0
283 #define LL_LPTIM_INPUT1_SRC_COMP3 (LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)
284 #if defined(COMP5)
285 #define LL_LPTIM_INPUT1_SRC_COMP5 (LPTIM_OR_IN1_2 | LPTIM_OR_IN1_0)
286 #endif /* COMP5 */
287 #if defined(COMP7)
288 #define LL_LPTIM_INPUT1_SRC_COMP7 (LPTIM_OR_IN1_2 | LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)
289 #endif /* COMP7 */
290 /**
291 * @}
292 */
293
294 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
295 * @{
296 */
297 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U
298 #define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_IN2_0
299 #define LL_LPTIM_INPUT2_SRC_COMP4 (LPTIM_OR_IN2_1 | LPTIM_OR_IN2_0)
300 #if defined(COMP6)
301 #define LL_LPTIM_INPUT2_SRC_COMP6 (LPTIM_OR_IN2_2 | LPTIM_OR_IN2_0)
302 #endif /* COMP6 */
303 /**
304 * @}
305 */
306
307 /**
308 * @}
309 */
310
311 /* Exported macro ------------------------------------------------------------*/
312 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
313 * @{
314 */
315
316 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
317 * @{
318 */
319
320 /**
321 * @brief Write a value in LPTIM register
322 * @param __INSTANCE__ LPTIM Instance
323 * @param __REG__ Register to be written
324 * @param __VALUE__ Value to be written in the register
325 * @retval None
326 */
327 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
328
329 /**
330 * @brief Read a value in LPTIM register
331 * @param __INSTANCE__ LPTIM Instance
332 * @param __REG__ Register to be read
333 * @retval Register value
334 */
335 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
336 /**
337 * @}
338 */
339
340 /**
341 * @}
342 */
343
344 /* Exported functions --------------------------------------------------------*/
345 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
346 * @{
347 */
348
349 #if defined(USE_FULL_LL_DRIVER)
350 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
351 * @{
352 */
353
354 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
355 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
356 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
357 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
358 /**
359 * @}
360 */
361 #endif /* USE_FULL_LL_DRIVER */
362
363 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
364 * @{
365 */
366
367 /**
368 * @brief Enable the LPTIM instance
369 * @note After setting the ENABLE bit, a delay of two counter clock is needed
370 * before the LPTIM instance is actually enabled.
371 * @rmtoll CR ENABLE LL_LPTIM_Enable
372 * @param LPTIMx Low-Power Timer instance
373 * @retval None
374 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)375 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
376 {
377 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
378 }
379
380 /**
381 * @brief Indicates whether the LPTIM instance is enabled.
382 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
383 * @param LPTIMx Low-Power Timer instance
384 * @retval State of bit (1 or 0).
385 */
LL_LPTIM_IsEnabled(LPTIM_TypeDef * LPTIMx)386 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
387 {
388 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
389 }
390
391 /**
392 * @brief Starts the LPTIM counter in the desired mode.
393 * @note LPTIM instance must be enabled before starting the counter.
394 * @note It is possible to change on the fly from One Shot mode to
395 * Continuous mode.
396 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
397 * CR SNGSTRT LL_LPTIM_StartCounter
398 * @param LPTIMx Low-Power Timer instance
399 * @param OperatingMode This parameter can be one of the following values:
400 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
401 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
402 * @retval None
403 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)404 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
405 {
406 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
407 }
408
409 /**
410 * @brief Enable reset after read.
411 * @note After calling this function any read access to LPTIM_CNT
412 * register will asynchronously reset the LPTIM_CNT register content.
413 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
414 * @param LPTIMx Low-Power Timer instance
415 * @retval None
416 */
LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef * LPTIMx)417 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
418 {
419 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
420 }
421
422 /**
423 * @brief Disable reset after read.
424 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
425 * @param LPTIMx Low-Power Timer instance
426 * @retval None
427 */
LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef * LPTIMx)428 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
429 {
430 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
431 }
432
433 /**
434 * @brief Indicate whether the reset after read feature is enabled.
435 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
436 * @param LPTIMx Low-Power Timer instance
437 * @retval State of bit (1 or 0).
438 */
LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef * LPTIMx)439 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)
440 {
441 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
442 }
443
444 /**
445 * @brief Reset of the LPTIM_CNT counter register (synchronous).
446 * @note Due to the synchronous nature of this reset, it only takes
447 * place after a synchronization delay of 3 LPTIM core clock cycles
448 * (LPTIM core clock may be different from APB clock).
449 * @note COUNTRST is automatically cleared by hardware
450 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
451 * @param LPTIMx Low-Power Timer instance
452 * @retval None
453 */
LL_LPTIM_ResetCounter(LPTIM_TypeDef * LPTIMx)454 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
455 {
456 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
457 }
458
459 /**
460 * @brief Set the LPTIM registers update mode (enable/disable register preload)
461 * @note This function must be called when the LPTIM instance is disabled.
462 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
463 * @param LPTIMx Low-Power Timer instance
464 * @param UpdateMode This parameter can be one of the following values:
465 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
466 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
467 * @retval None
468 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)469 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
470 {
471 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
472 }
473
474 /**
475 * @brief Get the LPTIM registers update mode
476 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
477 * @param LPTIMx Low-Power Timer instance
478 * @retval Returned value can be one of the following values:
479 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
480 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
481 */
LL_LPTIM_GetUpdateMode(LPTIM_TypeDef * LPTIMx)482 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
483 {
484 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
485 }
486
487 /**
488 * @brief Set the auto reload value
489 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
490 * @note After a write to the LPTIMx_ARR register a new write operation to the
491 * same register can only be performed when the previous write operation
492 * is completed. Any successive write before the ARROK flag is set, will
493 * lead to unpredictable results.
494 * @note autoreload value be strictly greater than the compare value.
495 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
496 * @param LPTIMx Low-Power Timer instance
497 * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
498 * @retval None
499 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)500 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
501 {
502 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
503 }
504
505 /**
506 * @brief Get actual auto reload value
507 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
508 * @param LPTIMx Low-Power Timer instance
509 * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
510 */
LL_LPTIM_GetAutoReload(LPTIM_TypeDef * LPTIMx)511 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
512 {
513 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
514 }
515
516 /**
517 * @brief Set the compare value
518 * @note After a write to the LPTIMx_CMP register a new write operation to the
519 * same register can only be performed when the previous write operation
520 * is completed. Any successive write before the CMPOK flag is set, will
521 * lead to unpredictable results.
522 * @rmtoll CMP CMP LL_LPTIM_SetCompare
523 * @param LPTIMx Low-Power Timer instance
524 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
525 * @retval None
526 */
LL_LPTIM_SetCompare(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)527 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
528 {
529 MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
530 }
531
532 /**
533 * @brief Get actual compare value
534 * @rmtoll CMP CMP LL_LPTIM_GetCompare
535 * @param LPTIMx Low-Power Timer instance
536 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
537 */
LL_LPTIM_GetCompare(LPTIM_TypeDef * LPTIMx)538 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
539 {
540 return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
541 }
542
543 /**
544 * @brief Get actual counter value
545 * @note When the LPTIM instance is running with an asynchronous clock, reading
546 * the LPTIMx_CNT register may return unreliable values. So in this case
547 * it is necessary to perform two consecutive read accesses and verify
548 * that the two returned values are identical.
549 * @rmtoll CNT CNT LL_LPTIM_GetCounter
550 * @param LPTIMx Low-Power Timer instance
551 * @retval Counter value
552 */
LL_LPTIM_GetCounter(LPTIM_TypeDef * LPTIMx)553 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
554 {
555 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
556 }
557
558 /**
559 * @brief Set the counter mode (selection of the LPTIM counter clock source).
560 * @note The counter mode can be set only when the LPTIM instance is disabled.
561 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
562 * @param LPTIMx Low-Power Timer instance
563 * @param CounterMode This parameter can be one of the following values:
564 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
565 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
566 * @retval None
567 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)568 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
569 {
570 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
571 }
572
573 /**
574 * @brief Get the counter mode
575 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
576 * @param LPTIMx Low-Power Timer instance
577 * @retval Returned value can be one of the following values:
578 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
579 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
580 */
LL_LPTIM_GetCounterMode(LPTIM_TypeDef * LPTIMx)581 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
582 {
583 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
584 }
585
586 /**
587 * @brief Configure the LPTIM instance output (LPTIMx_OUT)
588 * @note This function must be called when the LPTIM instance is disabled.
589 * @note Regarding the LPTIM output polarity the change takes effect
590 * immediately, so the output default value will change immediately after
591 * the polarity is re-configured, even before the timer is enabled.
592 * @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n
593 * CFGR WAVPOL LL_LPTIM_ConfigOutput
594 * @param LPTIMx Low-Power Timer instance
595 * @param Waveform This parameter can be one of the following values:
596 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
597 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
598 * @param Polarity This parameter can be one of the following values:
599 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
600 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
601 * @retval None
602 */
LL_LPTIM_ConfigOutput(LPTIM_TypeDef * LPTIMx,uint32_t Waveform,uint32_t Polarity)603 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
604 {
605 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
606 }
607
608 /**
609 * @brief Set waveform shape
610 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
611 * @param LPTIMx Low-Power Timer instance
612 * @param Waveform This parameter can be one of the following values:
613 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
614 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
615 * @retval None
616 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)617 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
618 {
619 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
620 }
621
622 /**
623 * @brief Get actual waveform shape
624 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
625 * @param LPTIMx Low-Power Timer instance
626 * @retval Returned value can be one of the following values:
627 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
628 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
629 */
LL_LPTIM_GetWaveform(LPTIM_TypeDef * LPTIMx)630 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
631 {
632 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
633 }
634
635 /**
636 * @brief Set output polarity
637 * @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity
638 * @param LPTIMx Low-Power Timer instance
639 * @param Polarity This parameter can be one of the following values:
640 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
641 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
642 * @retval None
643 */
LL_LPTIM_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Polarity)644 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
645 {
646 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
647 }
648
649 /**
650 * @brief Get actual output polarity
651 * @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity
652 * @param LPTIMx Low-Power Timer instance
653 * @retval Returned value can be one of the following values:
654 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
655 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
656 */
LL_LPTIM_GetPolarity(LPTIM_TypeDef * LPTIMx)657 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
658 {
659 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
660 }
661
662 /**
663 * @brief Set actual prescaler division ratio.
664 * @note This function must be called when the LPTIM instance is disabled.
665 * @note When the LPTIM is configured to be clocked by an internal clock source
666 * and the LPTIM counter is configured to be updated by active edges
667 * detected on the LPTIM external Input1, the internal clock provided to
668 * the LPTIM must be not be prescaled.
669 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
670 * @param LPTIMx Low-Power Timer instance
671 * @param Prescaler This parameter can be one of the following values:
672 * @arg @ref LL_LPTIM_PRESCALER_DIV1
673 * @arg @ref LL_LPTIM_PRESCALER_DIV2
674 * @arg @ref LL_LPTIM_PRESCALER_DIV4
675 * @arg @ref LL_LPTIM_PRESCALER_DIV8
676 * @arg @ref LL_LPTIM_PRESCALER_DIV16
677 * @arg @ref LL_LPTIM_PRESCALER_DIV32
678 * @arg @ref LL_LPTIM_PRESCALER_DIV64
679 * @arg @ref LL_LPTIM_PRESCALER_DIV128
680 * @retval None
681 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)682 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
683 {
684 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
685 }
686
687 /**
688 * @brief Get actual prescaler division ratio.
689 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
690 * @param LPTIMx Low-Power Timer instance
691 * @retval Returned value can be one of the following values:
692 * @arg @ref LL_LPTIM_PRESCALER_DIV1
693 * @arg @ref LL_LPTIM_PRESCALER_DIV2
694 * @arg @ref LL_LPTIM_PRESCALER_DIV4
695 * @arg @ref LL_LPTIM_PRESCALER_DIV8
696 * @arg @ref LL_LPTIM_PRESCALER_DIV16
697 * @arg @ref LL_LPTIM_PRESCALER_DIV32
698 * @arg @ref LL_LPTIM_PRESCALER_DIV64
699 * @arg @ref LL_LPTIM_PRESCALER_DIV128
700 */
LL_LPTIM_GetPrescaler(LPTIM_TypeDef * LPTIMx)701 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
702 {
703 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
704 }
705
706 /**
707 * @brief Set LPTIM input 1 source (default GPIO).
708 * @rmtoll OR IN1 LL_LPTIM_SetInput1Src
709 * @param LPTIMx Low-Power Timer instance
710 * @param Src This parameter can be one of the following values:
711 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
712 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
713 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP3
714 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP5 (*)
715 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP7 (*)
716 * (*) Value not defined for all devices
717 * @retval None
718 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)719 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
720 {
721 MODIFY_REG(LPTIMx->OR, LPTIM_OR_IN1, Src);
722 }
723
724 /**
725 * @brief Set LPTIM input 2 source (default GPIO).
726 * @rmtoll OR IN2 LL_LPTIM_SetInput2Src
727 * @param LPTIMx Low-Power Timer instance
728 * @param Src This parameter can be one of the following values:
729 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
730 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
731 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP4
732 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP6 (*)
733 * (*) Value not defined for all devices
734 * @retval None
735 */
LL_LPTIM_SetInput2Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)736 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
737 {
738 MODIFY_REG(LPTIMx->OR, LPTIM_OR_IN2, Src);
739 }
740
741 /**
742 * @}
743 */
744
745 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
746 * @{
747 */
748
749 /**
750 * @brief Enable the timeout function
751 * @note This function must be called when the LPTIM instance is disabled.
752 * @note The first trigger event will start the timer, any successive trigger
753 * event will reset the counter and the timer will restart.
754 * @note The timeout value corresponds to the compare value; if no trigger
755 * occurs within the expected time frame, the MCU is waked-up by the
756 * compare match event.
757 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
758 * @param LPTIMx Low-Power Timer instance
759 * @retval None
760 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)761 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
762 {
763 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
764 }
765
766 /**
767 * @brief Disable the timeout function
768 * @note This function must be called when the LPTIM instance is disabled.
769 * @note A trigger event arriving when the timer is already started will be
770 * ignored.
771 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
772 * @param LPTIMx Low-Power Timer instance
773 * @retval None
774 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)775 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
776 {
777 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
778 }
779
780 /**
781 * @brief Indicate whether the timeout function is enabled.
782 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
783 * @param LPTIMx Low-Power Timer instance
784 * @retval State of bit (1 or 0).
785 */
LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef * LPTIMx)786 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
787 {
788 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
789 }
790
791 /**
792 * @brief Start the LPTIM counter
793 * @note This function must be called when the LPTIM instance is disabled.
794 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
795 * @param LPTIMx Low-Power Timer instance
796 * @retval None
797 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)798 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
799 {
800 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
801 }
802
803 /**
804 * @brief Configure the external trigger used as a trigger event for the LPTIM.
805 * @note This function must be called when the LPTIM instance is disabled.
806 * @note An internal clock source must be present when a digital filter is
807 * required for the trigger.
808 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
809 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
810 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
811 * @param LPTIMx Low-Power Timer instance
812 * @param Source This parameter can be one of the following values:
813 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
814 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
815 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
816 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
817 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
818 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
819 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
820 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
821 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP3
822 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP4
823 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP5 (*)
824 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP6 (*)
825 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP7 (*)
826 *
827 * (*) Value not defined in all devices. \n
828 *
829 * @param Filter This parameter can be one of the following values:
830 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
831 * @arg @ref LL_LPTIM_TRIG_FILTER_2
832 * @arg @ref LL_LPTIM_TRIG_FILTER_4
833 * @arg @ref LL_LPTIM_TRIG_FILTER_8
834 * @param Polarity This parameter can be one of the following values:
835 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
836 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
837 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
838 * @retval None
839 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)840 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
841 {
842 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
843 }
844
845 /**
846 * @brief Get actual external trigger source.
847 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
848 * @param LPTIMx Low-Power Timer instance
849 * @retval Returned value can be one of the following values:
850 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
851 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
852 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
853 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
854 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
855 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
856 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
857 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
858 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP3
859 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP4
860 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP5 (*)
861 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP6 (*)
862 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP7 (*)
863 *
864 * (*) Value not defined in all devices. \n
865 */
LL_LPTIM_GetTriggerSource(LPTIM_TypeDef * LPTIMx)866 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
867 {
868 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
869 }
870
871 /**
872 * @brief Get actual external trigger filter.
873 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
874 * @param LPTIMx Low-Power Timer instance
875 * @retval Returned value can be one of the following values:
876 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
877 * @arg @ref LL_LPTIM_TRIG_FILTER_2
878 * @arg @ref LL_LPTIM_TRIG_FILTER_4
879 * @arg @ref LL_LPTIM_TRIG_FILTER_8
880 */
LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef * LPTIMx)881 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
882 {
883 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
884 }
885
886 /**
887 * @brief Get actual external trigger polarity.
888 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
889 * @param LPTIMx Low-Power Timer instance
890 * @retval Returned value can be one of the following values:
891 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
892 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
893 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
894 */
LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef * LPTIMx)895 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
896 {
897 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
898 }
899
900 /**
901 * @}
902 */
903
904 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
905 * @{
906 */
907
908 /**
909 * @brief Set the source of the clock used by the LPTIM instance.
910 * @note This function must be called when the LPTIM instance is disabled.
911 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
912 * @param LPTIMx Low-Power Timer instance
913 * @param ClockSource This parameter can be one of the following values:
914 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
915 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
916 * @retval None
917 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)918 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
919 {
920 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
921 }
922
923 /**
924 * @brief Get actual LPTIM instance clock source.
925 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
926 * @param LPTIMx Low-Power Timer instance
927 * @retval Returned value can be one of the following values:
928 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
929 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
930 */
LL_LPTIM_GetClockSource(LPTIM_TypeDef * LPTIMx)931 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
932 {
933 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
934 }
935
936 /**
937 * @brief Configure the active edge or edges used by the counter when
938 the LPTIM is clocked by an external clock source.
939 * @note This function must be called when the LPTIM instance is disabled.
940 * @note When both external clock signal edges are considered active ones,
941 * the LPTIM must also be clocked by an internal clock source with a
942 * frequency equal to at least four times the external clock frequency.
943 * @note An internal clock source must be present when a digital filter is
944 * required for external clock.
945 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
946 * CFGR CKPOL LL_LPTIM_ConfigClock
947 * @param LPTIMx Low-Power Timer instance
948 * @param ClockFilter This parameter can be one of the following values:
949 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
950 * @arg @ref LL_LPTIM_CLK_FILTER_2
951 * @arg @ref LL_LPTIM_CLK_FILTER_4
952 * @arg @ref LL_LPTIM_CLK_FILTER_8
953 * @param ClockPolarity This parameter can be one of the following values:
954 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
955 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
956 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
957 * @retval None
958 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)959 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
960 {
961 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
962 }
963
964 /**
965 * @brief Get actual clock polarity
966 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
967 * @param LPTIMx Low-Power Timer instance
968 * @retval Returned value can be one of the following values:
969 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
970 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
971 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
972 */
LL_LPTIM_GetClockPolarity(LPTIM_TypeDef * LPTIMx)973 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
974 {
975 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
976 }
977
978 /**
979 * @brief Get actual clock digital filter
980 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
981 * @param LPTIMx Low-Power Timer instance
982 * @retval Returned value can be one of the following values:
983 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
984 * @arg @ref LL_LPTIM_CLK_FILTER_2
985 * @arg @ref LL_LPTIM_CLK_FILTER_4
986 * @arg @ref LL_LPTIM_CLK_FILTER_8
987 */
LL_LPTIM_GetClockFilter(LPTIM_TypeDef * LPTIMx)988 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
989 {
990 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
991 }
992
993 /**
994 * @}
995 */
996
997 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
998 * @{
999 */
1000
1001 /**
1002 * @brief Configure the encoder mode.
1003 * @note This function must be called when the LPTIM instance is disabled.
1004 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
1005 * @param LPTIMx Low-Power Timer instance
1006 * @param EncoderMode This parameter can be one of the following values:
1007 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1008 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1009 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1010 * @retval None
1011 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)1012 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
1013 {
1014 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
1015 }
1016
1017 /**
1018 * @brief Get actual encoder mode.
1019 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1020 * @param LPTIMx Low-Power Timer instance
1021 * @retval Returned value can be one of the following values:
1022 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1023 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1024 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1025 */
LL_LPTIM_GetEncoderMode(LPTIM_TypeDef * LPTIMx)1026 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
1027 {
1028 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1029 }
1030
1031 /**
1032 * @brief Enable the encoder mode
1033 * @note This function must be called when the LPTIM instance is disabled.
1034 * @note In this mode the LPTIM instance must be clocked by an internal clock
1035 * source. Also, the prescaler division ratio must be equal to 1.
1036 * @note LPTIM instance must be configured in continuous mode prior enabling
1037 * the encoder mode.
1038 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1039 * @param LPTIMx Low-Power Timer instance
1040 * @retval None
1041 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)1042 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1043 {
1044 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1045 }
1046
1047 /**
1048 * @brief Disable the encoder mode
1049 * @note This function must be called when the LPTIM instance is disabled.
1050 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1051 * @param LPTIMx Low-Power Timer instance
1052 * @retval None
1053 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)1054 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1055 {
1056 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1057 }
1058
1059 /**
1060 * @brief Indicates whether the LPTIM operates in encoder mode.
1061 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1062 * @param LPTIMx Low-Power Timer instance
1063 * @retval State of bit (1 or 0).
1064 */
LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef * LPTIMx)1065 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
1066 {
1067 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
1068 }
1069
1070 /**
1071 * @}
1072 */
1073
1074 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1075 * @{
1076 */
1077
1078 /**
1079 * @brief Clear the compare match flag (CMPMCF)
1080 * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
1081 * @param LPTIMx Low-Power Timer instance
1082 * @retval None
1083 */
LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef * LPTIMx)1084 __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
1085 {
1086 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
1087 }
1088
1089 /**
1090 * @brief Inform application whether a compare match interrupt has occurred.
1091 * @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
1092 * @param LPTIMx Low-Power Timer instance
1093 * @retval State of bit (1 or 0).
1094 */
LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef * LPTIMx)1095 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
1096 {
1097 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
1098 }
1099
1100 /**
1101 * @brief Clear the autoreload match flag (ARRMCF)
1102 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
1103 * @param LPTIMx Low-Power Timer instance
1104 * @retval None
1105 */
LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef * LPTIMx)1106 __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
1107 {
1108 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1109 }
1110
1111 /**
1112 * @brief Inform application whether a autoreload match interrupt has occurred.
1113 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1114 * @param LPTIMx Low-Power Timer instance
1115 * @retval State of bit (1 or 0).
1116 */
LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef * LPTIMx)1117 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1118 {
1119 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
1120 }
1121
1122 /**
1123 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1124 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1125 * @param LPTIMx Low-Power Timer instance
1126 * @retval None
1127 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1128 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1129 {
1130 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1131 }
1132
1133 /**
1134 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1135 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1136 * @param LPTIMx Low-Power Timer instance
1137 * @retval State of bit (1 or 0).
1138 */
LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1139 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1140 {
1141 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
1142 }
1143
1144 /**
1145 * @brief Clear the compare register update interrupt flag (CMPOKCF).
1146 * @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
1147 * @param LPTIMx Low-Power Timer instance
1148 * @retval None
1149 */
LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef * LPTIMx)1150 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1151 {
1152 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
1153 }
1154
1155 /**
1156 * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully
1157 completed. If so, a new one can be initiated.
1158 * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
1159 * @param LPTIMx Low-Power Timer instance
1160 * @retval State of bit (1 or 0).
1161 */
LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef * LPTIMx)1162 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1163 {
1164 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
1165 }
1166
1167 /**
1168 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1169 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1170 * @param LPTIMx Low-Power Timer instance
1171 * @retval None
1172 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)1173 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1174 {
1175 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1176 }
1177
1178 /**
1179 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
1180 completed. If so, a new one can be initiated.
1181 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1182 * @param LPTIMx Low-Power Timer instance
1183 * @retval State of bit (1 or 0).
1184 */
LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef * LPTIMx)1185 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1186 {
1187 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
1188 }
1189
1190 /**
1191 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1192 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1193 * @param LPTIMx Low-Power Timer instance
1194 * @retval None
1195 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)1196 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1197 {
1198 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1199 }
1200
1201 /**
1202 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
1203 operates in encoder mode).
1204 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1205 * @param LPTIMx Low-Power Timer instance
1206 * @retval State of bit (1 or 0).
1207 */
LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef * LPTIMx)1208 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
1209 {
1210 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
1211 }
1212
1213 /**
1214 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1215 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1216 * @param LPTIMx Low-Power Timer instance
1217 * @retval None
1218 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)1219 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1220 {
1221 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1222 }
1223
1224 /**
1225 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
1226 operates in encoder mode).
1227 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1228 * @param LPTIMx Low-Power Timer instance
1229 * @retval State of bit (1 or 0).
1230 */
LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef * LPTIMx)1231 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1232 {
1233 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
1234 }
1235
1236 /**
1237 * @}
1238 */
1239
1240 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1241 * @{
1242 */
1243
1244 /**
1245 * @brief Enable compare match interrupt (CMPMIE).
1246 * @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM
1247 * @param LPTIMx Low-Power Timer instance
1248 * @retval None
1249 */
LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef * LPTIMx)1250 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1251 {
1252 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1253 }
1254
1255 /**
1256 * @brief Disable compare match interrupt (CMPMIE).
1257 * @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM
1258 * @param LPTIMx Low-Power Timer instance
1259 * @retval None
1260 */
LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef * LPTIMx)1261 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1262 {
1263 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1264 }
1265
1266 /**
1267 * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
1268 * @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
1269 * @param LPTIMx Low-Power Timer instance
1270 * @retval State of bit (1 or 0).
1271 */
LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef * LPTIMx)1272 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
1273 {
1274 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
1275 }
1276
1277 /**
1278 * @brief Enable autoreload match interrupt (ARRMIE).
1279 * @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM
1280 * @param LPTIMx Low-Power Timer instance
1281 * @retval None
1282 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)1283 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1284 {
1285 SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1286 }
1287
1288 /**
1289 * @brief Disable autoreload match interrupt (ARRMIE).
1290 * @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM
1291 * @param LPTIMx Low-Power Timer instance
1292 * @retval None
1293 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)1294 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1295 {
1296 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1297 }
1298
1299 /**
1300 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
1301 * @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
1302 * @param LPTIMx Low-Power Timer instance
1303 * @retval State of bit (1 or 0).
1304 */
LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef * LPTIMx)1305 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
1306 {
1307 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
1308 }
1309
1310 /**
1311 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
1312 * @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
1313 * @param LPTIMx Low-Power Timer instance
1314 * @retval None
1315 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1316 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1317 {
1318 SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1319 }
1320
1321 /**
1322 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
1323 * @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
1324 * @param LPTIMx Low-Power Timer instance
1325 * @retval None
1326 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1327 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1328 {
1329 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1330 }
1331
1332 /**
1333 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
1334 * @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
1335 * @param LPTIMx Low-Power Timer instance
1336 * @retval State of bit (1 or 0).
1337 */
LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1338 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1339 {
1340 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
1341 }
1342
1343 /**
1344 * @brief Enable compare register write completed interrupt (CMPOKIE).
1345 * @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
1346 * @param LPTIMx Low-Power Timer instance
1347 * @retval None
1348 */
LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1349 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1350 {
1351 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1352 }
1353
1354 /**
1355 * @brief Disable compare register write completed interrupt (CMPOKIE).
1356 * @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
1357 * @param LPTIMx Low-Power Timer instance
1358 * @retval None
1359 */
LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1360 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1361 {
1362 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1363 }
1364
1365 /**
1366 * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
1367 * @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
1368 * @param LPTIMx Low-Power Timer instance
1369 * @retval State of bit (1 or 0).
1370 */
LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef * LPTIMx)1371 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1372 {
1373 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
1374 }
1375
1376 /**
1377 * @brief Enable autoreload register write completed interrupt (ARROKIE).
1378 * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
1379 * @param LPTIMx Low-Power Timer instance
1380 * @retval None
1381 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)1382 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1383 {
1384 SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1385 }
1386
1387 /**
1388 * @brief Disable autoreload register write completed interrupt (ARROKIE).
1389 * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
1390 * @param LPTIMx Low-Power Timer instance
1391 * @retval None
1392 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)1393 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1394 {
1395 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1396 }
1397
1398 /**
1399 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
1400 * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
1401 * @param LPTIMx Low-Power Timer instance
1402 * @retval State of bit(1 or 0).
1403 */
LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef * LPTIMx)1404 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
1405 {
1406 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
1407 }
1408
1409 /**
1410 * @brief Enable direction change to up interrupt (UPIE).
1411 * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
1412 * @param LPTIMx Low-Power Timer instance
1413 * @retval None
1414 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)1415 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
1416 {
1417 SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1418 }
1419
1420 /**
1421 * @brief Disable direction change to up interrupt (UPIE).
1422 * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
1423 * @param LPTIMx Low-Power Timer instance
1424 * @retval None
1425 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)1426 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
1427 {
1428 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1429 }
1430
1431 /**
1432 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
1433 * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
1434 * @param LPTIMx Low-Power Timer instance
1435 * @retval State of bit(1 or 0).
1436 */
LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef * LPTIMx)1437 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
1438 {
1439 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
1440 }
1441
1442 /**
1443 * @brief Enable direction change to down interrupt (DOWNIE).
1444 * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
1445 * @param LPTIMx Low-Power Timer instance
1446 * @retval None
1447 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)1448 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1449 {
1450 SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1451 }
1452
1453 /**
1454 * @brief Disable direction change to down interrupt (DOWNIE).
1455 * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
1456 * @param LPTIMx Low-Power Timer instance
1457 * @retval None
1458 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)1459 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1460 {
1461 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1462 }
1463
1464 /**
1465 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
1466 * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
1467 * @param LPTIMx Low-Power Timer instance
1468 * @retval State of bit(1 or 0).
1469 */
LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef * LPTIMx)1470 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
1471 {
1472 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
1473 }
1474
1475 /**
1476 * @}
1477 */
1478
1479 /**
1480 * @}
1481 */
1482
1483 /**
1484 * @}
1485 */
1486
1487
1488
1489 /**
1490 * @}
1491 */
1492
1493 #ifdef __cplusplus
1494 }
1495 #endif
1496
1497 #endif /* STM32G4xx_LL_LPTIM_H */
1498
