1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_hrtim.h
4 * @author MCD Application Team
5 * @brief Header file of HRTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32G4xx_LL_HRTIM_H
21 #define STM32G4xx_LL_HRTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g4xx.h"
29
30 /** @addtogroup STM32G4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (HRTIM1)
35
36 /** @defgroup HRTIM_LL HRTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables
43 * @{
44 */
45 static const uint16_t REG_OFFSET_TAB_TIMER[] =
46 {
47 0x00U, /* 0: MASTER */
48 0x80U, /* 1: TIMER A */
49 0x100U, /* 2: TIMER B */
50 0x180U, /* 3: TIMER C */
51 0x200U, /* 4: TIMER D */
52 0x280U, /* 5: TIMER E */
53 0x300U, /* 6: TIMER F */
54 };
55
56 static const uint8_t REG_OFFSET_TAB_ADCER[] =
57 {
58 0x00U, /* LL_HRTIM_ADCTRIG_1: HRTIM_ADC1R */
59 0x04U, /* LL_HRTIM_ADCTRIG_2: HRTIM_ADC2R */
60 0x08U, /* LL_HRTIM_ADCTRIG_3: HRTIM_ADC3R */
61 0x0CU, /* LL_HRTIM_ADCTRIG_4: HRTIM_ADC4R */
62 0x3CU, /* LL_HRTIM_ADCTRIG_5: HRTIM_ADCER */
63 0x3CU, /* LL_HRTIM_ADCTRIG_6: HRTIM_ADCER */
64 0x3CU, /* LL_HRTIM_ADCTRIG_7: HRTIM_ADCER */
65 0x3CU, /* LL_HRTIM_ADCTRIG_8: HRTIM_ADCER */
66 0x3CU, /* LL_HRTIM_ADCTRIG_9: HRTIM_ADCER */
67 0x3CU, /* LL_HRTIM_ADCTRIG_10: HRTIM_ADCER */
68 };
69
70 static const uint8_t REG_OFFSET_TAB_ADCUR[] =
71 {
72 0x00U, /* LL_HRTIM_ADCTRIG_1: HRTIM_CR1 */
73 0x00U, /* LL_HRTIM_ADCTRIG_2: HRTIM_CR1 */
74 0x00U, /* LL_HRTIM_ADCTRIG_3: HRTIM_CR1 */
75 0x00U, /* LL_HRTIM_ADCTRIG_4: HRTIM_CR1 */
76 0x7CU, /* LL_HRTIM_ADCTRIG_5: HRTIM_ADCUR */
77 0x7CU, /* LL_HRTIM_ADCTRIG_6: HRTIM_ADCUR */
78 0x7CU, /* LL_HRTIM_ADCTRIG_7: HRTIM_ADCUR */
79 0x7CU, /* LL_HRTIM_ADCTRIG_8: HRTIM_ADCUR */
80 0x7CU, /* LL_HRTIM_ADCTRIG_9: HRTIM_ADCUR */
81 0x7CU, /* LL_HRTIM_ADCTRIG_10: HRTIM_ADCUR */
82 };
83
84 static const uint8_t REG_SHIFT_TAB_ADCER[] =
85 {
86 0, /* LL_HRTIM_ADCTRIG_1 */
87 0, /* LL_HRTIM_ADCTRIG_2 */
88 0, /* LL_HRTIM_ADCTRIG_3 */
89 0, /* LL_HRTIM_ADCTRIG_4 */
90 0, /* LL_HRTIM_ADCTRIG_5 */
91 5, /* LL_HRTIM_ADCTRIG_6 */
92 10, /* LL_HRTIM_ADCTRIG_7 */
93 16, /* LL_HRTIM_ADCTRIG_8 */
94 21, /* LL_HRTIM_ADCTRIG_9 */
95 26 /* LL_HRTIM_ADCTRIG_10 */
96 };
97
98 static const uint8_t REG_SHIFT_TAB_ADCUR[] =
99 {
100 16, /* LL_HRTIM_ADCTRIG_1 */
101 19, /* LL_HRTIM_ADCTRIG_2 */
102 22, /* LL_HRTIM_ADCTRIG_3 */
103 25, /* LL_HRTIM_ADCTRIG_4 */
104 0, /* LL_HRTIM_ADCTRIG_5 */
105 4, /* LL_HRTIM_ADCTRIG_6 */
106 8, /* LL_HRTIM_ADCTRIG_7 */
107 12, /* LL_HRTIM_ADCTRIG_8 */
108 16, /* LL_HRTIM_ADCTRIG_9 */
109 20 /* LL_HRTIM_ADCTRIG_10 */
110 };
111
112 static const uint32_t REG_MASK_TAB_ADCER[] =
113 {
114 0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_1 */
115 0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_2 */
116 0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_3 */
117 0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_4 */
118 0x0000001FU, /* LL_HRTIM_ADCTRIG_5 */
119 0x000003E0U, /* LL_HRTIM_ADCTRIG_6 */
120 0x00007C00U, /* LL_HRTIM_ADCTRIG_7 */
121 0x001F0000U, /* LL_HRTIM_ADCTRIG_8 */
122 0x03E00000U, /* LL_HRTIM_ADCTRIG_9 */
123 0x7C000000U /* LL_HRTIM_ADCTRIG_10 */
124 };
125
126 static const uint32_t REG_MASK_TAB_ADCUR[] =
127 {
128 0x00070000U, /* LL_HRTIM_ADCTRIG_1 */
129 0x00380000U, /* LL_HRTIM_ADCTRIG_2 */
130 0x01C00000U, /* LL_HRTIM_ADCTRIG_3 */
131 0x0E000000U, /* LL_HRTIM_ADCTRIG_4 */
132 0x00000007U, /* LL_HRTIM_ADCTRIG_5 */
133 0x00000070U, /* LL_HRTIM_ADCTRIG_6 */
134 0x00000700U, /* LL_HRTIM_ADCTRIG_7 */
135 0x00007000U, /* LL_HRTIM_ADCTRIG_8 */
136 0x00070000U, /* LL_HRTIM_ADCTRIG_9 */
137 0x00700000U /* LL_HRTIM_ADCTRIG_10 */
138 };
139
140 static const uint8_t REG_OFFSET_TAB_ADCPSx[] =
141 {
142 0U, /* 0: HRTIM_ADC1R */
143 6U, /* 1: HRTIM_ADC2R */
144 12U, /* 2: HRTIM_ADC3R */
145 18U, /* 3: HRTIM_ADC4R */
146 24U, /* 4: HRTIM_ADC5R */
147 32U, /* 5: HRTIM_ADC6R */
148 38U, /* 6: HRTIM_ADC7R */
149 44U, /* 7: HRTIM_ADC8R */
150 50U, /* 8: HRTIM_ADC9R */
151 56U /* 9: HRTIM_ADC10R */
152 };
153
154 static const uint16_t REG_OFFSET_TAB_SETxR[] =
155 {
156 0x00U, /* 0: TA1 */
157 0x08U, /* 1: TA2 */
158 0x80U, /* 2: TB1 */
159 0x88U, /* 3: TB2 */
160 0x100U, /* 4: TC1 */
161 0x108U, /* 5: TC2 */
162 0x180U, /* 6: TD1 */
163 0x188U, /* 7: TD2 */
164 0x200U, /* 8: TE1 */
165 0x208U, /* 9: TE2 */
166 0x280U, /* 10: TF1 */
167 0x288U /* 11: TF2 */
168 };
169
170 static const uint16_t REG_OFFSET_TAB_OUTxR[] =
171 {
172 0x00U, /* 0: TA1 */
173 0x00U, /* 1: TA2 */
174 0x80U, /* 2: TB1 */
175 0x80U, /* 3: TB2 */
176 0x100U, /* 4: TC1 */
177 0x100U, /* 5: TC2 */
178 0x180U, /* 6: TD1 */
179 0x180U, /* 7: TD2 */
180 0x200U, /* 8: TE1 */
181 0x200U, /* 9: TE2 */
182 0x280U, /* 10: TF1 */
183 0x280U /* 11: TF2 */
184 };
185
186 static const uint8_t REG_OFFSET_TAB_EECR[] =
187 {
188 0x00U, /* LL_HRTIM_EVENT_1 */
189 0x00U, /* LL_HRTIM_EVENT_2 */
190 0x00U, /* LL_HRTIM_EVENT_3 */
191 0x00U, /* LL_HRTIM_EVENT_4 */
192 0x00U, /* LL_HRTIM_EVENT_5 */
193 0x04U, /* LL_HRTIM_EVENT_6 */
194 0x04U, /* LL_HRTIM_EVENT_7 */
195 0x04U, /* LL_HRTIM_EVENT_8 */
196 0x04U, /* LL_HRTIM_EVENT_9 */
197 0x04U /* LL_HRTIM_EVENT_10 */
198 };
199
200 static const uint8_t REG_OFFSET_TAB_FLTINR[] =
201 {
202 0x00U, /* LL_HRTIM_FAULT_1 */
203 0x00U, /* LL_HRTIM_FAULT_2 */
204 0x00U, /* LL_HRTIM_FAULT_3 */
205 0x00U, /* LL_HRTIM_FAULT_4 */
206 0x04U, /* LL_HRTIM_FAULT_5 */
207 0x04U /* LL_HRTIM_FAULT_6 */
208 };
209
210 static const uint32_t REG_MASK_TAB_UPDATETRIG[] =
211 {
212 0x20000000U, /* 0: MASTER */
213 0x01FF0000U, /* 1: TIMER A */
214 0x01FF0000U, /* 2: TIMER B */
215 0x01FF0000U, /* 3: TIMER C */
216 0x01FF0000U, /* 4: TIMER D */
217 0x01FF0000U, /* 5: TIMER E */
218 0x01FF0000U, /* 5: TIMER E */
219 0x01FF0000U /* 6: TIMER F */
220 };
221
222 static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] =
223 {
224 12U, /* 0: MASTER */
225 0U, /* 1: TIMER A */
226 0U, /* 2: TIMER B */
227 0U, /* 3: TIMER C */
228 0U, /* 4: TIMER D */
229 0U, /* 5: TIMER E */
230 0U /* 6: TIMER F */
231 };
232
233 static const uint8_t REG_SHIFT_TAB_EExSRC[] =
234 {
235 0U, /* LL_HRTIM_EVENT_1 */
236 6U, /* LL_HRTIM_EVENT_2 */
237 12U, /* LL_HRTIM_EVENT_3 */
238 18U, /* LL_HRTIM_EVENT_4 */
239 24U, /* LL_HRTIM_EVENT_5 */
240 0U, /* LL_HRTIM_EVENT_6 */
241 6U, /* LL_HRTIM_EVENT_7 */
242 12U, /* LL_HRTIM_EVENT_8 */
243 18U, /* LL_HRTIM_EVENT_9 */
244 24U /* LL_HRTIM_EVENT_10 */
245 };
246
247 static const uint32_t REG_MASK_TAB_UPDATEGATING[] =
248 {
249 HRTIM_MCR_BRSTDMA, /* 0: MASTER */
250 HRTIM_TIMCR_UPDGAT, /* 1: TIMER A */
251 HRTIM_TIMCR_UPDGAT, /* 2: TIMER B */
252 HRTIM_TIMCR_UPDGAT, /* 3: TIMER C */
253 HRTIM_TIMCR_UPDGAT, /* 4: TIMER D */
254 HRTIM_TIMCR_UPDGAT, /* 5: TIMER E */
255 HRTIM_TIMCR_UPDGAT /* 6: TIMER F */
256 };
257
258 static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] =
259 {
260 2U, /* 0: MASTER */
261 0U, /* 1: TIMER A */
262 0U, /* 2: TIMER B */
263 0U, /* 3: TIMER C */
264 0U, /* 4: TIMER D */
265 0U, /* 5: TIMER E */
266 0U /* 6: TIMER F */
267 };
268
269 static const uint8_t REG_SHIFT_TAB_OUTxR[] =
270 {
271 0U, /* 0: TA1 */
272 16U, /* 1: TA2 */
273 0U, /* 2: TB1 */
274 16U, /* 3: TB2 */
275 0U, /* 4: TC1 */
276 16U, /* 5: TC2 */
277 0U, /* 6: TD1 */
278 16U, /* 7: TD2 */
279 0U, /* 8: TE1 */
280 16U, /* 9: TE2 */
281 0U, /* 10: TF1 */
282 16U /* 11: TF2 */
283 };
284
285 static const uint8_t REG_SHIFT_TAB_OxSTAT[] =
286 {
287 0U, /* 0: TA1 */
288 1U, /* 1: TA2 */
289 0U, /* 2: TB1 */
290 1U, /* 3: TB2 */
291 0U, /* 4: TC1 */
292 1U, /* 5: TC2 */
293 0U, /* 6: TD1 */
294 1U, /* 7: TD2 */
295 0U, /* 8: TE1 */
296 1U, /* 9: TE2 */
297 0U, /* 10: TF1 */
298 1U /* 11: TF2 */
299 };
300
301 static const uint8_t REG_SHIFT_TAB_FLTxE[] =
302 {
303 0U, /* LL_HRTIM_FAULT_1 */
304 8U, /* LL_HRTIM_FAULT_2 */
305 16U, /* LL_HRTIM_FAULT_3 */
306 24U, /* LL_HRTIM_FAULT_4 */
307 0U, /* LL_HRTIM_FAULT_5 */
308 8U /* LL_HRTIM_FAULT_6 */
309 };
310
311 static const uint8_t REG_SHIFT_TAB_FLTxF[] =
312 {
313 0U, /* LL_HRTIM_FAULT_1 */
314 8U, /* LL_HRTIM_FAULT_2 */
315 16U, /* LL_HRTIM_FAULT_3 */
316 24U, /* LL_HRTIM_FAULT_4 */
317 32U, /* LL_HRTIM_FAULT_5 */
318 40U /* LL_HRTIM_FAULT_6 */
319 };
320
321 static const uint8_t REG_SHIFT_TAB_FLTx[] =
322 {
323 0, /* LL_HRTIM_FAULT_1 */
324 1, /* LL_HRTIM_FAULT_2 */
325 2, /* LL_HRTIM_FAULT_3 */
326 3, /* LL_HRTIM_FAULT_4 */
327 4, /* LL_HRTIM_FAULT_5 */
328 5 /* LL_HRTIM_FAULT_6 */
329 };
330
331 static const uint8_t REG_SHIFT_TAB_INTLVD[] =
332 {
333 0U, /* 0: MASTER */
334 1U, /* 1: TIMER A */
335 1U, /* 2: TIMER B */
336 1U, /* 3: TIMER C */
337 1U, /* 4: TIMER D */
338 1U, /* 5: TIMER E */
339 1U, /* 6: TIMER F */
340 };
341
342 static const uint32_t REG_MASK_TAB_INTLVD[] =
343 {
344 0x000000E0U, /* 0: MASTER */
345 0x000001A0U, /* 1: TIMER A */
346 0x000001A0U, /* 2: TIMER B */
347 0x000001A0U, /* 3: TIMER C */
348 0x000001A0U, /* 4: TIMER D */
349 0x000001A0U, /* 5: TIMER E */
350 0x000001A0U, /* 6: TIMER F */
351 };
352
353 static const uint8_t REG_SHIFT_TAB_CPT[] =
354 {
355 12U, /* 1: TIMER A */
356 16U, /* 2: TIMER B */
357 20U, /* 3: TIMER C */
358 24U, /* 4: TIMER D */
359 28U, /* 5: TIMER E */
360 32U, /* 6: TIMER F */
361 };
362
363 static const uint32_t REG_MASK_TAB_CPT[] =
364 {
365 0xFFFF0000U, /* 1: TIMER A */
366 0xFFF0F000U, /* 2: TIMER B */
367 0xFF0FF000U, /* 3: TIMER C */
368 0xF0FFF000U, /* 4: TIMER D */
369 0x0FFFF000U, /* 5: TIMER E */
370 0xFFFFF000U, /* 6: TIMER F */
371 };
372
373 /**
374 * @}
375 */
376
377
378 /* Private constants ---------------------------------------------------------*/
379 /** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants
380 * @{
381 */
382 #define HRTIM_CR1_UDIS_MASK ((uint32_t)(HRTIM_CR1_MUDIS |\
383 HRTIM_CR1_TAUDIS |\
384 HRTIM_CR1_TBUDIS |\
385 HRTIM_CR1_TCUDIS |\
386 HRTIM_CR1_TDUDIS |\
387 HRTIM_CR1_TEUDIS |\
388 HRTIM_CR1_TFUDIS))
389
390 #define HRTIM_CR2_SWUPD_MASK ((uint32_t)(HRTIM_CR2_MSWU |\
391 HRTIM_CR2_TASWU |\
392 HRTIM_CR2_TBSWU |\
393 HRTIM_CR2_TCSWU |\
394 HRTIM_CR2_TDSWU |\
395 HRTIM_CR2_TESWU |\
396 HRTIM_CR2_TFSWU))
397
398 #define HRTIM_CR2_SWAP_MASK ((uint32_t)(HRTIM_CR2_SWPA |\
399 HRTIM_CR2_SWPB |\
400 HRTIM_CR2_SWPC |\
401 HRTIM_CR2_SWPD |\
402 HRTIM_CR2_SWPE |\
403 HRTIM_CR2_SWPF))
404
405 #define HRTIM_CR2_SWRST_MASK ((uint32_t)(HRTIM_CR2_MRST |\
406 HRTIM_CR2_TARST |\
407 HRTIM_CR2_TBRST |\
408 HRTIM_CR2_TCRST |\
409 HRTIM_CR2_TDRST |\
410 HRTIM_CR2_TERST |\
411 HRTIM_CR2_TFRST))
412
413 #define HRTIM_OENR_OEN_MASK ((uint32_t)(HRTIM_OENR_TA1OEN |\
414 HRTIM_OENR_TA2OEN |\
415 HRTIM_OENR_TB1OEN |\
416 HRTIM_OENR_TB2OEN |\
417 HRTIM_OENR_TC1OEN |\
418 HRTIM_OENR_TC2OEN |\
419 HRTIM_OENR_TD1OEN |\
420 HRTIM_OENR_TD2OEN |\
421 HRTIM_OENR_TE1OEN |\
422 HRTIM_OENR_TE2OEN |\
423 HRTIM_OENR_TF1OEN |\
424 HRTIM_OENR_TF2OEN))
425
426 #define HRTIM_OENR_ODIS_MASK ((uint32_t)(HRTIM_ODISR_TA1ODIS |\
427 HRTIM_ODISR_TA2ODIS |\
428 HRTIM_ODISR_TB1ODIS |\
429 HRTIM_ODISR_TB2ODIS |\
430 HRTIM_ODISR_TC1ODIS |\
431 HRTIM_ODISR_TC2ODIS |\
432 HRTIM_ODISR_TD1ODIS |\
433 HRTIM_ODISR_TD2ODIS |\
434 HRTIM_ODISR_TE1ODIS |\
435 HRTIM_ODISR_TE2ODIS |\
436 HRTIM_ODISR_TF1ODIS |\
437 HRTIM_ODISR_TF2ODIS))
438
439 #define HRTIM_OUT_CONFIG_MASK ((uint32_t)(HRTIM_OUTR_POL1 |\
440 HRTIM_OUTR_IDLM1 |\
441 HRTIM_OUTR_IDLES1 |\
442 HRTIM_OUTR_FAULT1 |\
443 HRTIM_OUTR_CHP1 |\
444 HRTIM_OUTR_DIDL1))
445
446 #define HRTIM_EE_CONFIG_MASK ((uint32_t)(HRTIM_EECR1_EE1SRC |\
447 HRTIM_EECR1_EE1POL |\
448 HRTIM_EECR1_EE1SNS |\
449 HRTIM_EECR1_EE1FAST))
450
451 #define HRTIM_FLT_CONFIG_MASK ((uint32_t)(HRTIM_FLTINR1_FLT1P |\
452 HRTIM_FLTINR1_FLT1SRC_0 ))
453
454 #define HRTIM_FLT_SRC_1_MASK ((uint32_t)(HRTIM_FLTINR2_FLT6SRC_1 |\
455 HRTIM_FLTINR2_FLT5SRC_1 |\
456 HRTIM_FLTINR2_FLT4SRC_1 |\
457 HRTIM_FLTINR2_FLT3SRC_1 |\
458 HRTIM_FLTINR2_FLT2SRC_1 |\
459 HRTIM_FLTINR2_FLT1SRC_1))
460
461 #define HRTIM_BM_CONFIG_MASK ((uint32_t)( HRTIM_BMCR_BMPRSC |\
462 HRTIM_BMCR_BMCLK |\
463 HRTIM_BMCR_BMOM))
464
465 /**
466 * @}
467 */
468
469
470 /* Private macros ------------------------------------------------------------*/
471 /* Exported types ------------------------------------------------------------*/
472 /* Exported constants --------------------------------------------------------*/
473 /** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
474 * @{
475 */
476
477 /** @defgroup HRTIM_LL_EC_GET_FLAG Get Flags Defines
478 * @brief Flags defines which can be used with LL_HRTIM_ReadReg function
479 * @{
480 */
481 #define LL_HRTIM_ISR_FLT1 HRTIM_ISR_FLT1
482 #define LL_HRTIM_ISR_FLT2 HRTIM_ISR_FLT2
483 #define LL_HRTIM_ISR_FLT3 HRTIM_ISR_FLT3
484 #define LL_HRTIM_ISR_FLT4 HRTIM_ISR_FLT4
485 #define LL_HRTIM_ISR_FLT5 HRTIM_ISR_FLT5
486 #define LL_HRTIM_ISR_FLT6 HRTIM_ISR_FLT6
487 #define LL_HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT
488 #define LL_HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY
489 #define LL_HRTIM_ISR_BMPER HRTIM_ISR_BMPER
490
491 #define LL_HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1
492 #define LL_HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2
493 #define LL_HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3
494 #define LL_HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4
495 #define LL_HRTIM_MISR_MREP HRTIM_MISR_MREP
496 #define LL_HRTIM_MISR_SYNC HRTIM_MISR_SYNC
497 #define LL_HRTIM_MISR_MUPD HRTIM_MISR_MUPD
498
499 #define LL_HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1
500 #define LL_HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2
501 #define LL_HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3
502 #define LL_HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4
503 #define LL_HRTIM_TIMISR_REP HRTIM_TIMISR_REP
504 #define LL_HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD
505 #define LL_HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1
506 #define LL_HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2
507 #define LL_HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1
508 #define LL_HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1
509 #define LL_HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2
510 #define LL_HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2
511 #define LL_HRTIM_TIMISR_RST HRTIM_TIMISR_RST
512 #define LL_HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT
513 /**
514 * @}
515 */
516
517 /** @defgroup HRTIM_LL_EC_IT IT Defines
518 * @brief IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions
519 * @{
520 */
521 #define LL_HRTIM_IER_FLT1IE HRTIM_IER_FLT1IE
522 #define LL_HRTIM_IER_FLT2IE HRTIM_IER_FLT2IE
523 #define LL_HRTIM_IER_FLT3IE HRTIM_IER_FLT3IE
524 #define LL_HRTIM_IER_FLT4IE HRTIM_IER_FLT4IE
525 #define LL_HRTIM_IER_FLT5IE HRTIM_IER_FLT5IE
526 #define LL_HRTIM_IER_FLT6IE HRTIM_IER_FLT6IE
527 #define LL_HRTIM_IER_SYSFLTIE HRTIM_IER_SYSFLTIE
528 #define LL_HRTIM_IER_DLLRDYIE HRTIM_IER_DLLRDYIE
529 #define LL_HRTIM_IER_BMPERIE HRTIM_IER_BMPERIE
530
531 #define LL_HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE
532 #define LL_HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE
533 #define LL_HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE
534 #define LL_HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE
535 #define LL_HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE
536 #define LL_HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE
537 #define LL_HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE
538
539 #define LL_HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE
540 #define LL_HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE
541 #define LL_HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE
542 #define LL_HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE
543 #define LL_HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE
544 #define LL_HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE
545 #define LL_HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE
546 #define LL_HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE
547 #define LL_HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE
548 #define LL_HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE
549 #define LL_HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE
550 #define LL_HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE
551 #define LL_HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE
552 #define LL_HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE
553 /**
554 * @}
555 */
556
557 /** @defgroup HRTIM_LL_EC_SYNCIN_SRC SYNCHRONIZATION INPUT SOURCE
558 * @{
559 * @brief Constants defining defining the synchronization input source.
560 */
561 #define LL_HRTIM_SYNCIN_SRC_NONE 0x00000000U /*!< HRTIM is not synchronized and runs in standalone mode */
562 #define LL_HRTIM_SYNCIN_SRC_TIM_EVENT (HRTIM_MCR_SYNC_IN_1) /*!< The HRTIM is synchronized with the on-chip timer */
563 #define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
564 /**
565 * @}
566 */
567
568 /** @defgroup HRTIM_LL_EC_SYNCOUT_SRC SYNCHRONIZATION OUTPUT SOURCE
569 * @{
570 * @brief Constants defining the source and event to be sent on the synchronization output.
571 */
572 #define LL_HRTIM_SYNCOUT_SRC_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */
573 #define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */
574 #define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */
575 #define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */
576 /**
577 * @}
578 */
579
580 /** @defgroup HRTIM_LL_EC_SYNCOUT_POLARITY SYNCHRONIZATION OUTPUT POLARITY
581 * @{
582 * @brief Constants defining the routing and conditioning of the synchronization output event.
583 */
584 #define LL_HRTIM_SYNCOUT_DISABLED 0x00000000U /*!< Synchronization output event is disabled */
585 #define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
586 #define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
587 /**
588 * @}
589 */
590
591 /** @defgroup HRTIM_LL_EC_TIMER TIMER ID
592 * @{
593 * @brief Constants identifying a timing unit.
594 */
595 #define LL_HRTIM_TIMER_NONE 0U /*!< Master timer identifier */
596 #define LL_HRTIM_TIMER_MASTER HRTIM_MCR_MCEN /*!< Master timer identifier */
597 #define LL_HRTIM_TIMER_A HRTIM_MCR_TACEN /*!< Timer A identifier */
598 #define LL_HRTIM_TIMER_B HRTIM_MCR_TBCEN /*!< Timer B identifier */
599 #define LL_HRTIM_TIMER_C HRTIM_MCR_TCCEN /*!< Timer C identifier */
600 #define LL_HRTIM_TIMER_D HRTIM_MCR_TDCEN /*!< Timer D identifier */
601 #define LL_HRTIM_TIMER_E HRTIM_MCR_TECEN /*!< Timer E identifier */
602 #define LL_HRTIM_TIMER_F HRTIM_MCR_TFCEN /*!< Timer F identifier */
603
604 #define LL_HRTIM_TIMER_X (HRTIM_MCR_TFCEN | HRTIM_MCR_TACEN |\
605 HRTIM_MCR_TBCEN | HRTIM_MCR_TCCEN |\
606 HRTIM_MCR_TDCEN | HRTIM_MCR_TECEN )
607 #define LL_HRTIM_TIMER_ALL (LL_HRTIM_TIMER_MASTER | LL_HRTIM_TIMER_X)
608
609 /**
610 * @}
611 */
612
613 /** @defgroup HRTIM_LL_EC_OUTPUT OUTPUT ID
614 * @{
615 * @brief Constants identifying an HRTIM output.
616 */
617 #define LL_HRTIM_OUTPUT_TA1 HRTIM_OENR_TA1OEN /*!< Timer A - Output 1 identifier */
618 #define LL_HRTIM_OUTPUT_TA2 HRTIM_OENR_TA2OEN /*!< Timer A - Output 2 identifier */
619 #define LL_HRTIM_OUTPUT_TB1 HRTIM_OENR_TB1OEN /*!< Timer B - Output 1 identifier */
620 #define LL_HRTIM_OUTPUT_TB2 HRTIM_OENR_TB2OEN /*!< Timer B - Output 2 identifier */
621 #define LL_HRTIM_OUTPUT_TC1 HRTIM_OENR_TC1OEN /*!< Timer C - Output 1 identifier */
622 #define LL_HRTIM_OUTPUT_TC2 HRTIM_OENR_TC2OEN /*!< Timer C - Output 2 identifier */
623 #define LL_HRTIM_OUTPUT_TD1 HRTIM_OENR_TD1OEN /*!< Timer D - Output 1 identifier */
624 #define LL_HRTIM_OUTPUT_TD2 HRTIM_OENR_TD2OEN /*!< Timer D - Output 2 identifier */
625 #define LL_HRTIM_OUTPUT_TE1 HRTIM_OENR_TE1OEN /*!< Timer E - Output 1 identifier */
626 #define LL_HRTIM_OUTPUT_TE2 HRTIM_OENR_TE2OEN /*!< Timer E - Output 2 identifier */
627 #define LL_HRTIM_OUTPUT_TF1 HRTIM_OENR_TF1OEN /*!< Timer F - Output 1 identifier */
628 #define LL_HRTIM_OUTPUT_TF2 HRTIM_OENR_TF2OEN /*!< Timer F - Output 2 identifier */
629 /**
630 * @}
631 */
632
633 /** @defgroup HRTIM_LL_EC_COMPAREUNIT COMPARE UNIT ID
634 * @{
635 * @brief Constants identifying a compare unit.
636 */
637 #define LL_HRTIM_COMPAREUNIT_2 HRTIM_TIMCR_DELCMP2 /*!< Compare unit 2 identifier */
638 #define LL_HRTIM_COMPAREUNIT_4 HRTIM_TIMCR_DELCMP4 /*!< Compare unit 4 identifier */
639 /**
640 * @}
641 */
642
643 /** @defgroup HRTIM_LL_EC_CAPTUREUNIT CAPTURE UNIT ID
644 * @{
645 * @brief Constants identifying a capture unit.
646 */
647 #define LL_HRTIM_CAPTUREUNIT_1 0 /*!< Capture unit 1 identifier */
648 #define LL_HRTIM_CAPTUREUNIT_2 1 /*!< Capture unit 2 identifier */
649 /**
650 * @}
651 */
652
653 /** @defgroup HRTIM_LL_EC_FAULT FAULT ID
654 * @{
655 * @brief Constants identifying a fault channel.
656 */
657 #define LL_HRTIM_FAULT_1 HRTIM_FLTR_FLT1EN /*!< Fault channel 1 identifier */
658 #define LL_HRTIM_FAULT_2 HRTIM_FLTR_FLT2EN /*!< Fault channel 2 identifier */
659 #define LL_HRTIM_FAULT_3 HRTIM_FLTR_FLT3EN /*!< Fault channel 3 identifier */
660 #define LL_HRTIM_FAULT_4 HRTIM_FLTR_FLT4EN /*!< Fault channel 4 identifier */
661 #define LL_HRTIM_FAULT_5 HRTIM_FLTR_FLT5EN /*!< Fault channel 5 identifier */
662 #define LL_HRTIM_FAULT_6 HRTIM_FLTR_FLT6EN /*!< Fault channel 6 identifier */
663 /**
664 * @}
665 */
666
667 /** @defgroup HRTIM_LL_EC_EVENT EXTERNAL EVENT ID
668 * @{
669 * @brief Constants identifying an external event channel.
670 */
671 #define LL_HRTIM_EVENT_1 ((uint32_t)0x00000001U) /*!< External event channel 1 identifier */
672 #define LL_HRTIM_EVENT_2 ((uint32_t)0x00000002U) /*!< External event channel 2 identifier */
673 #define LL_HRTIM_EVENT_3 ((uint32_t)0x00000004U) /*!< External event channel 3 identifier */
674 #define LL_HRTIM_EVENT_4 ((uint32_t)0x00000008U) /*!< External event channel 4 identifier */
675 #define LL_HRTIM_EVENT_5 ((uint32_t)0x00000010U) /*!< External event channel 5 identifier */
676 #define LL_HRTIM_EVENT_6 ((uint32_t)0x00000020U) /*!< External event channel 6 identifier */
677 #define LL_HRTIM_EVENT_7 ((uint32_t)0x00000040U) /*!< External event channel 7 identifier */
678 #define LL_HRTIM_EVENT_8 ((uint32_t)0x00000080U) /*!< External event channel 8 identifier */
679 #define LL_HRTIM_EVENT_9 ((uint32_t)0x00000100U) /*!< External event channel 9 identifier */
680 #define LL_HRTIM_EVENT_10 ((uint32_t)0x00000200U) /*!< External event channel 10 identifier */
681 /**
682 * @}
683 */
684
685 /** @defgroup HRTIM_LL_EC_OUTPUTSTATE OUTPUT STATE
686 * @{
687 * @brief Constants defining the state of an HRTIM output.
688 */
689 #define LL_HRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */
690 #define LL_HRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */
691 #define LL_HRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */
692 /**
693 * @}
694 */
695
696 /** @defgroup HRTIM_LL_EC_ADCTRIG ADC TRIGGER
697 * @{
698 * @brief Constants identifying an ADC trigger.
699 */
700 #define LL_HRTIM_ADCTRIG_1 ((uint32_t)0x00000000U) /*!< ADC trigger 1 identifier */
701 #define LL_HRTIM_ADCTRIG_2 ((uint32_t)0x00000001U) /*!< ADC trigger 2 identifier */
702 #define LL_HRTIM_ADCTRIG_3 ((uint32_t)0x00000002U) /*!< ADC trigger 3 identifier */
703 #define LL_HRTIM_ADCTRIG_4 ((uint32_t)0x00000003U) /*!< ADC trigger 4 identifier */
704 #define LL_HRTIM_ADCTRIG_5 ((uint32_t)0x00000004U) /*!< ADC trigger 5 identifier */
705 #define LL_HRTIM_ADCTRIG_6 ((uint32_t)0x00000005U) /*!< ADC trigger 6 identifier */
706 #define LL_HRTIM_ADCTRIG_7 ((uint32_t)0x00000006U) /*!< ADC trigger 7 identifier */
707 #define LL_HRTIM_ADCTRIG_8 ((uint32_t)0x00000007U) /*!< ADC trigger 8 identifier */
708 #define LL_HRTIM_ADCTRIG_9 ((uint32_t)0x00000008U) /*!< ADC trigger 9 identifier */
709 #define LL_HRTIM_ADCTRIG_10 ((uint32_t)0x00000009U) /*!< ADC trigger 10 identifier */
710 /**
711 * @}
712 */
713
714 /** @defgroup HRTIM_LL_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE
715 * @{
716 * @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).
717 */
718 #define LL_HRTIM_ADCTRIG_UPDATE_MASTER 0x00000000U /*!< HRTIM_ADCxR register update is triggered by the Master timer */
719 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A 0x00000001U /*!< HRTIM_ADCxR register update is triggered by the Timer A */
720 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B 0x00000002U /*!< HRTIM_ADCxR register update is triggered by the Timer B */
721 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C 0x00000003U /*!< HRTIM_ADCxR register update is triggered by the Timer C */
722 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D 0x00000004U /*!< HRTIM_ADCxR register update is triggered by the Timer D */
723 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E 0x00000005U /*!< HRTIM_ADCxR register update is triggered by the Timer E */
724 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_F 0x00000006U /*!< HRTIM_ADCxR register update is triggered by the Timer F */
725 /**
726 * @}
727 */
728
729 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC13 ADC TRIGGER 1/3 SOURCE
730 * @{
731 * @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3.
732 */
733 #define LL_HRTIM_ADCTRIG_SRC13_NONE 0x00000000U /*!< No ADC trigger event */
734 #define LL_HRTIM_ADCTRIG_SRC13_MCMP1 HRTIM_ADC1R_AD1MC1 /*!< ADC Trigger on master compare 1 */
735 #define LL_HRTIM_ADCTRIG_SRC13_MCMP2 HRTIM_ADC1R_AD1MC2 /*!< ADC Trigger on master compare 2 */
736 #define LL_HRTIM_ADCTRIG_SRC13_MCMP3 HRTIM_ADC1R_AD1MC3 /*!< ADC Trigger on master compare 3 */
737 #define LL_HRTIM_ADCTRIG_SRC13_MCMP4 HRTIM_ADC1R_AD1MC4 /*!< ADC Trigger on master compare 4 */
738 #define LL_HRTIM_ADCTRIG_SRC13_MPER HRTIM_ADC1R_AD1MPER /*!< ADC Trigger on master period */
739 #define LL_HRTIM_ADCTRIG_SRC13_EEV1 HRTIM_ADC1R_AD1EEV1 /*!< ADC Trigger on external event 1 */
740 #define LL_HRTIM_ADCTRIG_SRC13_EEV2 HRTIM_ADC1R_AD1EEV2 /*!< ADC Trigger on external event 2 */
741 #define LL_HRTIM_ADCTRIG_SRC13_EEV3 HRTIM_ADC1R_AD1EEV3 /*!< ADC Trigger on external event 3 */
742 #define LL_HRTIM_ADCTRIG_SRC13_EEV4 HRTIM_ADC1R_AD1EEV4 /*!< ADC Trigger on external event 4 */
743 #define LL_HRTIM_ADCTRIG_SRC13_EEV5 HRTIM_ADC1R_AD1EEV5 /*!< ADC Trigger on external event 5 */
744 #define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2 HRTIM_ADC1R_AD1TFC2 /*!< ADC Trigger on Timer F compare 2 */
745 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 HRTIM_ADC1R_AD1TAC3 /*!< ADC Trigger on Timer A compare 3 */
746 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 HRTIM_ADC1R_AD1TAC4 /*!< ADC Trigger on Timer A compare 4 */
747 #define LL_HRTIM_ADCTRIG_SRC13_TIMAPER HRTIM_ADC1R_AD1TAPER /*!< ADC Trigger on Timer A period */
748 #define LL_HRTIM_ADCTRIG_SRC13_TIMARST HRTIM_ADC1R_AD1TARST /*!< ADC Trigger on Timer A reset */
749 #define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3 HRTIM_ADC1R_AD1TFC3 /*!< ADC Trigger on Timer F compare 3 */
750 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 HRTIM_ADC1R_AD1TBC3 /*!< ADC Trigger on Timer B compare 3 */
751 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 HRTIM_ADC1R_AD1TBC4 /*!< ADC Trigger on Timer B compare 4 */
752 #define LL_HRTIM_ADCTRIG_SRC13_TIMBPER HRTIM_ADC1R_AD1TBPER /*!< ADC Trigger on Timer B period */
753 #define LL_HRTIM_ADCTRIG_SRC13_TIMBRST HRTIM_ADC1R_AD1TBRST /*!< ADC Trigger on Timer B reset */
754 #define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4 HRTIM_ADC1R_AD1TFC4 /*!< ADC Trigger on Timer F compare 4 */
755 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 HRTIM_ADC1R_AD1TCC3 /*!< ADC Trigger on Timer C compare 3 */
756 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 HRTIM_ADC1R_AD1TCC4 /*!< ADC Trigger on Timer C compare 4 */
757 #define LL_HRTIM_ADCTRIG_SRC13_TIMCPER HRTIM_ADC1R_AD1TCPER /*!< ADC Trigger on Timer C period */
758 #define LL_HRTIM_ADCTRIG_SRC13_TIMFPER HRTIM_ADC1R_AD1TFPER /*!< ADC Trigger on Timer F period */
759 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 HRTIM_ADC1R_AD1TDC3 /*!< ADC Trigger on Timer D compare 3 */
760 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 HRTIM_ADC1R_AD1TDC4 /*!< ADC Trigger on Timer D compare 4 */
761 #define LL_HRTIM_ADCTRIG_SRC13_TIMDPER HRTIM_ADC1R_AD1TDPER /*!< ADC Trigger on Timer D period */
762 #define LL_HRTIM_ADCTRIG_SRC13_TIMFRST HRTIM_ADC1R_AD1TFRST /*!< ADC Trigger on Timer F reset */
763 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 HRTIM_ADC1R_AD1TEC3 /*!< ADC Trigger on Timer E compare 3 */
764 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 HRTIM_ADC1R_AD1TEC4 /*!< ADC Trigger on Timer E compare 4 */
765 #define LL_HRTIM_ADCTRIG_SRC13_TIMEPER HRTIM_ADC1R_AD1TEPER /*!< ADC Trigger on Timer E period */
766 /**
767 * @}
768 */
769
770 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC24 ADC TRIGGER 2/4 SOURCE
771 * @{
772 * @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4.
773 */
774 #define LL_HRTIM_ADCTRIG_SRC24_NONE 0x00000000U /*!< No ADC trigger event */
775 #define LL_HRTIM_ADCTRIG_SRC24_MCMP1 HRTIM_ADC2R_AD2MC1 /*!< ADC Trigger on master compare 1 */
776 #define LL_HRTIM_ADCTRIG_SRC24_MCMP2 HRTIM_ADC2R_AD2MC2 /*!< ADC Trigger on master compare 2 */
777 #define LL_HRTIM_ADCTRIG_SRC24_MCMP3 HRTIM_ADC2R_AD2MC3 /*!< ADC Trigger on master compare 3 */
778 #define LL_HRTIM_ADCTRIG_SRC24_MCMP4 HRTIM_ADC2R_AD2MC4 /*!< ADC Trigger on master compare 4 */
779 #define LL_HRTIM_ADCTRIG_SRC24_MPER HRTIM_ADC2R_AD2MPER /*!< ADC Trigger on master period */
780 #define LL_HRTIM_ADCTRIG_SRC24_EEV6 HRTIM_ADC2R_AD2EEV6 /*!< ADC Trigger on external event 6 */
781 #define LL_HRTIM_ADCTRIG_SRC24_EEV7 HRTIM_ADC2R_AD2EEV7 /*!< ADC Trigger on external event 7 */
782 #define LL_HRTIM_ADCTRIG_SRC24_EEV8 HRTIM_ADC2R_AD2EEV8 /*!< ADC Trigger on external event 8 */
783 #define LL_HRTIM_ADCTRIG_SRC24_EEV9 HRTIM_ADC2R_AD2EEV9 /*!< ADC Trigger on external event 9 */
784 #define LL_HRTIM_ADCTRIG_SRC24_EEV10 HRTIM_ADC2R_AD2EEV10 /*!< ADC Trigger on external event 10 */
785 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 HRTIM_ADC2R_AD2TAC2 /*!< ADC Trigger on Timer A compare 2 */
786 #define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2 HRTIM_ADC2R_AD2TFC2 /*!< ADC Trigger on Timer F compare 2 */
787 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 HRTIM_ADC2R_AD2TAC4 /*!< ADC Trigger on Timer A compare 4 */
788 #define LL_HRTIM_ADCTRIG_SRC24_TIMAPER HRTIM_ADC2R_AD2TAPER /*!< ADC Trigger on Timer A period */
789 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 HRTIM_ADC2R_AD2TBC2 /*!< ADC Trigger on Timer B compare 2 */
790 #define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3 HRTIM_ADC2R_AD2TFC3 /*!< ADC Trigger on Timer F compare 3 */
791 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 HRTIM_ADC2R_AD2TBC4 /*!< ADC Trigger on Timer B compare 4 */
792 #define LL_HRTIM_ADCTRIG_SRC24_TIMBPER HRTIM_ADC2R_AD2TBPER /*!< ADC Trigger on Timer B period */
793 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 HRTIM_ADC2R_AD2TCC2 /*!< ADC Trigger on Timer C compare 2 */
794 #define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4 HRTIM_ADC2R_AD2TFC4 /*!< ADC Trigger on Timer F compare 4 */
795 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 HRTIM_ADC2R_AD2TCC4 /*!< ADC Trigger on Timer C compare 4 */
796 #define LL_HRTIM_ADCTRIG_SRC24_TIMCPER HRTIM_ADC2R_AD2TCPER /*!< ADC Trigger on Timer C period */
797 #define LL_HRTIM_ADCTRIG_SRC24_TIMCRST HRTIM_ADC2R_AD2TCRST /*!< ADC Trigger on Timer C reset */
798 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 HRTIM_ADC2R_AD2TDC2 /*!< ADC Trigger on Timer D compare 2 */
799 #define LL_HRTIM_ADCTRIG_SRC24_TIMFPER HRTIM_ADC2R_AD2TFPER /*!< ADC Trigger on Timer F period */
800 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 HRTIM_ADC2R_AD2TDC4 /*!< ADC Trigger on Timer D compare 4 */
801 #define LL_HRTIM_ADCTRIG_SRC24_TIMDPER HRTIM_ADC2R_AD2TDPER /*!< ADC Trigger on Timer D period */
802 #define LL_HRTIM_ADCTRIG_SRC24_TIMDRST HRTIM_ADC2R_AD2TDRST /*!< ADC Trigger on Timer D reset */
803 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 HRTIM_ADC2R_AD2TEC2 /*!< ADC Trigger on Timer E compare 2 */
804 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 HRTIM_ADC2R_AD2TEC3 /*!< ADC Trigger on Timer E compare 3 */
805 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 HRTIM_ADC2R_AD2TEC4 /*!< ADC Trigger on Timer E compare 4 */
806 #define LL_HRTIM_ADCTRIG_SRC24_TIMERST HRTIM_ADC2R_AD2TERST /*!< ADC Trigger on Timer E reset */
807 /**
808 * @}
809 */
810
811 /** @defgroup HRTIM_ADC_TRIG HRTIM ADC TRIGGER SELECTION
812 * @{
813 * @brief Constants defining the selection that can be used as ADC trigger source for extended ADC 6, 8 ,10.
814 */
815 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP1 (uint32_t)0x00 /*!< ADC extended Trigger on Master Compare 1 */
816 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP2 (uint32_t)0x01 /*!< ADC extended Trigger on Master Compare 2 */
817 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP3 (uint32_t)0x02 /*!< ADC extended Trigger on Master Compare 3 */
818 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP4 (uint32_t)0x03 /*!< ADC extended Trigger on Master Compare 4 */
819 #define LL_HRTIM_ADCTRIG_SRC6810_MPER (uint32_t)0x04 /*!< ADC extended Trigger on Master Period */
820 #define LL_HRTIM_ADCTRIG_SRC6810_EEV6 (uint32_t)0x05 /*!< ADC extended Trigger on External Event 6 */
821 #define LL_HRTIM_ADCTRIG_SRC6810_EEV7 (uint32_t)0x06 /*!< ADC extended Trigger on External Event 7 */
822 #define LL_HRTIM_ADCTRIG_SRC6810_EEV8 (uint32_t)0x07 /*!< ADC extended Trigger on External Event 8 */
823 #define LL_HRTIM_ADCTRIG_SRC6810_EEV9 (uint32_t)0x08 /*!< ADC extended Trigger on External Event 9 */
824 #define LL_HRTIM_ADCTRIG_SRC6810_EEV10 (uint32_t)0x09 /*!< ADC extended Trigger on External Event 10 */
825 #define LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2 (uint32_t)0x0A /*!< ADC extended Trigger on Timer A Compare 2 */
826 #define LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4 (uint32_t)0x0B /*!< ADC extended Trigger on Timer A Compare 4 */
827 #define LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER (uint32_t)0x0C /*!< ADC extended Trigger on Timer A Period */
828 #define LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2 (uint32_t)0x0D /*!< ADC extended Trigger on Timer B Compare 2 */
829 #define LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4 (uint32_t)0x0E /*!< ADC extended Trigger on Timer B Compare 4 */
830 #define LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER (uint32_t)0x0F /*!< ADC extended Trigger on Timer B Period */
831 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2 (uint32_t)0x10 /*!< ADC extended Trigger on Timer C Compare 2 */
832 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4 (uint32_t)0x11 /*!< ADC extended Trigger on Timer C Compare 4 */
833 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER (uint32_t)0x12 /*!< ADC extended Trigger on Timer C Period */
834 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST (uint32_t)0x13 /*!< ADC extended Trigger on Timer C Reset and counter roll-over */
835 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2 (uint32_t)0x14 /*!< ADC extended Trigger on Timer D Compare 2 */
836 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4 (uint32_t)0x15 /*!< ADC extended Trigger on Timer D Compare 4 */
837 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER (uint32_t)0x16 /*!< ADC extended Trigger on Timer D Period */
838 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST (uint32_t)0x17 /*!< ADC extended Trigger on Timer D Reset and counter roll-over */
839 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2 (uint32_t)0x18 /*!< ADC extended Trigger on Timer E Compare 2 */
840 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3 (uint32_t)0x19 /*!< ADC extended Trigger on Timer E Compare 3 */
841 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4 (uint32_t)0x1A /*!< ADC extended Trigger on Timer E Compare 4 */
842 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_RST (uint32_t)0x1B /*!< ADC extended Trigger on Timer E Reset and counter roll-over */
843 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2 (uint32_t)0x1C /*!< ADC extended Trigger on Timer F Compare 2 */
844 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3 (uint32_t)0x1D /*!< ADC extended Trigger on Timer F Compare 3 */
845 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4 (uint32_t)0x1E /*!< ADC extended Trigger on Timer F Compare 4 */
846 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER (uint32_t)0x1F /*!< ADC extended Trigger on Timer F Period */
847 /**
848 * @}
849 */
850
851 /** @defgroup HRTIM_ADC_TRIG HRTIM ADC TRIGGER SELECTION
852 * @{
853 * @brief Constants defining the selection that can be used as ADC trigger source for extended ADC 5, 7 ,9.
854 */
855 #define LL_HRTIM_ADCTRIG_SRC579_MCMP1 (uint32_t)0x00 /*!< ADC extended Trigger on Master Compare 1 */
856 #define LL_HRTIM_ADCTRIG_SRC579_MCMP2 (uint32_t)0x01 /*!< ADC extended Trigger on Master Compare 2 */
857 #define LL_HRTIM_ADCTRIG_SRC579_MCMP3 (uint32_t)0x02 /*!< ADC extended Trigger on Master Compare 3 */
858 #define LL_HRTIM_ADCTRIG_SRC579_MCMP4 (uint32_t)0x03 /*!< ADC extended Trigger on Master Compare 4 */
859 #define LL_HRTIM_ADCTRIG_SRC579_MPER (uint32_t)0x04 /*!< ADC extended Trigger on Master Period */
860 #define LL_HRTIM_ADCTRIG_SRC579_EEV1 (uint32_t)0x05 /*!< ADC extended Trigger on External Event 1 */
861 #define LL_HRTIM_ADCTRIG_SRC579_EEV2 (uint32_t)0x06 /*!< ADC extended Trigger on External Event 2 */
862 #define LL_HRTIM_ADCTRIG_SRC579_EEV3 (uint32_t)0x07 /*!< ADC extended Trigger on External Event 3 */
863 #define LL_HRTIM_ADCTRIG_SRC579_EEV4 (uint32_t)0x08 /*!< ADC extended Trigger on External Event 4 */
864 #define LL_HRTIM_ADCTRIG_SRC579_EEV5 (uint32_t)0x09 /*!< ADC extended Trigger on External Event 5 */
865 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3 (uint32_t)0x0A /*!< ADC extended Trigger on Timer A Compare 3 */
866 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4 (uint32_t)0x0B /*!< ADC extended Trigger on Timer A Compare 4 */
867 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_PER (uint32_t)0x0C /*!< ADC extended Trigger on Timer A Period */
868 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_RST (uint32_t)0x0D /*!< ADC extended Trigger on Timer A Period */
869 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3 (uint32_t)0x0E /*!< ADC extended Trigger on Timer B Compare 3 */
870 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4 (uint32_t)0x0F /*!< ADC extended Trigger on Timer B Compare 4 */
871 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_PER (uint32_t)0x10 /*!< ADC extended Trigger on Timer B Period */
872 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_RST (uint32_t)0x11 /*!< ADC extended Trigger on Timer B Reset and counter roll-over */
873 #define LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3 (uint32_t)0x12 /*!< ADC extended Trigger on Timer C Compare 3 */
874 #define LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4 (uint32_t)0x13 /*!< ADC extended Trigger on Timer C Compare 4 */
875 #define LL_HRTIM_ADCTRIG_SRC579_TIMC_PER (uint32_t)0x14 /*!< ADC extended Trigger on Timer C Period */
876 #define LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3 (uint32_t)0x15 /*!< ADC extended Trigger on Timer D Compare 3 */
877 #define LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4 (uint32_t)0x16 /*!< ADC extended Trigger on Timer D Compare 4 */
878 #define LL_HRTIM_ADCTRIG_SRC579_TIMD_PER (uint32_t)0x17 /*!< ADC extended Trigger on Timer D Period */
879 #define LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3 (uint32_t)0x18 /*!< ADC extended Trigger on Timer E Compare 3 */
880 #define LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4 (uint32_t)0x19 /*!< ADC extended Trigger on Timer E Compare 4 */
881 #define LL_HRTIM_ADCTRIG_SRC579_TIME_PER (uint32_t)0x1A /*!< ADC extended Trigger on Timer E Period */
882 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2 (uint32_t)0x1B /*!< ADC extended Trigger on Timer F Compare 2 */
883 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3 (uint32_t)0x1C /*!< ADC extended Trigger on Timer F Compare 3 */
884 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4 (uint32_t)0x1D /*!< ADC extended Trigger on Timer F Compare 4 */
885 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_PER (uint32_t)0x1E /*!< ADC extended Trigger on Timer F Period */
886 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_RST (uint32_t)0x1F /*!< ADC extended Trigger on Timer F Reset and counter roll-over */
887 /**
888 * @}
889 */
890
891 /** @defgroup HRTIM_LL_EC_DLLCALIBRATION_MODE DLL CALIBRATION MODE
892 * @{
893 * @brief Constants defining the DLL calibration mode.
894 */
895 #define LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT 0x00000000U /*!<Calibration is performed only once */
896 #define LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS HRTIM_DLLCR_CALEN /*!<Calibration is performed periodically */
897 /**
898 * @}
899 */
900
901 /** @defgroup HRTIM_LL_EC_CALIBRATIONRATE DLL CALIBRATION RATE
902 * @{
903 * @brief Constants defining the DLL calibration periods (in micro seconds).
904 */
905 #define LL_HRTIM_DLLCALIBRATION_RATE_0 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (6.168 ms) */
906 #define LL_HRTIM_DLLCALIBRATION_RATE_1 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.771 ms) */
907 #define LL_HRTIM_DLLCALIBRATION_RATE_2 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.096 ms) */
908 #define LL_HRTIM_DLLCALIBRATION_RATE_3 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048U * tHRTIM (0.012 ms) */
909 /**
910 * @}
911 */
912
913 /** @defgroup HRTIM_LL_EC_PRESCALERRATIO PRESCALER RATIO
914 * @{
915 * @brief Constants defining timer high-resolution clock prescaler ratio.
916 */
917 #define LL_HRTIM_PRESCALERRATIO_MUL32 0x00000000U /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
918 #define LL_HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001U) /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
919 #define LL_HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002U) /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
920 #define LL_HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003U) /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
921 #define LL_HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004U) /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
922 #define LL_HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
923 #define LL_HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U) /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
924 #define LL_HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U) /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
925 /**
926 * @}
927 */
928
929 /** @defgroup HRTIM_LL_EC_MODE COUNTER MODE
930 * @{
931 * @brief Constants defining timer counter operating mode.
932 */
933 #define LL_HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008U) /*!< The timer operates in continuous (free-running) mode */
934 #define LL_HRTIM_MODE_SINGLESHOT 0x00000000U /*!< The timer operates in non retriggerable single-shot mode */
935 #define LL_HRTIM_MODE_RETRIGGERABLE ((uint32_t)0x00000010U) /*!< The timer operates in retriggerable single-shot mode */
936 /**
937 * @}
938 */
939
940 /** @defgroup HRTIM_LL_EC_DACTRIG DAC TRIGGER
941 * @{
942 * @brief Constants defining on which output the DAC synchronization event is sent.
943 */
944 #define LL_HRTIM_DACTRIG_NONE 0x00000000U /*!< No DAC synchronization event generated */
945 #define LL_HRTIM_DACTRIG_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
946 #define LL_HRTIM_DACTRIG_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
947 #define LL_HRTIM_DACTRIG_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut3 output upon timer update */
948 /**
949 * @}
950 */
951
952 /** @defgroup HRTIM_LL_EC_UPDATETRIG UPDATE TRIGGER
953 * @{
954 * @brief Constants defining whether the registers update is done synchronously with any other timer or master update.
955 */
956 #define LL_HRTIM_UPDATETRIG_NONE 0x00000000U /*!< Register update is disabled */
957 #define LL_HRTIM_UPDATETRIG_MASTER HRTIM_TIMCR_MSTU /*!< Register update is triggered by the master timer update */
958 #define LL_HRTIM_UPDATETRIG_TIMER_A HRTIM_TIMCR_TAU /*!< Register update is triggered by the timer A update */
959 #define LL_HRTIM_UPDATETRIG_TIMER_B HRTIM_TIMCR_TBU /*!< Register update is triggered by the timer B update */
960 #define LL_HRTIM_UPDATETRIG_TIMER_C HRTIM_TIMCR_TCU /*!< Register update is triggered by the timer C update*/
961 #define LL_HRTIM_UPDATETRIG_TIMER_D HRTIM_TIMCR_TDU /*!< Register update is triggered by the timer D update */
962 #define LL_HRTIM_UPDATETRIG_TIMER_E HRTIM_TIMCR_TEU /*!< Register update is triggered by the timer E update */
963 #define LL_HRTIM_UPDATETRIG_TIMER_F HRTIM_TIMCR_TFU /*!< Register update is triggered by the timer F update */
964 #define LL_HRTIM_UPDATETRIG_REPETITION HRTIM_TIMCR_TREPU /*!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0*/
965 #define LL_HRTIM_UPDATETRIG_RESET HRTIM_TIMCR_TRSTU /*!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */
966 /**
967 * @}
968 */
969
970 /** @defgroup HRTIM_LL_EC_UPDATEGATING UPDATE GATING
971 * @{
972 * @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.
973 */
974 #define LL_HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */
975 #define LL_HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
976 #define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
977 #define LL_HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
978 #define LL_HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
979 #define LL_HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
980 #define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */
981 #define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
982 #define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
983 /**
984 * @}
985 */
986
987 /** @defgroup HRTIM_LL_EC_COMPAREMODE COMPARE MODE
988 * @{
989 * @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode.
990 */
991 #define LL_HRTIM_COMPAREMODE_REGULAR 0x00000000U /*!< standard compare mode */
992 #define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */
993 #define LL_HRTIM_COMPAREMODE_DELAY_CMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
994 #define LL_HRTIM_COMPAREMODE_DELAY_CMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
995 /**
996 * @}
997 */
998
999 /** @defgroup HRTIM_LL_EC_RESETTRIG RESET TRIGGER
1000 * @{
1001 * @brief Constants defining the events that can be selected to trigger the reset of the timer counter.
1002 */
1003 #define LL_HRTIM_RESETTRIG_NONE 0x00000000U /*!< No counter reset trigger */
1004 #define LL_HRTIM_RESETTRIG_UPDATE HRTIM_RSTR_UPDATE /*!< The timer counter is reset upon update event */
1005 #define LL_HRTIM_RESETTRIG_CMP2 HRTIM_RSTR_CMP2 /*!< The timer counter is reset upon Timer Compare 2 event */
1006 #define LL_HRTIM_RESETTRIG_CMP4 HRTIM_RSTR_CMP4 /*!< The timer counter is reset upon Timer Compare 4 event */
1007 #define LL_HRTIM_RESETTRIG_MASTER_PER HRTIM_RSTR_MSTPER /*!< The timer counter is reset upon master timer period event */
1008 #define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1 /*!< The timer counter is reset upon master timer Compare 1 event */
1009 #define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2 /*!< The timer counter is reset upon master timer Compare 2 event */
1010 #define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3 /*!< The timer counter is reset upon master timer Compare 3 event */
1011 #define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4 /*!< The timer counter is reset upon master timer Compare 4 event */
1012 #define LL_HRTIM_RESETTRIG_EEV_1 HRTIM_RSTR_EXTEVNT1 /*!< The timer counter is reset upon external event 1 */
1013 #define LL_HRTIM_RESETTRIG_EEV_2 HRTIM_RSTR_EXTEVNT2 /*!< The timer counter is reset upon external event 2 */
1014 #define LL_HRTIM_RESETTRIG_EEV_3 HRTIM_RSTR_EXTEVNT3 /*!< The timer counter is reset upon external event 3 */
1015 #define LL_HRTIM_RESETTRIG_EEV_4 HRTIM_RSTR_EXTEVNT4 /*!< The timer counter is reset upon external event 4 */
1016 #define LL_HRTIM_RESETTRIG_EEV_5 HRTIM_RSTR_EXTEVNT5 /*!< The timer counter is reset upon external event 5 */
1017 #define LL_HRTIM_RESETTRIG_EEV_6 HRTIM_RSTR_EXTEVNT6 /*!< The timer counter is reset upon external event 6 */
1018 #define LL_HRTIM_RESETTRIG_EEV_7 HRTIM_RSTR_EXTEVNT7 /*!< The timer counter is reset upon external event 7 */
1019 #define LL_HRTIM_RESETTRIG_EEV_8 HRTIM_RSTR_EXTEVNT8 /*!< The timer counter is reset upon external event 8 */
1020 #define LL_HRTIM_RESETTRIG_EEV_9 HRTIM_RSTR_EXTEVNT9 /*!< The timer counter is reset upon external event 9 */
1021 #define LL_HRTIM_RESETTRIG_EEV_10 HRTIM_RSTR_EXTEVNT10 /*!< The timer counter is reset upon external event 10 */
1022 #define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1023 #define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1024 #define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
1025 #define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1026 #define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1027 #define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
1028 #define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1029 #define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1030 #define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
1031 #define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1032 #define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1033 #define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
1034 #define LL_HRTIM_RESETTRIG_OTHER5_CMP1 HRTIM_RSTR_TIMFCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1035 #define LL_HRTIM_RESETTRIG_OTHER5_CMP2 HRTIM_RSTR_TIMFCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1036 /**
1037 * @}
1038 */
1039
1040 /** @defgroup HRTIM_LL_EC_CAPTURETRIG CAPTURE TRIGGER
1041 * @{
1042 * @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter.
1043 */
1044 #define LL_HRTIM_CAPTURETRIG_NONE (uint64_t)0 /*!< Capture trigger is disabled */
1045 #define LL_HRTIM_CAPTURETRIG_SW (uint64_t)HRTIM_CPT1CR_SWCPT /*!< The sw event triggers the Capture */
1046 #define LL_HRTIM_CAPTURETRIG_UPDATE (uint64_t)HRTIM_CPT1CR_UPDCPT /*!< The update event triggers the Capture */
1047 #define LL_HRTIM_CAPTURETRIG_EEV_1 (uint64_t)HRTIM_CPT1CR_EXEV1CPT /*!< The External event 1 triggers the Capture */
1048 #define LL_HRTIM_CAPTURETRIG_EEV_2 (uint64_t)HRTIM_CPT1CR_EXEV2CPT /*!< The External event 2 triggers the Capture */
1049 #define LL_HRTIM_CAPTURETRIG_EEV_3 (uint64_t)HRTIM_CPT1CR_EXEV3CPT /*!< The External event 3 triggers the Capture */
1050 #define LL_HRTIM_CAPTURETRIG_EEV_4 (uint64_t)HRTIM_CPT1CR_EXEV4CPT /*!< The External event 4 triggers the Capture */
1051 #define LL_HRTIM_CAPTURETRIG_EEV_5 (uint64_t)HRTIM_CPT1CR_EXEV5CPT /*!< The External event 5 triggers the Capture */
1052 #define LL_HRTIM_CAPTURETRIG_EEV_6 (uint64_t)HRTIM_CPT1CR_EXEV6CPT /*!< The External event 6 triggers the Capture */
1053 #define LL_HRTIM_CAPTURETRIG_EEV_7 (uint64_t)HRTIM_CPT1CR_EXEV7CPT /*!< The External event 7 triggers the Capture */
1054 #define LL_HRTIM_CAPTURETRIG_EEV_8 (uint64_t)HRTIM_CPT1CR_EXEV8CPT /*!< The External event 8 triggers the Capture */
1055 #define LL_HRTIM_CAPTURETRIG_EEV_9 (uint64_t)HRTIM_CPT1CR_EXEV9CPT /*!< The External event 9 triggers the Capture */
1056 #define LL_HRTIM_CAPTURETRIG_EEV_10 (uint64_t)HRTIM_CPT1CR_EXEV10CPT /*!< The External event 10 triggers the Capture */
1057 #define LL_HRTIM_CAPTURETRIG_TA1_SET (uint64_t)(HRTIM_CPT1CR_TA1SET ) <<32 /*!< Capture is triggered by TA1 output inactive to active transition */
1058 #define LL_HRTIM_CAPTURETRIG_TA1_RESET (uint64_t)(HRTIM_CPT1CR_TA1RST ) <<32 /*!< Capture is triggered by TA1 output active to inactive transition */
1059 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMACMP1 ) <<32 /*!< Timer A Compare 1 triggers Capture */
1060 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMACMP2 ) <<32 /*!< Timer A Compare 2 triggers Capture */
1061 #define LL_HRTIM_CAPTURETRIG_TB1_SET (uint64_t)(HRTIM_CPT1CR_TB1SET ) <<32 /*!< Capture is triggered by TB1 output inactive to active transition */
1062 #define LL_HRTIM_CAPTURETRIG_TB1_RESET (uint64_t)(HRTIM_CPT1CR_TB1RST ) <<32 /*!< Capture is triggered by TB1 output active to inactive transition */
1063 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMBCMP1 ) <<32 /*!< Timer B Compare 1 triggers Capture */
1064 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMBCMP2 ) <<32 /*!< Timer B Compare 2 triggers Capture */
1065 #define LL_HRTIM_CAPTURETRIG_TC1_SET (uint64_t)(HRTIM_CPT1CR_TC1SET ) <<32 /*!< Capture is triggered by TC1 output inactive to active transition */
1066 #define LL_HRTIM_CAPTURETRIG_TC1_RESET (uint64_t)(HRTIM_CPT1CR_TC1RST ) <<32 /*!< Capture is triggered by TC1 output active to inactive transition */
1067 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMCCMP1 ) <<32 /*!< Timer C Compare 1 triggers Capture */
1068 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMCCMP2 ) <<32 /*!< Timer C Compare 2 triggers Capture */
1069 #define LL_HRTIM_CAPTURETRIG_TD1_SET (uint64_t)(HRTIM_CPT1CR_TD1SET ) <<32 /*!< Capture is triggered by TD1 output inactive to active transition */
1070 #define LL_HRTIM_CAPTURETRIG_TD1_RESET (uint64_t)(HRTIM_CPT1CR_TD1RST ) <<32 /*!< Capture is triggered by TD1 output active to inactive transition */
1071 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMDCMP1 ) <<32 /*!< Timer D Compare 1 triggers Capture */
1072 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMDCMP2 ) <<32 /*!< Timer D Compare 2 triggers Capture */
1073 #define LL_HRTIM_CAPTURETRIG_TE1_SET (uint64_t)(HRTIM_CPT1CR_TE1SET ) <<32 /*!< Capture is triggered by TE1 output inactive to active transition */
1074 #define LL_HRTIM_CAPTURETRIG_TE1_RESET (uint64_t)(HRTIM_CPT1CR_TE1RST ) <<32 /*!< Capture is triggered by TE1 output active to inactive transition */
1075 #define LL_HRTIM_CAPTURETRIG_TIME_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMECMP1 ) <<32 /*!< Timer E Compare 1 triggers Capture */
1076 #define LL_HRTIM_CAPTURETRIG_TIME_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMECMP2 ) <<32 /*!< Timer E Compare 2 triggers Capture */
1077 #define LL_HRTIM_CAPTURETRIG_TF1_SET (uint64_t)(HRTIM_CPT1CR_TF1SET ) <<32 /*!< Capture is triggered by TF1 output inactive to active transition */
1078 #define LL_HRTIM_CAPTURETRIG_TF1_RESET (uint64_t)(HRTIM_CPT1CR_TF1RST ) <<32 /*!< Capture is triggered by TF1 output active to inactive transition */
1079 #define LL_HRTIM_CAPTURETRIG_TIMF_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMFCMP1 ) <<32 /*!< Timer F Compare 1 triggers Capture */
1080 #define LL_HRTIM_CAPTURETRIG_TIMF_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMFCMP2 ) <<32 /*!< Timer F Compare 2 triggers Capture */
1081 /**
1082 * @}
1083 */
1084
1085 /** @defgroup HRTIM_LL_EC_DLYPRT DELAYED PROTECTION (DLYPRT) MODE
1086 * @{
1087 * @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied).
1088 */
1089 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6 0x00000000U /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */
1090 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */
1091 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */
1092 #define LL_HRTIM_DLYPRT_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 6 */
1093 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7 (HRTIM_OUTR_DLYPRT_2) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */
1094 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */
1095 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */
1096 #define LL_HRTIM_DLYPRT_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 7 */
1097
1098 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8 0x00000000U /*!< Timers D, E: Output 1 delayed Idle on external Event 8 */
1099 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 8 */
1100 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */
1101 #define LL_HRTIM_DLYPRT_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 8 */
1102 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9 (HRTIM_OUTR_DLYPRT_2) /*!< Timers D, E: Output 1 delayed Idle on external Event 9 */
1103 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 9 */
1104 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */
1105 #define LL_HRTIM_DLYPRT_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 9 */
1106 /**
1107 * @}
1108 */
1109
1110 /** @defgroup HRTIM_LL_EC_BURSTMODE BURST MODE
1111 * @{
1112 * @brief Constants defining how the timer behaves during a burst mode operation.
1113 */
1114 #define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
1115 #define LL_HRTIM_BURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
1116 /**
1117 * @}
1118 */
1119
1120 /** @defgroup HRTIM_LL_EC_BURSTDMA BURST DMA
1121 * @{
1122 * @brief Constants defining the registers that can be written during a burst DMA operation.
1123 */
1124 #define LL_HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */
1125 #define LL_HRTIM_BURSTDMA_MCR (HRTIM_BDMUPR_MCR) /*!< MCR register is updated by Burst DMA accesses */
1126 #define LL_HRTIM_BURSTDMA_MICR (HRTIM_BDMUPR_MICR) /*!< MICR register is updated by Burst DMA accesses */
1127 #define LL_HRTIM_BURSTDMA_MDIER (HRTIM_BDMUPR_MDIER) /*!< MDIER register is updated by Burst DMA accesses */
1128 #define LL_HRTIM_BURSTDMA_MCNT (HRTIM_BDMUPR_MCNT) /*!< MCNTR register is updated by Burst DMA accesses */
1129 #define LL_HRTIM_BURSTDMA_MPER (HRTIM_BDMUPR_MPER) /*!< MPER register is updated by Burst DMA accesses */
1130 #define LL_HRTIM_BURSTDMA_MREP (HRTIM_BDMUPR_MREP) /*!< MREPR register is updated by Burst DMA accesses */
1131 #define LL_HRTIM_BURSTDMA_MCMP1 (HRTIM_BDMUPR_MCMP1) /*!< MCMP1R register is updated by Burst DMA accesses */
1132 #define LL_HRTIM_BURSTDMA_MCMP2 (HRTIM_BDMUPR_MCMP2) /*!< MCMP2R register is updated by Burst DMA accesses */
1133 #define LL_HRTIM_BURSTDMA_MCMP3 (HRTIM_BDMUPR_MCMP3) /*!< MCMP3R register is updated by Burst DMA accesses */
1134 #define LL_HRTIM_BURSTDMA_MCMP4 (HRTIM_BDMUPR_MCMP4) /*!< MCMP4R register is updated by Burst DMA accesses */
1135 #define LL_HRTIM_BURSTDMA_TIMMCR (HRTIM_BDTUPR_TIMCR) /*!< TIMxCR register is updated by Burst DMA accesses */
1136 #define LL_HRTIM_BURSTDMA_TIMICR (HRTIM_BDTUPR_TIMICR) /*!< TIMxICR register is updated by Burst DMA accesses */
1137 #define LL_HRTIM_BURSTDMA_TIMDIER (HRTIM_BDTUPR_TIMDIER) /*!< TIMxDIER register is updated by Burst DMA accesses */
1138 #define LL_HRTIM_BURSTDMA_TIMCNT (HRTIM_BDTUPR_TIMCNT) /*!< CNTxCR register is updated by Burst DMA accesses */
1139 #define LL_HRTIM_BURSTDMA_TIMPER (HRTIM_BDTUPR_TIMPER) /*!< PERxR register is updated by Burst DMA accesses */
1140 #define LL_HRTIM_BURSTDMA_TIMREP (HRTIM_BDTUPR_TIMREP) /*!< REPxR register is updated by Burst DMA accesses */
1141 #define LL_HRTIM_BURSTDMA_TIMCMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< CMP1xR register is updated by Burst DMA accesses */
1142 #define LL_HRTIM_BURSTDMA_TIMCMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< CMP2xR register is updated by Burst DMA accesses */
1143 #define LL_HRTIM_BURSTDMA_TIMCMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< CMP3xR register is updated by Burst DMA accesses */
1144 #define LL_HRTIM_BURSTDMA_TIMCMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< CMP4xR register is updated by Burst DMA accesses */
1145 #define LL_HRTIM_BURSTDMA_TIMDTR (HRTIM_BDTUPR_TIMDTR) /*!< DTxR register is updated by Burst DMA accesses */
1146 #define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
1147 #define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
1148 #define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
1149 #define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
1150 #define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
1151 #define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
1152 #define LL_HRTIM_BURSTDMA_TIMRSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
1153 #define LL_HRTIM_BURSTDMA_TIMCHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
1154 #define LL_HRTIM_BURSTDMA_TIMOUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
1155 #define LL_HRTIM_BURSTDMA_TIMFLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
1156 #define LL_HRTIM_BURSTDMA_CR2 (HRTIM_BDTUPR_TIMCR2) /*!< TIMxCR2 register is updated by Burst DMA accesses */
1157 #define LL_HRTIM_BURSTDMA_EEFR3 (HRTIM_BDTUPR_TIMEEFR3) /*!< EEFxR3 register is updated by Burst DMA accesses */
1158 /**
1159 * @}
1160 */
1161
1162 /** @defgroup HRTIM_LL_EC_CPPSTAT CURRENT PUSH-PULL STATUS
1163 * @{
1164 * @brief Constants defining on which output the signal is currently applied in push-pull mode.
1165 */
1166 #define LL_HRTIM_CPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Signal applied on output 1 and output 2 forced inactive */
1167 #define LL_HRTIM_CPPSTAT_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
1168 /**
1169 * @}
1170 */
1171
1172 /** @defgroup HRTIM_LL_EC_IPPSTAT IDLE PUSH-PULL STATUS
1173 * @{
1174 * @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.
1175 */
1176 #define LL_HRTIM_IPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
1177 #define LL_HRTIM_IPPSTAT_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
1178 /**
1179 * @}
1180 */
1181
1182 /** @defgroup HRTIM_LL_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER
1183 * @{
1184 * @brief Constants defining the event filtering applied to external events by a timer.
1185 */
1186 #define LL_HRTIM_EEFLTR_NONE (0x00000000U)
1187 #define LL_HRTIM_EEFLTR_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */
1188 #define LL_HRTIM_EEFLTR_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */
1189 #define LL_HRTIM_EEFLTR_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */
1190 #define LL_HRTIM_EEFLTR_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */
1191 /* Blanking Filter for TIMER A */
1192 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1193 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1194 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1195 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1196 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1197 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1198 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1199 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1200 /* Blanking Filter for TIMER B */
1201 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1202 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1203 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1204 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1205 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1206 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1207 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1208 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1209 /* Blanking Filter for TIMER C */
1210 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1211 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1212 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1213 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1214 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1215 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1216 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1217 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1218 /* Blanking Filter for TIMER D */
1219 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1220 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1221 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1222 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1223 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1224 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1225 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1226 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1227 /* Blanking Filter for TIMER E */
1228 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1229 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1230 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1231 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1232 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1233 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1234 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1235 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1236 /* Blanking Filter for TIMER F */
1237 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1238 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1239 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1240 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1241 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1242 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1243 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1244 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1245
1246 #define LL_HRTIM_EEFLTR_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */
1247 #define LL_HRTIM_EEFLTR_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */
1248 #define LL_HRTIM_EEFLTR_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1\
1249 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
1250 /**
1251 * @}
1252 */
1253
1254 /** @defgroup HRTIM_LL_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS
1255 * @{
1256 * @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.
1257 */
1258 #define LL_HRTIM_EELATCH_DISABLED 0x00000000U /*!< Event is ignored if it happens during a blank, or passed through during a window */
1259 #define LL_HRTIM_EELATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
1260 /**
1261 * @}
1262 */
1263
1264 /** @defgroup HRTIM_LL_EC_DT_PRESCALER DEADTIME PRESCALER
1265 * @{
1266 * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG).
1267 */
1268 #define LL_HRTIM_DT_PRESCALER_MUL8 0x00000000U /*!< fDTG = fHRTIM * 8 */
1269 #define LL_HRTIM_DT_PRESCALER_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4 */
1270 #define LL_HRTIM_DT_PRESCALER_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2 */
1271 #define LL_HRTIM_DT_PRESCALER_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
1272 #define LL_HRTIM_DT_PRESCALER_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2 */
1273 #define LL_HRTIM_DT_PRESCALER_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4 */
1274 #define LL_HRTIM_DT_PRESCALER_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8 */
1275 #define LL_HRTIM_DT_PRESCALER_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16 */
1276 /**
1277 * @}
1278 */
1279
1280 /** @defgroup HRTIM_LL_EC_DT_RISING_SIGN DEADTIME RISING SIGN
1281 * @{
1282 * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.
1283 */
1284 #define LL_HRTIM_DT_RISING_POSITIVE 0x00000000U /*!< Positive deadtime on rising edge */
1285 #define LL_HRTIM_DT_RISING_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
1286 /**
1287 * @}
1288 */
1289
1290 /** @defgroup HRTIM_LL_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN
1291 * @{
1292 * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.
1293 */
1294 #define LL_HRTIM_DT_FALLING_POSITIVE 0x00000000U /*!< Positive deadtime on falling edge */
1295 #define LL_HRTIM_DT_FALLING_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
1296 /**
1297 * @}
1298 */
1299
1300 /** @defgroup HRTIM_LL_EC_CHP_PRESCALER CHOPPER MODE PRESCALER
1301 * @{
1302 * @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ).
1303 */
1304 #define LL_HRTIM_CHP_PRESCALER_DIV16 0x00000000U /*!< fCHPFRQ = fHRTIM / 16 */
1305 #define LL_HRTIM_CHP_PRESCALER_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */
1306 #define LL_HRTIM_CHP_PRESCALER_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */
1307 #define LL_HRTIM_CHP_PRESCALER_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
1308 #define LL_HRTIM_CHP_PRESCALER_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */
1309 #define LL_HRTIM_CHP_PRESCALER_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
1310 #define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
1311 #define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
1312 #define LL_HRTIM_CHP_PRESCALER_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */
1313 #define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
1314 #define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
1315 #define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
1316 #define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
1317 #define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
1318 #define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
1319 #define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
1320 /**
1321 * @}
1322 */
1323
1324 /** @defgroup HRTIM_LL_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE
1325 * @{
1326 * @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8).
1327 */
1328 #define LL_HRTIM_CHP_DUTYCYCLE_0 0x00000000U /*!< Only 1st pulse is present */
1329 #define LL_HRTIM_CHP_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5 % */
1330 #define LL_HRTIM_CHP_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25 % */
1331 #define LL_HRTIM_CHP_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5 % */
1332 #define LL_HRTIM_CHP_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50 % */
1333 #define LL_HRTIM_CHP_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5 % */
1334 #define LL_HRTIM_CHP_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75 % */
1335 #define LL_HRTIM_CHP_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */
1336 /**
1337 * @}
1338 */
1339
1340 /** @defgroup HRTIM_LL_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH
1341 * @{
1342 * @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier.
1343 */
1344 #define LL_HRTIM_CHP_PULSEWIDTH_16 0x00000000U /*!< tSTPW = tHRTIM x 16 */
1345 #define LL_HRTIM_CHP_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */
1346 #define LL_HRTIM_CHP_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */
1347 #define LL_HRTIM_CHP_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
1348 #define LL_HRTIM_CHP_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */
1349 #define LL_HRTIM_CHP_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
1350 #define LL_HRTIM_CHP_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
1351 #define LL_HRTIM_CHP_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
1352 #define LL_HRTIM_CHP_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */
1353 #define LL_HRTIM_CHP_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
1354 #define LL_HRTIM_CHP_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
1355 #define LL_HRTIM_CHP_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
1356 #define LL_HRTIM_CHP_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
1357 #define LL_HRTIM_CHP_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
1358 #define LL_HRTIM_CHP_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
1359 #define LL_HRTIM_CHP_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
1360 /**
1361 * @}
1362 */
1363
1364 /** @defgroup HRTIM_LL_EC_OUTPUTSET_INPUT OUTPUTSET INPUT
1365 * @{
1366 * @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.
1367 */
1368 #define LL_HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */
1369 #define LL_HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transition */
1370 #define LL_HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transition */
1371 #define LL_HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transition */
1372 #define LL_HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transition */
1373 #define LL_HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transition */
1374 #define LL_HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transition */
1375 #define LL_HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transition */
1376 #define LL_HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transition */
1377 #define LL_HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transition */
1378 #define LL_HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transition */
1379 #define LL_HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transition */
1380 /* Timer Events mapping for Timer A */
1381 #define LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1382 #define LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1383 #define LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1384 #define LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1385 #define LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1386 #define LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1387 #define LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1388 #define LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1389 #define LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1390 /* Timer Events mapping for Timer B */
1391 #define LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1392 #define LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1393 #define LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1394 #define LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1395 #define LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1396 #define LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1397 #define LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1398 #define LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1399 #define LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1400 /* Timer Events mapping for Timer C */
1401 #define LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1402 #define LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1403 #define LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1404 #define LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1405 #define LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1406 #define LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1407 #define LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1408 #define LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1409 #define LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1410 /* Timer Events mapping for Timer D */
1411 #define LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1412 #define LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1413 #define LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1414 #define LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1415 #define LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1416 #define LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1417 #define LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1418 #define LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1419 #define LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1420 /* Timer Events mapping for Timer E */
1421 #define LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1422 #define LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1423 #define LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1424 #define LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1425 #define LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1426 #define LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1427 #define LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1428 #define LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1429 #define LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1430 /* Timer Events mapping for Timer F */
1431 #define LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1432 #define LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1433 #define LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1434 #define LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1435 #define LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1436 #define LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1437 #define LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1438 #define LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1439 #define LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1440 #define LL_HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transition */
1441 #define LL_HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transition */
1442 #define LL_HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transition */
1443 #define LL_HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transition */
1444 #define LL_HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transition */
1445 #define LL_HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transition */
1446 #define LL_HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transition */
1447 #define LL_HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transition */
1448 #define LL_HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transition */
1449 #define LL_HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transition */
1450 #define LL_HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transition */
1451 /**
1452 * @}
1453 */
1454
1455 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
1456 * @{
1457 * @brief Constants defining the events that can be selected to configure the
1458 * set crossbar of a timer output
1459 */
1460 #define LL_HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */
1461 #define LL_HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
1462 #define LL_HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
1463 #define LL_HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
1464 #define LL_HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
1465 #define LL_HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
1466 #define LL_HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
1467 #define LL_HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
1468 #define LL_HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
1469 #define LL_HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
1470 #define LL_HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
1471 #define LL_HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
1472 /* Timer Events mapping for Timer A */
1473 #define LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1474 #define LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1475 #define LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1476 #define LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1477 #define LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1478 #define LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1479 #define LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1480 #define LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1481 #define LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1482 /* Timer Events mapping for Timer B */
1483 #define LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1484 #define LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1485 #define LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1486 #define LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1487 #define LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1488 #define LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1489 #define LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1490 #define LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1491 #define LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1492 /* Timer Events mapping for Timer C */
1493 #define LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1494 #define LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1495 #define LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1496 #define LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1497 #define LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1498 #define LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1499 #define LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1500 #define LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1501 #define LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1502 /* Timer Events mapping for Timer D */
1503 #define LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1504 #define LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1505 #define LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1506 #define LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1507 #define LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1508 #define LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1509 #define LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1510 #define LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1511 #define LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1512 /* Timer Events mapping for Timer E */
1513 #define LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1514 #define LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1515 #define LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1516 #define LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1517 #define LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1518 #define LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1519 #define LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1520 #define LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1521 #define LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1522 /* Timer Events mapping for Timer F */
1523 #define LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1524 #define LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1525 #define LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1526 #define LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1527 #define LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1528 #define LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1529 #define LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1530 #define LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1531 #define LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1532 #define LL_HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
1533 #define LL_HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
1534 #define LL_HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
1535 #define LL_HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
1536 #define LL_HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
1537 #define LL_HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
1538 #define LL_HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
1539 #define LL_HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
1540 #define LL_HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
1541 #define LL_HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
1542 #define LL_HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
1543 /**
1544 * @}
1545 */
1546
1547 /** @defgroup HRTIM_LL_EC_OUT_POLARITY OUPUT_POLARITY
1548 * @{
1549 * @brief Constants defining the polarity of a timer output.
1550 */
1551 #define LL_HRTIM_OUT_POSITIVE_POLARITY 0x00000000U /*!< Output is active HIGH */
1552 #define LL_HRTIM_OUT_NEGATIVE_POLARITY (HRTIM_OUTR_POL1) /*!< Output is active LOW */
1553 /**
1554 * @}
1555 */
1556
1557 /** @defgroup HRTIM_LL_EC_OUT_IDLEMODE OUTPUT IDLE MODE
1558 * @{
1559 * @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.
1560 */
1561 #define LL_HRTIM_OUT_NO_IDLE 0x00000000U /*!< The output is not affected by the burst mode operation */
1562 #define LL_HRTIM_OUT_IDLE_WHEN_BURST (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
1563 /**
1564 * @}
1565 */
1566
1567 /** @defgroup HRTIM_LL_EC_INTLVD_MODE INTLVD MODE
1568 * @{
1569 * @brief Constants defining the interleaved mode of an HRTIM Timer instance.
1570 */
1571 #define LL_HRTIM_INTERLEAVED_MODE_DISABLED 0x000U /*!< HRTIM interleaved Mode is disabled */
1572 #define LL_HRTIM_INTERLEAVED_MODE_DUAL HRTIM_MCR_HALF /*!< HRTIM interleaved Mode is Dual */
1573 #define LL_HRTIM_INTERLEAVED_MODE_TRIPLE HRTIM_MCR_INTLVD_0 /*!< HRTIM interleaved Mode is Triple */
1574 #define LL_HRTIM_INTERLEAVED_MODE_QUAD HRTIM_MCR_INTLVD_1 /*!< HRTIM interleaved Mode is Quad */
1575 /**
1576 * @}
1577 */
1578 /** @defgroup HRTIM_LL_EC_HALF_MODE HALF MODE
1579 * @{
1580 * @brief Constants defining the half mode of an HRTIM Timer instance.
1581 */
1582 #define LL_HRTIM_HALF_MODE_DISABLED 0x000U /*!< HRTIM Half Mode is disabled */
1583 #define LL_HRTIM_HALF_MODE_ENABLE HRTIM_MCR_HALF /*!< HRTIM Half Mode is Half */
1584 /**
1585 * @}
1586 */
1587
1588 /** @defgroup HRTIM_LL_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL
1589 * @{
1590 * @brief Constants defining the output level when output is in IDLE state
1591 */
1592 #define LL_HRTIM_OUT_IDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */
1593 #define LL_HRTIM_OUT_IDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
1594 /**
1595 * @}
1596 */
1597
1598 /** @defgroup HRTIM_LL_EC_OUT_FAULTSTATE OUTPUT FAULT STATE
1599 * @{
1600 * @brief Constants defining the output level when output is in FAULT state.
1601 */
1602 #define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 0x00000000U /*!< The output is not affected by the fault input */
1603 #define LL_HRTIM_OUT_FAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
1604 #define LL_HRTIM_OUT_FAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
1605 #define LL_HRTIM_OUT_FAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
1606 /**
1607 * @}
1608 */
1609
1610 /** @defgroup HRTIM_LL_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE
1611 * @{
1612 * @brief Constants defining whether or not chopper mode is enabled for a timer output.
1613 */
1614 #define LL_HRTIM_OUT_CHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */
1615 #define LL_HRTIM_OUT_CHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
1616 /**
1617 * @}
1618 */
1619
1620 /** @defgroup HRTIM_LL_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE
1621 * @{
1622 * @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state
1623 during a programmable period before the output takes its idle state.
1624 */
1625 #define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */
1626 #define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
1627 /**
1628 * @}
1629 */
1630 /** @defgroup HRTIM_LL_EC_OUT_LEVEL OUTPUT LEVEL
1631 * @{
1632 * @brief Constants defining the level of a timer output.
1633 */
1634 #define LL_HRTIM_OUT_LEVEL_INACTIVE 0x00000000U /*!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */
1635 #define LL_HRTIM_OUT_LEVEL_ACTIVE ((uint32_t)0x00000001) /*!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */
1636 /**
1637 * @}
1638 */
1639
1640 /** @defgroup HRTIM_LL_EC_EE_SRC EXTERNAL EVENT SOURCE
1641 * @{
1642 * @brief Constants defining available sources associated to external events.
1643 */
1644 #define LL_HRTIM_EEV1SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 1 */
1645 #define LL_HRTIM_EEV2SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 2 */
1646 #define LL_HRTIM_EEV3SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 3 */
1647 #define LL_HRTIM_EEV4SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 4 */
1648 #define LL_HRTIM_EEV5SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 5 */
1649 #define LL_HRTIM_EEV6SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 6 */
1650 #define LL_HRTIM_EEV7SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 7 */
1651 #define LL_HRTIM_EEV8SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 8 */
1652 #define LL_HRTIM_EEV9SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 9 */
1653 #define LL_HRTIM_EEV10SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 10 */
1654 #define LL_HRTIM_EEV1SRC_COMP2_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 1 */
1655 #define LL_HRTIM_EEV2SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 2 */
1656 #define LL_HRTIM_EEV3SRC_COMP6_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 3 */
1657 #define LL_HRTIM_EEV4SRC_COMP1_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 4 */
1658 #define LL_HRTIM_EEV5SRC_COMP3_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 5 */
1659 #define LL_HRTIM_EEV6SRC_COMP2_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 6 */
1660 #define LL_HRTIM_EEV7SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 7 */
1661 #define LL_HRTIM_EEV8SRC_COMP6_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 8 */
1662 #define LL_HRTIM_EEV9SRC_COMP5_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 9 */
1663 #define LL_HRTIM_EEV10SRC_COMP7_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 10 */
1664 #define LL_HRTIM_EEV1SRC_TIM1_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 1 */
1665 #define LL_HRTIM_EEV2SRC_TIM2_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 2 */
1666 #define LL_HRTIM_EEV3SRC_TIM3_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 3 */
1667 #define LL_HRTIM_EEV4SRC_COMP5_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 4 */
1668 #define LL_HRTIM_EEV5SRC_COMP7_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 5 */
1669 #define LL_HRTIM_EEV6SRC_COMP1_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 6 */
1670 #define LL_HRTIM_EEV7SRC_TIM7_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 7 */
1671 #define LL_HRTIM_EEV8SRC_COMP3_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 8 */
1672 #define LL_HRTIM_EEV9SRC_TIM15_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 9 */
1673 #define LL_HRTIM_EEV10SRC_TIM6_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 10 */
1674 #define LL_HRTIM_EEV1SRC_ADC1_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 1 */
1675 #define LL_HRTIM_EEV2SRC_ADC1_AWD2 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 2 */
1676 #define LL_HRTIM_EEV3SRC_ADC1_AWD3 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 3 */
1677 #define LL_HRTIM_EEV4SRC_ADC2_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 4 */
1678 #define LL_HRTIM_EEV5SRC_ADC2_AWD2 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 5 */
1679 #define LL_HRTIM_EEV6SRC_ADC2_AWD3 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 6 */
1680 #define LL_HRTIM_EEV7SRC_ADC3_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 7 */
1681 #define LL_HRTIM_EEV8SRC_ADC4_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 8 */
1682 #define LL_HRTIM_EEV9SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 9 */
1683 #define LL_HRTIM_EEV10SRC_ADC5_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 10 */
1684 /**
1685 * @}
1686 */
1687 /** @defgroup HRTIM_LL_EC_EE_POLARITY EXTERNAL EVENT POLARITY
1688 * @{
1689 * @brief Constants defining the polarity of an external event.
1690 */
1691 #define LL_HRTIM_EE_POLARITY_HIGH 0x00000000U /*!< External event is active high */
1692 #define LL_HRTIM_EE_POLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
1693 /**
1694 * @}
1695 */
1696
1697 /** @defgroup HRTIM_LL_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY
1698 * @{
1699 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.
1700 */
1701 #define LL_HRTIM_EE_SENSITIVITY_LEVEL 0x00000000U /*!< External event is active on level */
1702 #define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
1703 #define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
1704 #define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
1705 /**
1706 * @}
1707 */
1708
1709 /** @defgroup HRTIM_LL_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE
1710 * @{
1711 * @brief Constants defining whether or not an external event is programmed in fast mode.
1712 */
1713 #define LL_HRTIM_EE_FASTMODE_DISABLE 0x00000000U /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
1714 #define LL_HRTIM_EE_FASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */
1715 /**
1716 * @}
1717 */
1718
1719 /** @defgroup HRTIM_LL_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER
1720 * @{
1721 * @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied.
1722 */
1723 #define LL_HRTIM_EE_FILTER_NONE 0x00000000U /*!< Filter disabled */
1724 #define LL_HRTIM_EE_FILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=2 */
1725 #define LL_HRTIM_EE_FILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fHRTIM, N=4 */
1726 #define LL_HRTIM_EE_FILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=8 */
1727 #define LL_HRTIM_EE_FILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/2, N=6 */
1728 #define LL_HRTIM_EE_FILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/2, N=8 */
1729 #define LL_HRTIM_EE_FILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/4, N=6 */
1730 #define LL_HRTIM_EE_FILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/4, N=8 */
1731 #define LL_HRTIM_EE_FILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING = fEEVS/8, N=6 */
1732 #define LL_HRTIM_EE_FILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/8, N=8 */
1733 #define LL_HRTIM_EE_FILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/16, N=5 */
1734 #define LL_HRTIM_EE_FILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/16, N=6 */
1735 #define LL_HRTIM_EE_FILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/16, N=8 */
1736 #define LL_HRTIM_EE_FILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=5 */
1737 #define LL_HRTIM_EE_FILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/32, N=6 */
1738 #define LL_HRTIM_EE_FILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=8 */
1739 /**
1740 * @}
1741 */
1742
1743 /** @defgroup HRTIM_LL_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER
1744 * @{
1745 * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.
1746 */
1747 #define LL_HRTIM_EE_PRESCALER_DIV1 0x00000000U /*!< fEEVS = fHRTIM */
1748 #define LL_HRTIM_EE_PRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 2 */
1749 #define LL_HRTIM_EE_PRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS = fHRTIM / 4 */
1750 #define LL_HRTIM_EE_PRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 8 */
1751 /**
1752 * @}
1753 */
1754
1755 /** @defgroup HRTIM_LL_EC_EE_COUNTER EXTERNAL EVENT A or B COUNTER
1756 * @{
1757 * @brief Constants defining the external event counter.
1758 */
1759 #define LL_HRTIM_EE_COUNTER_A ((uint32_t)0U) /*!< External Event A Counter */
1760 #define LL_HRTIM_EE_COUNTER_B ((uint32_t)16U) /*!< External Event B Counter */
1761 /**
1762 * @}
1763 */
1764
1765 /** @defgroup HRTIM_LL_EC_EE_COUNTERRSTMODE EXTERNAL EVENT A or B RESET MODE
1766 * @{
1767 * @brief Constants defining the external event reset mode.
1768 */
1769 #define LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL ((uint32_t)0U) /*!< External Event counter is reset on each reset / roll-over event */
1770 #define LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL ((uint32_t)HRTIM_EEFR3_EEVARSTM) /*!< External Event counter is reset on each reset / roll-over event only if no event occurs during last counting period */
1771 /**
1772 * @}
1773 */
1774
1775 /** @defgroup HRTIM_LL_EC_FLT_SRC FAULT SOURCE
1776 * @{
1777 * @brief Constants defining whether a faults is be triggered by any external or internal fault source.
1778 */
1779 #define LL_HRTIM_FLT_SRC_DIGITALINPUT 0x00000000U /*!< Fault input is FLT input pin */
1780 #define LL_HRTIM_FLT_SRC_INTERNAL HRTIM_FLTINR1_FLT1SRC_0 /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
1781 #define LL_HRTIM_FLT_SRC_EEVINPUT HRTIM_FLTINR2_FLT1SRC_1 /*!< Fault input is external event pin */
1782 /**
1783 * @}
1784 */
1785
1786 /** @defgroup HRTIM_LL_EC_FLT_POLARITY FAULT POLARITY
1787 * @{
1788 * @brief Constants defining the polarity of a fault event.
1789 */
1790 #define LL_HRTIM_FLT_POLARITY_LOW 0x00000000U /*!< Fault input is active low */
1791 #define LL_HRTIM_FLT_POLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
1792 /**
1793 * @}
1794 */
1795
1796 /** @defgroup HRTIM_LL_EC_FLT_FILTER FAULT DIGITAL FILTER
1797 * @{
1798 * @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied.
1799 */
1800 #define LL_HRTIM_FLT_FILTER_NONE 0x00000000U /*!< Filter disabled */
1801 #define LL_HRTIM_FLT_FILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */
1802 #define LL_HRTIM_FLT_FILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */
1803 #define LL_HRTIM_FLT_FILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */
1804 #define LL_HRTIM_FLT_FILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */
1805 #define LL_HRTIM_FLT_FILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */
1806 #define LL_HRTIM_FLT_FILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */
1807 #define LL_HRTIM_FLT_FILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */
1808 #define LL_HRTIM_FLT_FILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */
1809 #define LL_HRTIM_FLT_FILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */
1810 #define LL_HRTIM_FLT_FILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */
1811 #define LL_HRTIM_FLT_FILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */
1812 #define LL_HRTIM_FLT_FILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */
1813 #define LL_HRTIM_FLT_FILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */
1814 #define LL_HRTIM_FLT_FILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */
1815 #define LL_HRTIM_FLT_FILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */
1816 /**
1817 * @}
1818 */
1819
1820 /** @defgroup HRTIM_LL_EC_FLT_PRESCALER BURST FAULT PRESCALER
1821 * @{
1822 * @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used by the digital filters.
1823 */
1824 #define LL_HRTIM_FLT_PRESCALER_DIV1 0x00000000U /*!< fFLTS = fHRTIM */
1825 #define LL_HRTIM_FLT_PRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 2 */
1826 #define LL_HRTIM_FLT_PRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS = fHRTIM / 4 */
1827 #define LL_HRTIM_FLT_PRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 8 */
1828 /**
1829 * @}
1830 */
1831
1832 /** @defgroup HRTIM_LL_EC_FLT_BLKS FAULT BLANKING Source
1833 * @{
1834 * @brief Constants defining the Blanking Source of a fault event.
1835 */
1836 #define LL_HRTIM_FLT_BLANKING_RSTALIGNED 0x00000000U /*!< Fault blanking source is Reset-aligned */
1837 #define LL_HRTIM_FLT_BLANKING_MOVING (HRTIM_FLTINR3_FLT1BLKS) /*!< Fault blanking source is Moving window */
1838 /**
1839 * @}
1840 */
1841
1842 /** @defgroup HRTIM_LL_EC_FLT_RSTM FAULT Counter RESET Mode
1843 * @{
1844 * @brief Constants defining the Counter RESet Mode of a fault event.
1845 */
1846 #define LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL 0x00000000U /*!< Fault counter is reset on each reset / roll-over event */
1847 #define LL_HRTIM_FLT_COUNTERRST_CONDITIONAL (HRTIM_FLTINR3_FLT1RSTM) /*!< Fault counter is reset on each reset / roll-over event only if no fault occurred during last counting
1848 period. */
1849 /**
1850 * @}
1851 */
1852
1853 /** @defgroup HRTIM_LL_EC_BM_MODE BURST MODE OPERATING MODE
1854 * @{
1855 * @brief Constants defining if the burst mode is entered once or if it is continuously operating.
1856 */
1857 #define LL_HRTIM_BM_MODE_SINGLESHOT 0x00000000U /*!< Burst mode operates in single shot mode */
1858 #define LL_HRTIM_BM_MODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
1859 /**
1860 * @}
1861 */
1862
1863 /** @defgroup HRTIM_LL_EC_BM_CLKSRC BURST MODE CLOCK SOURCE
1864 * @{
1865 * @brief Constants defining the clock source for the burst mode counter.
1866 */
1867 #define LL_HRTIM_BM_CLKSRC_MASTER 0x00000000U /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
1868 #define LL_HRTIM_BM_CLKSRC_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
1869 #define LL_HRTIM_BM_CLKSRC_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
1870 #define LL_HRTIM_BM_CLKSRC_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
1871 #define LL_HRTIM_BM_CLKSRC_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
1872 #define LL_HRTIM_BM_CLKSRC_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
1873 #define LL_HRTIM_BM_CLKSRC_TIMER_F (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer F counter reset/roll-over is used as clock source for the burst mode counter */
1874 #define LL_HRTIM_BM_CLKSRC_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
1875 #define LL_HRTIM_BM_CLKSRC_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
1876 #define LL_HRTIM_BM_CLKSRC_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
1877 #define LL_HRTIM_BM_CLKSRC_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
1878 /**
1879 * @}
1880 */
1881
1882 /** @defgroup HRTIM_LL_EC_BM_PRESCALER BURST MODE PRESCALER
1883 * @{
1884 * @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST).
1885 */
1886 #define LL_HRTIM_BM_PRESCALER_DIV1 0x00000000U /*!< fBRST = fHRTIM */
1887 #define LL_HRTIM_BM_PRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2 */
1888 #define LL_HRTIM_BM_PRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4 */
1889 #define LL_HRTIM_BM_PRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8 */
1890 #define LL_HRTIM_BM_PRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16 */
1891 #define LL_HRTIM_BM_PRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32 */
1892 #define LL_HRTIM_BM_PRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64 */
1893 #define LL_HRTIM_BM_PRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128 */
1894 #define LL_HRTIM_BM_PRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256 */
1895 #define LL_HRTIM_BM_PRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512 */
1896 #define LL_HRTIM_BM_PRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024 */
1897 #define LL_HRTIM_BM_PRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048*/
1898 #define LL_HRTIM_BM_PRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096 */
1899 #define LL_HRTIM_BM_PRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192 */
1900 #define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384 */
1901 #define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
1902 /**
1903 * @}
1904 */
1905
1906 /** @defgroup HRTIM_LL_EC_BM_TRIG HRTIM BURST MODE TRIGGER
1907 * @{
1908 * @brief Constants defining the events that can be used to trig the burst mode operation.
1909 */
1910 #define LL_HRTIM_BM_TRIG_NONE 0x00000000U /*!< No trigger */
1911 #define LL_HRTIM_BM_TRIG_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master timer reset event is starting the burst mode operation */
1912 #define LL_HRTIM_BM_TRIG_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master timer repetition event is starting the burst mode operation */
1913 #define LL_HRTIM_BM_TRIG_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master timer compare 1 event is starting the burst mode operation */
1914 #define LL_HRTIM_BM_TRIG_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master timer compare 2 event is starting the burst mode operation */
1915 #define LL_HRTIM_BM_TRIG_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master timer compare 3 event is starting the burst mode operation */
1916 #define LL_HRTIM_BM_TRIG_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master timer compare 4 event is starting the burst mode operation */
1917 #define LL_HRTIM_BM_TRIG_TIMA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset event is starting the burst mode operation */
1918 #define LL_HRTIM_BM_TRIG_TIMA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition event is starting the burst mode operation */
1919 #define LL_HRTIM_BM_TRIG_TIMA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 event is starting the burst mode operation */
1920 #define LL_HRTIM_BM_TRIG_TIMA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 event is starting the burst mode operation */
1921 #define LL_HRTIM_BM_TRIG_TIMB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset event is starting the burst mode operation */
1922 #define LL_HRTIM_BM_TRIG_TIMB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition event is starting the burst mode operation */
1923 #define LL_HRTIM_BM_TRIG_TIMB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 event is starting the burst mode operation */
1924 #define LL_HRTIM_BM_TRIG_TIMB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 event is starting the burst mode operation */
1925 #define LL_HRTIM_BM_TRIG_TIMC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C resetevent is starting the burst mode operation */
1926 #define LL_HRTIM_BM_TRIG_TIMC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition event is starting the burst mode operation */
1927 #define LL_HRTIM_BM_TRIG_TIMC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 event is starting the burst mode operation */
1928 #define LL_HRTIM_BM_TRIG_TIMD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset event is starting the burst mode operation */
1929 #define LL_HRTIM_BM_TRIG_TIMD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition event is starting the burst mode operation */
1930 #define LL_HRTIM_BM_TRIG_TIMD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 event is starting the burst mode operation */
1931 #define LL_HRTIM_BM_TRIG_TIME_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition event is starting the burst mode operation */
1932 #define LL_HRTIM_BM_TRIG_TIME_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 event is starting the burst mode operation */
1933 #define LL_HRTIM_BM_TRIG_TIME_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 event is starting the burst mode operation */
1934 #define LL_HRTIM_BM_TRIG_TIMF_RESET (HRTIM_BMTRGR_TFRST) /*!< Timer F reset event is starting the burst mode operation */
1935 #define LL_HRTIM_BM_TRIG_TIMF_REPETITION (HRTIM_BMTRGR_TFREP) /*!< Timer F repetition event is starting the burst mode operation */
1936 #define LL_HRTIM_BM_TRIG_TIMF_CMP1 (HRTIM_BMTRGR_TFCMP1) /*!< Timer F compare 1 event is starting the burst mode operation */
1937 #define LL_HRTIM_BM_TRIG_TIMA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst mode operation */
1938 #define LL_HRTIM_BM_TRIG_TIMD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst mode operation */
1939 #define LL_HRTIM_BM_TRIG_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External event 7 conditioned by TIMA filters is starting the burst mode operation */
1940 #define LL_HRTIM_BM_TRIG_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External event 8 conditioned by TIMD filters is starting the burst mode operation */
1941 #define LL_HRTIM_BM_TRIG_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode operation */
1942 /**
1943 * @}
1944 */
1945
1946 /** @defgroup HRTIM_LL_EC_BM_STATUS HRTIM BURST MODE STATUS
1947 * @{
1948 * @brief Constants defining the operating state of the burst mode controller.
1949 */
1950 #define LL_HRTIM_BM_STATUS_NORMAL 0x00000000U /*!< Normal operation */
1951 #define LL_HRTIM_BM_STATUS_BURST_ONGOING HRTIM_BMCR_BMSTAT /*!< Burst operation on-going */
1952 /**
1953 * @}
1954 */
1955
1956 /** @defgroup HRTIM_LL_COUNTER_MODE Counter Mode
1957 * @{
1958 * @brief Constants defining the Counter Up Down Mode.
1959 */
1960 #define LL_HRTIM_COUNTING_MODE_UP 0x00000000U /*!< counter is operating in up-counting mode */
1961 #define LL_HRTIM_COUNTING_MODE_UP_DOWN HRTIM_TIMCR2_UDM /*!< counter is operating in up-down counting mode */
1962 /**
1963 * @}
1964 */
1965
1966 /** @defgroup HRTIM_LL_COUNTER_Roll-Over counter Mode
1967 * @{
1968 * @brief Constants defining the Roll-Over counter Mode.
1969 */
1970 #define LL_HRTIM_ROLLOVER_MODE_PER 2U /*!< Event generated when counter reaches period value ('crest' mode) */
1971 #define LL_HRTIM_ROLLOVER_MODE_RST 1U /*!< Event generated when counter equals 0 ('valley' mode) */
1972 #define LL_HRTIM_ROLLOVER_MODE_BOTH 0U /*!< Event generated when counter reach both conditions (0 or HRTIM_PERxR value) */
1973 /**
1974 * @}
1975 */
1976
1977 /** @defgroup HRTIM_Timer_TrigHalf_Mode HRTIM Timer Triggered-Half Mode
1978 * @{
1979 * @brief Constants defining how the timer counter operates.
1980 */
1981 #define LL_HRTIM_TRIGHALF_DISABLED 0x00000000U /*!< Timer Compare 2 register is behaving in standard mode */
1982 #define LL_HRTIM_TRIGHALF_ENABLED HRTIM_TIMCR2_TRGHLF /*!< Timer Compare 2 register is behaving in triggered-half mode */
1983 /**
1984 * @}
1985 */
1986
1987 /** @defgroup HRTIM_LL_COUNTER_Compare Greater than compare PWM Mode
1988 * @{
1989 * @brief Constants defining the greater than compare 1 or 3 PWM Mode.
1990 */
1991 #define LL_HRTIM_GTCMP1_EQUAL 0x00000000U /*!< event is generated when counter is equal to compare value */
1992 #define LL_HRTIM_GTCMP1_GREATER HRTIM_TIMCR2_GTCMP1 /*!< event is generated when counter is greater than compare value */
1993 #define LL_HRTIM_GTCMP3_EQUAL 0x00000000U /*!< event is generated when counter is equal to compare value */
1994 #define LL_HRTIM_GTCMP3_GREATER HRTIM_TIMCR2_GTCMP3 /*!< event is generated when counter is greater than compare value */
1995 /**
1996 * @}
1997 */
1998
1999 /** @defgroup HRTIM_LL_COUNTER_DCDE Enabling the Dual Channel DAC Triggering
2000 * @{
2001 * @brief Constants enabling the Dual Channel DAC Reset trigger mechanism.
2002 */
2003 #define LL_HRTIM_DCDE_DISABLED 0x00000000U /*!< Dual Channel DAC trigger is generated on counter reset or roll-over event */
2004 #define LL_HRTIM_DCDE_ENABLED HRTIM_TIMCR2_DCDE /*!< Dual Channel DAC trigger is generated on output 1 set event */
2005 /**
2006 * @}
2007 */
2008
2009 /** @defgroup HRTIM_LL_COUNTER_DCDR Dual Channel DAC Reset Trigger
2010 * @{
2011 * @brief Constants defining the Dual Channel DAC Reset trigger.
2012 */
2013 #define LL_HRTIM_DCDR_COUNTER 0x00000000U /*!< Dual Channel DAC trigger is generated on counter reset or roll-over event */
2014 #define LL_HRTIM_DCDR_OUT1SET HRTIM_TIMCR2_DCDR /*!< Dual Channel DAC trigger is generated on output 1 set event */
2015 /**
2016 * @}
2017 */
2018
2019 /** @defgroup HRTIM_LL_COUNTER_DCDS Dual Channel DAC Step trigger
2020 * @{
2021 * @brief Constants defining the Dual Channel DAC Step trigger.
2022 */
2023 #define LL_HRTIM_DCDS_CMP2 0x00000000U /*!< trigger is generated on compare 2 event */
2024 #define LL_HRTIM_DCDS_OUT1RST HRTIM_TIMCR2_DCDS /*!< trigger is generated on output 1 reset event */
2025 /**
2026 * @}
2027 */
2028
2029 /**
2030 * @}
2031 */
2032
2033 /* Exported macro ------------------------------------------------------------*/
2034 /** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros
2035 * @{
2036 */
2037
2038 /** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros
2039 * @{
2040 */
2041
2042 /**
2043 * @brief Write a value in HRTIM register
2044 * @param __INSTANCE__ HRTIM Instance
2045 * @param __REG__ Register to be written
2046 * @param __VALUE__ Value to be written in the register
2047 * @retval None
2048 */
2049 #define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
2050
2051 /**
2052 * @brief Read a value in HRTIM register
2053 * @param __INSTANCE__ HRTIM Instance
2054 * @param __REG__ Register to be read
2055 * @retval Register value
2056 */
2057 #define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
2058 /**
2059 * @}
2060 */
2061
2062 /** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros
2063 * @{
2064 */
2065 /**
2066 * @brief HELPER macro returning the output state from output enable/disable status
2067 * @param __OUTPUT_STATUS_EN__ output enable status
2068 * @param __OUTPUT_STATUS_DIS__ output Disable status
2069 * @retval Returned value can be one of the following values:
2070 * @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE
2071 * @arg @ref LL_HRTIM_OUTPUTSTATE_RUN
2072 * @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT
2073 */
2074 #define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\
2075 (((__OUTPUT_STATUS_EN__) == 1) ? LL_HRTIM_OUTPUTSTATE_RUN :\
2076 ((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT)
2077 /**
2078 * @}
2079 */
2080
2081 /**
2082 * @}
2083 */
2084
2085 /* Exported functions --------------------------------------------------------*/
2086 /** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions
2087 * @{
2088 */
2089 /** @defgroup HRTIM_LL_EF_HRTIM_Control HRTIM_Control
2090 * @{
2091 */
2092
2093 /**
2094 * @brief Select the HRTIM synchronization input source.
2095 * @note This function must not be called when the concerned timer(s) is (are) enabled .
2096 * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
2097 * @param HRTIMx High Resolution Timer instance
2098 * @param SyncInSrc This parameter can be one of the following values:
2099 * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
2100 * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
2101 * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
2102 * @retval None
2103 */
LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef * HRTIMx,uint32_t SyncInSrc)2104 __STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncInSrc)
2105 {
2106 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN, SyncInSrc);
2107 }
2108
2109 /**
2110 * @brief Get actual HRTIM synchronization input source.
2111 * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
2112 * @param HRTIMx High Resolution Timer instance
2113 * @retval SyncInSrc Returned value can be one of the following values:
2114 * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
2115 * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
2116 * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
2117 */
LL_HRTIM_GetSyncInSrc(HRTIM_TypeDef * HRTIMx)2118 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(HRTIM_TypeDef *HRTIMx)
2119 {
2120 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN));
2121 }
2122
2123 /**
2124 * @brief Configure the HRTIM synchronization output.
2125 * @rmtoll MCR SYNCSRC LL_HRTIM_ConfigSyncOut\n
2126 * MCR SYNCOUT LL_HRTIM_ConfigSyncOut
2127 * @param HRTIMx High Resolution Timer instance
2128 * @param Config This parameter can be one of the following values:
2129 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
2130 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
2131 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
2132 * @param Src This parameter can be one of the following values:
2133 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
2134 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
2135 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
2136 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
2137 * @retval None
2138 */
LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef * HRTIMx,uint32_t Config,uint32_t Src)2139 __STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src)
2140 {
2141 MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT | HRTIM_MCR_SYNC_SRC), (Config | Src));
2142 }
2143
2144 /**
2145 * @brief Set the routing and conditioning of the synchronization output event.
2146 * @rmtoll MCR SYNCOUT LL_HRTIM_SetSyncOutConfig
2147 * @note This function can be called only when the master timer is enabled.
2148 * @param HRTIMx High Resolution Timer instance
2149 * @param SyncOutConfig This parameter can be one of the following values:
2150 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
2151 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
2152 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
2153 * @retval None
2154 */
LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef * HRTIMx,uint32_t SyncOutConfig)2155 __STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutConfig)
2156 {
2157 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT, SyncOutConfig);
2158 }
2159
2160 /**
2161 * @brief Get actual routing and conditioning of the synchronization output event.
2162 * @rmtoll MCR SYNCOUT LL_HRTIM_GetSyncOutConfig
2163 * @param HRTIMx High Resolution Timer instance
2164 * @retval SyncOutConfig Returned value can be one of the following values:
2165 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
2166 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
2167 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
2168 */
LL_HRTIM_GetSyncOutConfig(HRTIM_TypeDef * HRTIMx)2169 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(HRTIM_TypeDef *HRTIMx)
2170 {
2171 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT));
2172 }
2173
2174 /**
2175 * @brief Set the source and event to be sent on the HRTIM synchronization output.
2176 * @rmtoll MCR SYNCSRC LL_HRTIM_SetSyncOutSrc
2177 * @param HRTIMx High Resolution Timer instance
2178 * @param SyncOutSrc This parameter can be one of the following values:
2179 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
2180 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
2181 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
2182 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
2183 * @retval None
2184 */
LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef * HRTIMx,uint32_t SyncOutSrc)2185 __STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutSrc)
2186 {
2187 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC, SyncOutSrc);
2188 }
2189
2190 /**
2191 * @brief Get actual source and event sent on the HRTIM synchronization output.
2192 * @rmtoll MCR SYNCSRC LL_HRTIM_GetSyncOutSrc
2193 * @param HRTIMx High Resolution Timer instance
2194 * @retval SyncOutSrc Returned value can be one of the following values:
2195 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
2196 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
2197 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
2198 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
2199 */
LL_HRTIM_GetSyncOutSrc(HRTIM_TypeDef * HRTIMx)2200 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(HRTIM_TypeDef *HRTIMx)
2201 {
2202 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC));
2203 }
2204
2205 /**
2206 * @brief Disable (temporarily) update event generation.
2207 * @rmtoll CR1 MUDIS LL_HRTIM_SuspendUpdate\n
2208 * CR1 TAUDIS LL_HRTIM_SuspendUpdate\n
2209 * CR1 TBUDIS LL_HRTIM_SuspendUpdate\n
2210 * CR1 TCUDIS LL_HRTIM_SuspendUpdate\n
2211 * CR1 TDUDIS LL_HRTIM_SuspendUpdate\n
2212 * CR1 TEUDIS LL_HRTIM_SuspendUpdate\n
2213 * CR1 TFUDIS LL_HRTIM_SuspendUpdate
2214 * @note Allow to temporarily disable the transfer from preload to active
2215 * registers, whatever the selected update event. This allows to modify
2216 * several registers in multiple timers.
2217 * @param HRTIMx High Resolution Timer instance
2218 * @param Timers This parameter can be a combination of the following values:
2219 * @arg @ref LL_HRTIM_TIMER_MASTER
2220 * @arg @ref LL_HRTIM_TIMER_A
2221 * @arg @ref LL_HRTIM_TIMER_B
2222 * @arg @ref LL_HRTIM_TIMER_C
2223 * @arg @ref LL_HRTIM_TIMER_D
2224 * @arg @ref LL_HRTIM_TIMER_E
2225 * @arg @ref LL_HRTIM_TIMER_F
2226 * @retval None
2227 */
LL_HRTIM_SuspendUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timers)2228 __STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
2229 {
2230 /* clear register before applying the new value */
2231 CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((LL_HRTIM_TIMER_ALL >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
2232 SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
2233 }
2234
2235 /**
2236 * @brief Enable update event generation.
2237 * @rmtoll CR1 MUDIS LL_HRTIM_ResumeUpdate\n
2238 * CR1 TAUDIS LL_HRTIM_ResumeUpdate\n
2239 * CR1 TBUDIS LL_HRTIM_ResumeUpdate\n
2240 * CR1 TCUDIS LL_HRTIM_ResumeUpdate\n
2241 * CR1 TDUDIS LL_HRTIM_ResumeUpdate\n
2242 * CR1 TEUDIS LL_HRTIM_ResumeUpdate\n
2243 * CR1 TFUDIS LL_HRTIM_ResumeUpdate
2244 * @note The regular update event takes place.
2245 * @param HRTIMx High Resolution Timer instance
2246 * @param Timers This parameter can be a combination of the following values:
2247 * @arg @ref LL_HRTIM_TIMER_MASTER
2248 * @arg @ref LL_HRTIM_TIMER_A
2249 * @arg @ref LL_HRTIM_TIMER_B
2250 * @arg @ref LL_HRTIM_TIMER_C
2251 * @arg @ref LL_HRTIM_TIMER_D
2252 * @arg @ref LL_HRTIM_TIMER_E
2253 * @arg @ref LL_HRTIM_TIMER_F
2254 * @retval None
2255 */
LL_HRTIM_ResumeUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timers)2256 __STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
2257 {
2258 CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
2259 }
2260
2261 /**
2262 * @brief Force an immediate transfer from the preload to the active register .
2263 * @rmtoll CR2 MSWU LL_HRTIM_ForceUpdate\n
2264 * CR2 TASWU LL_HRTIM_ForceUpdate\n
2265 * CR2 TBSWU LL_HRTIM_ForceUpdate\n
2266 * CR2 TCSWU LL_HRTIM_ForceUpdate\n
2267 * CR2 TDSWU LL_HRTIM_ForceUpdate\n
2268 * CR2 TESWU LL_HRTIM_ForceUpdate\n
2269 * CR2 TFSWU LL_HRTIM_ForceUpdate
2270 * @note Any pending update request is cancelled.
2271 * @param HRTIMx High Resolution Timer instance
2272 * @param Timers This parameter can be a combination of the following values:
2273 * @arg @ref LL_HRTIM_TIMER_MASTER
2274 * @arg @ref LL_HRTIM_TIMER_A
2275 * @arg @ref LL_HRTIM_TIMER_B
2276 * @arg @ref LL_HRTIM_TIMER_C
2277 * @arg @ref LL_HRTIM_TIMER_D
2278 * @arg @ref LL_HRTIM_TIMER_E
2279 * @arg @ref LL_HRTIM_TIMER_F
2280 * @retval None
2281 */
LL_HRTIM_ForceUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timers)2282 __STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
2283 {
2284 SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK));
2285 }
2286
2287 /**
2288 * @brief Reset the HRTIM timer(s) counter.
2289 * @rmtoll CR2 MRST LL_HRTIM_CounterReset\n
2290 * CR2 TARST LL_HRTIM_CounterReset\n
2291 * CR2 TBRST LL_HRTIM_CounterReset\n
2292 * CR2 TCRST LL_HRTIM_CounterReset\n
2293 * CR2 TDRST LL_HRTIM_CounterReset\n
2294 * CR2 TERST LL_HRTIM_CounterReset\n
2295 * CR2 TFRST LL_HRTIM_CounterReset
2296 * @param HRTIMx High Resolution Timer instance
2297 * @param Timers This parameter can be a combination of the following values:
2298 * @arg @ref LL_HRTIM_TIMER_MASTER
2299 * @arg @ref LL_HRTIM_TIMER_A
2300 * @arg @ref LL_HRTIM_TIMER_B
2301 * @arg @ref LL_HRTIM_TIMER_C
2302 * @arg @ref LL_HRTIM_TIMER_D
2303 * @arg @ref LL_HRTIM_TIMER_E
2304 * @arg @ref LL_HRTIM_TIMER_F
2305 * @retval None
2306 */
LL_HRTIM_CounterReset(HRTIM_TypeDef * HRTIMx,uint32_t Timers)2307 __STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
2308 {
2309 SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK));
2310 }
2311
2312 /**
2313 * @brief enable the swap of the Timer Output.
2314 * @note the HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
2315 * and the HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
2316 * @note This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
2317 * @rmtoll CR2 SWPA LL_HRTIM_EnableSwapOutputs\n
2318 * CR2 SWPB LL_HRTIM_EnableSwapOutputs\n
2319 * CR2 SWPC LL_HRTIM_EnableSwapOutputs\n
2320 * CR2 SWPD LL_HRTIM_EnableSwapOutputs\n
2321 * CR2 SWPE LL_HRTIM_EnableSwapOutputs\n
2322 * CR2 SWPF LL_HRTIM_EnableSwapOutputs
2323 * @param HRTIMx High Resolution Timer instance
2324 * @param Timer This parameter can be one of the following values:
2325 * @arg @ref LL_HRTIM_TIMER_A
2326 * @arg @ref LL_HRTIM_TIMER_B
2327 * @arg @ref LL_HRTIM_TIMER_C
2328 * @arg @ref LL_HRTIM_TIMER_D
2329 * @arg @ref LL_HRTIM_TIMER_E
2330 * @arg @ref LL_HRTIM_TIMER_F
2331 * @retval None
2332 */
LL_HRTIM_EnableSwapOutputs(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2333 __STATIC_INLINE void LL_HRTIM_EnableSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2334 {
2335 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
2336
2337 SET_BIT(HRTIMx->sCommonRegs.CR2, (uint32_t)(HRTIM_CR2_SWPA) << iTimer);
2338 }
2339
2340 /**
2341 * @brief disable the swap of the Timer Output.
2342 * @note the HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
2343 * and the HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
2344 * @note This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
2345 * @rmtoll CR2 SWPA LL_HRTIM_DisableSwapOutputs\n
2346 * CR2 SWPB LL_HRTIM_DisableSwapOutputs\n
2347 * CR2 SWPC LL_HRTIM_DisableSwapOutputs\n
2348 * CR2 SWPD LL_HRTIM_DisableSwapOutputs\n
2349 * CR2 SWPE LL_HRTIM_DisableSwapOutputs\n
2350 * CR2 SWPF LL_HRTIM_DisableSwapOutputs
2351 * @param HRTIMx High Resolution Timer instance
2352 * @param Timer This parameter can be one of the following values:
2353 * @arg @ref LL_HRTIM_TIMER_A
2354 * @arg @ref LL_HRTIM_TIMER_B
2355 * @arg @ref LL_HRTIM_TIMER_C
2356 * @arg @ref LL_HRTIM_TIMER_D
2357 * @arg @ref LL_HRTIM_TIMER_E
2358 * @arg @ref LL_HRTIM_TIMER_F
2359 * @retval None
2360 */
LL_HRTIM_DisableSwapOutputs(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2361 __STATIC_INLINE void LL_HRTIM_DisableSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2362 {
2363 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
2364
2365 CLEAR_BIT(HRTIMx->sCommonRegs.CR2, (HRTIM_CR2_SWPA << iTimer));
2366 }
2367
2368 /**
2369 * @brief reports the Timer Outputs swap position.
2370 * @note This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
2371 * @rmtoll CR2 SWPA LL_HRTIM_IsEnabledSwapOutputs\n
2372 * CR2 SWPB LL_HRTIM_IsEnabledSwapOutputs\n
2373 * CR2 SWPC LL_HRTIM_IsEnabledSwapOutputs\n
2374 * CR2 SWPD LL_HRTIM_IsEnabledSwapOutputs\n
2375 * CR2 SWPE LL_HRTIM_IsEnabledSwapOutputs\n
2376 * CR2 SWPF LL_HRTIM_IsEnabledSwapOutputs
2377 * @param HRTIMx High Resolution Timer instance
2378 * @param Timer This parameter can be one of the following values:
2379 * @arg @ref LL_HRTIM_TIMER_A
2380 * @arg @ref LL_HRTIM_TIMER_B
2381 * @arg @ref LL_HRTIM_TIMER_C
2382 * @arg @ref LL_HRTIM_TIMER_D
2383 * @arg @ref LL_HRTIM_TIMER_E
2384 * @arg @ref LL_HRTIM_TIMER_F
2385 * @retval
2386 * 1: HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
2387 * HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
2388 * 0: HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
2389 * HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
2390 */
LL_HRTIM_IsEnabledSwapOutputs(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2391 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2392 {
2393 uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos) & 0x1FU);
2394
2395 return (READ_BIT(HRTIMx->sCommonRegs.CR2, (uint32_t)(HRTIM_CR2_SWPA) << iTimer) >> ((HRTIM_CR2_SWPA_Pos + iTimer)));
2396 }
2397
2398 /**
2399 * @brief Enable the HRTIM timer(s) output(s) .
2400 * @rmtoll OENR TA1OEN LL_HRTIM_EnableOutput\n
2401 * OENR TA2OEN LL_HRTIM_EnableOutput\n
2402 * OENR TB1OEN LL_HRTIM_EnableOutput\n
2403 * OENR TB2OEN LL_HRTIM_EnableOutput\n
2404 * OENR TC1OEN LL_HRTIM_EnableOutput\n
2405 * OENR TC2OEN LL_HRTIM_EnableOutput\n
2406 * OENR TD1OEN LL_HRTIM_EnableOutput\n
2407 * OENR TD2OEN LL_HRTIM_EnableOutput\n
2408 * OENR TE1OEN LL_HRTIM_EnableOutput\n
2409 * OENR TE2OEN LL_HRTIM_EnableOutput\n
2410 * OENR TF1OEN LL_HRTIM_EnableOutput\n
2411 * OENR TF2OEN LL_HRTIM_EnableOutput
2412 * @param HRTIMx High Resolution Timer instance
2413 * @param Outputs This parameter can be a combination of the following values:
2414 * @arg @ref LL_HRTIM_OUTPUT_TA1
2415 * @arg @ref LL_HRTIM_OUTPUT_TA2
2416 * @arg @ref LL_HRTIM_OUTPUT_TB1
2417 * @arg @ref LL_HRTIM_OUTPUT_TB2
2418 * @arg @ref LL_HRTIM_OUTPUT_TC1
2419 * @arg @ref LL_HRTIM_OUTPUT_TC2
2420 * @arg @ref LL_HRTIM_OUTPUT_TD1
2421 * @arg @ref LL_HRTIM_OUTPUT_TD2
2422 * @arg @ref LL_HRTIM_OUTPUT_TE1
2423 * @arg @ref LL_HRTIM_OUTPUT_TE2
2424 * @arg @ref LL_HRTIM_OUTPUT_TF1
2425 * @arg @ref LL_HRTIM_OUTPUT_TF2
2426 * @retval None
2427 */
LL_HRTIM_EnableOutput(HRTIM_TypeDef * HRTIMx,uint32_t Outputs)2428 __STATIC_INLINE void LL_HRTIM_EnableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
2429 {
2430 SET_BIT(HRTIMx->sCommonRegs.OENR, (Outputs & HRTIM_OENR_OEN_MASK));
2431 }
2432
2433 /**
2434 * @brief Disable the HRTIM timer(s) output(s) .
2435 * @rmtoll OENR TA1OEN LL_HRTIM_DisableOutput\n
2436 * OENR TA2OEN LL_HRTIM_DisableOutput\n
2437 * OENR TB1OEN LL_HRTIM_DisableOutput\n
2438 * OENR TB2OEN LL_HRTIM_DisableOutput\n
2439 * OENR TC1OEN LL_HRTIM_DisableOutput\n
2440 * OENR TC2OEN LL_HRTIM_DisableOutput\n
2441 * OENR TD1OEN LL_HRTIM_DisableOutput\n
2442 * OENR TD2OEN LL_HRTIM_DisableOutput\n
2443 * OENR TE1OEN LL_HRTIM_DisableOutput\n
2444 * OENR TE2OEN LL_HRTIM_DisableOutput\n
2445 * OENR TF1OEN LL_HRTIM_DisableOutput\n
2446 * OENR TF2OEN LL_HRTIM_DisableOutput
2447 * @param HRTIMx High Resolution Timer instance
2448 * @param Outputs This parameter can be a combination of the following values:
2449 * @arg @ref LL_HRTIM_OUTPUT_TA1
2450 * @arg @ref LL_HRTIM_OUTPUT_TA2
2451 * @arg @ref LL_HRTIM_OUTPUT_TB1
2452 * @arg @ref LL_HRTIM_OUTPUT_TB2
2453 * @arg @ref LL_HRTIM_OUTPUT_TC1
2454 * @arg @ref LL_HRTIM_OUTPUT_TC2
2455 * @arg @ref LL_HRTIM_OUTPUT_TD1
2456 * @arg @ref LL_HRTIM_OUTPUT_TD2
2457 * @arg @ref LL_HRTIM_OUTPUT_TE1
2458 * @arg @ref LL_HRTIM_OUTPUT_TE2
2459 * @arg @ref LL_HRTIM_OUTPUT_TF1
2460 * @arg @ref LL_HRTIM_OUTPUT_TF2
2461 * @retval None
2462 */
LL_HRTIM_DisableOutput(HRTIM_TypeDef * HRTIMx,uint32_t Outputs)2463 __STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
2464 {
2465 SET_BIT(HRTIMx->sCommonRegs.ODISR, (Outputs & HRTIM_OENR_ODIS_MASK));
2466 }
2467
2468 /**
2469 * @brief Indicates whether the HRTIM timer output is enabled.
2470 * @rmtoll OENR TA1OEN LL_HRTIM_IsEnabledOutput\n
2471 * OENR TA2OEN LL_HRTIM_IsEnabledOutput\n
2472 * OENR TB1OEN LL_HRTIM_IsEnabledOutput\n
2473 * OENR TB2OEN LL_HRTIM_IsEnabledOutput\n
2474 * OENR TC1OEN LL_HRTIM_IsEnabledOutput\n
2475 * OENR TC2OEN LL_HRTIM_IsEnabledOutput\n
2476 * OENR TD1OEN LL_HRTIM_IsEnabledOutput\n
2477 * OENR TD2OEN LL_HRTIM_IsEnabledOutput\n
2478 * OENR TE1OEN LL_HRTIM_IsEnabledOutput\n
2479 * OENR TE2OEN LL_HRTIM_IsEnabledOutput\n
2480 * OENR TF1OEN LL_HRTIM_IsEnabledOutput\n
2481 * OENR TF2OEN LL_HRTIM_IsEnabledOutput
2482 * @param HRTIMx High Resolution Timer instance
2483 * @param Output This parameter can be one of the following values:
2484 * @arg @ref LL_HRTIM_OUTPUT_TA1
2485 * @arg @ref LL_HRTIM_OUTPUT_TA2
2486 * @arg @ref LL_HRTIM_OUTPUT_TB1
2487 * @arg @ref LL_HRTIM_OUTPUT_TB2
2488 * @arg @ref LL_HRTIM_OUTPUT_TC1
2489 * @arg @ref LL_HRTIM_OUTPUT_TC2
2490 * @arg @ref LL_HRTIM_OUTPUT_TD1
2491 * @arg @ref LL_HRTIM_OUTPUT_TD2
2492 * @arg @ref LL_HRTIM_OUTPUT_TE1
2493 * @arg @ref LL_HRTIM_OUTPUT_TE2
2494 * @arg @ref LL_HRTIM_OUTPUT_TF1
2495 * @arg @ref LL_HRTIM_OUTPUT_TF2
2496 * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0).
2497 */
LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef * HRTIMx,uint32_t Output)2498 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
2499 {
2500 return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output) ? 1UL : 0UL);
2501 }
2502
2503 /**
2504 * @brief Indicates whether the HRTIM timer output is disabled.
2505 * @rmtoll ODISR TA1ODIS LL_HRTIM_IsDisabledOutput\n
2506 * ODISR TA2ODIS LL_HRTIM_IsDisabledOutput\n
2507 * ODISR TB1ODIS LL_HRTIM_IsDisabledOutput\n
2508 * ODISR TB2ODIS LL_HRTIM_IsDisabledOutput\n
2509 * ODISR TC1ODIS LL_HRTIM_IsDisabledOutput\n
2510 * ODISR TC2ODIS LL_HRTIM_IsDisabledOutput\n
2511 * ODISR TD1ODIS LL_HRTIM_IsDisabledOutput\n
2512 * ODISR TD2ODIS LL_HRTIM_IsDisabledOutput\n
2513 * ODISR TE1ODIS LL_HRTIM_IsDisabledOutput\n
2514 * ODISR TE2ODIS LL_HRTIM_IsDisabledOutput\n
2515 * ODISR TF1ODIS LL_HRTIM_IsDisabledOutput\n
2516 * ODISR TF2ODIS LL_HRTIM_IsDisabledOutput
2517 * @param HRTIMx High Resolution Timer instance
2518 * @param Output This parameter can be one of the following values:
2519 * @arg @ref LL_HRTIM_OUTPUT_TA1
2520 * @arg @ref LL_HRTIM_OUTPUT_TA2
2521 * @arg @ref LL_HRTIM_OUTPUT_TB1
2522 * @arg @ref LL_HRTIM_OUTPUT_TB2
2523 * @arg @ref LL_HRTIM_OUTPUT_TC1
2524 * @arg @ref LL_HRTIM_OUTPUT_TC2
2525 * @arg @ref LL_HRTIM_OUTPUT_TD1
2526 * @arg @ref LL_HRTIM_OUTPUT_TD2
2527 * @arg @ref LL_HRTIM_OUTPUT_TE1
2528 * @arg @ref LL_HRTIM_OUTPUT_TE2
2529 * @arg @ref LL_HRTIM_OUTPUT_TF1
2530 * @arg @ref LL_HRTIM_OUTPUT_TF2
2531 * @retval State of TxyODS bit in HRTIM_OENR register (1 or 0).
2532 */
LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef * HRTIMx,uint32_t Output)2533 __STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
2534 {
2535 return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == 0U) ? 1UL : 0UL);
2536 }
2537
2538 /**
2539 * @brief Configure an ADC trigger.
2540 * @rmtoll CR1 ADC1USRC LL_HRTIM_ConfigADCTrig\n
2541 * CR1 ADC2USRC LL_HRTIM_ConfigADCTrig\n
2542 * CR1 ADC3USRC LL_HRTIM_ConfigADCTrig\n
2543 * CR1 ADC4USRC LL_HRTIM_ConfigADCTrig\n
2544 * ADC1R ADC1MC1 LL_HRTIM_ConfigADCTrig\n
2545 * ADC1R ADC1MC2 LL_HRTIM_ConfigADCTrig\n
2546 * ADC1R ADC1MC3 LL_HRTIM_ConfigADCTrig\n
2547 * ADC1R ADC1MC4 LL_HRTIM_ConfigADCTrig\n
2548 * ADC1R ADC1MPER LL_HRTIM_ConfigADCTrig\n
2549 * ADC1R ADC1EEV1 LL_HRTIM_ConfigADCTrig\n
2550 * ADC1R ADC1EEV2 LL_HRTIM_ConfigADCTrig\n
2551 * ADC1R ADC1EEV3 LL_HRTIM_ConfigADCTrig\n
2552 * ADC1R ADC1EEV4 LL_HRTIM_ConfigADCTrig\n
2553 * ADC1R ADC1EEV5 LL_HRTIM_ConfigADCTrig\n
2554 * ADC1R ADC1TFC2 LL_HRTIM_ConfigADCTrig\n
2555 * ADC1R ADC1TAC3 LL_HRTIM_ConfigADCTrig\n
2556 * ADC1R ADC1TAC4 LL_HRTIM_ConfigADCTrig\n
2557 * ADC1R ADC1TAPER LL_HRTIM_ConfigADCTrig\n
2558 * ADC1R ADC1TARST LL_HRTIM_ConfigADCTrig\n
2559 * ADC1R ADC1TFC3 LL_HRTIM_ConfigADCTrig\n
2560 * ADC1R ADC1TBC3 LL_HRTIM_ConfigADCTrig\n
2561 * ADC1R ADC1TBC4 LL_HRTIM_ConfigADCTrig\n
2562 * ADC1R ADC1TBPER LL_HRTIM_ConfigADCTrig\n
2563 * ADC1R ADC1TBRST LL_HRTIM_ConfigADCTrig\n
2564 * ADC1R ADC1TFC4 LL_HRTIM_ConfigADCTrig\n
2565 * ADC1R ADC1TCC3 LL_HRTIM_ConfigADCTrig\n
2566 * ADC1R ADC1TCC4 LL_HRTIM_ConfigADCTrig\n
2567 * ADC1R ADC1TCPER LL_HRTIM_ConfigADCTrig\n
2568 * ADC1R ADC1TFPER LL_HRTIM_ConfigADCTrig\n
2569 * ADC1R ADC1TDC3 LL_HRTIM_ConfigADCTrig\n
2570 * ADC1R ADC1TDC4 LL_HRTIM_ConfigADCTrig\n
2571 * ADC1R ADC1TDPER LL_HRTIM_ConfigADCTrig\n
2572 * ADC1R ADC1TFRST LL_HRTIM_ConfigADCTrig\n
2573 * ADC1R ADC1TEC3 LL_HRTIM_ConfigADCTrig\n
2574 * ADC1R ADC1TEC4 LL_HRTIM_ConfigADCTrig\n
2575 * ADC1R ADC1TEPER LL_HRTIM_ConfigADCTrig\n
2576 * ADC2R ADC2MC1 LL_HRTIM_ConfigADCTrig\n
2577 * ADC2R ADC2MC2 LL_HRTIM_ConfigADCTrig\n
2578 * ADC2R ADC2MC3 LL_HRTIM_ConfigADCTrig\n
2579 * ADC2R ADC2MC4 LL_HRTIM_ConfigADCTrig\n
2580 * ADC2R ADC2MPER LL_HRTIM_ConfigADCTrig\n
2581 * ADC2R ADC2EEV6 LL_HRTIM_ConfigADCTrig\n
2582 * ADC2R ADC2EEV7 LL_HRTIM_ConfigADCTrig\n
2583 * ADC2R ADC2EEV8 LL_HRTIM_ConfigADCTrig\n
2584 * ADC2R ADC2EEV9 LL_HRTIM_ConfigADCTrig\n
2585 * ADC2R ADC2EEV10 LL_HRTIM_ConfigADCTrig\n
2586 * ADC2R ADC2TAC2 LL_HRTIM_ConfigADCTrig\n
2587 * ADC2R ADC2TFC2 LL_HRTIM_ConfigADCTrig\n
2588 * ADC2R ADC2TAC4 LL_HRTIM_ConfigADCTrig\n
2589 * ADC2R ADC2TAPER LL_HRTIM_ConfigADCTrig\n
2590 * ADC2R ADC2TBC2 LL_HRTIM_ConfigADCTrig\n
2591 * ADC2R ADC2TFC3 LL_HRTIM_ConfigADCTrig\n
2592 * ADC2R ADC2TBC4 LL_HRTIM_ConfigADCTrig\n
2593 * ADC2R ADC2TBPER LL_HRTIM_ConfigADCTrig\n
2594 * ADC2R ADC2TCC2 LL_HRTIM_ConfigADCTrig\n
2595 * ADC2R ADC2TFC4 LL_HRTIM_ConfigADCTrig\n
2596 * ADC2R ADC2TCC4 LL_HRTIM_ConfigADCTrig\n
2597 * ADC2R ADC2TCPER LL_HRTIM_ConfigADCTrig\n
2598 * ADC2R ADC2TCRST LL_HRTIM_ConfigADCTrig\n
2599 * ADC2R ADC2TDC2 LL_HRTIM_ConfigADCTrig\n
2600 * ADC2R ADC2TFPER LL_HRTIM_ConfigADCTrig\n
2601 * ADC2R ADC2TDC4 LL_HRTIM_ConfigADCTrig\n
2602 * ADC2R ADC2TDPER LL_HRTIM_ConfigADCTrig\n
2603 * ADC2R ADC2TDRST LL_HRTIM_ConfigADCTrig\n
2604 * ADC2R ADC2TEC2 LL_HRTIM_ConfigADCTrig\n
2605 * ADC2R ADC2TEC3 LL_HRTIM_ConfigADCTrig\n
2606 * ADC2R ADC2TEC4 LL_HRTIM_ConfigADCTrig\n
2607 * ADC2R ADC2TERST LL_HRTIM_ConfigADCTrig\n
2608 * ADC3R ADC3MC1 LL_HRTIM_ConfigADCTrig\n
2609 * ADC3R ADC3MC2 LL_HRTIM_ConfigADCTrig\n
2610 * ADC3R ADC3MC3 LL_HRTIM_ConfigADCTrig\n
2611 * ADC3R ADC3MC4 LL_HRTIM_ConfigADCTrig\n
2612 * ADC3R ADC3MPER LL_HRTIM_ConfigADCTrig\n
2613 * ADC3R ADC3EEV1 LL_HRTIM_ConfigADCTrig\n
2614 * ADC3R ADC3EEV2 LL_HRTIM_ConfigADCTrig\n
2615 * ADC3R ADC3EEV3 LL_HRTIM_ConfigADCTrig\n
2616 * ADC3R ADC3EEV4 LL_HRTIM_ConfigADCTrig\n
2617 * ADC3R ADC3EEV5 LL_HRTIM_ConfigADCTrig\n
2618 * ADC3R ADC3TFC2 LL_HRTIM_ConfigADCTrig\n
2619 * ADC3R ADC3TAC3 LL_HRTIM_ConfigADCTrig\n
2620 * ADC3R ADC3TAC4 LL_HRTIM_ConfigADCTrig\n
2621 * ADC3R ADC3TAPER LL_HRTIM_ConfigADCTrig\n
2622 * ADC3R ADC3TARST LL_HRTIM_ConfigADCTrig\n
2623 * ADC3R ADC3TFC3 LL_HRTIM_ConfigADCTrig\n
2624 * ADC3R ADC3TBC3 LL_HRTIM_ConfigADCTrig\n
2625 * ADC3R ADC3TBC4 LL_HRTIM_ConfigADCTrig\n
2626 * ADC3R ADC3TBPER LL_HRTIM_ConfigADCTrig\n
2627 * ADC3R ADC3TBRST LL_HRTIM_ConfigADCTrig\n
2628 * ADC3R ADC3TFC4 LL_HRTIM_ConfigADCTrig\n
2629 * ADC3R ADC3TCC3 LL_HRTIM_ConfigADCTrig\n
2630 * ADC3R ADC3TCC4 LL_HRTIM_ConfigADCTrig\n
2631 * ADC3R ADC3TCPER LL_HRTIM_ConfigADCTrig\n
2632 * ADC3R ADC3TFPER LL_HRTIM_ConfigADCTrig\n
2633 * ADC3R ADC3TDC3 LL_HRTIM_ConfigADCTrig\n
2634 * ADC3R ADC3TDC4 LL_HRTIM_ConfigADCTrig\n
2635 * ADC3R ADC3TDPER LL_HRTIM_ConfigADCTrig\n
2636 * ADC3R ADC3TFRST LL_HRTIM_ConfigADCTrig\n
2637 * ADC3R ADC3TEC3 LL_HRTIM_ConfigADCTrig\n
2638 * ADC3R ADC3TEC4 LL_HRTIM_ConfigADCTrig\n
2639 * ADC3R ADC3TEPER LL_HRTIM_ConfigADCTrig\n
2640 * ADC4R ADC4MC1 LL_HRTIM_ConfigADCTrig\n
2641 * ADC4R ADC4MC2 LL_HRTIM_ConfigADCTrig\n
2642 * ADC4R ADC4MC3 LL_HRTIM_ConfigADCTrig\n
2643 * ADC4R ADC4MC4 LL_HRTIM_ConfigADCTrig\n
2644 * ADC4R ADC4MPER LL_HRTIM_ConfigADCTrig\n
2645 * ADC4R ADC4EEV6 LL_HRTIM_ConfigADCTrig\n
2646 * ADC4R ADC4EEV7 LL_HRTIM_ConfigADCTrig\n
2647 * ADC4R ADC4EEV8 LL_HRTIM_ConfigADCTrig\n
2648 * ADC4R ADC4EEV9 LL_HRTIM_ConfigADCTrig\n
2649 * ADC4R ADC4EEV10 LL_HRTIM_ConfigADCTrig\n
2650 * ADC4R ADC4TAC2 LL_HRTIM_ConfigADCTrig\n
2651 * ADC4R ADC4TFC2 LL_HRTIM_ConfigADCTrig\n
2652 * ADC4R ADC4TAC4 LL_HRTIM_ConfigADCTrig\n
2653 * ADC4R ADC4TAPER LL_HRTIM_ConfigADCTrig\n
2654 * ADC4R ADC4TBC2 LL_HRTIM_ConfigADCTrig\n
2655 * ADC4R ADC4TFC3 LL_HRTIM_ConfigADCTrig\n
2656 * ADC4R ADC4TBC4 LL_HRTIM_ConfigADCTrig\n
2657 * ADC4R ADC4TBPER LL_HRTIM_ConfigADCTrig\n
2658 * ADC4R ADC4TCC2 LL_HRTIM_ConfigADCTrig\n
2659 * ADC4R ADC4TFC4 LL_HRTIM_ConfigADCTrig\n
2660 * ADC4R ADC4TCC4 LL_HRTIM_ConfigADCTrig\n
2661 * ADC4R ADC4TCPER LL_HRTIM_ConfigADCTrig\n
2662 * ADC4R ADC4TCRST LL_HRTIM_ConfigADCTrig\n
2663 * ADC4R ADC4TDC2 LL_HRTIM_ConfigADCTrig\n
2664 * ADC4R ADC4TFPER LL_HRTIM_ConfigADCTrig\n
2665 * ADC4R ADC4TDC4 LL_HRTIM_ConfigADCTrig\n
2666 * ADC4R ADC4TDPER LL_HRTIM_ConfigADCTrig\n
2667 * ADC4R ADC4TDRST LL_HRTIM_ConfigADCTrig\n
2668 * ADC4R ADC4TEC2 LL_HRTIM_ConfigADCTrig\n
2669 * ADC4R ADC4TEC3 LL_HRTIM_ConfigADCTrig\n
2670 * ADC4R ADC4TEC4 LL_HRTIM_ConfigADCTrig\n
2671 * ADC4R ADC4TERST LL_HRTIM_ConfigADCTrig
2672 * @param HRTIMx High Resolution Timer instance
2673 * @param ADCTrig This parameter can be one of the following values:
2674 * @arg @ref LL_HRTIM_ADCTRIG_1
2675 * @arg @ref LL_HRTIM_ADCTRIG_2
2676 * @arg @ref LL_HRTIM_ADCTRIG_3
2677 * @arg @ref LL_HRTIM_ADCTRIG_4
2678 * @param Update This parameter can be one of the following values:
2679 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
2680 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
2681 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
2682 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
2683 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
2684 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
2685 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
2686 * @param Src This parameter can be a combination of the following values:
2687 *
2688 * For ADC trigger 1 and ADC trigger 3:
2689 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
2690 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
2691 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
2692 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
2693 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
2694 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
2695 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
2696 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
2697 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
2698 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
2699 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
2700 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
2701 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
2702 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
2703 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
2704 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
2705 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
2706 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
2707 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
2708 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
2709 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
2710 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
2711 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
2712 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
2713 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
2714 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
2715 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
2716 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
2717 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
2718 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
2719 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
2720 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
2721 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
2722 *
2723 * For ADC trigger 2 and ADC trigger 4:
2724 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
2725 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
2726 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
2727 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
2728 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
2729 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
2730 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
2731 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
2732 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
2733 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
2734 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
2735 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
2736 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
2737 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
2738 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
2739 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
2740 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
2741 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
2742 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
2743 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
2744 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
2745 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
2746 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
2747 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
2748 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
2749 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
2750 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
2751 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
2752 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
2753 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
2754 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
2755 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
2756 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
2757 *
2758 * For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
2759 * can be one of the following values:
2760 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
2761 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
2762 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
2763 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
2764 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
2765 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
2766 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
2767 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
2768 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
2769 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
2770 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
2771 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
2772 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
2773 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
2774 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
2775 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
2776 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
2777 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
2778 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
2779 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
2780 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
2781 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
2782 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
2783 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
2784 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
2785 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
2786 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
2787 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
2788 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
2789 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
2790 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
2791 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
2792 *
2793 * For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
2794 * can be one of the following values:
2795 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
2796 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
2797 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
2798 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
2799 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
2800 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
2801 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
2802 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
2803 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
2804 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
2805 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
2806 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
2807 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
2808 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
2809 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
2810 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
2811 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
2812 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
2813 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
2814 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
2815 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
2816 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
2817 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
2818 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
2819 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
2820 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
2821 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
2822 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
2823 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
2824 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
2825 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
2826 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
2827 * @retval None
2828 */
LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig,uint32_t Update,uint32_t Src)2829 __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src)
2830 {
2831 __IO uint32_t *padcur = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
2832 REG_OFFSET_TAB_ADCUR[ADCTrig]));
2833 __IO uint32_t *padcer = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
2834 REG_OFFSET_TAB_ADCER[ADCTrig]));
2835 MODIFY_REG(*padcur, REG_MASK_TAB_ADCUR[ADCTrig], (Update << REG_SHIFT_TAB_ADCUR[ADCTrig]));
2836 MODIFY_REG(*padcer, REG_MASK_TAB_ADCER[ADCTrig], (Src << REG_SHIFT_TAB_ADCER[ADCTrig]));
2837 }
2838
2839 /**
2840 * @brief Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register.
2841 * @rmtoll CR1 ADC1USRC LL_HRTIM_SetADCTrigUpdate\n
2842 * CR1 ADC2USRC LL_HRTIM_SetADCTrigUpdate\n
2843 * CR1 ADC3USRC LL_HRTIM_SetADCTrigUpdate\n
2844 * CR1 ADC4USRC LL_HRTIM_SetADCTrigUpdate\n
2845 * ADCUR ADC5USRC LL_HRTIM_SetADCTrigUpdate\n
2846 * ADCUR ADC6USRC LL_HRTIM_SetADCTrigUpdate\n
2847 * ADCUR ADC7USRC LL_HRTIM_SetADCTrigUpdate\n
2848 * ADCUR ADC8USRC LL_HRTIM_SetADCTrigUpdate\n
2849 * ADCUR ADC9USRC LL_HRTIM_SetADCTrigUpdate\n
2850 * ADCUR ADC10USRC LL_HRTIM_SetADCTrigUpdate
2851 * @note When the preload is disabled in the source timer, the HRTIM_ADCxR
2852 * registers are not preloaded either: a write access will result in an
2853 * immediate update of the trigger source.
2854 * @param HRTIMx High Resolution Timer instance
2855 * @param ADCTrig This parameter can be one of the following values:
2856 * @arg @ref LL_HRTIM_ADCTRIG_1
2857 * @arg @ref LL_HRTIM_ADCTRIG_2
2858 * @arg @ref LL_HRTIM_ADCTRIG_3
2859 * @arg @ref LL_HRTIM_ADCTRIG_4
2860 * @arg @ref LL_HRTIM_ADCTRIG_5
2861 * @arg @ref LL_HRTIM_ADCTRIG_6
2862 * @arg @ref LL_HRTIM_ADCTRIG_7
2863 * @arg @ref LL_HRTIM_ADCTRIG_8
2864 * @arg @ref LL_HRTIM_ADCTRIG_9
2865 * @arg @ref LL_HRTIM_ADCTRIG_10
2866 * @param Update This parameter can be one of the following values:
2867 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
2868 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
2869 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
2870 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
2871 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
2872 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
2873 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
2874 * @retval None
2875 */
LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig,uint32_t Update)2876 __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update)
2877 {
2878 __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
2879 REG_OFFSET_TAB_ADCUR[ADCTrig]));
2880 MODIFY_REG(*preg, REG_MASK_TAB_ADCUR[ADCTrig], (Update << REG_SHIFT_TAB_ADCUR[ADCTrig]));
2881 }
2882
2883 /**
2884 * @brief Get the source timer triggering the update of the HRTIM_ADCxR register.
2885 * @rmtoll CR1 ADC1USRC LL_HRTIM_GetADCTrigUpdate\n
2886 * CR1 ADC2USRC LL_HRTIM_GetADCTrigUpdate\n
2887 * CR1 ADC3USRC LL_HRTIM_GetADCTrigUpdate\n
2888 * CR1 ADC4USRC LL_HRTIM_GetADCTrigUpdate\n
2889 * ADCUR ADC5USRC LL_HRTIM_GetADCTrigUpdate\n
2890 * ADCUR ADC6USRC LL_HRTIM_GetADCTrigUpdate\n
2891 * ADCUR ADC7USRC LL_HRTIM_GetADCTrigUpdate\n
2892 * ADCUR ADC8USRC LL_HRTIM_GetADCTrigUpdate\n
2893 * ADCUR ADC9USRC LL_HRTIM_GetADCTrigUpdate\n
2894 * ADCUR ADC10USRC LL_HRTIM_GetADCTrigUpdate
2895 * @param HRTIMx High Resolution Timer instance
2896 * @param ADCTrig This parameter can be one of the following values:
2897 * @arg @ref LL_HRTIM_ADCTRIG_1
2898 * @arg @ref LL_HRTIM_ADCTRIG_2
2899 * @arg @ref LL_HRTIM_ADCTRIG_3
2900 * @arg @ref LL_HRTIM_ADCTRIG_4
2901 * @arg @ref LL_HRTIM_ADCTRIG_5
2902 * @arg @ref LL_HRTIM_ADCTRIG_6
2903 * @arg @ref LL_HRTIM_ADCTRIG_7
2904 * @arg @ref LL_HRTIM_ADCTRIG_8
2905 * @arg @ref LL_HRTIM_ADCTRIG_9
2906 * @arg @ref LL_HRTIM_ADCTRIG_10
2907 * @retval Update Returned value can be one of the following values:
2908 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
2909 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
2910 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
2911 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
2912 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
2913 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
2914 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
2915 */
LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig)2916 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
2917 {
2918 const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
2919 REG_OFFSET_TAB_ADCUR[ADCTrig]));
2920 return (READ_BIT(*preg, (REG_MASK_TAB_ADCUR[ADCTrig])) >> REG_SHIFT_TAB_ADCUR[ADCTrig]);
2921 }
2922
2923 /**
2924 * @brief Specify which events (timer events and/or external events) are used as triggers for ADC conversion.
2925 * @rmtoll ADC1R ADC1MC1 LL_HRTIM_SetADCTrigSrc\n
2926 * ADC1R ADC1MC2 LL_HRTIM_SetADCTrigSrc\n
2927 * ADC1R ADC1MC3 LL_HRTIM_SetADCTrigSrc\n
2928 * ADC1R ADC1MC4 LL_HRTIM_SetADCTrigSrc\n
2929 * ADC1R ADC1MPER LL_HRTIM_SetADCTrigSrc\n
2930 * ADC1R ADC1EEV1 LL_HRTIM_SetADCTrigSrc\n
2931 * ADC1R ADC1EEV2 LL_HRTIM_SetADCTrigSrc\n
2932 * ADC1R ADC1EEV3 LL_HRTIM_SetADCTrigSrc\n
2933 * ADC1R ADC1EEV4 LL_HRTIM_SetADCTrigSrc\n
2934 * ADC1R ADC1EEV5 LL_HRTIM_SetADCTrigSrc\n
2935 * ADC1R ADC1TFC2 LL_HRTIM_SetADCTrigSrc\n
2936 * ADC1R ADC1TAC3 LL_HRTIM_SetADCTrigSrc\n
2937 * ADC1R ADC1TAC4 LL_HRTIM_SetADCTrigSrc\n
2938 * ADC1R ADC1TAPER LL_HRTIM_SetADCTrigSrc\n
2939 * ADC1R ADC1TARST LL_HRTIM_SetADCTrigSrc\n
2940 * ADC1R ADC1TFC3 LL_HRTIM_SetADCTrigSrc\n
2941 * ADC1R ADC1TBC3 LL_HRTIM_SetADCTrigSrc\n
2942 * ADC1R ADC1TBC4 LL_HRTIM_SetADCTrigSrc\n
2943 * ADC1R ADC1TBPER LL_HRTIM_SetADCTrigSrc\n
2944 * ADC1R ADC1TBRST LL_HRTIM_SetADCTrigSrc\n
2945 * ADC1R ADC1TFC4 LL_HRTIM_SetADCTrigSrc\n
2946 * ADC1R ADC1TCC3 LL_HRTIM_SetADCTrigSrc\n
2947 * ADC1R ADC1TCC4 LL_HRTIM_SetADCTrigSrc\n
2948 * ADC1R ADC1TCPER LL_HRTIM_SetADCTrigSrc\n
2949 * ADC1R ADC1TFPER LL_HRTIM_SetADCTrigSrc\n
2950 * ADC1R ADC1TDC3 LL_HRTIM_SetADCTrigSrc\n
2951 * ADC1R ADC1TDC4 LL_HRTIM_SetADCTrigSrc\n
2952 * ADC1R ADC1TDPER LL_HRTIM_SetADCTrigSrc\n
2953 * ADC1R ADC1TFRST LL_HRTIM_SetADCTrigSrc\n
2954 * ADC1R ADC1TEC3 LL_HRTIM_SetADCTrigSrc\n
2955 * ADC1R ADC1TEC4 LL_HRTIM_SetADCTrigSrc\n
2956 * ADC1R ADC1TEPER LL_HRTIM_SetADCTrigSrc\n
2957 * ADC2R ADC2MC1 LL_HRTIM_SetADCTrigSrc\n
2958 * ADC2R ADC2MC2 LL_HRTIM_SetADCTrigSrc\n
2959 * ADC2R ADC2MC3 LL_HRTIM_SetADCTrigSrc\n
2960 * ADC2R ADC2MC4 LL_HRTIM_SetADCTrigSrc\n
2961 * ADC2R ADC2MPER LL_HRTIM_SetADCTrigSrc\n
2962 * ADC2R ADC2EEV6 LL_HRTIM_SetADCTrigSrc\n
2963 * ADC2R ADC2EEV7 LL_HRTIM_SetADCTrigSrc\n
2964 * ADC2R ADC2EEV8 LL_HRTIM_SetADCTrigSrc\n
2965 * ADC2R ADC2EEV9 LL_HRTIM_SetADCTrigSrc\n
2966 * ADC2R ADC2EEV10 LL_HRTIM_SetADCTrigSrc\n
2967 * ADC2R ADC2TAC2 LL_HRTIM_SetADCTrigSrc\n
2968 * ADC2R ADC2TFC2 LL_HRTIM_SetADCTrigSrc\n
2969 * ADC2R ADC2TAC4 LL_HRTIM_SetADCTrigSrc\n
2970 * ADC2R ADC2TAPER LL_HRTIM_SetADCTrigSrc\n
2971 * ADC2R ADC2TBC2 LL_HRTIM_SetADCTrigSrc\n
2972 * ADC2R ADC2TFC3 LL_HRTIM_SetADCTrigSrc\n
2973 * ADC2R ADC2TBC4 LL_HRTIM_SetADCTrigSrc\n
2974 * ADC2R ADC2TBPER LL_HRTIM_SetADCTrigSrc\n
2975 * ADC2R ADC2TCC2 LL_HRTIM_SetADCTrigSrc\n
2976 * ADC2R ADC2TFC4 LL_HRTIM_SetADCTrigSrc\n
2977 * ADC2R ADC2TCC4 LL_HRTIM_SetADCTrigSrc\n
2978 * ADC2R ADC2TCPER LL_HRTIM_SetADCTrigSrc\n
2979 * ADC2R ADC2TCRST LL_HRTIM_SetADCTrigSrc\n
2980 * ADC2R ADC2TDC2 LL_HRTIM_SetADCTrigSrc\n
2981 * ADC2R ADC2TFPER LL_HRTIM_SetADCTrigSrc\n
2982 * ADC2R ADC2TDC4 LL_HRTIM_SetADCTrigSrc\n
2983 * ADC2R ADC2TDPER LL_HRTIM_SetADCTrigSrc\n
2984 * ADC2R ADC2TDRST LL_HRTIM_SetADCTrigSrc\n
2985 * ADC2R ADC2TEC2 LL_HRTIM_SetADCTrigSrc\n
2986 * ADC2R ADC2TEC3 LL_HRTIM_SetADCTrigSrc\n
2987 * ADC2R ADC2TEC4 LL_HRTIM_SetADCTrigSrc\n
2988 * ADC2R ADC2TERST LL_HRTIM_SetADCTrigSrc\n
2989 * ADC3R ADC3MC1 LL_HRTIM_SetADCTrigSrc\n
2990 * ADC3R ADC3MC2 LL_HRTIM_SetADCTrigSrc\n
2991 * ADC3R ADC3MC3 LL_HRTIM_SetADCTrigSrc\n
2992 * ADC3R ADC3MC4 LL_HRTIM_SetADCTrigSrc\n
2993 * ADC3R ADC3MPER LL_HRTIM_SetADCTrigSrc\n
2994 * ADC3R ADC3EEV1 LL_HRTIM_SetADCTrigSrc\n
2995 * ADC3R ADC3EEV2 LL_HRTIM_SetADCTrigSrc\n
2996 * ADC3R ADC3EEV3 LL_HRTIM_SetADCTrigSrc\n
2997 * ADC3R ADC3EEV4 LL_HRTIM_SetADCTrigSrc\n
2998 * ADC3R ADC3EEV5 LL_HRTIM_SetADCTrigSrc\n
2999 * ADC3R ADC3TFC2 LL_HRTIM_SetADCTrigSrc\n
3000 * ADC3R ADC3TAC3 LL_HRTIM_SetADCTrigSrc\n
3001 * ADC3R ADC3TAC4 LL_HRTIM_SetADCTrigSrc\n
3002 * ADC3R ADC3TAPER LL_HRTIM_SetADCTrigSrc\n
3003 * ADC3R ADC3TARST LL_HRTIM_SetADCTrigSrc\n
3004 * ADC3R ADC3TFC3 LL_HRTIM_SetADCTrigSrc\n
3005 * ADC3R ADC3TBC3 LL_HRTIM_SetADCTrigSrc\n
3006 * ADC3R ADC3TBC4 LL_HRTIM_SetADCTrigSrc\n
3007 * ADC3R ADC3TBPER LL_HRTIM_SetADCTrigSrc\n
3008 * ADC3R ADC3TBRST LL_HRTIM_SetADCTrigSrc\n
3009 * ADC3R ADC3TFC4 LL_HRTIM_SetADCTrigSrc\n
3010 * ADC3R ADC3TCC3 LL_HRTIM_SetADCTrigSrc\n
3011 * ADC3R ADC3TCC4 LL_HRTIM_SetADCTrigSrc\n
3012 * ADC3R ADC3TCPER LL_HRTIM_SetADCTrigSrc\n
3013 * ADC3R ADC3TFPER LL_HRTIM_SetADCTrigSrc\n
3014 * ADC3R ADC3TDC3 LL_HRTIM_SetADCTrigSrc\n
3015 * ADC3R ADC3TDC4 LL_HRTIM_SetADCTrigSrc\n
3016 * ADC3R ADC3TDPER LL_HRTIM_SetADCTrigSrc\n
3017 * ADC3R ADC3TFRST LL_HRTIM_SetADCTrigSrc\n
3018 * ADC3R ADC3TEC3 LL_HRTIM_SetADCTrigSrc\n
3019 * ADC3R ADC3TEC4 LL_HRTIM_SetADCTrigSrc\n
3020 * ADC3R ADC3TEPER LL_HRTIM_SetADCTrigSrc\n
3021 * ADC4R ADC4MC1 LL_HRTIM_SetADCTrigSrc\n
3022 * ADC4R ADC4MC2 LL_HRTIM_SetADCTrigSrc\n
3023 * ADC4R ADC4MC3 LL_HRTIM_SetADCTrigSrc\n
3024 * ADC4R ADC4MC4 LL_HRTIM_SetADCTrigSrc\n
3025 * ADC4R ADC4MPER LL_HRTIM_SetADCTrigSrc\n
3026 * ADC4R ADC4EEV6 LL_HRTIM_SetADCTrigSrc\n
3027 * ADC4R ADC4EEV7 LL_HRTIM_SetADCTrigSrc\n
3028 * ADC4R ADC4EEV8 LL_HRTIM_SetADCTrigSrc\n
3029 * ADC4R ADC4EEV9 LL_HRTIM_SetADCTrigSrc\n
3030 * ADC4R ADC4EEV10 LL_HRTIM_SetADCTrigSrc\n
3031 * ADC4R ADC4TAC2 LL_HRTIM_SetADCTrigSrc\n
3032 * ADC4R ADC4TFC2 LL_HRTIM_SetADCTrigSrc\n
3033 * ADC4R ADC4TAC4 LL_HRTIM_SetADCTrigSrc\n
3034 * ADC4R ADC4TAPER LL_HRTIM_SetADCTrigSrc\n
3035 * ADC4R ADC4TBC2 LL_HRTIM_SetADCTrigSrc\n
3036 * ADC4R ADC4TFC3 LL_HRTIM_SetADCTrigSrc\n
3037 * ADC4R ADC4TBC4 LL_HRTIM_SetADCTrigSrc\n
3038 * ADC4R ADC4TBPER LL_HRTIM_SetADCTrigSrc\n
3039 * ADC4R ADC4TCC2 LL_HRTIM_SetADCTrigSrc\n
3040 * ADC4R ADC4TFC4 LL_HRTIM_SetADCTrigSrc\n
3041 * ADC4R ADC4TCC4 LL_HRTIM_SetADCTrigSrc\n
3042 * ADC4R ADC4TCPER LL_HRTIM_SetADCTrigSrc\n
3043 * ADC4R ADC4TCRST LL_HRTIM_SetADCTrigSrc\n
3044 * ADC4R ADC4TDC2 LL_HRTIM_SetADCTrigSrc\n
3045 * ADC4R ADC4TFPER LL_HRTIM_SetADCTrigSrc\n
3046 * ADC4R ADC4TDC4 LL_HRTIM_SetADCTrigSrc\n
3047 * ADC4R ADC4TDPER LL_HRTIM_SetADCTrigSrc\n
3048 * ADC4R ADC4TDRST LL_HRTIM_SetADCTrigSrc\n
3049 * ADC4R ADC4TEC2 LL_HRTIM_SetADCTrigSrc\n
3050 * ADC4R ADC4TEC3 LL_HRTIM_SetADCTrigSrc\n
3051 * ADC4R ADC4TEC4 LL_HRTIM_SetADCTrigSrc\n
3052 * ADC4R ADC4TERST LL_HRTIM_SetADCTrigSrc\n
3053 * ADCER ADC5TRG LL_HRTIM_SetADCTrigSrc\n
3054 * ADCER ADC6TRG LL_HRTIM_SetADCTrigSrc\n
3055 * ADCER ADC7TRG LL_HRTIM_SetADCTrigSrc\n
3056 * ADCER ADC8TRG LL_HRTIM_SetADCTrigSrc\n
3057 * ADCER ADC9TRG LL_HRTIM_SetADCTrigSrc\n
3058 * ADCER ADC10TRG LL_HRTIM_SetADCTrigSrc
3059 * @param HRTIMx High Resolution Timer instance
3060 * @param ADCTrig This parameter can be one of the following values:
3061 * @arg @ref LL_HRTIM_ADCTRIG_1
3062 * @arg @ref LL_HRTIM_ADCTRIG_2
3063 * @arg @ref LL_HRTIM_ADCTRIG_3
3064 * @arg @ref LL_HRTIM_ADCTRIG_4
3065 * @arg @ref LL_HRTIM_ADCTRIG_5
3066 * @arg @ref LL_HRTIM_ADCTRIG_6
3067 * @arg @ref LL_HRTIM_ADCTRIG_7
3068 * @arg @ref LL_HRTIM_ADCTRIG_8
3069 * @arg @ref LL_HRTIM_ADCTRIG_9
3070 * @arg @ref LL_HRTIM_ADCTRIG_10
3071 * @param Src
3072 * For ADC trigger 1 and ADC trigger 3 this parameter can be a
3073 * combination of the following values:
3074 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
3075 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
3076 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
3077 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
3078 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
3079 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
3080 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
3081 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
3082 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
3083 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
3084 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
3085 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
3086 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
3087 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
3088 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
3089 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
3090 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
3091 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
3092 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
3093 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
3094 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
3095 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
3096 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
3097 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
3098 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
3099 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
3100 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
3101 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
3102 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
3103 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
3104 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
3105 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
3106 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
3107 *
3108 * For ADC trigger 2 and ADC trigger 4 this parameter can be a
3109 * combination of the following values:
3110 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
3111 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
3112 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
3113 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
3114 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
3115 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
3116 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
3117 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
3118 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
3119 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
3120 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
3121 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
3122 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
3123 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
3124 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
3125 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
3126 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
3127 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
3128 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
3129 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
3130 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
3131 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
3132 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
3133 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
3134 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
3135 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
3136 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
3137 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
3138 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
3139 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
3140 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
3141 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
3142 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
3143 *
3144 * For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
3145 * can be one of the following values:
3146 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
3147 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
3148 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
3149 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
3150 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
3151 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
3152 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
3153 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
3154 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
3155 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
3156 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
3157 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
3158 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
3159 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
3160 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
3161 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
3162 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
3163 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
3164 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
3165 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
3166 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
3167 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
3168 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
3169 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
3170 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
3171 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
3172 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
3173 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
3174 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
3175 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
3176 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
3177 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
3178 *
3179 * For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
3180 * can be one of the following values:
3181 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
3182 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
3183 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
3184 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
3185 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
3186 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
3187 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
3188 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
3189 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
3190 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
3191 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
3192 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
3193 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
3194 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
3195 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
3196 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
3197 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
3198 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
3199 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
3200 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
3201 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
3202 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
3203 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
3204 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
3205 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
3206 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
3207 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
3208 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
3209 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
3210 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
3211 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
3212 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
3213 * @retval None
3214 */
LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig,uint32_t Src)3215 __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src)
3216 {
3217 __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
3218 REG_OFFSET_TAB_ADCER[ADCTrig]));
3219 MODIFY_REG(*preg, REG_MASK_TAB_ADCER[ADCTrig], (Src << REG_SHIFT_TAB_ADCER[ADCTrig]));
3220 }
3221
3222 /**
3223 * @brief Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion.
3224 * @rmtoll ADC1R ADC1MC1 LL_HRTIM_GetADCTrigSrc\n
3225 * ADC1R ADC1MC2 LL_HRTIM_GetADCTrigSrc\n
3226 * ADC1R ADC1MC3 LL_HRTIM_GetADCTrigSrc\n
3227 * ADC1R ADC1MC4 LL_HRTIM_GetADCTrigSrc\n
3228 * ADC1R ADC1MPER LL_HRTIM_GetADCTrigSrc\n
3229 * ADC1R ADC1EEV1 LL_HRTIM_GetADCTrigSrc\n
3230 * ADC1R ADC1EEV2 LL_HRTIM_GetADCTrigSrc\n
3231 * ADC1R ADC1EEV3 LL_HRTIM_GetADCTrigSrc\n
3232 * ADC1R ADC1EEV4 LL_HRTIM_GetADCTrigSrc\n
3233 * ADC1R ADC1EEV5 LL_HRTIM_GetADCTrigSrc\n
3234 * ADC1R ADC1TFC2 LL_HRTIM_GetADCTrigSrc\n
3235 * ADC1R ADC1TAC3 LL_HRTIM_GetADCTrigSrc\n
3236 * ADC1R ADC1TAC4 LL_HRTIM_GetADCTrigSrc\n
3237 * ADC1R ADC1TAPER LL_HRTIM_GetADCTrigSrc\n
3238 * ADC1R ADC1TARST LL_HRTIM_GetADCTrigSrc\n
3239 * ADC1R ADC1TFC3 LL_HRTIM_GetADCTrigSrc\n
3240 * ADC1R ADC1TBC3 LL_HRTIM_GetADCTrigSrc\n
3241 * ADC1R ADC1TBC4 LL_HRTIM_GetADCTrigSrc\n
3242 * ADC1R ADC1TBPER LL_HRTIM_GetADCTrigSrc\n
3243 * ADC1R ADC1TBRST LL_HRTIM_GetADCTrigSrc\n
3244 * ADC1R ADC1TFC4 LL_HRTIM_GetADCTrigSrc\n
3245 * ADC1R ADC1TCC3 LL_HRTIM_GetADCTrigSrc\n
3246 * ADC1R ADC1TCC4 LL_HRTIM_GetADCTrigSrc\n
3247 * ADC1R ADC1TCPER LL_HRTIM_GetADCTrigSrc\n
3248 * ADC1R ADC1TFPER LL_HRTIM_GetADCTrigSrc\n
3249 * ADC1R ADC1TDC3 LL_HRTIM_GetADCTrigSrc\n
3250 * ADC1R ADC1TDC4 LL_HRTIM_GetADCTrigSrc\n
3251 * ADC1R ADC1TDPER LL_HRTIM_GetADCTrigSrc\n
3252 * ADC1R ADC1TFRST LL_HRTIM_GetADCTrigSrc\n
3253 * ADC1R ADC1TEC3 LL_HRTIM_GetADCTrigSrc\n
3254 * ADC1R ADC1TEC4 LL_HRTIM_GetADCTrigSrc\n
3255 * ADC1R ADC1TEPER LL_HRTIM_GetADCTrigSrc\n
3256 * ADC2R ADC2MC1 LL_HRTIM_GetADCTrigSrc\n
3257 * ADC2R ADC2MC2 LL_HRTIM_GetADCTrigSrc\n
3258 * ADC2R ADC2MC3 LL_HRTIM_GetADCTrigSrc\n
3259 * ADC2R ADC2MC4 LL_HRTIM_GetADCTrigSrc\n
3260 * ADC2R ADC2MPER LL_HRTIM_GetADCTrigSrc\n
3261 * ADC2R ADC2EEV6 LL_HRTIM_GetADCTrigSrc\n
3262 * ADC2R ADC2EEV7 LL_HRTIM_GetADCTrigSrc\n
3263 * ADC2R ADC2EEV8 LL_HRTIM_GetADCTrigSrc\n
3264 * ADC2R ADC2EEV9 LL_HRTIM_GetADCTrigSrc\n
3265 * ADC2R ADC2EEV10 LL_HRTIM_GetADCTrigSrc\n
3266 * ADC2R ADC2TAC2 LL_HRTIM_GetADCTrigSrc\n
3267 * ADC2R ADC2TFC2 LL_HRTIM_GetADCTrigSrc\n
3268 * ADC2R ADC2TAC4 LL_HRTIM_GetADCTrigSrc\n
3269 * ADC2R ADC2TAPER LL_HRTIM_GetADCTrigSrc\n
3270 * ADC2R ADC2TBC2 LL_HRTIM_GetADCTrigSrc\n
3271 * ADC2R ADC2TFC3 LL_HRTIM_GetADCTrigSrc\n
3272 * ADC2R ADC2TBC4 LL_HRTIM_GetADCTrigSrc\n
3273 * ADC2R ADC2TBPER LL_HRTIM_GetADCTrigSrc\n
3274 * ADC2R ADC2TCC2 LL_HRTIM_GetADCTrigSrc\n
3275 * ADC2R ADC2TFC4 LL_HRTIM_GetADCTrigSrc\n
3276 * ADC2R ADC2TCC4 LL_HRTIM_GetADCTrigSrc\n
3277 * ADC2R ADC2TCPER LL_HRTIM_GetADCTrigSrc\n
3278 * ADC2R ADC2TCRST LL_HRTIM_GetADCTrigSrc\n
3279 * ADC2R ADC2TDC2 LL_HRTIM_GetADCTrigSrc\n
3280 * ADC2R ADC2TFPER LL_HRTIM_GetADCTrigSrc\n
3281 * ADC2R ADC2TDC4 LL_HRTIM_GetADCTrigSrc\n
3282 * ADC2R ADC2TDPER LL_HRTIM_GetADCTrigSrc\n
3283 * ADC2R ADC2TDRST LL_HRTIM_GetADCTrigSrc\n
3284 * ADC2R ADC2TEC2 LL_HRTIM_GetADCTrigSrc\n
3285 * ADC2R ADC2TEC3 LL_HRTIM_GetADCTrigSrc\n
3286 * ADC2R ADC2TEC4 LL_HRTIM_GetADCTrigSrc\n
3287 * ADC2R ADC2TERST LL_HRTIM_GetADCTrigSrc\n
3288 * ADC3R ADC3MC1 LL_HRTIM_GetADCTrigSrc\n
3289 * ADC3R ADC3MC2 LL_HRTIM_GetADCTrigSrc\n
3290 * ADC3R ADC3MC3 LL_HRTIM_GetADCTrigSrc\n
3291 * ADC3R ADC3MC4 LL_HRTIM_GetADCTrigSrc\n
3292 * ADC3R ADC3MPER LL_HRTIM_GetADCTrigSrc\n
3293 * ADC3R ADC3EEV1 LL_HRTIM_GetADCTrigSrc\n
3294 * ADC3R ADC3EEV2 LL_HRTIM_GetADCTrigSrc\n
3295 * ADC3R ADC3EEV3 LL_HRTIM_GetADCTrigSrc\n
3296 * ADC3R ADC3EEV4 LL_HRTIM_GetADCTrigSrc\n
3297 * ADC3R ADC3EEV5 LL_HRTIM_GetADCTrigSrc\n
3298 * ADC3R ADC3TFC2 LL_HRTIM_GetADCTrigSrc\n
3299 * ADC3R ADC3TAC3 LL_HRTIM_GetADCTrigSrc\n
3300 * ADC3R ADC3TAC4 LL_HRTIM_GetADCTrigSrc\n
3301 * ADC3R ADC3TAPER LL_HRTIM_GetADCTrigSrc\n
3302 * ADC3R ADC3TARST LL_HRTIM_GetADCTrigSrc\n
3303 * ADC3R ADC3TFC3 LL_HRTIM_GetADCTrigSrc\n
3304 * ADC3R ADC3TBC3 LL_HRTIM_GetADCTrigSrc\n
3305 * ADC3R ADC3TBC4 LL_HRTIM_GetADCTrigSrc\n
3306 * ADC3R ADC3TBPER LL_HRTIM_GetADCTrigSrc\n
3307 * ADC3R ADC3TBRST LL_HRTIM_GetADCTrigSrc\n
3308 * ADC3R ADC3TFC4 LL_HRTIM_GetADCTrigSrc\n
3309 * ADC3R ADC3TCC3 LL_HRTIM_GetADCTrigSrc\n
3310 * ADC3R ADC3TCC4 LL_HRTIM_GetADCTrigSrc\n
3311 * ADC3R ADC3TCPER LL_HRTIM_GetADCTrigSrc\n
3312 * ADC3R ADC3TFPER LL_HRTIM_GetADCTrigSrc\n
3313 * ADC3R ADC3TDC3 LL_HRTIM_GetADCTrigSrc\n
3314 * ADC3R ADC3TDC4 LL_HRTIM_GetADCTrigSrc\n
3315 * ADC3R ADC3TDPER LL_HRTIM_GetADCTrigSrc\n
3316 * ADC3R ADC3TFRST LL_HRTIM_GetADCTrigSrc\n
3317 * ADC3R ADC3TEC3 LL_HRTIM_GetADCTrigSrc\n
3318 * ADC3R ADC3TEC4 LL_HRTIM_GetADCTrigSrc\n
3319 * ADC3R ADC3TEPER LL_HRTIM_GetADCTrigSrc\n
3320 * ADC4R ADC4MC1 LL_HRTIM_GetADCTrigSrc\n
3321 * ADC4R ADC4MC2 LL_HRTIM_GetADCTrigSrc\n
3322 * ADC4R ADC4MC3 LL_HRTIM_GetADCTrigSrc\n
3323 * ADC4R ADC4MC4 LL_HRTIM_GetADCTrigSrc\n
3324 * ADC4R ADC4MPER LL_HRTIM_GetADCTrigSrc\n
3325 * ADC4R ADC4EEV6 LL_HRTIM_GetADCTrigSrc\n
3326 * ADC4R ADC4EEV7 LL_HRTIM_GetADCTrigSrc\n
3327 * ADC4R ADC4EEV8 LL_HRTIM_GetADCTrigSrc\n
3328 * ADC4R ADC4EEV9 LL_HRTIM_GetADCTrigSrc\n
3329 * ADC4R ADC4EEV10 LL_HRTIM_GetADCTrigSrc\n
3330 * ADC4R ADC4TAC2 LL_HRTIM_GetADCTrigSrc\n
3331 * ADC4R ADC4TFC2 LL_HRTIM_GetADCTrigSrc\n
3332 * ADC4R ADC4TAC4 LL_HRTIM_GetADCTrigSrc\n
3333 * ADC4R ADC4TAPER LL_HRTIM_GetADCTrigSrc\n
3334 * ADC4R ADC4TBC2 LL_HRTIM_GetADCTrigSrc\n
3335 * ADC4R ADC4TFC3 LL_HRTIM_GetADCTrigSrc\n
3336 * ADC4R ADC4TBC4 LL_HRTIM_GetADCTrigSrc\n
3337 * ADC4R ADC4TBPER LL_HRTIM_GetADCTrigSrc\n
3338 * ADC4R ADC4TCC2 LL_HRTIM_GetADCTrigSrc\n
3339 * ADC4R ADC4TFC4 LL_HRTIM_GetADCTrigSrc\n
3340 * ADC4R ADC4TCC4 LL_HRTIM_GetADCTrigSrc\n
3341 * ADC4R ADC4TCPER LL_HRTIM_GetADCTrigSrc\n
3342 * ADC4R ADC4TCRST LL_HRTIM_GetADCTrigSrc\n
3343 * ADC4R ADC4TDC2 LL_HRTIM_GetADCTrigSrc\n
3344 * ADC4R ADC4TFPER LL_HRTIM_GetADCTrigSrc\n
3345 * ADC4R ADC4TDC4 LL_HRTIM_GetADCTrigSrc\n
3346 * ADC4R ADC4TDPER LL_HRTIM_GetADCTrigSrc\n
3347 * ADC4R ADC4TDRST LL_HRTIM_GetADCTrigSrc\n
3348 * ADC4R ADC4TEC2 LL_HRTIM_GetADCTrigSrc\n
3349 * ADC4R ADC4TEC3 LL_HRTIM_GetADCTrigSrc\n
3350 * ADC4R ADC4TEC4 LL_HRTIM_GetADCTrigSrc\n
3351 * ADC4R ADC4TERST LL_HRTIM_GetADCTrigSrc
3352 * ADCER ADC5TRG LL_HRTIM_SetADCTrigSrc\n
3353 * ADCER ADC6TRG LL_HRTIM_SetADCTrigSrc\n
3354 * ADCER ADC7TRG LL_HRTIM_SetADCTrigSrc\n
3355 * ADCER ADC8TRG LL_HRTIM_SetADCTrigSrc\n
3356 * ADCER ADC9TRG LL_HRTIM_SetADCTrigSrc\n
3357 * ADCER ADC10TRG LL_HRTIM_SetADCTrigSrc
3358 * @param HRTIMx High Resolution Timer instance
3359 * @param HRTIMx High Resolution Timer instance
3360 * @param ADCTrig This parameter can be one of the following values:
3361 * @arg @ref LL_HRTIM_ADCTRIG_1
3362 * @arg @ref LL_HRTIM_ADCTRIG_2
3363 * @arg @ref LL_HRTIM_ADCTRIG_3
3364 * @arg @ref LL_HRTIM_ADCTRIG_4
3365 * @arg @ref LL_HRTIM_ADCTRIG_5
3366 * @arg @ref LL_HRTIM_ADCTRIG_6
3367 * @arg @ref LL_HRTIM_ADCTRIG_7
3368 * @arg @ref LL_HRTIM_ADCTRIG_8
3369 * @arg @ref LL_HRTIM_ADCTRIG_9
3370 * @arg @ref LL_HRTIM_ADCTRIG_10
3371 * @retval Src This parameter can be a combination of the following values:
3372 *
3373 * For ADC trigger 1 and ADC trigger 3 this parameter can be a
3374 * combination of the following values:
3375 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
3376 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
3377 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
3378 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
3379 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
3380 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
3381 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
3382 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
3383 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
3384 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
3385 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
3386 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
3387 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
3388 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
3389 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
3390 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
3391 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
3392 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
3393 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
3394 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
3395 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
3396 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
3397 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
3398 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
3399 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
3400 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
3401 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
3402 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
3403 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
3404 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
3405 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
3406 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
3407 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
3408 *
3409 * For ADC trigger 2 and ADC trigger 4 this parameter can be a
3410 * combination of the following values:
3411 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
3412 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
3413 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
3414 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
3415 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
3416 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
3417 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
3418 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
3419 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
3420 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
3421 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
3422 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
3423 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
3424 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
3425 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
3426 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
3427 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
3428 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
3429 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
3430 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
3431 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
3432 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
3433 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
3434 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
3435 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
3436 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
3437 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
3438 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
3439 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
3440 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
3441 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
3442 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
3443 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
3444 *
3445 * For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
3446 * can be one of the following values:
3447 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
3448 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
3449 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
3450 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
3451 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
3452 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
3453 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
3454 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
3455 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
3456 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
3457 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
3458 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
3459 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
3460 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
3461 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
3462 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
3463 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
3464 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
3465 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
3466 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
3467 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
3468 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
3469 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
3470 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
3471 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
3472 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
3473 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
3474 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
3475 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
3476 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
3477 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
3478 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
3479 *
3480 * For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
3481 * can be one of the following values:
3482 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
3483 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
3484 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
3485 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
3486 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
3487 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
3488 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
3489 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
3490 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
3491 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
3492 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
3493 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
3494 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
3495 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
3496 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
3497 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
3498 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
3499 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
3500 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
3501 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
3502 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
3503 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
3504 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
3505 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
3506 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
3507 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
3508 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
3509 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
3510 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
3511 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
3512 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
3513 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
3514 */
LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig)3515 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
3516 {
3517 const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
3518 REG_OFFSET_TAB_ADCER[ADCTrig]));
3519 return (READ_BIT(*preg, (REG_MASK_TAB_ADCER[ADCTrig])) >> REG_SHIFT_TAB_ADCER[ADCTrig]);
3520
3521 }
3522
3523
3524 /**
3525 * @brief Select the ADC post scaler.
3526 * @note This function allows to adjust each ADC trigger rate individually.
3527 * @note In center-aligned mode, the ADC trigger rate is also dependent on
3528 * ADROM[1:0] bitfield, programmed in the source timer
3529 * (see function @ref LL_HRTIM_TIM_SetADCRollOverMode)
3530 * @rmtoll ADCPS2 ADC10PSC LL_HRTIM_SetADCPostScaler\n
3531 * ADCPS2 ADC9PSC LL_HRTIM_SetADCPostScaler\n
3532 * ADCPS2 ADC8PSC LL_HRTIM_SetADCPostScaler\n
3533 * ADCPS2 ADC7PSC LL_HRTIM_SetADCPostScaler\n
3534 * ADCPS2 ADC6PSC LL_HRTIM_SetADCPostScaler\n
3535 * ADCPS1 ADC5PSC LL_HRTIM_SetADCPostScaler\n
3536 * ADCPS1 ADC4PSC LL_HRTIM_SetADCPostScaler\n
3537 * ADCPS1 ADC3PSC LL_HRTIM_SetADCPostScaler\n
3538 * ADCPS1 ADC2PSC LL_HRTIM_SetADCPostScaler\n
3539 * ADCPS1 ADC1PSC LL_HRTIM_SetADCPostScaler
3540 * @param HRTIMx High Resolution Timer instance
3541 * @param ADCTrig This parameter can be one of the following values:
3542 * @arg @ref LL_HRTIM_ADCTRIG_1
3543 * @arg @ref LL_HRTIM_ADCTRIG_2
3544 * @arg @ref LL_HRTIM_ADCTRIG_3
3545 * @arg @ref LL_HRTIM_ADCTRIG_4
3546 * @arg @ref LL_HRTIM_ADCTRIG_5
3547 * @arg @ref LL_HRTIM_ADCTRIG_6
3548 * @arg @ref LL_HRTIM_ADCTRIG_7
3549 * @arg @ref LL_HRTIM_ADCTRIG_8
3550 * @arg @ref LL_HRTIM_ADCTRIG_9
3551 * @arg @ref LL_HRTIM_ADCTRIG_10
3552 * @param PostScaler This parameter can be a number between Min_Data=0 and Max_Data=31
3553 * @retval None
3554 */
LL_HRTIM_SetADCPostScaler(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig,uint32_t PostScaler)3555 __STATIC_INLINE void LL_HRTIM_SetADCPostScaler(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t PostScaler)
3556 {
3557
3558 uint64_t mask = (uint64_t)(HRTIM_ADCPS1_AD1PSC) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]);
3559 uint64_t ratio = (uint64_t)(PostScaler) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]);
3560
3561 MODIFY_REG(HRTIMx->sCommonRegs.ADCPS1, (uint32_t)mask, (uint32_t)ratio);
3562 MODIFY_REG(HRTIMx->sCommonRegs.ADCPS2, (uint32_t)(mask >> 32U), (uint32_t)(ratio >> 32U));
3563
3564 }
3565
3566 /**
3567 * @brief Get the selected ADC post scaler.
3568 * @rmtoll ADCPS2 ADC10PSC LL_HRTIM_GetADCPostScaler\n
3569 * ADCPS2 ADC9PSC LL_HRTIM_GetADCPostScaler\n
3570 * ADCPS2 ADC8PSC LL_HRTIM_GetADCPostScaler\n
3571 * ADCPS2 ADC7PSC LL_HRTIM_GetADCPostScaler\n
3572 * ADCPS2 ADC6PSC LL_HRTIM_GetADCPostScaler\n
3573 * ADCPS1 ADC5PSC LL_HRTIM_GetADCPostScaler\n
3574 * ADCPS1 ADC4PSC LL_HRTIM_GetADCPostScaler\n
3575 * ADCPS1 ADC3PSC LL_HRTIM_GetADCPostScaler\n
3576 * ADCPS1 ADC2PSC LL_HRTIM_GetADCPostScaler\n
3577 * ADCPS1 ADC1PSC LL_HRTIM_GetADCPostScaler
3578 * @param HRTIMx High Resolution Timer instance
3579 * @param ADCTrig This parameter can be one of the following values:
3580 * @arg @ref LL_HRTIM_ADCTRIG_1
3581 * @arg @ref LL_HRTIM_ADCTRIG_2
3582 * @arg @ref LL_HRTIM_ADCTRIG_3
3583 * @arg @ref LL_HRTIM_ADCTRIG_4
3584 * @arg @ref LL_HRTIM_ADCTRIG_5
3585 * @arg @ref LL_HRTIM_ADCTRIG_6
3586 * @arg @ref LL_HRTIM_ADCTRIG_7
3587 * @arg @ref LL_HRTIM_ADCTRIG_8
3588 * @arg @ref LL_HRTIM_ADCTRIG_9
3589 * @arg @ref LL_HRTIM_ADCTRIG_10
3590 * @retval PostScaler This parameter can be a number between Min_Data=0 and Max_Data=31
3591 */
LL_HRTIM_GetADCPostScaler(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig)3592 __STATIC_INLINE uint32_t LL_HRTIM_GetADCPostScaler(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
3593 {
3594
3595 uint32_t reg1 = READ_REG(HRTIMx->sCommonRegs.ADCPS1);
3596 uint32_t reg2 = READ_REG(HRTIMx->sCommonRegs.ADCPS2);
3597
3598 uint64_t mask = (uint64_t)(HRTIM_ADCPS1_AD1PSC) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]);
3599 uint64_t ratio = (uint64_t)(reg1) | ((uint64_t)(reg2) << 32U);
3600
3601 return (uint32_t)((ratio & mask) >> (REG_OFFSET_TAB_ADCPSx[ADCTrig])) ;
3602
3603 }
3604
3605 /**
3606 * @brief Configure the DLL calibration mode.
3607 * @rmtoll DLLCR CALEN LL_HRTIM_ConfigDLLCalibration\n
3608 * DLLCR CALRTE LL_HRTIM_ConfigDLLCalibration
3609 * @param HRTIMx High Resolution Timer instance
3610 * @param Mode This parameter can be one of the following values:
3611 * @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT
3612 * @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS
3613 * @param Period This parameter can be one of the following values:
3614 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_0
3615 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_1
3616 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_2
3617 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_3
3618 * @retval None
3619 */
LL_HRTIM_ConfigDLLCalibration(HRTIM_TypeDef * HRTIMx,uint32_t Mode,uint32_t Period)3620 __STATIC_INLINE void LL_HRTIM_ConfigDLLCalibration(HRTIM_TypeDef *HRTIMx, uint32_t Mode, uint32_t Period)
3621 {
3622 MODIFY_REG(HRTIMx->sCommonRegs.DLLCR, (HRTIM_DLLCR_CALEN | HRTIM_DLLCR_CALRTE), (Mode | Period));
3623 }
3624
3625 /**
3626 * @brief Launch DLL calibration
3627 * @rmtoll DLLCR CAL LL_HRTIM_StartDLLCalibration
3628 * @param HRTIMx High Resolution Timer instance
3629 * @retval None
3630 */
LL_HRTIM_StartDLLCalibration(HRTIM_TypeDef * HRTIMx)3631 __STATIC_INLINE void LL_HRTIM_StartDLLCalibration(HRTIM_TypeDef *HRTIMx)
3632 {
3633 SET_BIT(HRTIMx->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
3634 }
3635
3636 /**
3637 * @}
3638 */
3639
3640 /** @defgroup HRTIM_LL_EF_HRTIM_Timer_Control HRTIM_Timer_Control
3641 * @{
3642 */
3643
3644 /**
3645 * @brief Enable timer(s) counter.
3646 * @rmtoll MDIER TFCEN LL_HRTIM_TIM_CounterEnable\n
3647 * MDIER TECEN LL_HRTIM_TIM_CounterEnable\n
3648 * MDIER TDCEN LL_HRTIM_TIM_CounterEnable\n
3649 * MDIER TCCEN LL_HRTIM_TIM_CounterEnable\n
3650 * MDIER TBCEN LL_HRTIM_TIM_CounterEnable\n
3651 * MDIER TACEN LL_HRTIM_TIM_CounterEnable\n
3652 * MDIER MCEN LL_HRTIM_TIM_CounterEnable
3653 * @param HRTIMx High Resolution Timer instance
3654 * @param Timers This parameter can be a combination of the following values:
3655 * @arg @ref LL_HRTIM_TIMER_MASTER
3656 * @arg @ref LL_HRTIM_TIMER_A
3657 * @arg @ref LL_HRTIM_TIMER_B
3658 * @arg @ref LL_HRTIM_TIMER_C
3659 * @arg @ref LL_HRTIM_TIMER_D
3660 * @arg @ref LL_HRTIM_TIMER_E
3661 * @arg @ref LL_HRTIM_TIMER_F
3662 * @retval None
3663 */
LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef * HRTIMx,uint32_t Timers)3664 __STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
3665 {
3666 SET_BIT(HRTIMx->sMasterRegs.MCR, Timers);
3667 }
3668
3669 /**
3670 * @brief Disable timer(s) counter.
3671 * @rmtoll MDIER TFCEN LL_HRTIM_TIM_CounterDisable\n
3672 * MDIER TECEN LL_HRTIM_TIM_CounterDisable\n
3673 * MDIER TDCEN LL_HRTIM_TIM_CounterDisable\n
3674 * MDIER TCCEN LL_HRTIM_TIM_CounterDisable\n
3675 * MDIER TBCEN LL_HRTIM_TIM_CounterDisable\n
3676 * MDIER TACEN LL_HRTIM_TIM_CounterDisable\n
3677 * MDIER MCEN LL_HRTIM_TIM_CounterDisable
3678 * @param HRTIMx High Resolution Timer instance
3679 * @param Timers This parameter can be a combination of the following values:
3680 * @arg @ref LL_HRTIM_TIMER_MASTER
3681 * @arg @ref LL_HRTIM_TIMER_A
3682 * @arg @ref LL_HRTIM_TIMER_B
3683 * @arg @ref LL_HRTIM_TIMER_C
3684 * @arg @ref LL_HRTIM_TIMER_D
3685 * @arg @ref LL_HRTIM_TIMER_E
3686 * @arg @ref LL_HRTIM_TIMER_F
3687 * @retval None
3688 */
LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef * HRTIMx,uint32_t Timers)3689 __STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
3690 {
3691 CLEAR_BIT(HRTIMx->sMasterRegs.MCR, Timers);
3692 }
3693
3694 /**
3695 * @brief Indicate whether the timer counter is enabled.
3696 * @rmtoll MDIER TFCEN LL_HRTIM_TIM_IsCounterEnabled\n
3697 * MDIER TECEN LL_HRTIM_TIM_IsCounterEnabled\n
3698 * MDIER TDCEN LL_HRTIM_TIM_IsCounterEnabled\n
3699 * MDIER TCCEN LL_HRTIM_TIM_IsCounterEnabled\n
3700 * MDIER TBCEN LL_HRTIM_TIM_IsCounterEnabled\n
3701 * MDIER TACEN LL_HRTIM_TIM_IsCounterEnabled\n
3702 * MDIER MCEN LL_HRTIM_TIM_IsCounterEnabled
3703 * @param HRTIMx High Resolution Timer instance
3704 * @param Timer This parameter can be one of the following values:
3705 * @arg @ref LL_HRTIM_TIMER_MASTER
3706 * @arg @ref LL_HRTIM_TIMER_A
3707 * @arg @ref LL_HRTIM_TIMER_B
3708 * @arg @ref LL_HRTIM_TIMER_C
3709 * @arg @ref LL_HRTIM_TIMER_D
3710 * @arg @ref LL_HRTIM_TIMER_E
3711 * @arg @ref LL_HRTIM_TIMER_F
3712 * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0).
3713 */
LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3714 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3715 {
3716 return ((READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer)) ? 1UL : 0UL);
3717 }
3718
3719 /**
3720 * @brief Set the timer clock prescaler ratio.
3721 * @rmtoll MCR CKPSC LL_HRTIM_TIM_SetPrescaler\n
3722 * TIMxCR CKPSC LL_HRTIM_TIM_SetPrescaler
3723 * @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0].
3724 * @note The prescaling ratio cannot be modified once the timer counter is enabled.
3725 * @param HRTIMx High Resolution Timer instance
3726 * @param Timer This parameter can be one of the following values:
3727 * @arg @ref LL_HRTIM_TIMER_MASTER
3728 * @arg @ref LL_HRTIM_TIMER_A
3729 * @arg @ref LL_HRTIM_TIMER_B
3730 * @arg @ref LL_HRTIM_TIMER_C
3731 * @arg @ref LL_HRTIM_TIMER_D
3732 * @arg @ref LL_HRTIM_TIMER_E
3733 * @arg @ref LL_HRTIM_TIMER_F
3734 * @param Prescaler This parameter can be one of the following values:
3735 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
3736 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
3737 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
3738 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
3739 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
3740 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
3741 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
3742 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
3743 * @retval None
3744 */
LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Prescaler)3745 __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
3746 {
3747 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3748 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3749 MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler);
3750 }
3751
3752 /**
3753 * @brief Get the timer clock prescaler ratio
3754 * @rmtoll MCR CKPSC LL_HRTIM_TIM_GetPrescaler\n
3755 * TIMxCR CKPSC LL_HRTIM_TIM_GetPrescaler
3756 * @param HRTIMx High Resolution Timer instance
3757 * @param Timer This parameter can be one of the following values:
3758 * @arg @ref LL_HRTIM_TIMER_MASTER
3759 * @arg @ref LL_HRTIM_TIMER_A
3760 * @arg @ref LL_HRTIM_TIMER_B
3761 * @arg @ref LL_HRTIM_TIMER_C
3762 * @arg @ref LL_HRTIM_TIMER_D
3763 * @arg @ref LL_HRTIM_TIMER_E
3764 * @arg @ref LL_HRTIM_TIMER_F
3765 * @retval Prescaler Returned value can be one of the following values:
3766 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
3767 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
3768 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
3769 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
3770 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
3771 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
3772 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
3773 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
3774 */
LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3775 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3776 {
3777 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3778 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3779 return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC));
3780 }
3781
3782 /**
3783 * @brief Set the counter operating mode mode (single-shot, continuous or re-triggerable).
3784 * @rmtoll MCR CONT LL_HRTIM_TIM_SetCounterMode\n
3785 * MCR RETRIG LL_HRTIM_TIM_SetCounterMode\n
3786 * TIMxCR CONT LL_HRTIM_TIM_SetCounterMode\n
3787 * TIMxCR RETRIG LL_HRTIM_TIM_SetCounterMode
3788 * @param HRTIMx High Resolution Timer instance
3789 * @param Timer This parameter can be one of the following values:
3790 * @arg @ref LL_HRTIM_TIMER_MASTER
3791 * @arg @ref LL_HRTIM_TIMER_A
3792 * @arg @ref LL_HRTIM_TIMER_B
3793 * @arg @ref LL_HRTIM_TIMER_C
3794 * @arg @ref LL_HRTIM_TIMER_D
3795 * @arg @ref LL_HRTIM_TIMER_E
3796 * @arg @ref LL_HRTIM_TIMER_F
3797 * @param Mode This parameter can be one of the following values:
3798 * @arg @ref LL_HRTIM_MODE_CONTINUOUS
3799 * @arg @ref LL_HRTIM_MODE_SINGLESHOT
3800 * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
3801 * @retval None
3802 */
LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)3803 __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
3804 {
3805 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3806 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3807 MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode);
3808 }
3809
3810 /**
3811 * @brief Get the counter operating mode mode
3812 * @rmtoll MCR CONT LL_HRTIM_TIM_GetCounterMode\n
3813 * MCR RETRIG LL_HRTIM_TIM_GetCounterMode\n
3814 * TIMxCR CONT LL_HRTIM_TIM_GetCounterMode\n
3815 * TIMxCR RETRIG LL_HRTIM_TIM_GetCounterMode
3816 * @param HRTIMx High Resolution Timer instance
3817 * @param Timer This parameter can be one of the following values:
3818 * @arg @ref LL_HRTIM_TIMER_MASTER
3819 * @arg @ref LL_HRTIM_TIMER_A
3820 * @arg @ref LL_HRTIM_TIMER_B
3821 * @arg @ref LL_HRTIM_TIMER_C
3822 * @arg @ref LL_HRTIM_TIMER_D
3823 * @arg @ref LL_HRTIM_TIMER_E
3824 * @arg @ref LL_HRTIM_TIMER_F
3825 * @retval Mode Returned value can be one of the following values:
3826 * @arg @ref LL_HRTIM_MODE_CONTINUOUS
3827 * @arg @ref LL_HRTIM_MODE_SINGLESHOT
3828 * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
3829 */
LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3830 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3831 {
3832 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3833 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3834 return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT)));
3835 }
3836
3837 /**
3838 * @brief Enable the half duty-cycle mode.
3839 * @rmtoll MCR HALF LL_HRTIM_TIM_EnableHalfMode\n
3840 * TIMxCR HALF LL_HRTIM_TIM_EnableHalfMode
3841 * @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR)
3842 * active register is automatically updated with HRTIM_MPER/2
3843 * (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
3844 * @param HRTIMx High Resolution Timer instance
3845 * @param Timer This parameter can be one of the following values:
3846 * @arg @ref LL_HRTIM_TIMER_MASTER
3847 * @arg @ref LL_HRTIM_TIMER_A
3848 * @arg @ref LL_HRTIM_TIMER_B
3849 * @arg @ref LL_HRTIM_TIMER_C
3850 * @arg @ref LL_HRTIM_TIMER_D
3851 * @arg @ref LL_HRTIM_TIMER_E
3852 * @arg @ref LL_HRTIM_TIMER_F
3853 * @retval None
3854 */
LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3855 __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3856 {
3857 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3858 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3859 SET_BIT(*pReg, HRTIM_MCR_HALF);
3860 }
3861
3862 /**
3863 * @brief Disable the half duty-cycle mode.
3864 * @rmtoll MCR HALF LL_HRTIM_TIM_DisableHalfMode\n
3865 * TIMxCR HALF LL_HRTIM_TIM_DisableHalfMode
3866 * @param HRTIMx High Resolution Timer instance
3867 * @param Timer This parameter can be one of the following values:
3868 * @arg @ref LL_HRTIM_TIMER_MASTER
3869 * @arg @ref LL_HRTIM_TIMER_A
3870 * @arg @ref LL_HRTIM_TIMER_B
3871 * @arg @ref LL_HRTIM_TIMER_C
3872 * @arg @ref LL_HRTIM_TIMER_D
3873 * @arg @ref LL_HRTIM_TIMER_E
3874 * @arg @ref LL_HRTIM_TIMER_F
3875 * @retval None
3876 */
LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3877 __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3878 {
3879 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3880 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3881 CLEAR_BIT(*pReg, HRTIM_MCR_HALF);
3882 CLEAR_BIT(*pReg, HRTIM_MCR_INTLVD << REG_SHIFT_TAB_INTLVD[iTimer]);
3883 }
3884
3885 /**
3886 * @brief Indicate whether half duty-cycle mode is enabled for a given timer.
3887 * @rmtoll MCR HALF LL_HRTIM_TIM_IsEnabledHalfMode\n
3888 * TIMxCR HALF LL_HRTIM_TIM_IsEnabledHalfMode
3889 * @param HRTIMx High Resolution Timer instance
3890 * @param Timer This parameter can be one of the following values:
3891 * @arg @ref LL_HRTIM_TIMER_MASTER
3892 * @arg @ref LL_HRTIM_TIMER_A
3893 * @arg @ref LL_HRTIM_TIMER_B
3894 * @arg @ref LL_HRTIM_TIMER_C
3895 * @arg @ref LL_HRTIM_TIMER_D
3896 * @arg @ref LL_HRTIM_TIMER_E
3897 * @arg @ref LL_HRTIM_TIMER_F
3898 * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
3899 */
LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3900 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3901 {
3902 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3903 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3904
3905 return ((READ_BIT(*pReg, HRTIM_MCR_HALF) == (HRTIM_MCR_HALF)) ? 1UL : 0UL);
3906 }
3907
3908 /**
3909 * @brief Enable the Re-Syncronisation Update.
3910 * @note The update coming from adjacent timers (when MSTU, TAU, TBU, TCU, TDU, TEU, TFU bit is set)
3911 * or from a software update (TxSWU bit) is taken into account on the following reset/roll-over.
3912 * @note LL_HRTIM_ForceUpdate must be called prior programming the syncrhonization mode to force
3913 * immediate update of the slave timer registers.
3914 * @rmtoll TIMxCR RSYNCU LL_HRTIM_TIM_EnableResyncUpdate
3915 * @param HRTIMx High Resolution Timer instance
3916 * @param Timer This parameter can be one of the following values:
3917 * @arg @ref LL_HRTIM_TIMER_A
3918 * @arg @ref LL_HRTIM_TIMER_B
3919 * @arg @ref LL_HRTIM_TIMER_C
3920 * @arg @ref LL_HRTIM_TIMER_D
3921 * @arg @ref LL_HRTIM_TIMER_E
3922 * @arg @ref LL_HRTIM_TIMER_F
3923 * @retval None
3924 */
LL_HRTIM_TIM_EnableResyncUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3925 __STATIC_INLINE void LL_HRTIM_TIM_EnableResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3926 {
3927 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3928 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3929 REG_OFFSET_TAB_TIMER[iTimer]));
3930 SET_BIT(*pReg, HRTIM_TIMCR_RSYNCU);
3931 /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
3932 }
3933
3934 /**
3935 * @brief Disable the Re-Syncronisation Update.
3936 * @note The update coming from adjacent timers (when MSTU, TAU, TBU, TCU, TDU, TEU, TFU bit is set)
3937 * or from a software update (TxSWU bit) is taken into account immediately.
3938 * @rmtoll TIMxCR RSYNCU LL_HRTIM_TIM_DisableResyncUpdate
3939 * @param HRTIMx High Resolution Timer instance
3940 * @param Timer This parameter can be one of the following values:
3941 * @arg @ref LL_HRTIM_TIMER_A
3942 * @arg @ref LL_HRTIM_TIMER_B
3943 * @arg @ref LL_HRTIM_TIMER_C
3944 * @arg @ref LL_HRTIM_TIMER_D
3945 * @arg @ref LL_HRTIM_TIMER_E
3946 * @arg @ref LL_HRTIM_TIMER_F
3947 * @retval None
3948 */
LL_HRTIM_TIM_DisableResyncUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3949 __STATIC_INLINE void LL_HRTIM_TIM_DisableResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3950 {
3951 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3952 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3953 REG_OFFSET_TAB_TIMER[iTimer]));
3954
3955 CLEAR_BIT(*pReg, HRTIM_TIMCR_RSYNCU);
3956 /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
3957 }
3958
3959 /**
3960 * @brief Indicate whether the Re-Syncronisation Update is enabled.
3961 * @note This bit specifies whether update source coming outside
3962 * from the timing unit must be synchronized
3963 * @rmtoll TIMxCR RSYNCU LL_HRTIM_TIM_IsEnabledResyncUpdate
3964 * @param HRTIMx High Resolution Timer instance
3965 * @param Timer This parameter can be one of the following values:
3966 * @arg @ref LL_HRTIM_TIMER_A
3967 * @arg @ref LL_HRTIM_TIMER_B
3968 * @arg @ref LL_HRTIM_TIMER_C
3969 * @arg @ref LL_HRTIM_TIMER_D
3970 * @arg @ref LL_HRTIM_TIMER_E
3971 * @arg @ref LL_HRTIM_TIMER_F
3972 * @retval State of RSYNC bit in HRTIM_TIMxCR register (1 or 0).
3973 */
LL_HRTIM_TIM_IsEnabledResyncUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3974 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3975 {
3976 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3977 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3978 REG_OFFSET_TAB_TIMER[iTimer]));
3979
3980 return ((READ_BIT(*pReg, HRTIM_TIMCR_RSYNCU) == (HRTIM_TIMCR_RSYNCU)) ? 1UL : 0UL);
3981 /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
3982 }
3983
3984 /**
3985 * @note Interleaved mode complements the Half mode and helps the implementation of interleaved topologies.
3986 * @note When interleaved mode is enabled, the content of the compare registers is overridden.
3987 * @rmtoll MCR HALF LL_HRTIM_TIM_SetInterleavedMode\n
3988 * MCR INTLVD LL_HRTIM_TIM_SetInterleavedMode\n
3989 * TIMxCR HALF LL_HRTIM_TIM_SetInterleavedMode\n
3990 * TIMxCR INTLVD LL_HRTIM_TIM_SetInterleavedMode
3991 * @param HRTIMx High Resolution Timer instance
3992 * @param Timer This parameter can be one of the following values:
3993 * @arg @ref LL_HRTIM_TIMER_MASTER
3994 * @arg @ref LL_HRTIM_TIMER_A
3995 * @arg @ref LL_HRTIM_TIMER_B
3996 * @arg @ref LL_HRTIM_TIMER_C
3997 * @arg @ref LL_HRTIM_TIMER_D
3998 * @arg @ref LL_HRTIM_TIMER_E
3999 * @arg @ref LL_HRTIM_TIMER_F
4000 * @param Mode This parameter can be one of the following values:
4001 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_DISABLED
4002 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_DUAL
4003 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_TRIPLE
4004 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_QUAD
4005 * @retval None
4006 */
LL_HRTIM_TIM_SetInterleavedMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)4007 __STATIC_INLINE void LL_HRTIM_TIM_SetInterleavedMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
4008 {
4009 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4010 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4011
4012 MODIFY_REG(*pReg, REG_MASK_TAB_INTLVD[iTimer],
4013 ((Mode & HRTIM_MCR_HALF) | ((Mode & HRTIM_MCR_INTLVD) << REG_SHIFT_TAB_INTLVD[iTimer])));
4014 }
4015
4016 /**
4017 * @brief get the Interleaved configuration.
4018 * @rmtoll MCR INTLVD LL_HRTIM_TIM_GetInterleavedMode\n
4019 * TIMxCR INTLVD LL_HRTIM_TIM_GetInterleavedMode
4020 * @note The interleaved Mode is Triple or Quad if HALF bit is disabled
4021 * the interleaved Mode is dual if HALF bit is set,
4022
4023 * HRTIM_MCMP1R (or HRTIM_CMP1xR) active register is automatically updated
4024 * with HRTIM_MPER/2 or HRTIM_MPER/4
4025 * (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
4026
4027 * @param HRTIMx High Resolution Timer instance
4028 * @param Timer This parameter can be one of the following values:
4029 * @arg @ref LL_HRTIM_TIMER_MASTER
4030 * @arg @ref LL_HRTIM_TIMER_A
4031 * @arg @ref LL_HRTIM_TIMER_B
4032 * @arg @ref LL_HRTIM_TIMER_C
4033 * @arg @ref LL_HRTIM_TIMER_D
4034 * @arg @ref LL_HRTIM_TIMER_E
4035 * @arg @ref LL_HRTIM_TIMER_F
4036 * @retval This parameter can be one of the following values:
4037 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_DISABLED
4038 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_DUAL
4039 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_TRIPLE
4040 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_QUAD
4041 */
LL_HRTIM_TIM_GetInterleavedMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4042 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetInterleavedMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4043 {
4044 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4045 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4046
4047 uint32_t Mode = READ_BIT(*pReg, (REG_MASK_TAB_INTLVD[iTimer]));
4048 return ((Mode & HRTIM_MCR_HALF) | ((Mode >> REG_SHIFT_TAB_INTLVD[iTimer]) & HRTIM_MCR_INTLVD));
4049 }
4050
4051 /**
4052 * @brief Enable the timer start when receiving a synchronization input event.
4053 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_EnableStartOnSync\n
4054 * TIMxCR SYNSTRTA LL_HRTIM_TIM_EnableStartOnSync
4055 * @param HRTIMx High Resolution Timer instance
4056 * @param Timer This parameter can be one of the following values:
4057 * @arg @ref LL_HRTIM_TIMER_MASTER
4058 * @arg @ref LL_HRTIM_TIMER_A
4059 * @arg @ref LL_HRTIM_TIMER_B
4060 * @arg @ref LL_HRTIM_TIMER_C
4061 * @arg @ref LL_HRTIM_TIMER_D
4062 * @arg @ref LL_HRTIM_TIMER_E
4063 * @arg @ref LL_HRTIM_TIMER_F
4064 * @retval None
4065 */
LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4066 __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4067 {
4068 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4069 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4070 SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
4071 }
4072
4073 /**
4074 * @brief Disable the timer start when receiving a synchronization input event.
4075 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_DisableStartOnSync\n
4076 * TIMxCR SYNSTRTA LL_HRTIM_TIM_DisableStartOnSync
4077 * @param HRTIMx High Resolution Timer instance
4078 * @param Timer This parameter can be one of the following values:
4079 * @arg @ref LL_HRTIM_TIMER_MASTER
4080 * @arg @ref LL_HRTIM_TIMER_A
4081 * @arg @ref LL_HRTIM_TIMER_B
4082 * @arg @ref LL_HRTIM_TIMER_C
4083 * @arg @ref LL_HRTIM_TIMER_D
4084 * @arg @ref LL_HRTIM_TIMER_E
4085 * @arg @ref LL_HRTIM_TIMER_F
4086 * @retval None
4087 */
LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4088 __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4089 {
4090 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4091 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4092 CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
4093 }
4094
4095 /**
4096 * @brief Indicate whether the timer start when receiving a synchronization input event.
4097 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_IsEnabledStartOnSync\n
4098 * TIMxCR SYNSTRTA LL_HRTIM_TIM_IsEnabledStartOnSync
4099 * @param HRTIMx High Resolution Timer instance
4100 * @param Timer This parameter can be one of the following values:
4101 * @arg @ref LL_HRTIM_TIMER_MASTER
4102 * @arg @ref LL_HRTIM_TIMER_A
4103 * @arg @ref LL_HRTIM_TIMER_B
4104 * @arg @ref LL_HRTIM_TIMER_C
4105 * @arg @ref LL_HRTIM_TIMER_D
4106 * @arg @ref LL_HRTIM_TIMER_E
4107 * @arg @ref LL_HRTIM_TIMER_F
4108 * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
4109 */
LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4110 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4111 {
4112 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4113 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4114
4115 return ((READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == (HRTIM_MCR_SYNCSTRTM)) ? 1UL : 0UL);
4116 }
4117
4118 /**
4119 * @brief Enable the timer reset when receiving a synchronization input event.
4120 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_EnableResetOnSync\n
4121 * TIMxCR SYNCRSTA LL_HRTIM_TIM_EnableResetOnSync
4122 * @param HRTIMx High Resolution Timer instance
4123 * @param Timer This parameter can be one of the following values:
4124 * @arg @ref LL_HRTIM_TIMER_MASTER
4125 * @arg @ref LL_HRTIM_TIMER_A
4126 * @arg @ref LL_HRTIM_TIMER_B
4127 * @arg @ref LL_HRTIM_TIMER_C
4128 * @arg @ref LL_HRTIM_TIMER_D
4129 * @arg @ref LL_HRTIM_TIMER_E
4130 * @arg @ref LL_HRTIM_TIMER_F
4131 * @retval None
4132 */
LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4133 __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4134 {
4135 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4136 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4137 SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
4138 }
4139
4140 /**
4141 * @brief Disable the timer reset when receiving a synchronization input event.
4142 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_DisableResetOnSync\n
4143 * TIMxCR SYNCRSTA LL_HRTIM_TIM_DisableResetOnSync
4144 * @param HRTIMx High Resolution Timer instance
4145 * @param Timer This parameter can be one of the following values:
4146 * @arg @ref LL_HRTIM_TIMER_MASTER
4147 * @arg @ref LL_HRTIM_TIMER_A
4148 * @arg @ref LL_HRTIM_TIMER_B
4149 * @arg @ref LL_HRTIM_TIMER_C
4150 * @arg @ref LL_HRTIM_TIMER_D
4151 * @arg @ref LL_HRTIM_TIMER_E
4152 * @arg @ref LL_HRTIM_TIMER_F
4153 * @retval None
4154 */
LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4155 __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4156 {
4157 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4158 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4159 CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
4160 }
4161
4162 /**
4163 * @brief Indicate whether the timer reset when receiving a synchronization input event.
4164 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_IsEnabledResetOnSync\n
4165 * TIMxCR SYNCRSTA LL_HRTIM_TIM_IsEnabledResetOnSync
4166 * @param HRTIMx High Resolution Timer instance
4167 * @param Timer This parameter can be one of the following values:
4168 * @arg @ref LL_HRTIM_TIMER_MASTER
4169 * @arg @ref LL_HRTIM_TIMER_A
4170 * @arg @ref LL_HRTIM_TIMER_B
4171 * @arg @ref LL_HRTIM_TIMER_C
4172 * @arg @ref LL_HRTIM_TIMER_D
4173 * @arg @ref LL_HRTIM_TIMER_E
4174 * @arg @ref LL_HRTIM_TIMER_F
4175 * @retval None
4176 */
LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4177 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4178 {
4179 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4180 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4181
4182 return ((READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == (HRTIM_MCR_SYNCRSTM)) ? 1UL : 0UL);
4183 }
4184
4185 /**
4186 * @brief Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
4187 * @rmtoll MCR DACSYNC LL_HRTIM_TIM_SetDACTrig\n
4188 * TIMxCR DACSYNC LL_HRTIM_TIM_SetDACTrig
4189 * @param HRTIMx High Resolution Timer instance
4190 * @param Timer This parameter can be one of the following values:
4191 * @arg @ref LL_HRTIM_TIMER_MASTER
4192 * @arg @ref LL_HRTIM_TIMER_A
4193 * @arg @ref LL_HRTIM_TIMER_B
4194 * @arg @ref LL_HRTIM_TIMER_C
4195 * @arg @ref LL_HRTIM_TIMER_D
4196 * @arg @ref LL_HRTIM_TIMER_E
4197 * @arg @ref LL_HRTIM_TIMER_F
4198 * @param DACTrig This parameter can be one of the following values:
4199 * @arg @ref LL_HRTIM_DACTRIG_NONE
4200 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
4201 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
4202 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
4203 * @retval None
4204 */
LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t DACTrig)4205 __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig)
4206 {
4207 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4208 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4209 MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig);
4210 }
4211
4212 /**
4213 * @brief Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
4214 * @rmtoll MCR DACSYNC LL_HRTIM_TIM_GetDACTrig\n
4215 * TIMxCR DACSYNC LL_HRTIM_TIM_GetDACTrig
4216 * @param HRTIMx High Resolution Timer instance
4217 * @param Timer This parameter can be one of the following values:
4218 * @arg @ref LL_HRTIM_TIMER_MASTER
4219 * @arg @ref LL_HRTIM_TIMER_A
4220 * @arg @ref LL_HRTIM_TIMER_B
4221 * @arg @ref LL_HRTIM_TIMER_C
4222 * @arg @ref LL_HRTIM_TIMER_D
4223 * @arg @ref LL_HRTIM_TIMER_E
4224 * @arg @ref LL_HRTIM_TIMER_F
4225 * @retval DACTrig Returned value can be one of the following values:
4226 * @arg @ref LL_HRTIM_DACTRIG_NONE
4227 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
4228 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
4229 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
4230 */
LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4231 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4232 {
4233 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4234 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4235 return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC));
4236 }
4237
4238 /**
4239 * @brief Enable the timer registers preload mechanism.
4240 * @rmtoll MCR PREEN LL_HRTIM_TIM_EnablePreload\n
4241 * TIMxCR PREEN LL_HRTIM_TIM_EnablePreload
4242 * @note When the preload mode is enabled, accessed registers are shadow registers.
4243 * Their content is transferred into the active register after an update request,
4244 * either software or synchronized with an event.
4245 * @param HRTIMx High Resolution Timer instance
4246 * @param Timer This parameter can be one of the following values:
4247 * @arg @ref LL_HRTIM_TIMER_MASTER
4248 * @arg @ref LL_HRTIM_TIMER_A
4249 * @arg @ref LL_HRTIM_TIMER_B
4250 * @arg @ref LL_HRTIM_TIMER_C
4251 * @arg @ref LL_HRTIM_TIMER_D
4252 * @arg @ref LL_HRTIM_TIMER_E
4253 * @arg @ref LL_HRTIM_TIMER_F
4254 * @retval None
4255 */
LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4256 __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4257 {
4258 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4259 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4260 SET_BIT(*pReg, HRTIM_MCR_PREEN);
4261 }
4262
4263 /**
4264 * @brief Disable the timer registers preload mechanism.
4265 * @rmtoll MCR PREEN LL_HRTIM_TIM_DisablePreload\n
4266 * TIMxCR PREEN LL_HRTIM_TIM_DisablePreload
4267 * @param HRTIMx High Resolution Timer instance
4268 * @param Timer This parameter can be one of the following values:
4269 * @arg @ref LL_HRTIM_TIMER_MASTER
4270 * @arg @ref LL_HRTIM_TIMER_A
4271 * @arg @ref LL_HRTIM_TIMER_B
4272 * @arg @ref LL_HRTIM_TIMER_C
4273 * @arg @ref LL_HRTIM_TIMER_D
4274 * @arg @ref LL_HRTIM_TIMER_E
4275 * @arg @ref LL_HRTIM_TIMER_F
4276 * @retval None
4277 */
LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4278 __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4279 {
4280 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4281 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4282 CLEAR_BIT(*pReg, HRTIM_MCR_PREEN);
4283 }
4284
4285 /**
4286 * @brief Indicate whether the timer registers preload mechanism is enabled.
4287 * @rmtoll MCR PREEN LL_HRTIM_TIM_IsEnabledPreload\n
4288 * TIMxCR PREEN LL_HRTIM_TIM_IsEnabledPreload
4289 * @param HRTIMx High Resolution Timer instance
4290 * @param Timer This parameter can be one of the following values:
4291 * @arg @ref LL_HRTIM_TIMER_MASTER
4292 * @arg @ref LL_HRTIM_TIMER_A
4293 * @arg @ref LL_HRTIM_TIMER_B
4294 * @arg @ref LL_HRTIM_TIMER_C
4295 * @arg @ref LL_HRTIM_TIMER_D
4296 * @arg @ref LL_HRTIM_TIMER_E
4297 * @arg @ref LL_HRTIM_TIMER_F
4298 * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
4299 */
LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4300 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4301 {
4302 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4303 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4304
4305 return ((READ_BIT(*pReg, HRTIM_MCR_PREEN) == (HRTIM_MCR_PREEN)) ? 1UL : 0UL);
4306 }
4307
4308 /**
4309 * @brief Set the timer register update trigger.
4310 * @rmtoll MCR MREPU LL_HRTIM_TIM_SetUpdateTrig\n
4311 * TIMxCR TAU LL_HRTIM_TIM_SetUpdateTrig\n
4312 * TIMxCR TBU LL_HRTIM_TIM_SetUpdateTrig\n
4313 * TIMxCR TCU LL_HRTIM_TIM_SetUpdateTrig\n
4314 * TIMxCR TDU LL_HRTIM_TIM_SetUpdateTrig\n
4315 * TIMxCR TEU LL_HRTIM_TIM_SetUpdateTrig\n
4316 * TIMxCR TFU LL_HRTIM_TIM_SetUpdateTrig\n
4317 * TIMxCR MSTU LL_HRTIM_TIM_SetUpdateTrig
4318 * @param HRTIMx High Resolution Timer instance
4319 * @param Timer This parameter can be one of the following values:
4320 * @arg @ref LL_HRTIM_TIMER_MASTER
4321 * @arg @ref LL_HRTIM_TIMER_A
4322 * @arg @ref LL_HRTIM_TIMER_B
4323 * @arg @ref LL_HRTIM_TIMER_C
4324 * @arg @ref LL_HRTIM_TIMER_D
4325 * @arg @ref LL_HRTIM_TIMER_E
4326 * @arg @ref LL_HRTIM_TIMER_F
4327 * @param UpdateTrig This parameter can be one of the following values:
4328 *
4329 * For the master timer this parameter can be one of the following values:
4330 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
4331 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
4332 *
4333 * For timer A..F this parameter can be:
4334 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
4335 * or a combination of the following values:
4336 * @arg @ref LL_HRTIM_UPDATETRIG_MASTER
4337 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
4338 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
4339 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
4340 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
4341 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
4342 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_F
4343 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
4344 * @arg @ref LL_HRTIM_UPDATETRIG_RESET
4345 * @retval None
4346 */
LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t UpdateTrig)4347 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig)
4348 {
4349 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4350 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4351 MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]);
4352 }
4353
4354 /**
4355 * @brief Get the timer register update trigger.
4356 * @rmtoll MCR MREPU LL_HRTIM_TIM_GetUpdateTrig\n
4357 * TIMxCR TBU LL_HRTIM_TIM_GetUpdateTrig\n
4358 * TIMxCR TCU LL_HRTIM_TIM_GetUpdateTrig\n
4359 * TIMxCR TDU LL_HRTIM_TIM_GetUpdateTrig\n
4360 * TIMxCR TEU LL_HRTIM_TIM_GetUpdateTrig\n
4361 * TIMxCR TFU LL_HRTIM_TIM_GetUpdateTrig\n
4362 * TIMxCR MSTU LL_HRTIM_TIM_GetUpdateTrig
4363 * @param HRTIMx High Resolution Timer instance
4364 * @param Timer This parameter can be one of the following values:
4365 * @arg @ref LL_HRTIM_TIMER_MASTER
4366 * @arg @ref LL_HRTIM_TIMER_A
4367 * @arg @ref LL_HRTIM_TIMER_B
4368 * @arg @ref LL_HRTIM_TIMER_C
4369 * @arg @ref LL_HRTIM_TIMER_D
4370 * @arg @ref LL_HRTIM_TIMER_E
4371 * @arg @ref LL_HRTIM_TIMER_F
4372 * @retval UpdateTrig Returned value can be one of the following values:
4373 *
4374 * For the master timer this parameter can be one of the following values:
4375 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
4376 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
4377 *
4378 * For timer A..F this parameter can be:
4379 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
4380 * or a combination of the following values:
4381 * @arg @ref LL_HRTIM_UPDATETRIG_MASTER
4382 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
4383 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
4384 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
4385 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
4386 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
4387 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_F
4388 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
4389 * @arg @ref LL_HRTIM_UPDATETRIG_RESET
4390 */
LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4391 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4392 {
4393 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4394 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4395 return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >> REG_SHIFT_TAB_UPDATETRIG[iTimer]);
4396 }
4397
4398 /**
4399 * @brief Set the timer registers update condition (how the registers update occurs relatively to the burst DMA transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])).
4400 * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_SetUpdateGating\n
4401 * TIMxCR UPDGAT LL_HRTIM_TIM_SetUpdateGating
4402 * @param HRTIMx High Resolution Timer instance
4403 * @param Timer This parameter can be one of the following values:
4404 * @arg @ref LL_HRTIM_TIMER_MASTER
4405 * @arg @ref LL_HRTIM_TIMER_A
4406 * @arg @ref LL_HRTIM_TIMER_B
4407 * @arg @ref LL_HRTIM_TIMER_C
4408 * @arg @ref LL_HRTIM_TIMER_D
4409 * @arg @ref LL_HRTIM_TIMER_E
4410 * @arg @ref LL_HRTIM_TIMER_F
4411 * @param UpdateGating This parameter can be one of the following values:
4412 *
4413 * For the master timer this parameter can be one of the following values:
4414 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
4415 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
4416 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
4417 *
4418 * For the timer A..F this parameter can be one of the following values:
4419 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
4420 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
4421 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
4422 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
4423 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
4424 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
4425 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
4426 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
4427 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
4428 * @retval None
4429 */
LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t UpdateGating)4430 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating)
4431 {
4432 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4433 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4434 MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer]));
4435 }
4436
4437 /**
4438 * @brief Get the timer registers update condition.
4439 * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_GetUpdateGating\n
4440 * TIMxCR UPDGAT LL_HRTIM_TIM_GetUpdateGating
4441 * @param HRTIMx High Resolution Timer instance
4442 * @param Timer This parameter can be one of the following values:
4443 * @arg @ref LL_HRTIM_TIMER_MASTER
4444 * @arg @ref LL_HRTIM_TIMER_A
4445 * @arg @ref LL_HRTIM_TIMER_B
4446 * @arg @ref LL_HRTIM_TIMER_C
4447 * @arg @ref LL_HRTIM_TIMER_D
4448 * @arg @ref LL_HRTIM_TIMER_E
4449 * @arg @ref LL_HRTIM_TIMER_F
4450 * @retval UpdateGating Returned value can be one of the following values:
4451 *
4452 * For the master timer this parameter can be one of the following values:
4453 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
4454 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
4455 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
4456 *
4457 * For the timer A..F this parameter can be one of the following values:
4458 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
4459 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
4460 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
4461 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
4462 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
4463 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
4464 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
4465 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
4466 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
4467 */
LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4468 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4469 {
4470 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4471 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4472 return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]);
4473 }
4474
4475 /**
4476 * @brief Enable the push-pull mode.
4477 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_EnablePushPullMode
4478 * @param HRTIMx High Resolution Timer instance
4479 * @param Timer This parameter can be one of the following values:
4480 * @arg @ref LL_HRTIM_TIMER_A
4481 * @arg @ref LL_HRTIM_TIMER_B
4482 * @arg @ref LL_HRTIM_TIMER_C
4483 * @arg @ref LL_HRTIM_TIMER_D
4484 * @arg @ref LL_HRTIM_TIMER_E
4485 * @arg @ref LL_HRTIM_TIMER_F
4486 * @retval None
4487 */
LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4488 __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4489 {
4490 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4491 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4492 REG_OFFSET_TAB_TIMER[iTimer]));
4493 SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
4494 }
4495
4496 /**
4497 * @brief Disable the push-pull mode.
4498 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_DisablePushPullMode
4499 * @param HRTIMx High Resolution Timer instance
4500 * @param Timer This parameter can be one of the following values:
4501 * @arg @ref LL_HRTIM_TIMER_A
4502 * @arg @ref LL_HRTIM_TIMER_B
4503 * @arg @ref LL_HRTIM_TIMER_C
4504 * @arg @ref LL_HRTIM_TIMER_D
4505 * @arg @ref LL_HRTIM_TIMER_E
4506 * @arg @ref LL_HRTIM_TIMER_F
4507 * @retval None
4508 */
LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4509 __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4510 {
4511 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4512 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4513 REG_OFFSET_TAB_TIMER[iTimer]));
4514 CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
4515 }
4516
4517 /**
4518 * @brief Indicate whether the push-pull mode is enabled.
4519 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_IsEnabledPushPullMode\n
4520 * @param HRTIMx High Resolution Timer instance
4521 * @param Timer This parameter can be one of the following values:
4522 * @arg @ref LL_HRTIM_TIMER_A
4523 * @arg @ref LL_HRTIM_TIMER_B
4524 * @arg @ref LL_HRTIM_TIMER_C
4525 * @arg @ref LL_HRTIM_TIMER_D
4526 * @arg @ref LL_HRTIM_TIMER_E
4527 * @arg @ref LL_HRTIM_TIMER_F
4528 * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0).
4529 */
LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4530 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4531 {
4532 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4533 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4534 REG_OFFSET_TAB_TIMER[iTimer]));
4535 return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL);
4536 }
4537
4538 /**
4539 * @brief Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode).
4540 * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_SetCompareMode\n
4541 * TIMxCR DELCMP4 LL_HRTIM_TIM_SetCompareMode
4542 * @note In auto-delayed mode the compare match occurs independently from the timer counter value.
4543 * @param HRTIMx High Resolution Timer instance
4544 * @param Timer This parameter can be one of the following values:
4545 * @arg @ref LL_HRTIM_TIMER_A
4546 * @arg @ref LL_HRTIM_TIMER_B
4547 * @arg @ref LL_HRTIM_TIMER_C
4548 * @arg @ref LL_HRTIM_TIMER_D
4549 * @arg @ref LL_HRTIM_TIMER_E
4550 * @arg @ref LL_HRTIM_TIMER_F
4551 * @param CompareUnit This parameter can be one of the following values:
4552 * @arg @ref LL_HRTIM_COMPAREUNIT_2
4553 * @arg @ref LL_HRTIM_COMPAREUNIT_4
4554 * @param Mode This parameter can be one of the following values:
4555 * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
4556 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
4557 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
4558 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
4559 * @retval None
4560 */
LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareUnit,uint32_t Mode)4561 __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit,
4562 uint32_t Mode)
4563 {
4564 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4565 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4566 REG_OFFSET_TAB_TIMER[iTimer]));
4567 uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
4568 MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift));
4569 }
4570
4571 /**
4572 * @brief Get the functioning mode of the compare unit.
4573 * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_GetCompareMode\n
4574 * TIMxCR DELCMP4 LL_HRTIM_TIM_GetCompareMode
4575 * @param HRTIMx High Resolution Timer instance
4576 * @param Timer This parameter can be one of the following values:
4577 * @arg @ref LL_HRTIM_TIMER_A
4578 * @arg @ref LL_HRTIM_TIMER_B
4579 * @arg @ref LL_HRTIM_TIMER_C
4580 * @arg @ref LL_HRTIM_TIMER_D
4581 * @arg @ref LL_HRTIM_TIMER_E
4582 * @arg @ref LL_HRTIM_TIMER_F
4583 * @param CompareUnit This parameter can be one of the following values:
4584 * @arg @ref LL_HRTIM_COMPAREUNIT_2
4585 * @arg @ref LL_HRTIM_COMPAREUNIT_4
4586 * @retval Mode Returned value can be one of the following values:
4587 * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
4588 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
4589 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
4590 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
4591 */
LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareUnit)4592 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)
4593 {
4594 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4595 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4596 REG_OFFSET_TAB_TIMER[iTimer]));
4597 uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
4598 return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift);
4599 }
4600
4601 /**
4602 * @brief Set the timer counter value.
4603 * @rmtoll MCNTR MCNT LL_HRTIM_TIM_SetCounter\n
4604 * CNTxR CNTx LL_HRTIM_TIM_SetCounter
4605 * @note This function can only be called when the timer is stopped.
4606 * @note For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least
4607 * significant bits of the counter are not significant. They cannot be
4608 * written and return 0 when read.
4609 * @note The timer behavior is not guaranteed if the counter value is set above
4610 * the period.
4611 * @param HRTIMx High Resolution Timer instance
4612 * @param Timer This parameter can be one of the following values:
4613 * @arg @ref LL_HRTIM_TIMER_MASTER
4614 * @arg @ref LL_HRTIM_TIMER_A
4615 * @arg @ref LL_HRTIM_TIMER_B
4616 * @arg @ref LL_HRTIM_TIMER_C
4617 * @arg @ref LL_HRTIM_TIMER_D
4618 * @arg @ref LL_HRTIM_TIMER_E
4619 * @arg @ref LL_HRTIM_TIMER_F
4620 * @param Counter Value between 0 and 0xFFFF
4621 * @retval None
4622 */
LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Counter)4623 __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter)
4624 {
4625 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4626 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
4627 REG_OFFSET_TAB_TIMER[iTimer]));
4628 MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter);
4629 }
4630
4631 /**
4632 * @brief Get actual timer counter value.
4633 * @rmtoll MCNTR MCNT LL_HRTIM_TIM_GetCounter\n
4634 * CNTxR CNTx LL_HRTIM_TIM_GetCounter
4635 * @param HRTIMx High Resolution Timer instance
4636 * @param Timer This parameter can be one of the following values:
4637 * @arg @ref LL_HRTIM_TIMER_MASTER
4638 * @arg @ref LL_HRTIM_TIMER_A
4639 * @arg @ref LL_HRTIM_TIMER_B
4640 * @arg @ref LL_HRTIM_TIMER_C
4641 * @arg @ref LL_HRTIM_TIMER_D
4642 * @arg @ref LL_HRTIM_TIMER_E
4643 * @arg @ref LL_HRTIM_TIMER_F
4644 * @retval Counter Value between 0 and 0xFFFF
4645 */
LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4646 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4647 {
4648 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4649 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
4650 REG_OFFSET_TAB_TIMER[iTimer]));
4651 return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR));
4652 }
4653
4654 /**
4655 * @brief Set the timer period value.
4656 * @rmtoll MPER MPER LL_HRTIM_TIM_SetPeriod\n
4657 * PERxR PERx LL_HRTIM_TIM_SetPeriod
4658 * @param HRTIMx High Resolution Timer instance
4659 * @param Timer This parameter can be one of the following values:
4660 * @arg @ref LL_HRTIM_TIMER_MASTER
4661 * @arg @ref LL_HRTIM_TIMER_A
4662 * @arg @ref LL_HRTIM_TIMER_B
4663 * @arg @ref LL_HRTIM_TIMER_C
4664 * @arg @ref LL_HRTIM_TIMER_D
4665 * @arg @ref LL_HRTIM_TIMER_E
4666 * @arg @ref LL_HRTIM_TIMER_F
4667 * @param Period Value between 0 and 0xFFFF
4668 * @retval None
4669 */
LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Period)4670 __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period)
4671 {
4672 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4673 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
4674 REG_OFFSET_TAB_TIMER[iTimer]));
4675 MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period);
4676 }
4677
4678 /**
4679 * @brief Get actual timer period value.
4680 * @rmtoll MPER MPER LL_HRTIM_TIM_GetPeriod\n
4681 * PERxR PERx LL_HRTIM_TIM_GetPeriod
4682 * @param HRTIMx High Resolution Timer instance
4683 * @param Timer This parameter can be one of the following values:
4684 * @arg @ref LL_HRTIM_TIMER_MASTER
4685 * @arg @ref LL_HRTIM_TIMER_A
4686 * @arg @ref LL_HRTIM_TIMER_B
4687 * @arg @ref LL_HRTIM_TIMER_C
4688 * @arg @ref LL_HRTIM_TIMER_D
4689 * @arg @ref LL_HRTIM_TIMER_E
4690 * @arg @ref LL_HRTIM_TIMER_F
4691 * @retval Period Value between 0 and 0xFFFF
4692 */
LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4693 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4694 {
4695 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4696 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
4697 REG_OFFSET_TAB_TIMER[iTimer]));
4698 return (READ_BIT(*pReg, HRTIM_MPER_MPER));
4699 }
4700
4701 /**
4702 * @brief Set the timer repetition period value.
4703 * @rmtoll MREP MREP LL_HRTIM_TIM_SetRepetition\n
4704 * REPxR REPx LL_HRTIM_TIM_SetRepetition
4705 * @param HRTIMx High Resolution Timer instance
4706 * @param Timer This parameter can be one of the following values:
4707 * @arg @ref LL_HRTIM_TIMER_MASTER
4708 * @arg @ref LL_HRTIM_TIMER_A
4709 * @arg @ref LL_HRTIM_TIMER_B
4710 * @arg @ref LL_HRTIM_TIMER_C
4711 * @arg @ref LL_HRTIM_TIMER_D
4712 * @arg @ref LL_HRTIM_TIMER_E
4713 * @arg @ref LL_HRTIM_TIMER_F
4714 * @param Repetition Value between 0 and 0xFF
4715 * @retval None
4716 */
LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Repetition)4717 __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition)
4718 {
4719 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4720 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
4721 REG_OFFSET_TAB_TIMER[iTimer]));
4722 MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition);
4723 }
4724
4725 /**
4726 * @brief Get actual timer repetition period value.
4727 * @rmtoll MREP MREP LL_HRTIM_TIM_GetRepetition\n
4728 * REPxR REPx LL_HRTIM_TIM_GetRepetition
4729 * @param HRTIMx High Resolution Timer instance
4730 * @param Timer This parameter can be one of the following values:
4731 * @arg @ref LL_HRTIM_TIMER_MASTER
4732 * @arg @ref LL_HRTIM_TIMER_A
4733 * @arg @ref LL_HRTIM_TIMER_B
4734 * @arg @ref LL_HRTIM_TIMER_C
4735 * @arg @ref LL_HRTIM_TIMER_D
4736 * @arg @ref LL_HRTIM_TIMER_E
4737 * @arg @ref LL_HRTIM_TIMER_F
4738 * @retval Repetition Value between 0 and 0xFF
4739 */
LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4740 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4741 {
4742 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4743 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
4744 REG_OFFSET_TAB_TIMER[iTimer]));
4745 return (READ_BIT(*pReg, HRTIM_MREP_MREP));
4746 }
4747
4748 /**
4749 * @brief Set the compare value of the compare unit 1.
4750 * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_SetCompare1\n
4751 * CMP1xR CMP1x LL_HRTIM_TIM_SetCompare1
4752 * @param HRTIMx High Resolution Timer instance
4753 * @param Timer This parameter can be one of the following values:
4754 * @arg @ref LL_HRTIM_TIMER_MASTER
4755 * @arg @ref LL_HRTIM_TIMER_A
4756 * @arg @ref LL_HRTIM_TIMER_B
4757 * @arg @ref LL_HRTIM_TIMER_C
4758 * @arg @ref LL_HRTIM_TIMER_D
4759 * @arg @ref LL_HRTIM_TIMER_E
4760 * @arg @ref LL_HRTIM_TIMER_F
4761 * @param CompareValue Compare value must be above or equal to 3
4762 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4763 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4764 * @retval None
4765 */
LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)4766 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
4767 {
4768 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4769 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
4770 REG_OFFSET_TAB_TIMER[iTimer]));
4771 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue);
4772 }
4773
4774 /**
4775 * @brief Get actual compare value of the compare unit 1.
4776 * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_GetCompare1\n
4777 * CMP1xR CMP1x LL_HRTIM_TIM_GetCompare1
4778 * @param HRTIMx High Resolution Timer instance
4779 * @param Timer This parameter can be one of the following values:
4780 * @arg @ref LL_HRTIM_TIMER_MASTER
4781 * @arg @ref LL_HRTIM_TIMER_A
4782 * @arg @ref LL_HRTIM_TIMER_B
4783 * @arg @ref LL_HRTIM_TIMER_C
4784 * @arg @ref LL_HRTIM_TIMER_D
4785 * @arg @ref LL_HRTIM_TIMER_E
4786 * @arg @ref LL_HRTIM_TIMER_F
4787 * @retval CompareValue Compare value must be above or equal to 3
4788 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4789 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4790 */
LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4791 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4792 {
4793 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4794 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
4795 REG_OFFSET_TAB_TIMER[iTimer]));
4796 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R));
4797 }
4798
4799 /**
4800 * @brief Set the compare value of the compare unit 2.
4801 * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_SetCompare2\n
4802 * CMP2xR CMP2x LL_HRTIM_TIM_SetCompare2
4803 * @param HRTIMx High Resolution Timer instance
4804 * @param Timer This parameter can be one of the following values:
4805 * @arg @ref LL_HRTIM_TIMER_MASTER
4806 * @arg @ref LL_HRTIM_TIMER_A
4807 * @arg @ref LL_HRTIM_TIMER_B
4808 * @arg @ref LL_HRTIM_TIMER_C
4809 * @arg @ref LL_HRTIM_TIMER_D
4810 * @arg @ref LL_HRTIM_TIMER_E
4811 * @arg @ref LL_HRTIM_TIMER_F
4812 * @param CompareValue Compare value must be above or equal to 3
4813 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4814 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4815 * @retval None
4816 */
LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)4817 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
4818 {
4819 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4820 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
4821 REG_OFFSET_TAB_TIMER[iTimer]));
4822 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue);
4823 }
4824
4825 /**
4826 * @brief Get actual compare value of the compare unit 2.
4827 * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_GetCompare2\n
4828 * CMP2xR CMP2x LL_HRTIM_TIM_GetCompare2\n
4829 * @param HRTIMx High Resolution Timer instance
4830 * @param Timer This parameter can be one of the following values:
4831 * @arg @ref LL_HRTIM_TIMER_MASTER
4832 * @arg @ref LL_HRTIM_TIMER_A
4833 * @arg @ref LL_HRTIM_TIMER_B
4834 * @arg @ref LL_HRTIM_TIMER_C
4835 * @arg @ref LL_HRTIM_TIMER_D
4836 * @arg @ref LL_HRTIM_TIMER_E
4837 * @arg @ref LL_HRTIM_TIMER_F
4838 * @retval CompareValue Compare value must be above or equal to 3
4839 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4840 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4841 */
LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4842 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4843 {
4844 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4845 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
4846 REG_OFFSET_TAB_TIMER[iTimer]));
4847 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R));
4848 }
4849
4850 /**
4851 * @brief Set the compare value of the compare unit 3.
4852 * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_SetCompare3\n
4853 * CMP3xR CMP3x LL_HRTIM_TIM_SetCompare3
4854 * @param HRTIMx High Resolution Timer instance
4855 * @param Timer This parameter can be one of the following values:
4856 * @arg @ref LL_HRTIM_TIMER_MASTER
4857 * @arg @ref LL_HRTIM_TIMER_A
4858 * @arg @ref LL_HRTIM_TIMER_B
4859 * @arg @ref LL_HRTIM_TIMER_C
4860 * @arg @ref LL_HRTIM_TIMER_D
4861 * @arg @ref LL_HRTIM_TIMER_E
4862 * @arg @ref LL_HRTIM_TIMER_F
4863 * @param CompareValue Compare value must be above or equal to 3
4864 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4865 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4866 * @retval None
4867 */
LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)4868 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
4869 {
4870 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4871 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
4872 REG_OFFSET_TAB_TIMER[iTimer]));
4873 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue);
4874 }
4875
4876 /**
4877 * @brief Get actual compare value of the compare unit 3.
4878 * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_GetCompare3\n
4879 * CMP3xR CMP3x LL_HRTIM_TIM_GetCompare3
4880 * @param HRTIMx High Resolution Timer instance
4881 * @param Timer This parameter can be one of the following values:
4882 * @arg @ref LL_HRTIM_TIMER_MASTER
4883 * @arg @ref LL_HRTIM_TIMER_A
4884 * @arg @ref LL_HRTIM_TIMER_B
4885 * @arg @ref LL_HRTIM_TIMER_C
4886 * @arg @ref LL_HRTIM_TIMER_D
4887 * @arg @ref LL_HRTIM_TIMER_E
4888 * @arg @ref LL_HRTIM_TIMER_F
4889 * @retval CompareValue Compare value must be above or equal to 3
4890 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4891 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4892 */
LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4893 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4894 {
4895 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4896 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
4897 REG_OFFSET_TAB_TIMER[iTimer]));
4898 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R));
4899 }
4900
4901 /**
4902 * @brief Set the compare value of the compare unit 4.
4903 * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_SetCompare4\n
4904 * CMP4xR CMP4x LL_HRTIM_TIM_SetCompare4
4905 * @param HRTIMx High Resolution Timer instance
4906 * @param Timer This parameter can be one of the following values:
4907 * @arg @ref LL_HRTIM_TIMER_MASTER
4908 * @arg @ref LL_HRTIM_TIMER_A
4909 * @arg @ref LL_HRTIM_TIMER_B
4910 * @arg @ref LL_HRTIM_TIMER_C
4911 * @arg @ref LL_HRTIM_TIMER_D
4912 * @arg @ref LL_HRTIM_TIMER_E
4913 * @arg @ref LL_HRTIM_TIMER_F
4914 * @param CompareValue Compare value must be above or equal to 3
4915 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4916 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4917 * @retval None
4918 */
LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)4919 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
4920 {
4921 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4922 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
4923 REG_OFFSET_TAB_TIMER[iTimer]));
4924 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue);
4925 }
4926
4927 /**
4928 * @brief Get actual compare value of the compare unit 4.
4929 * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_GetCompare4\n
4930 * CMP4xR CMP4x LL_HRTIM_TIM_GetCompare4
4931 * @param HRTIMx High Resolution Timer instance
4932 * @param Timer This parameter can be one of the following values:
4933 * @arg @ref LL_HRTIM_TIMER_MASTER
4934 * @arg @ref LL_HRTIM_TIMER_A
4935 * @arg @ref LL_HRTIM_TIMER_B
4936 * @arg @ref LL_HRTIM_TIMER_C
4937 * @arg @ref LL_HRTIM_TIMER_D
4938 * @arg @ref LL_HRTIM_TIMER_E
4939 * @arg @ref LL_HRTIM_TIMER_F
4940 * @retval CompareValue Compare value must be above or equal to 3
4941 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4942 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4943 */
LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4944 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4945 {
4946 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4947 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
4948 REG_OFFSET_TAB_TIMER[iTimer]));
4949 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R));
4950 }
4951
4952 /**
4953 * @brief Set the reset trigger of a timer counter.
4954 * @rmtoll RSTxR UPDT LL_HRTIM_TIM_SetResetTrig\n
4955 * RSTxR CMP2 LL_HRTIM_TIM_SetResetTrig\n
4956 * RSTxR CMP4 LL_HRTIM_TIM_SetResetTrig\n
4957 * RSTxR MSTPER LL_HRTIM_TIM_SetResetTrig\n
4958 * RSTxR MSTCMP1 LL_HRTIM_TIM_SetResetTrig\n
4959 * RSTxR MSTCMP2 LL_HRTIM_TIM_SetResetTrig\n
4960 * RSTxR MSTCMP3 LL_HRTIM_TIM_SetResetTrig\n
4961 * RSTxR MSTCMP4 LL_HRTIM_TIM_SetResetTrig\n
4962 * RSTxR EXTEVNT1 LL_HRTIM_TIM_SetResetTrig\n
4963 * RSTxR EXTEVNT2 LL_HRTIM_TIM_SetResetTrig\n
4964 * RSTxR EXTEVNT3 LL_HRTIM_TIM_SetResetTrig\n
4965 * RSTxR EXTEVNT4 LL_HRTIM_TIM_SetResetTrig\n
4966 * RSTxR EXTEVNT5 LL_HRTIM_TIM_SetResetTrig\n
4967 * RSTxR EXTEVNT6 LL_HRTIM_TIM_SetResetTrig\n
4968 * RSTxR EXTEVNT7 LL_HRTIM_TIM_SetResetTrig\n
4969 * RSTxR EXTEVNT8 LL_HRTIM_TIM_SetResetTrig\n
4970 * RSTxR EXTEVNT9 LL_HRTIM_TIM_SetResetTrig\n
4971 * RSTxR EXTEVNT10 LL_HRTIM_TIM_SetResetTrig\n
4972 * RSTxR TIMBCMP1 LL_HRTIM_TIM_SetResetTrig\n
4973 * RSTxR TIMBCMP2 LL_HRTIM_TIM_SetResetTrig\n
4974 * RSTxR TIMBCMP4 LL_HRTIM_TIM_SetResetTrig\n
4975 * RSTxR TIMCCMP1 LL_HRTIM_TIM_SetResetTrig\n
4976 * RSTxR TIMCCMP2 LL_HRTIM_TIM_SetResetTrig\n
4977 * RSTxR TIMCCMP4 LL_HRTIM_TIM_SetResetTrig\n
4978 * RSTxR TIMDCMP1 LL_HRTIM_TIM_SetResetTrig\n
4979 * RSTxR TIMDCMP2 LL_HRTIM_TIM_SetResetTrig\n
4980 * RSTxR TIMDCMP4 LL_HRTIM_TIM_SetResetTrig\n
4981 * RSTxR TIMECMP1 LL_HRTIM_TIM_SetResetTrig\n
4982 * RSTxR TIMECMP2 LL_HRTIM_TIM_SetResetTrig\n
4983 * RSTxR TIMECMP4 LL_HRTIM_TIM_SetResetTrig\n
4984 * RSTxR TIMFCMP1 LL_HRTIM_TIM_SetResetTrig\n
4985 * RSTxR TIMFCMP2 LL_HRTIM_TIM_SetResetTrig
4986 * @note The reset of the timer counter can be triggered by up to 30 events
4987 * that can be selected among the following sources:
4988 * @arg The timing unit: Compare 2, Compare 4 and Update (3 events).
4989 * @arg The master timer: Reset and Compare 1..4 (5 events).
4990 * @arg The external events EXTEVNT1..10 (10 events).
4991 * @arg All other timing units (e.g. Timer B..F for timer A): Compare 1, 2 and 4 (12 events).
4992 * @param HRTIMx High Resolution Timer instance
4993 * @param Timer This parameter can be one of the following values:
4994 * @arg @ref LL_HRTIM_TIMER_A
4995 * @arg @ref LL_HRTIM_TIMER_B
4996 * @arg @ref LL_HRTIM_TIMER_C
4997 * @arg @ref LL_HRTIM_TIMER_D
4998 * @arg @ref LL_HRTIM_TIMER_E
4999 * @arg @ref LL_HRTIM_TIMER_F
5000 * @param ResetTrig This parameter can be a combination of the following values:
5001 * @arg @ref LL_HRTIM_RESETTRIG_NONE
5002 * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
5003 * @arg @ref LL_HRTIM_RESETTRIG_CMP2
5004 * @arg @ref LL_HRTIM_RESETTRIG_CMP4
5005 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
5006 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
5007 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
5008 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
5009 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
5010 * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
5011 * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
5012 * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
5013 * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
5014 * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
5015 * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
5016 * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
5017 * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
5018 * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
5019 * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
5020 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
5021 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
5022 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
5023 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
5024 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
5025 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
5026 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
5027 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
5028 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
5029 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
5030 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
5031 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
5032 * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP1
5033 * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP2
5034 * @retval None
5035 */
LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t ResetTrig)5036 __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig)
5037 {
5038 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5039 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
5040 REG_OFFSET_TAB_TIMER[iTimer]));
5041 WRITE_REG(*pReg, ResetTrig);
5042 }
5043
5044 /**
5045 * @brief Get actual reset trigger of a timer counter.
5046 * @rmtoll RSTxR UPDT LL_HRTIM_TIM_GetResetTrig\n
5047 * RSTxR CMP2 LL_HRTIM_TIM_GetResetTrig\n
5048 * RSTxR CMP4 LL_HRTIM_TIM_GetResetTrig\n
5049 * RSTxR MSTPER LL_HRTIM_TIM_GetResetTrig\n
5050 * RSTxR MSTCMP1 LL_HRTIM_TIM_GetResetTrig\n
5051 * RSTxR MSTCMP2 LL_HRTIM_TIM_GetResetTrig\n
5052 * RSTxR MSTCMP3 LL_HRTIM_TIM_GetResetTrig\n
5053 * RSTxR MSTCMP4 LL_HRTIM_TIM_GetResetTrig\n
5054 * RSTxR EXTEVNT1 LL_HRTIM_TIM_GetResetTrig\n
5055 * RSTxR EXTEVNT2 LL_HRTIM_TIM_GetResetTrig\n
5056 * RSTxR EXTEVNT3 LL_HRTIM_TIM_GetResetTrig\n
5057 * RSTxR EXTEVNT4 LL_HRTIM_TIM_GetResetTrig\n
5058 * RSTxR EXTEVNT5 LL_HRTIM_TIM_GetResetTrig\n
5059 * RSTxR EXTEVNT6 LL_HRTIM_TIM_GetResetTrig\n
5060 * RSTxR EXTEVNT7 LL_HRTIM_TIM_GetResetTrig\n
5061 * RSTxR EXTEVNT8 LL_HRTIM_TIM_GetResetTrig\n
5062 * RSTxR EXTEVNT9 LL_HRTIM_TIM_GetResetTrig\n
5063 * RSTxR EXTEVNT10 LL_HRTIM_TIM_GetResetTrig\n
5064 * RSTxR TIMBCMP1 LL_HRTIM_TIM_GetResetTrig\n
5065 * RSTxR TIMBCMP2 LL_HRTIM_TIM_GetResetTrig\n
5066 * RSTxR TIMBCMP4 LL_HRTIM_TIM_GetResetTrig\n
5067 * RSTxR TIMCCMP1 LL_HRTIM_TIM_GetResetTrig\n
5068 * RSTxR TIMCCMP2 LL_HRTIM_TIM_GetResetTrig\n
5069 * RSTxR TIMCCMP4 LL_HRTIM_TIM_GetResetTrig\n
5070 * RSTxR TIMDCMP1 LL_HRTIM_TIM_GetResetTrig\n
5071 * RSTxR TIMDCMP2 LL_HRTIM_TIM_GetResetTrig\n
5072 * RSTxR TIMDCMP4 LL_HRTIM_TIM_GetResetTrig\n
5073 * RSTxR TIMECMP1 LL_HRTIM_TIM_GetResetTrig\n
5074 * RSTxR TIMECMP2 LL_HRTIM_TIM_GetResetTrig\n
5075 * RSTxR TIMECMP4 LL_HRTIM_TIM_GetResetTrig\n
5076 * RSTxR TIMFCMP1 LL_HRTIM_TIM_GetResetTrig\n
5077 * RSTxR TIMFCMP2 LL_HRTIM_TIM_GetResetTrig
5078 * @param HRTIMx High Resolution Timer instance
5079 * @param Timer This parameter can be one of the following values:
5080 * @arg @ref LL_HRTIM_TIMER_A
5081 * @arg @ref LL_HRTIM_TIMER_B
5082 * @arg @ref LL_HRTIM_TIMER_C
5083 * @arg @ref LL_HRTIM_TIMER_D
5084 * @arg @ref LL_HRTIM_TIMER_E
5085 * @arg @ref LL_HRTIM_TIMER_F
5086 * @retval ResetTrig Returned value can be one of the following values:
5087 * @arg @ref LL_HRTIM_RESETTRIG_NONE
5088 * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
5089 * @arg @ref LL_HRTIM_RESETTRIG_CMP2
5090 * @arg @ref LL_HRTIM_RESETTRIG_CMP4
5091 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
5092 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
5093 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
5094 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
5095 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
5096 * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
5097 * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
5098 * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
5099 * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
5100 * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
5101 * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
5102 * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
5103 * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
5104 * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
5105 * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
5106 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
5107 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
5108 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
5109 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
5110 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
5111 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
5112 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
5113 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
5114 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
5115 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
5116 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
5117 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
5118 * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP1
5119 * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP2
5120 */
LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5121 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5122 {
5123 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5124 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
5125 REG_OFFSET_TAB_TIMER[iTimer]));
5126 return (READ_REG(*pReg));
5127 }
5128
5129 /**
5130 * @brief Get captured value for capture unit 1.
5131 * @rmtoll CPT1xR CPT1x LL_HRTIM_TIM_GetCapture1
5132 * @param HRTIMx High Resolution Timer instance
5133 * @param Timer This parameter can be one of the following values:
5134 * @arg @ref LL_HRTIM_TIMER_A
5135 * @arg @ref LL_HRTIM_TIMER_B
5136 * @arg @ref LL_HRTIM_TIMER_C
5137 * @arg @ref LL_HRTIM_TIMER_D
5138 * @arg @ref LL_HRTIM_TIMER_E
5139 * @arg @ref LL_HRTIM_TIMER_F
5140 * @retval Captured value
5141 */
LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5142 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5143 {
5144 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5145 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
5146 REG_OFFSET_TAB_TIMER[iTimer]));
5147 return (READ_REG(*pReg));
5148 }
5149
5150 /**
5151 * @brief Get the counting direction when capture 1 event occurred.
5152 * @rmtoll CPT1xR DIR LL_HRTIM_TIM_GetCapture1Direction
5153 * @param HRTIMx High Resolution Timer instance
5154 * @param Timer This parameter can be one of the following values:
5155 * @arg @ref LL_HRTIM_TIMER_A
5156 * @arg @ref LL_HRTIM_TIMER_B
5157 * @arg @ref LL_HRTIM_TIMER_C
5158 * @arg @ref LL_HRTIM_TIMER_D
5159 * @arg @ref LL_HRTIM_TIMER_E
5160 * @arg @ref LL_HRTIM_TIMER_F
5161 * @retval Filter This parameter can be one of the following values:
5162 * @arg @ref LL_HRTIM_COUNTING_MODE_UP
5163 * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
5164 */
LL_HRTIM_TIM_GetCapture1Direction(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5165 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1Direction(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5166 {
5167 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5168 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
5169 REG_OFFSET_TAB_TIMER[iTimer]));
5170 return ((READ_BIT(*pReg, HRTIM_CPT1R_DIR) >> HRTIM_CPT1R_DIR_Pos) << HRTIM_TIMCR2_UDM_Pos);
5171 }
5172
5173 /**
5174 * @brief Get captured value for capture unit 2.
5175 * @rmtoll CPT2xR CPT2x LL_HRTIM_TIM_GetCapture2
5176 * @param HRTIMx High Resolution Timer instance
5177 * @param Timer This parameter can be one of the following values:
5178 * @arg @ref LL_HRTIM_TIMER_A
5179 * @arg @ref LL_HRTIM_TIMER_B
5180 * @arg @ref LL_HRTIM_TIMER_C
5181 * @arg @ref LL_HRTIM_TIMER_D
5182 * @arg @ref LL_HRTIM_TIMER_E
5183 * @arg @ref LL_HRTIM_TIMER_F
5184 * @retval Captured value
5185 */
LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5186 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5187 {
5188 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5189 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
5190 REG_OFFSET_TAB_TIMER[iTimer]));
5191 return (READ_REG(*pReg));
5192 }
5193
5194 /**
5195 * @brief Get the counting direction when capture 2 event occurred.
5196 * @rmtoll CPT2xR DIR LL_HRTIM_TIM_GetCapture2Direction
5197 * @param HRTIMx High Resolution Timer instance
5198 * @param Timer This parameter can be one of the following values:
5199 * @arg @ref LL_HRTIM_TIMER_A
5200 * @arg @ref LL_HRTIM_TIMER_B
5201 * @arg @ref LL_HRTIM_TIMER_C
5202 * @arg @ref LL_HRTIM_TIMER_D
5203 * @arg @ref LL_HRTIM_TIMER_E
5204 * @arg @ref LL_HRTIM_TIMER_F
5205 * @retval Filter This parameter can be one of the following values:
5206 * @arg @ref LL_HRTIM_COUNTING_MODE_UP
5207 * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
5208 */
LL_HRTIM_TIM_GetCapture2Direction(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5209 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2Direction(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5210 {
5211 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5212 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
5213 REG_OFFSET_TAB_TIMER[iTimer]));
5214 return ((READ_BIT(*pReg, HRTIM_CPT2R_DIR) >> HRTIM_CPT2R_DIR_Pos) << HRTIM_TIMCR2_UDM_Pos);
5215 }
5216
5217 /**
5218 * @brief Set the trigger of a capture unit for a given timer.
5219 * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_SetCaptureTrig\n
5220 * CPT1xCR UPDCPT LL_HRTIM_TIM_SetCaptureTrig\n
5221 * CPT1xCR EXEV1CPT LL_HRTIM_TIM_SetCaptureTrig\n
5222 * CPT1xCR EXEV2CPT LL_HRTIM_TIM_SetCaptureTrig\n
5223 * CPT1xCR EXEV3CPT LL_HRTIM_TIM_SetCaptureTrig\n
5224 * CPT1xCR EXEV4CPT LL_HRTIM_TIM_SetCaptureTrig\n
5225 * CPT1xCR EXEV5CPT LL_HRTIM_TIM_SetCaptureTrig\n
5226 * CPT1xCR EXEV6CPT LL_HRTIM_TIM_SetCaptureTrig\n
5227 * CPT1xCR EXEV7CPT LL_HRTIM_TIM_SetCaptureTrig\n
5228 * CPT1xCR EXEV8CPT LL_HRTIM_TIM_SetCaptureTrig\n
5229 * CPT1xCR EXEV9CPT LL_HRTIM_TIM_SetCaptureTrig\n
5230 * CPT1xCR EXEV10CPT LL_HRTIM_TIM_SetCaptureTrig\n
5231 * CPT1xCR TA1SET LL_HRTIM_TIM_SetCaptureTrig\n
5232 * CPT1xCR TA1RST LL_HRTIM_TIM_SetCaptureTrig\n
5233 * CPT1xCR TACMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5234 * CPT1xCR TACMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5235 * CPT1xCR TB1SET LL_HRTIM_TIM_SetCaptureTrig\n
5236 * CPT1xCR TB1RST LL_HRTIM_TIM_SetCaptureTrig\n
5237 * CPT1xCR TBCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5238 * CPT1xCR TBCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5239 * CPT1xCR TC1SET LL_HRTIM_TIM_SetCaptureTrig\n
5240 * CPT1xCR TC1RST LL_HRTIM_TIM_SetCaptureTrig\n
5241 * CPT1xCR TCCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5242 * CPT1xCR TCCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5243 * CPT1xCR TD1SET LL_HRTIM_TIM_SetCaptureTrig\n
5244 * CPT1xCR TD1RST LL_HRTIM_TIM_SetCaptureTrig\n
5245 * CPT1xCR TDCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5246 * CPT1xCR TDCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5247 * CPT1xCR TE1SET LL_HRTIM_TIM_SetCaptureTrig\n
5248 * CPT1xCR TE1RST LL_HRTIM_TIM_SetCaptureTrig\n
5249 * CPT1xCR TECMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5250 * CPT1xCR TECMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5251 * CPT1xCR TF1SET LL_HRTIM_TIM_SetCaptureTrig\n
5252 * CPT1xCR TF1RST LL_HRTIM_TIM_SetCaptureTrig\n
5253 * CPT1xCR TFCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5254 * CPT1xCR TFCMP2 LL_HRTIM_TIM_SetCaptureTrig
5255 * @param HRTIMx High Resolution Timer instance
5256 * @param Timer This parameter can be one of the following values:
5257 * @arg @ref LL_HRTIM_TIMER_A
5258 * @arg @ref LL_HRTIM_TIMER_B
5259 * @arg @ref LL_HRTIM_TIMER_C
5260 * @arg @ref LL_HRTIM_TIMER_D
5261 * @arg @ref LL_HRTIM_TIMER_E
5262 * @arg @ref LL_HRTIM_TIMER_F
5263 * @param CaptureUnit This parameter can be one of the following values:
5264 * @arg @ref LL_HRTIM_CAPTUREUNIT_1
5265 * @arg @ref LL_HRTIM_CAPTUREUNIT_2
5266 * @param CaptureTrig This parameter can be a combination of the following values:
5267 * @arg @ref LL_HRTIM_CAPTURETRIG_NONE
5268 * @arg @ref LL_HRTIM_CAPTURETRIG_SW
5269 * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
5270 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
5271 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
5272 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
5273 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
5274 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
5275 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
5276 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
5277 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
5278 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
5279 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
5280 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
5281 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
5282 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
5283 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
5284 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
5285 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
5286 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
5287 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
5288 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
5289 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
5290 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
5291 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
5292 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
5293 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
5294 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
5295 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
5296 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
5297 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
5298 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
5299 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
5300 * @arg @ref LL_HRTIM_CAPTURETRIG_TF1_SET
5301 * @arg @ref LL_HRTIM_CAPTURETRIG_TF1_RESET
5302 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP1
5303 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP2
5304 * @retval None
5305 */
LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CaptureUnit,uint64_t CaptureTrig)5306 __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit,
5307 uint64_t CaptureTrig)
5308 {
5309 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5310 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
5311 REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U)));
5312
5313 uint32_t cfg1 = (uint32_t)(CaptureTrig & 0x0000000000000FFFU);
5314 uint32_t cfg2 = (uint32_t)((CaptureTrig & 0xFFFFF00F00000000U) >> 32U);
5315
5316 cfg2 = (cfg2 & REG_MASK_TAB_CPT[iTimer]) | ((cfg2 & 0x0000000FU) << (REG_SHIFT_TAB_CPT[iTimer]));
5317
5318 WRITE_REG(*pReg, (cfg1 | cfg2));
5319
5320 }
5321
5322 /**
5323 * @brief Get actual trigger of a capture unit for a given timer.
5324 * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_GetCaptureTrig\n
5325 * CPT1xCR UPDCPT LL_HRTIM_TIM_GetCaptureTrig\n
5326 * CPT1xCR EXEV1CPT LL_HRTIM_TIM_GetCaptureTrig\n
5327 * CPT1xCR EXEV2CPT LL_HRTIM_TIM_GetCaptureTrig\n
5328 * CPT1xCR EXEV3CPT LL_HRTIM_TIM_GetCaptureTrig\n
5329 * CPT1xCR EXEV4CPT LL_HRTIM_TIM_GetCaptureTrig\n
5330 * CPT1xCR EXEV5CPT LL_HRTIM_TIM_GetCaptureTrig\n
5331 * CPT1xCR EXEV6CPT LL_HRTIM_TIM_GetCaptureTrig\n
5332 * CPT1xCR EXEV7CPT LL_HRTIM_TIM_GetCaptureTrig\n
5333 * CPT1xCR EXEV8CPT LL_HRTIM_TIM_GetCaptureTrig\n
5334 * CPT1xCR EXEV9CPT LL_HRTIM_TIM_GetCaptureTrig\n
5335 * CPT1xCR EXEV10CPT LL_HRTIM_TIM_GetCaptureTrig\n
5336 * CPT1xCR TA1SET LL_HRTIM_TIM_GetCaptureTrig\n
5337 * CPT1xCR TA1RST LL_HRTIM_TIM_GetCaptureTrig\n
5338 * CPT1xCR TACMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5339 * CPT1xCR TACMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5340 * CPT1xCR TB1SET LL_HRTIM_TIM_GetCaptureTrig\n
5341 * CPT1xCR TB1RST LL_HRTIM_TIM_GetCaptureTrig\n
5342 * CPT1xCR TBCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5343 * CPT1xCR TBCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5344 * CPT1xCR TC1SET LL_HRTIM_TIM_GetCaptureTrig\n
5345 * CPT1xCR TC1RST LL_HRTIM_TIM_GetCaptureTrig\n
5346 * CPT1xCR TCCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5347 * CPT1xCR TCCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5348 * CPT1xCR TD1SET LL_HRTIM_TIM_GetCaptureTrig\n
5349 * CPT1xCR TD1RST LL_HRTIM_TIM_GetCaptureTrig\n
5350 * CPT1xCR TDCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5351 * CPT1xCR TDCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5352 * CPT1xCR TE1SET LL_HRTIM_TIM_GetCaptureTrig\n
5353 * CPT1xCR TE1RST LL_HRTIM_TIM_GetCaptureTrig\n
5354 * CPT1xCR TECMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5355 * CPT1xCR TECMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5356 * CPT1xCR TF1SET LL_HRTIM_TIM_GetCaptureTrig\n
5357 * CPT1xCR TF1RST LL_HRTIM_TIM_GetCaptureTrig\n
5358 * CPT1xCR TFCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5359 * CPT1xCR TFCMP2 LL_HRTIM_TIM_GetCaptureTrig
5360 * @param HRTIMx High Resolution Timer instance
5361 * @param Timer This parameter can be one of the following values:
5362 * @arg @ref LL_HRTIM_TIMER_A
5363 * @arg @ref LL_HRTIM_TIMER_B
5364 * @arg @ref LL_HRTIM_TIMER_C
5365 * @arg @ref LL_HRTIM_TIMER_D
5366 * @arg @ref LL_HRTIM_TIMER_E
5367 * @arg @ref LL_HRTIM_TIMER_F
5368 * @param CaptureUnit This parameter can be one of the following values:
5369 * @arg @ref LL_HRTIM_CAPTUREUNIT_1
5370 * @arg @ref LL_HRTIM_CAPTUREUNIT_2
5371 * @retval CaptureTrig This parameter can be a combination of the following values:
5372 * @arg @ref LL_HRTIM_CAPTURETRIG_NONE
5373 * @arg @ref LL_HRTIM_CAPTURETRIG_SW
5374 * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
5375 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
5376 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
5377 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
5378 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
5379 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
5380 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
5381 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
5382 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
5383 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
5384 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
5385 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
5386 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
5387 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
5388 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
5389 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
5390 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
5391 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
5392 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
5393 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
5394 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
5395 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
5396 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
5397 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
5398 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
5399 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
5400 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
5401 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
5402 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
5403 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
5404 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
5405 * @arg @ref LL_HRTIM_CAPTURETRIG_TF1_SET
5406 * @arg @ref LL_HRTIM_CAPTURETRIG_TF1_RESET
5407 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP1
5408 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP2
5409 */
LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CaptureUnit)5410 __STATIC_INLINE uint64_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)
5411 {
5412 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5413 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
5414 (uint32_t)REG_OFFSET_TAB_TIMER[iTimer & 0x7U] + (CaptureUnit * 4U)));
5415
5416 uint64_t cfg;
5417 uint32_t CaptureTrig = READ_REG(*pReg);
5418
5419 cfg = (uint64_t)(uint32_t)(((CaptureTrig & 0xFFFFF000U) & (uint32_t)REG_MASK_TAB_CPT[iTimer]) | (((CaptureTrig & 0xFFFFF000U) & (uint32_t)~REG_MASK_TAB_CPT[iTimer]) >> (REG_SHIFT_TAB_CPT[iTimer])));
5420
5421 return ((uint64_t)(((uint64_t)CaptureTrig & (uint64_t)0x00000FFFU) | (uint64_t)((cfg) << 32U)));
5422 }
5423
5424 /**
5425 * @brief Enable deadtime insertion for a given timer.
5426 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_EnableDeadTime
5427 * @param HRTIMx High Resolution Timer instance
5428 * @param Timer This parameter can be one of the following values:
5429 * @arg @ref LL_HRTIM_TIMER_A
5430 * @arg @ref LL_HRTIM_TIMER_B
5431 * @arg @ref LL_HRTIM_TIMER_C
5432 * @arg @ref LL_HRTIM_TIMER_D
5433 * @arg @ref LL_HRTIM_TIMER_E
5434 * @arg @ref LL_HRTIM_TIMER_F
5435 * @retval None
5436 */
LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5437 __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5438 {
5439 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5440 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5441 REG_OFFSET_TAB_TIMER[iTimer]));
5442 SET_BIT(*pReg, HRTIM_OUTR_DTEN);
5443 }
5444
5445 /**
5446 * @brief Disable deadtime insertion for a given timer.
5447 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_DisableDeadTime
5448 * @param HRTIMx High Resolution Timer instance
5449 * @param Timer This parameter can be one of the following values:
5450 * @arg @ref LL_HRTIM_TIMER_A
5451 * @arg @ref LL_HRTIM_TIMER_B
5452 * @arg @ref LL_HRTIM_TIMER_C
5453 * @arg @ref LL_HRTIM_TIMER_D
5454 * @arg @ref LL_HRTIM_TIMER_E
5455 * @arg @ref LL_HRTIM_TIMER_F
5456 * @retval None
5457 */
LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5458 __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5459 {
5460 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5461 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5462 REG_OFFSET_TAB_TIMER[iTimer]));
5463 CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN);
5464 }
5465
5466 /**
5467 * @brief Indicate whether deadtime insertion is enabled for a given timer.
5468 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_IsEnabledDeadTime
5469 * @param HRTIMx High Resolution Timer instance
5470 * @param Timer This parameter can be one of the following values:
5471 * @arg @ref LL_HRTIM_TIMER_A
5472 * @arg @ref LL_HRTIM_TIMER_B
5473 * @arg @ref LL_HRTIM_TIMER_C
5474 * @arg @ref LL_HRTIM_TIMER_D
5475 * @arg @ref LL_HRTIM_TIMER_E
5476 * @arg @ref LL_HRTIM_TIMER_F
5477 * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0).
5478 */
LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5479 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5480 {
5481 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5482 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5483 REG_OFFSET_TAB_TIMER[iTimer]));
5484
5485 return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL);
5486 }
5487
5488 /**
5489 * @brief Set the delayed protection (DLYPRT) mode.
5490 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_SetDLYPRTMode\n
5491 * OUTxR DLYPRT LL_HRTIM_TIM_SetDLYPRTMode
5492 * @note This function must be called prior enabling the delayed protection
5493 * @note Balanced Idle mode is only available in push-pull mode
5494 * @param HRTIMx High Resolution Timer instance
5495 * @param Timer This parameter can be one of the following values:
5496 * @arg @ref LL_HRTIM_TIMER_A
5497 * @arg @ref LL_HRTIM_TIMER_B
5498 * @arg @ref LL_HRTIM_TIMER_C
5499 * @arg @ref LL_HRTIM_TIMER_D
5500 * @arg @ref LL_HRTIM_TIMER_E
5501 * @arg @ref LL_HRTIM_TIMER_F
5502 * @param DLYPRTMode Delayed protection (DLYPRT) mode
5503 *
5504 * For timers A, B and C this parameter can be one of the following values:
5505 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
5506 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
5507 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
5508 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
5509 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
5510 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
5511 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
5512 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
5513 *
5514 * For timers D, E and F this parameter can be one of the following values:
5515 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
5516 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
5517 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
5518 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
5519 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
5520 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
5521 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
5522 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
5523 * @retval None
5524 */
LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t DLYPRTMode)5525 __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode)
5526 {
5527 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5528 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5529 REG_OFFSET_TAB_TIMER[iTimer]));
5530 MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode);
5531 }
5532
5533 /**
5534 * @brief Get the delayed protection (DLYPRT) mode.
5535 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_GetDLYPRTMode\n
5536 * OUTxR DLYPRT LL_HRTIM_TIM_GetDLYPRTMode
5537 * @param HRTIMx High Resolution Timer instance
5538 * @param Timer This parameter can be one of the following values:
5539 * @arg @ref LL_HRTIM_TIMER_A
5540 * @arg @ref LL_HRTIM_TIMER_B
5541 * @arg @ref LL_HRTIM_TIMER_C
5542 * @arg @ref LL_HRTIM_TIMER_D
5543 * @arg @ref LL_HRTIM_TIMER_E
5544 * @arg @ref LL_HRTIM_TIMER_F
5545 * @retval DLYPRTMode Delayed protection (DLYPRT) mode
5546 *
5547 * For timers A, B and C this parameter can be one of the following values:
5548 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
5549 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
5550 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
5551 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
5552 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
5553 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
5554 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
5555 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
5556 *
5557 * For timers D, E and F this parameter can be one of the following values:
5558 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
5559 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
5560 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
5561 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
5562 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
5563 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
5564 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
5565 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
5566 */
LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5567 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5568 {
5569 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5570 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5571 REG_OFFSET_TAB_TIMER[iTimer]));
5572 return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT));
5573 }
5574
5575 /**
5576 * @brief Enable delayed protection (DLYPRT) for a given timer.
5577 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_EnableDLYPRT
5578 * @note This function must not be called once the concerned timer is enabled
5579 * @param HRTIMx High Resolution Timer instance
5580 * @param Timer This parameter can be one of the following values:
5581 * @arg @ref LL_HRTIM_TIMER_A
5582 * @arg @ref LL_HRTIM_TIMER_B
5583 * @arg @ref LL_HRTIM_TIMER_C
5584 * @arg @ref LL_HRTIM_TIMER_D
5585 * @arg @ref LL_HRTIM_TIMER_E
5586 * @arg @ref LL_HRTIM_TIMER_F
5587 * @retval None
5588 */
LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5589 __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5590 {
5591 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5592 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5593 REG_OFFSET_TAB_TIMER[iTimer]));
5594 SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
5595 }
5596
5597 /**
5598 * @brief Disable delayed protection (DLYPRT) for a given timer.
5599 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_DisableDLYPRT
5600 * @note This function must not be called once the concerned timer is enabled
5601 * @param HRTIMx High Resolution Timer instance
5602 * @param Timer This parameter can be one of the following values:
5603 * @arg @ref LL_HRTIM_TIMER_A
5604 * @arg @ref LL_HRTIM_TIMER_B
5605 * @arg @ref LL_HRTIM_TIMER_C
5606 * @arg @ref LL_HRTIM_TIMER_D
5607 * @arg @ref LL_HRTIM_TIMER_E
5608 * @arg @ref LL_HRTIM_TIMER_F
5609 * @retval None
5610 */
LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5611 __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5612 {
5613 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5614 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5615 REG_OFFSET_TAB_TIMER[iTimer]));
5616 CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
5617 }
5618
5619 /**
5620 * @brief Indicate whether delayed protection (DLYPRT) is enabled for a given timer.
5621 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_IsEnabledDLYPRT
5622 * @param HRTIMx High Resolution Timer instance
5623 * @param Timer This parameter can be one of the following values:
5624 * @arg @ref LL_HRTIM_TIMER_A
5625 * @arg @ref LL_HRTIM_TIMER_B
5626 * @arg @ref LL_HRTIM_TIMER_C
5627 * @arg @ref LL_HRTIM_TIMER_D
5628 * @arg @ref LL_HRTIM_TIMER_E
5629 * @arg @ref LL_HRTIM_TIMER_F
5630 * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
5631 */
LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5632 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5633 {
5634 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5635 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5636 REG_OFFSET_TAB_TIMER[iTimer]));
5637 return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL);
5638 }
5639
5640 /**
5641 * @brief Enable the Balanced Idle Automatic Resume (BIAR) for a given timer.
5642 * @rmtoll OUTxR BIAR LL_HRTIM_TIM_EnableBIAR
5643 * @note This function must not be called once the concerned timer is enabled
5644 * @param HRTIMx High Resolution Timer instance
5645 * @param Timer This parameter can be one of the following values:
5646 * @arg @ref LL_HRTIM_TIMER_A
5647 * @arg @ref LL_HRTIM_TIMER_B
5648 * @arg @ref LL_HRTIM_TIMER_C
5649 * @arg @ref LL_HRTIM_TIMER_D
5650 * @arg @ref LL_HRTIM_TIMER_E
5651 * @arg @ref LL_HRTIM_TIMER_F
5652 * @retval None
5653 */
LL_HRTIM_TIM_EnableBIAR(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5654 __STATIC_INLINE void LL_HRTIM_TIM_EnableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5655 {
5656 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5657 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5658 REG_OFFSET_TAB_TIMER[iTimer]));
5659 SET_BIT(*pReg, HRTIM_OUTR_BIAR);
5660 }
5661
5662 /**
5663 * @brief Disable the Balanced Idle Automatic Resume (BIAR) for a given timer.
5664 * @rmtoll OUTxR BIAR LL_HRTIM_TIM_DisableBIAR
5665 * @note This function must not be called once the concerned timer is enabled
5666 * @param HRTIMx High Resolution Timer instance
5667 * @param Timer This parameter can be one of the following values:
5668 * @arg @ref LL_HRTIM_TIMER_A
5669 * @arg @ref LL_HRTIM_TIMER_B
5670 * @arg @ref LL_HRTIM_TIMER_C
5671 * @arg @ref LL_HRTIM_TIMER_D
5672 * @arg @ref LL_HRTIM_TIMER_E
5673 * @arg @ref LL_HRTIM_TIMER_F
5674 * @retval None
5675 */
LL_HRTIM_TIM_DisableBIAR(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5676 __STATIC_INLINE void LL_HRTIM_TIM_DisableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5677 {
5678 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5679 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].OUTxR) +
5680 REG_OFFSET_TAB_TIMER[iTimer]));
5681 CLEAR_BIT(*pReg, HRTIM_OUTR_BIAR);
5682 }
5683
5684 /**
5685 * @brief Indicate whether the Balanced Idle Automatic Resume (BIAR) is enabled for a given timer.
5686 * @rmtoll OUTxR BIAR LL_HRTIM_TIM_IsEnabledBIAR
5687 * @param HRTIMx High Resolution Timer instance
5688 * @param Timer This parameter can be one of the following values:
5689 * @arg @ref LL_HRTIM_TIMER_A
5690 * @arg @ref LL_HRTIM_TIMER_B
5691 * @arg @ref LL_HRTIM_TIMER_C
5692 * @arg @ref LL_HRTIM_TIMER_D
5693 * @arg @ref LL_HRTIM_TIMER_E
5694 * @arg @ref LL_HRTIM_TIMER_F
5695 * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
5696 */
LL_HRTIM_TIM_IsEnabledBIAR(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5697 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5698 {
5699 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5700 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5701 REG_OFFSET_TAB_TIMER[iTimer]));
5702
5703 return ((READ_BIT(*pReg, HRTIM_OUTR_BIAR) == (HRTIM_OUTR_BIAR)) ? 1UL : 0UL);
5704 }
5705
5706 /**
5707 * @brief Enable the fault channel(s) for a given timer.
5708 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_EnableFault\n
5709 * FLTxR FLT2EN LL_HRTIM_TIM_EnableFault\n
5710 * FLTxR FLT3EN LL_HRTIM_TIM_EnableFault\n
5711 * FLTxR FLT4EN LL_HRTIM_TIM_EnableFault\n
5712 * FLTxR FLT5EN LL_HRTIM_TIM_EnableFault\n
5713 * FLTxR FLT6EN LL_HRTIM_TIM_EnableFault
5714 * @param HRTIMx High Resolution Timer instance
5715 * @param Timer This parameter can be one of the following values:
5716 * @arg @ref LL_HRTIM_TIMER_A
5717 * @arg @ref LL_HRTIM_TIMER_B
5718 * @arg @ref LL_HRTIM_TIMER_C
5719 * @arg @ref LL_HRTIM_TIMER_D
5720 * @arg @ref LL_HRTIM_TIMER_E
5721 * @arg @ref LL_HRTIM_TIMER_F
5722 * @param Faults This parameter can be a combination of the following values:
5723 * @arg @ref LL_HRTIM_FAULT_1
5724 * @arg @ref LL_HRTIM_FAULT_2
5725 * @arg @ref LL_HRTIM_FAULT_3
5726 * @arg @ref LL_HRTIM_FAULT_4
5727 * @arg @ref LL_HRTIM_FAULT_5
5728 * @arg @ref LL_HRTIM_FAULT_6
5729 * @retval None
5730 */
LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Faults)5731 __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
5732 {
5733 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5734 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
5735 REG_OFFSET_TAB_TIMER[iTimer]));
5736 SET_BIT(*pReg, Faults);
5737 }
5738
5739 /**
5740 * @brief Disable the fault channel(s) for a given timer.
5741 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_DisableFault\n
5742 * FLTxR FLT2EN LL_HRTIM_TIM_DisableFault\n
5743 * FLTxR FLT3EN LL_HRTIM_TIM_DisableFault\n
5744 * FLTxR FLT4EN LL_HRTIM_TIM_DisableFault\n
5745 * FLTxR FLT5EN LL_HRTIM_TIM_DisableFault\n
5746 * FLTxR FLT6EN LL_HRTIM_TIM_DisableFault
5747 * @param HRTIMx High Resolution Timer instance
5748 * @param Timer This parameter can be one of the following values:
5749 * @arg @ref LL_HRTIM_TIMER_A
5750 * @arg @ref LL_HRTIM_TIMER_B
5751 * @arg @ref LL_HRTIM_TIMER_C
5752 * @arg @ref LL_HRTIM_TIMER_D
5753 * @arg @ref LL_HRTIM_TIMER_E
5754 * @arg @ref LL_HRTIM_TIMER_F
5755 * @param Faults This parameter can be a combination of the following values:
5756 * @arg @ref LL_HRTIM_FAULT_1
5757 * @arg @ref LL_HRTIM_FAULT_2
5758 * @arg @ref LL_HRTIM_FAULT_3
5759 * @arg @ref LL_HRTIM_FAULT_4
5760 * @arg @ref LL_HRTIM_FAULT_5
5761 * @arg @ref LL_HRTIM_FAULT_6
5762 * @retval None
5763 */
LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Faults)5764 __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
5765 {
5766 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5767 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
5768 REG_OFFSET_TAB_TIMER[iTimer]));
5769 CLEAR_BIT(*pReg, Faults);
5770 }
5771
5772 /**
5773 * @brief Indicate whether the fault channel is enabled for a given timer.
5774 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_IsEnabledFault\n
5775 * FLTxR FLT2EN LL_HRTIM_TIM_IsEnabledFault\n
5776 * FLTxR FLT3EN LL_HRTIM_TIM_IsEnabledFault\n
5777 * FLTxR FLT4EN LL_HRTIM_TIM_IsEnabledFault\n
5778 * FLTxR FLT5EN LL_HRTIM_TIM_IsEnabledFault\n
5779 * FLTxR FLT6EN LL_HRTIM_TIM_IsEnabledFault
5780 * @param HRTIMx High Resolution Timer instance
5781 * @param Timer This parameter can be one of the following values:
5782 * @arg @ref LL_HRTIM_TIMER_A
5783 * @arg @ref LL_HRTIM_TIMER_B
5784 * @arg @ref LL_HRTIM_TIMER_C
5785 * @arg @ref LL_HRTIM_TIMER_D
5786 * @arg @ref LL_HRTIM_TIMER_E
5787 * @arg @ref LL_HRTIM_TIMER_F
5788 * @param Fault This parameter can be one of the following values:
5789 * @arg @ref LL_HRTIM_FAULT_1
5790 * @arg @ref LL_HRTIM_FAULT_2
5791 * @arg @ref LL_HRTIM_FAULT_3
5792 * @arg @ref LL_HRTIM_FAULT_4
5793 * @arg @ref LL_HRTIM_FAULT_5
5794 * @arg @ref LL_HRTIM_FAULT_6
5795 * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0).
5796 */
LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Fault)5797 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)
5798 {
5799 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5800 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
5801 REG_OFFSET_TAB_TIMER[iTimer]));
5802
5803 return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL);
5804 }
5805
5806 /**
5807 * @brief Lock the fault conditioning set-up for a given timer.
5808 * @rmtoll FLTxR FLTLCK LL_HRTIM_TIM_LockFault
5809 * @note Timer fault-related set-up is frozen until the next HRTIM or system reset
5810 * @param HRTIMx High Resolution Timer instance
5811 * @param Timer This parameter can be one of the following values:
5812 * @arg @ref LL_HRTIM_TIMER_A
5813 * @arg @ref LL_HRTIM_TIMER_B
5814 * @arg @ref LL_HRTIM_TIMER_C
5815 * @arg @ref LL_HRTIM_TIMER_D
5816 * @arg @ref LL_HRTIM_TIMER_E
5817 * @arg @ref LL_HRTIM_TIMER_F
5818 * @retval None
5819 */
LL_HRTIM_TIM_LockFault(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5820 __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5821 {
5822 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5823 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
5824 REG_OFFSET_TAB_TIMER[iTimer]));
5825 SET_BIT(*pReg, HRTIM_FLTR_FLTLCK);
5826 }
5827
5828 /**
5829 * @brief Define how the timer behaves during a burst mode operation.
5830 * @rmtoll BMCR MTBM LL_HRTIM_TIM_SetBurstModeOption\n
5831 * BMCR TABM LL_HRTIM_TIM_SetBurstModeOption\n
5832 * BMCR TBBM LL_HRTIM_TIM_SetBurstModeOption\n
5833 * BMCR TCBM LL_HRTIM_TIM_SetBurstModeOption\n
5834 * BMCR TDBM LL_HRTIM_TIM_SetBurstModeOption\n
5835 * BMCR TEBM LL_HRTIM_TIM_SetBurstModeOption\n
5836 * BMCR TFBM LL_HRTIM_TIM_SetBurstModeOption
5837 * @note This function must not be called when the burst mode is enabled
5838 * @param HRTIMx High Resolution Timer instance
5839 * @param Timer This parameter can be one of the following values:
5840 * @arg @ref LL_HRTIM_TIMER_MASTER
5841 * @arg @ref LL_HRTIM_TIMER_A
5842 * @arg @ref LL_HRTIM_TIMER_B
5843 * @arg @ref LL_HRTIM_TIMER_C
5844 * @arg @ref LL_HRTIM_TIMER_D
5845 * @arg @ref LL_HRTIM_TIMER_E
5846 * @arg @ref LL_HRTIM_TIMER_F
5847 * @param BurtsModeOption This parameter can be one of the following values:
5848 * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
5849 * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
5850 * @retval None
5851 */
LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t BurtsModeOption)5852 __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption)
5853 {
5854 uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
5855 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer);
5856 }
5857
5858 /**
5859 * @brief Retrieve how the timer behaves during a burst mode operation.
5860 * @rmtoll BMCR MCR LL_HRTIM_TIM_GetBurstModeOption\n
5861 * BMCR TABM LL_HRTIM_TIM_GetBurstModeOption\n
5862 * BMCR TBBM LL_HRTIM_TIM_GetBurstModeOption\n
5863 * BMCR TCBM LL_HRTIM_TIM_GetBurstModeOption\n
5864 * BMCR TDBM LL_HRTIM_TIM_GetBurstModeOption\n
5865 * BMCR TEBM LL_HRTIM_TIM_GetBurstModeOption\n
5866 * BMCR TFBM LL_HRTIM_TIM_GetBurstModeOption
5867 * @param HRTIMx High Resolution Timer instance
5868 * @param Timer This parameter can be one of the following values:
5869 * @arg @ref LL_HRTIM_TIMER_MASTER
5870 * @arg @ref LL_HRTIM_TIMER_A
5871 * @arg @ref LL_HRTIM_TIMER_B
5872 * @arg @ref LL_HRTIM_TIMER_C
5873 * @arg @ref LL_HRTIM_TIMER_D
5874 * @arg @ref LL_HRTIM_TIMER_E
5875 * @arg @ref LL_HRTIM_TIMER_F
5876 * @retval BurtsMode This parameter can be one of the following values:
5877 * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
5878 * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
5879 */
LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5880 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5881 {
5882 uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
5883 return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer);
5884 }
5885
5886 /**
5887 * @brief Program which registers are to be written by Burst DMA transfers.
5888 * @rmtoll BDMUPDR MTBM LL_HRTIM_TIM_ConfigBurstDMA\n
5889 * BDMUPDR MICR LL_HRTIM_TIM_ConfigBurstDMA\n
5890 * BDMUPDR MDIER LL_HRTIM_TIM_ConfigBurstDMA\n
5891 * BDMUPDR MCNT LL_HRTIM_TIM_ConfigBurstDMA\n
5892 * BDMUPDR MPER LL_HRTIM_TIM_ConfigBurstDMA\n
5893 * BDMUPDR MREP LL_HRTIM_TIM_ConfigBurstDMA\n
5894 * BDMUPDR MCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
5895 * BDMUPDR MCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
5896 * BDMUPDR MCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
5897 * BDMUPDR MCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
5898 * BDTxUPDR TIMxCR LL_HRTIM_TIM_ConfigBurstDMA\n
5899 * BDTxUPDR TIMxICR LL_HRTIM_TIM_ConfigBurstDMA\n
5900 * BDTxUPDR TIMxDIER LL_HRTIM_TIM_ConfigBurstDMA\n
5901 * BDTxUPDR TIMxCNT LL_HRTIM_TIM_ConfigBurstDMA\n
5902 * BDTxUPDR TIMxPER LL_HRTIM_TIM_ConfigBurstDMA\n
5903 * BDTxUPDR TIMxREP LL_HRTIM_TIM_ConfigBurstDMA\n
5904 * BDTxUPDR TIMxCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
5905 * BDTxUPDR TIMxCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
5906 * BDTxUPDR TIMxCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
5907 * BDTxUPDR TIMxCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
5908 * BDTxUPDR TIMxDTR LL_HRTIM_TIM_ConfigBurstDMA\n
5909 * BDTxUPDR TIMxSET1R LL_HRTIM_TIM_ConfigBurstDMA\n
5910 * BDTxUPDR TIMxRST1R LL_HRTIM_TIM_ConfigBurstDMA\n
5911 * BDTxUPDR TIMxSET2R LL_HRTIM_TIM_ConfigBurstDMA\n
5912 * BDTxUPDR TIMxRST2R LL_HRTIM_TIM_ConfigBurstDMA\n
5913 * BDTxUPDR TIMxEEFR1 LL_HRTIM_TIM_ConfigBurstDMA\n
5914 * BDTxUPDR TIMxEEFR2 LL_HRTIM_TIM_ConfigBurstDMA\n
5915 * BDTxUPDR TIMxRSTR LL_HRTIM_TIM_ConfigBurstDMA\n
5916 * BDTxUPDR TIMxOUTR LL_HRTIM_TIM_ConfigBurstDMA\n
5917 * BDTxUPDR TIMxLTCH LL_HRTIM_TIM_ConfigBurstDMA
5918 * @param HRTIMx High Resolution Timer instance
5919 * @param Timer This parameter can be one of the following values:
5920 * @arg @ref LL_HRTIM_TIMER_MASTER
5921 * @arg @ref LL_HRTIM_TIMER_A
5922 * @arg @ref LL_HRTIM_TIMER_B
5923 * @arg @ref LL_HRTIM_TIMER_C
5924 * @arg @ref LL_HRTIM_TIMER_D
5925 * @arg @ref LL_HRTIM_TIMER_E
5926 * @arg @ref LL_HRTIM_TIMER_F
5927 * @param Registers Registers to be updated by the DMA request
5928 *
5929 * For Master timer this parameter can be can be a combination of the following values:
5930 * @arg @ref LL_HRTIM_BURSTDMA_NONE
5931 * @arg @ref LL_HRTIM_BURSTDMA_MCR
5932 * @arg @ref LL_HRTIM_BURSTDMA_MICR
5933 * @arg @ref LL_HRTIM_BURSTDMA_MDIER
5934 * @arg @ref LL_HRTIM_BURSTDMA_MCNT
5935 * @arg @ref LL_HRTIM_BURSTDMA_MPER
5936 * @arg @ref LL_HRTIM_BURSTDMA_MREP
5937 * @arg @ref LL_HRTIM_BURSTDMA_MCMP1
5938 * @arg @ref LL_HRTIM_BURSTDMA_MCMP2
5939 * @arg @ref LL_HRTIM_BURSTDMA_MCMP3
5940 * @arg @ref LL_HRTIM_BURSTDMA_MCMP4
5941 *
5942 * For Timers A..F this parameter can be can be a combination of the following values:
5943 * @arg @ref LL_HRTIM_BURSTDMA_NONE
5944 * @arg @ref LL_HRTIM_BURSTDMA_TIMMCR
5945 * @arg @ref LL_HRTIM_BURSTDMA_TIMICR
5946 * @arg @ref LL_HRTIM_BURSTDMA_TIMDIER
5947 * @arg @ref LL_HRTIM_BURSTDMA_TIMCNT
5948 * @arg @ref LL_HRTIM_BURSTDMA_TIMPER
5949 * @arg @ref LL_HRTIM_BURSTDMA_TIMREP
5950 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP1
5951 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP2
5952 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP3
5953 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP4
5954 * @arg @ref LL_HRTIM_BURSTDMA_TIMDTR
5955 * @arg @ref LL_HRTIM_BURSTDMA_TIMSET1R
5956 * @arg @ref LL_HRTIM_BURSTDMA_TIMRST1R
5957 * @arg @ref LL_HRTIM_BURSTDMA_TIMSET2R
5958 * @arg @ref LL_HRTIM_BURSTDMA_TIMRST2R
5959 * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR1
5960 * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR2
5961 * @arg @ref LL_HRTIM_BURSTDMA_TIMRSTR
5962 * @arg @ref LL_HRTIM_BURSTDMA_TIMCHPR
5963 * @arg @ref LL_HRTIM_BURSTDMA_TIMOUTR
5964 * @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR
5965 * @arg @ref LL_HRTIM_BURSTDMA_CR2
5966 * @arg @ref LL_HRTIM_BURSTDMA_EEFR3
5967 * @retval None
5968 */
LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Registers)5969 __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers)
5970 {
5971 const uint8_t REG_OFFSET_TAB_BDTUPR[] =
5972 {
5973 0x00U, /* BDMUPR ; offset = 0x000 */
5974 0x04U, /* BDAUPR ; offset = 0x05C */
5975 0x08U, /* BDBUPR ; offset = 0x060 */
5976 0x0CU, /* BDCUPR ; offset = 0x064 */
5977 0x10U, /* BDDUPR ; offset = 0x068 */
5978 0x14U, /* BDEUPR ; offset = 0x06C */
5979 0x1CU /* BDFUPR ; offset = 0x074 */
5980 };
5981
5982 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
5983 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + REG_OFFSET_TAB_BDTUPR[iTimer]));
5984 WRITE_REG(*pReg, Registers);
5985 }
5986
5987 /**
5988 * @brief Indicate on which output the signal is currently applied.
5989 * @rmtoll TIMxISR CPPSTAT LL_HRTIM_TIM_GetCurrentPushPullStatus
5990 * @note Only significant when the timer operates in push-pull mode.
5991 * @param HRTIMx High Resolution Timer instance
5992 * @param Timer This parameter can be one of the following values:
5993 * @arg @ref LL_HRTIM_TIMER_A
5994 * @arg @ref LL_HRTIM_TIMER_B
5995 * @arg @ref LL_HRTIM_TIMER_C
5996 * @arg @ref LL_HRTIM_TIMER_D
5997 * @arg @ref LL_HRTIM_TIMER_E
5998 * @arg @ref LL_HRTIM_TIMER_F
5999 * @retval CPPSTAT This parameter can be one of the following values:
6000 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1
6001 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2
6002 */
LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6003 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6004 {
6005 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
6006 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
6007 REG_OFFSET_TAB_TIMER[iTimer]));
6008 return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT));
6009 }
6010
6011 /**
6012 * @brief Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.
6013 * @rmtoll TIMxISR IPPSTAT LL_HRTIM_TIM_GetIdlePushPullStatus
6014 * @param HRTIMx High Resolution Timer instance
6015 * @param Timer This parameter can be one of the following values:
6016 * @arg @ref LL_HRTIM_TIMER_A
6017 * @arg @ref LL_HRTIM_TIMER_B
6018 * @arg @ref LL_HRTIM_TIMER_C
6019 * @arg @ref LL_HRTIM_TIMER_D
6020 * @arg @ref LL_HRTIM_TIMER_E
6021 * @arg @ref LL_HRTIM_TIMER_F
6022 * @retval IPPSTAT This parameter can be one of the following values:
6023 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1
6024 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2
6025 */
LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6026 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6027 {
6028 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
6029 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
6030 REG_OFFSET_TAB_TIMER[iTimer]));
6031 return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT));
6032 }
6033
6034 /**
6035 * @brief Set the event filter for a given timer.
6036 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventFilter\n
6037 * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventFilter\n
6038 * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventFilter\n
6039 * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventFilter\n
6040 * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventFilter\n
6041 * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventFilter\n
6042 * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventFilter\n
6043 * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventFilter\n
6044 * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventFilter\n
6045 * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventFilter
6046 * @note This function must not be called when the timer counter is enabled.
6047 * @param HRTIMx High Resolution Timer instance
6048 * @param Timer This parameter can be one of the following values:
6049 * @arg @ref LL_HRTIM_TIMER_A
6050 * @arg @ref LL_HRTIM_TIMER_B
6051 * @arg @ref LL_HRTIM_TIMER_C
6052 * @arg @ref LL_HRTIM_TIMER_D
6053 * @arg @ref LL_HRTIM_TIMER_E
6054 * @arg @ref LL_HRTIM_TIMER_F
6055 * @param Event This parameter can be one of the following values:
6056 * @arg @ref LL_HRTIM_EVENT_1
6057 * @arg @ref LL_HRTIM_EVENT_2
6058 * @arg @ref LL_HRTIM_EVENT_3
6059 * @arg @ref LL_HRTIM_EVENT_4
6060 * @arg @ref LL_HRTIM_EVENT_5
6061 * @arg @ref LL_HRTIM_EVENT_6
6062 * @arg @ref LL_HRTIM_EVENT_7
6063 * @arg @ref LL_HRTIM_EVENT_8
6064 * @arg @ref LL_HRTIM_EVENT_9
6065 * @arg @ref LL_HRTIM_EVENT_10
6066 * @param Filter This parameter can be one of the following values:
6067 * @arg @ref LL_HRTIM_EEFLTR_NONE
6068 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
6069 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
6070 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
6071 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
6072 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1
6073 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4
6074 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2
6075 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1
6076 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4
6077 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1
6078 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1
6079 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2
6080 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1
6081 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4
6082 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2
6083 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1
6084 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2
6085 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2
6086 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2
6087 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1
6088 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2
6089 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1
6090 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4
6091 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1
6092 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1
6093 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4
6094 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2
6095 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4
6096 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1
6097 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2
6098 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1
6099 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2
6100 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2
6101 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1
6102 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4
6103 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4
6104 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2
6105 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1
6106 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1
6107 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4
6108 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2
6109 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1
6110 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4
6111 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2
6112 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4
6113 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2
6114 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4
6115 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2
6116 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4
6117 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1
6118 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4
6119 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2
6120 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
6121 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
6122 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
6123
6124 * @retval None
6125 */
LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event,uint32_t Filter)6126 __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter)
6127 {
6128 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6129 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6130 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
6131 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
6132 MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
6133 }
6134
6135 /**
6136 * @brief Get actual event filter settings for a given timer.
6137 * @rmtoll EEFxR1 EE1FLTR LL_HRTIM_TIM_GetEventFilter\n
6138 * EEFxR1 EE2FLTR LL_HRTIM_TIM_GetEventFilter\n
6139 * EEFxR1 EE3FLTR LL_HRTIM_TIM_GetEventFilter\n
6140 * EEFxR1 EE4FLTR LL_HRTIM_TIM_GetEventFilter\n
6141 * EEFxR1 EE5FLTR LL_HRTIM_TIM_GetEventFilter\n
6142 * EEFxR2 EE6FLTR LL_HRTIM_TIM_GetEventFilter\n
6143 * EEFxR2 EE7FLTR LL_HRTIM_TIM_GetEventFilter\n
6144 * EEFxR2 EE8FLTR LL_HRTIM_TIM_GetEventFilter\n
6145 * EEFxR2 EE9FLTR LL_HRTIM_TIM_GetEventFilter\n
6146 * EEFxR2 EE10FLTR LL_HRTIM_TIM_GetEventFilter
6147 * @param HRTIMx High Resolution Timer instance
6148 * @param Timer This parameter can be one of the following values:
6149 * @arg @ref LL_HRTIM_TIMER_A
6150 * @arg @ref LL_HRTIM_TIMER_B
6151 * @arg @ref LL_HRTIM_TIMER_C
6152 * @arg @ref LL_HRTIM_TIMER_D
6153 * @arg @ref LL_HRTIM_TIMER_E
6154 * @arg @ref LL_HRTIM_TIMER_F
6155 * @param Event This parameter can be one of the following values:
6156 * @arg @ref LL_HRTIM_EVENT_1
6157 * @arg @ref LL_HRTIM_EVENT_2
6158 * @arg @ref LL_HRTIM_EVENT_3
6159 * @arg @ref LL_HRTIM_EVENT_4
6160 * @arg @ref LL_HRTIM_EVENT_5
6161 * @arg @ref LL_HRTIM_EVENT_6
6162 * @arg @ref LL_HRTIM_EVENT_7
6163 * @arg @ref LL_HRTIM_EVENT_8
6164 * @arg @ref LL_HRTIM_EVENT_9
6165 * @arg @ref LL_HRTIM_EVENT_10
6166 * @retval Filter This parameter can be one of the following values:
6167 * @arg @ref LL_HRTIM_EEFLTR_NONE
6168 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
6169 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
6170 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
6171 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
6172 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1
6173 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4
6174 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2
6175 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1
6176 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4
6177 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1
6178 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1
6179 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2
6180 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1
6181 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4
6182 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2
6183 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1
6184 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2
6185 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2
6186 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2
6187 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1
6188 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2
6189 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1
6190 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4
6191 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1
6192 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1
6193 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4
6194 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2
6195 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4
6196 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1
6197 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2
6198 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1
6199 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2
6200 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2
6201 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1
6202 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4
6203 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4
6204 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2
6205 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1
6206 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1
6207 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4
6208 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2
6209 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1
6210 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4
6211 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2
6212 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4
6213 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2
6214 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4
6215 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2
6216 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4
6217 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1
6218 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4
6219 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2
6220 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
6221 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
6222 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
6223 */
LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event)6224 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
6225 {
6226 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6227 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6228 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
6229 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
6230 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
6231 }
6232
6233 /**
6234 * @brief Enable or disable event latch mechanism for a given timer.
6235 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6236 * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6237 * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6238 * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6239 * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6240 * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6241 * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6242 * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6243 * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6244 * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventLatchStatus
6245 * @note This function must not be called when the timer counter is enabled.
6246 * @param HRTIMx High Resolution Timer instance
6247 * @param Timer This parameter can be one of the following values:
6248 * @arg @ref LL_HRTIM_TIMER_A
6249 * @arg @ref LL_HRTIM_TIMER_B
6250 * @arg @ref LL_HRTIM_TIMER_C
6251 * @arg @ref LL_HRTIM_TIMER_D
6252 * @arg @ref LL_HRTIM_TIMER_E
6253 * @arg @ref LL_HRTIM_TIMER_F
6254 * @param Event This parameter can be one of the following values:
6255 * @arg @ref LL_HRTIM_EVENT_1
6256 * @arg @ref LL_HRTIM_EVENT_2
6257 * @arg @ref LL_HRTIM_EVENT_3
6258 * @arg @ref LL_HRTIM_EVENT_4
6259 * @arg @ref LL_HRTIM_EVENT_5
6260 * @arg @ref LL_HRTIM_EVENT_6
6261 * @arg @ref LL_HRTIM_EVENT_7
6262 * @arg @ref LL_HRTIM_EVENT_8
6263 * @arg @ref LL_HRTIM_EVENT_9
6264 * @arg @ref LL_HRTIM_EVENT_10
6265 * @param LatchStatus This parameter can be one of the following values:
6266 * @arg @ref LL_HRTIM_EELATCH_DISABLED
6267 * @arg @ref LL_HRTIM_EELATCH_ENABLED
6268 * @retval None
6269 */
LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event,uint32_t LatchStatus)6270 __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event,
6271 uint32_t LatchStatus)
6272 {
6273 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6274 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6275 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
6276 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
6277 MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent]));
6278 }
6279
6280 /**
6281 * @brief Get actual event latch status for a given timer.
6282 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6283 * EEFxR1 EE2LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6284 * EEFxR1 EE3LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6285 * EEFxR1 EE4LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6286 * EEFxR1 EE5LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6287 * EEFxR2 EE6LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6288 * EEFxR2 EE7LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6289 * EEFxR2 EE8LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6290 * EEFxR2 EE9LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6291 * EEFxR2 EE10LTCH LL_HRTIM_TIM_GetEventLatchStatus
6292 * @param HRTIMx High Resolution Timer instance
6293 * @param Timer This parameter can be one of the following values:
6294 * @arg @ref LL_HRTIM_TIMER_A
6295 * @arg @ref LL_HRTIM_TIMER_B
6296 * @arg @ref LL_HRTIM_TIMER_C
6297 * @arg @ref LL_HRTIM_TIMER_D
6298 * @arg @ref LL_HRTIM_TIMER_E
6299 * @arg @ref LL_HRTIM_TIMER_F
6300 * @param Event This parameter can be one of the following values:
6301 * @arg @ref LL_HRTIM_EVENT_1
6302 * @arg @ref LL_HRTIM_EVENT_2
6303 * @arg @ref LL_HRTIM_EVENT_3
6304 * @arg @ref LL_HRTIM_EVENT_4
6305 * @arg @ref LL_HRTIM_EVENT_5
6306 * @arg @ref LL_HRTIM_EVENT_6
6307 * @arg @ref LL_HRTIM_EVENT_7
6308 * @arg @ref LL_HRTIM_EVENT_8
6309 * @arg @ref LL_HRTIM_EVENT_9
6310 * @arg @ref LL_HRTIM_EVENT_10
6311 * @retval LatchStatus This parameter can be one of the following values:
6312 * @arg @ref LL_HRTIM_EELATCH_DISABLED
6313 * @arg @ref LL_HRTIM_EELATCH_ENABLED
6314 */
LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event)6315 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
6316 {
6317 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6318 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6319 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
6320 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
6321 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
6322 }
6323
6324 /**
6325 * @brief Select the Trigger-Half operating mode for a given timer.
6326 * @note This bitfield defines whether the compare 2 register
6327 * @note is behaving in standard mode (compare match issued as soon as counter equal compare)
6328 * @note or in triggered-half mode
6329 * @rmtoll TIMxCR2 TRGHLF LL_HRTIM_TIM_SetTriggeredHalfMode
6330 * @param HRTIMx High Resolution Timer instance
6331 * @param Timer This parameter can be one of the following values:
6332 * @arg @ref LL_HRTIM_TIMER_A
6333 * @arg @ref LL_HRTIM_TIMER_B
6334 * @arg @ref LL_HRTIM_TIMER_C
6335 * @arg @ref LL_HRTIM_TIMER_D
6336 * @arg @ref LL_HRTIM_TIMER_E
6337 * @arg @ref LL_HRTIM_TIMER_F
6338 * @param Mode This parameter can be one of the following values:
6339 * @arg @ref LL_HRTIM_TRIGHALF_ENABLED
6340 * @arg @ref LL_HRTIM_TRIGHALF_DISABLED
6341 * @retval None
6342 */
LL_HRTIM_TIM_SetTriggeredHalfMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6343 __STATIC_INLINE void LL_HRTIM_TIM_SetTriggeredHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6344 {
6345 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6346 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6347 REG_OFFSET_TAB_TIMER[iTimer]));
6348 MODIFY_REG(* pReg, HRTIM_TIMCR2_TRGHLF, Mode);
6349 }
6350
6351 /**
6352 * @brief Get the Trigger-Half operating mode for a given timer.
6353 * @note This bitfield reports whether the compare 2 register
6354 * @note is behaving in standard mode (compare match issued as soon as counter equal compare)
6355 * @note or in triggered-half mode
6356 * @rmtoll TIMxCR2 TRGHLF LL_HRTIM_TIM_GetTriggeredHalfMode
6357 * @param HRTIMx High Resolution Timer instance
6358 * @param Timer This parameter can be one of the following values:
6359 * @arg @ref LL_HRTIM_TIMER_A
6360 * @arg @ref LL_HRTIM_TIMER_B
6361 * @arg @ref LL_HRTIM_TIMER_C
6362 * @arg @ref LL_HRTIM_TIMER_D
6363 * @arg @ref LL_HRTIM_TIMER_E
6364 * @arg @ref LL_HRTIM_TIMER_F
6365 * @retval Mode This parameter can be one of the following values:
6366 * @arg @ref LL_HRTIM_TRIGHALF_ENABLED
6367 * @arg @ref LL_HRTIM_TRIGHALF_DISABLED
6368 */
LL_HRTIM_TIM_GetTriggeredHalfMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6369 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetTriggeredHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6370 {
6371 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6372 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6373 REG_OFFSET_TAB_TIMER[iTimer]));
6374 return (READ_BIT(* pReg, HRTIM_TIMCR2_TRGHLF));
6375 }
6376
6377 /**
6378 * @brief Select the compare 1 operating mode.
6379 * @note This bit defines the compare 1 operating mode:
6380 * @note 0: the compare 1 event is generated when the counter is equal to the compare value
6381 * @note 1: the compare 1 event is generated when the counter is greater than the compare value
6382 * @rmtoll TIMxCR2 GTCMP1 LL_HRTIM_TIM_SetComp1Mode
6383 * @param HRTIMx High Resolution Timer instance
6384 * @param Timer This parameter can be one of the following values:
6385 * @arg @ref LL_HRTIM_TIMER_A
6386 * @arg @ref LL_HRTIM_TIMER_B
6387 * @arg @ref LL_HRTIM_TIMER_C
6388 * @arg @ref LL_HRTIM_TIMER_D
6389 * @arg @ref LL_HRTIM_TIMER_E
6390 * @arg @ref LL_HRTIM_TIMER_F
6391 * @param Mode This parameter can be one of the following values:
6392 * @arg @ref LL_HRTIM_GTCMP1_EQUAL
6393 * @arg @ref LL_HRTIM_GTCMP1_GREATER
6394 * @retval None
6395 */
LL_HRTIM_TIM_SetComp1Mode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6396 __STATIC_INLINE void LL_HRTIM_TIM_SetComp1Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6397 {
6398 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6399 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6400 REG_OFFSET_TAB_TIMER[iTimer]));
6401 MODIFY_REG(* pReg, HRTIM_TIMCR2_GTCMP1, Mode);
6402 }
6403
6404 /**
6405 * @brief Get the selected compare 1 operating mode.
6406 * @note This bit reports the compare 1 operating mode:
6407 * @note 0: the compare 1 event is generated when the counter is equal to the compare value
6408 * @note 1: the compare 1 event is generated when the counter is greater than the compare value
6409 * @rmtoll TIMxCR2 GTCMP1 LL_HRTIM_TIM_GetComp1Mode
6410 * @param HRTIMx High Resolution Timer instance
6411 * @param Timer This parameter can be one of the following values:
6412 * @arg @ref LL_HRTIM_TIMER_A
6413 * @arg @ref LL_HRTIM_TIMER_B
6414 * @arg @ref LL_HRTIM_TIMER_C
6415 * @arg @ref LL_HRTIM_TIMER_D
6416 * @arg @ref LL_HRTIM_TIMER_E
6417 * @arg @ref LL_HRTIM_TIMER_F
6418 * @retval Mode This parameter can be one of the following values:
6419 * @arg @ref LL_HRTIM_GTCMP1_EQUAL
6420 * @arg @ref LL_HRTIM_GTCMP1_GREATER
6421 */
LL_HRTIM_TIM_GetComp1Mode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6422 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp1Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6423 {
6424 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6425 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6426 REG_OFFSET_TAB_TIMER[iTimer]));
6427 return (READ_BIT(* pReg, HRTIM_TIMCR2_GTCMP1));
6428 }
6429
6430 /**
6431 * @brief Select the compare 3 operating mode.
6432 * @note This bit defines the compare 3 operating mode:
6433 * @note 0: the compare 3 event is generated when the counter is equal to the compare value
6434 * @note 1: the compare 3 event is generated when the counter is greater than the compare value
6435 * @rmtoll TIMxCR2 GTCMP3 LL_HRTIM_TIM_SetComp3Mode
6436 * @param HRTIMx High Resolution Timer instance
6437 * @param Timer This parameter can be one of the following values:
6438 * @arg @ref LL_HRTIM_TIMER_A
6439 * @arg @ref LL_HRTIM_TIMER_B
6440 * @arg @ref LL_HRTIM_TIMER_C
6441 * @arg @ref LL_HRTIM_TIMER_D
6442 * @arg @ref LL_HRTIM_TIMER_E
6443 * @arg @ref LL_HRTIM_TIMER_F
6444 * @param Mode This parameter can be one of the following values:
6445 * @arg @ref LL_HRTIM_GTCMP3_EQUAL
6446 * @arg @ref LL_HRTIM_GTCMP3_GREATER
6447 * @retval None
6448 */
LL_HRTIM_TIM_SetComp3Mode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6449 __STATIC_INLINE void LL_HRTIM_TIM_SetComp3Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6450 {
6451 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6452 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6453 REG_OFFSET_TAB_TIMER[iTimer]));
6454 MODIFY_REG(* pReg, HRTIM_TIMCR2_GTCMP3, (Mode));
6455 }
6456
6457 /**
6458 * @brief Get the selected compare 3 operating mode.
6459 * @note This bit reports the compare 3 operating mode:
6460 * @note 0: the compare 3 event is generated when the counter is equal to the compare value
6461 * @note 1: the compare 3 event is generated when the counter is greater than the compare value
6462 * @rmtoll TIMxCR2 GTCMP3 LL_HRTIM_TIM_GetComp1Mode
6463 * @param HRTIMx High Resolution Timer instance
6464 * @param Timer This parameter can be one of the following values:
6465 * @arg @ref LL_HRTIM_TIMER_A
6466 * @arg @ref LL_HRTIM_TIMER_B
6467 * @arg @ref LL_HRTIM_TIMER_C
6468 * @arg @ref LL_HRTIM_TIMER_D
6469 * @arg @ref LL_HRTIM_TIMER_E
6470 * @arg @ref LL_HRTIM_TIMER_F
6471 * @retval Mode This parameter can be one of the following values:
6472 * @arg @ref LL_HRTIM_GTCMP3_EQUAL
6473 * @arg @ref LL_HRTIM_GTCMP3_GREATER
6474 */
LL_HRTIM_TIM_GetComp3Mode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6475 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp3Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6476 {
6477 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6478 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].TIMxCR2) +
6479 REG_OFFSET_TAB_TIMER[iTimer]));
6480 return (READ_BIT(* pReg, HRTIM_TIMCR2_GTCMP3));
6481 }
6482
6483 /**
6484 * @brief Select the roll-over mode.
6485 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6486 * @note Only concerns the Roll-over event with the following destinations: Update trigger, IRQ
6487 * and DMA requests, repetition counter decrement and External Event filtering.
6488 * @rmtoll TIMxCR2 ROM LL_HRTIM_TIM_SetRollOverMode
6489 * @param HRTIMx High Resolution Timer instance
6490 * @param Timer This parameter can be one of the following values:
6491 * @arg @ref LL_HRTIM_TIMER_A
6492 * @arg @ref LL_HRTIM_TIMER_B
6493 * @arg @ref LL_HRTIM_TIMER_C
6494 * @arg @ref LL_HRTIM_TIMER_D
6495 * @arg @ref LL_HRTIM_TIMER_E
6496 * @arg @ref LL_HRTIM_TIMER_F
6497 * @param Mode This parameter can be one of the following values:
6498 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6499 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6500 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6501 * @retval None
6502 */
LL_HRTIM_TIM_SetRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6503 __STATIC_INLINE void LL_HRTIM_TIM_SetRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6504 {
6505 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6506 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6507 REG_OFFSET_TAB_TIMER[iTimer]));
6508 MODIFY_REG(* pReg, HRTIM_TIMCR2_ROM, (Mode << HRTIM_TIMCR2_ROM_Pos));
6509 }
6510
6511 /**
6512 * @brief Get selected the roll-over mode.
6513 * @rmtoll TIMxCR2 ROM LL_HRTIM_TIM_GetRollOverMode
6514 * @param HRTIMx High Resolution Timer instance
6515 * @param Timer This parameter can be one of the following values:
6516 * @arg @ref LL_HRTIM_TIMER_A
6517 * @arg @ref LL_HRTIM_TIMER_B
6518 * @arg @ref LL_HRTIM_TIMER_C
6519 * @arg @ref LL_HRTIM_TIMER_D
6520 * @arg @ref LL_HRTIM_TIMER_E
6521 * @arg @ref LL_HRTIM_TIMER_F
6522 * @retval Mode returned value can be one of the following values:
6523 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6524 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6525 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6526 */
LL_HRTIM_TIM_GetRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6527 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6528 {
6529 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6530 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6531 REG_OFFSET_TAB_TIMER[iTimer]));
6532 return (READ_BIT(*pReg, HRTIM_TIMCR2_ROM) >> HRTIM_TIMCR2_ROM_Pos);
6533 }
6534
6535 /**
6536 * @brief Select Fault and Event roll-over mode.
6537 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6538 * @note only concerns the Roll-over event used by the Fault and Event counters.
6539 * @rmtoll TIMxCR2 FEROM LL_HRTIM_TIM_SetFaultEventRollOverMode
6540 * @param HRTIMx High Resolution Timer instance
6541 * @param Timer This parameter can be one of the following values:
6542 * @arg @ref LL_HRTIM_TIMER_A
6543 * @arg @ref LL_HRTIM_TIMER_B
6544 * @arg @ref LL_HRTIM_TIMER_C
6545 * @arg @ref LL_HRTIM_TIMER_D
6546 * @arg @ref LL_HRTIM_TIMER_E
6547 * @arg @ref LL_HRTIM_TIMER_F
6548 * @param Mode This parameter can be one of the following values:
6549 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6550 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6551 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6552 * @retval None
6553 */
LL_HRTIM_TIM_SetFaultEventRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6554 __STATIC_INLINE void LL_HRTIM_TIM_SetFaultEventRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6555 {
6556 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6557 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6558 REG_OFFSET_TAB_TIMER[iTimer]));
6559 MODIFY_REG(* pReg, HRTIM_TIMCR2_FEROM, (Mode << HRTIM_TIMCR2_FEROM_Pos));
6560 }
6561
6562 /**
6563 * @brief Get selected Fault and Event role-over mode.
6564 * @rmtoll TIMxCR2 FEROM LL_HRTIM_TIM_GetFaultEventRollOverMode
6565 * @param HRTIMx High Resolution Timer instance
6566 * @param Timer This parameter can be one of the following values:
6567 * @arg @ref LL_HRTIM_TIMER_A
6568 * @arg @ref LL_HRTIM_TIMER_B
6569 * @arg @ref LL_HRTIM_TIMER_C
6570 * @arg @ref LL_HRTIM_TIMER_D
6571 * @arg @ref LL_HRTIM_TIMER_E
6572 * @arg @ref LL_HRTIM_TIMER_F
6573 * @retval Mode returned value can be one of the following values:
6574 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6575 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6576 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6577 */
LL_HRTIM_TIM_GetFaultEventRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6578 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetFaultEventRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6579 {
6580 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6581 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6582 REG_OFFSET_TAB_TIMER[iTimer]));
6583 return (READ_BIT(*pReg, HRTIM_TIMCR2_FEROM) >> HRTIM_TIMCR2_FEROM_Pos);
6584 }
6585
6586 /**
6587 * @brief Select the Burst mode roll-over mode.
6588 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6589 * @note Only concerns the Roll-over event used in the Burst mode controller, as clock as as burst mode trigger.
6590 * @rmtoll TIMxCR2 BMROM LL_HRTIM_TIM_SetBMRollOverMode
6591 * @param HRTIMx High Resolution Timer instance
6592 * @param Timer This parameter can be one of the following values:
6593 * @arg @ref LL_HRTIM_TIMER_A
6594 * @arg @ref LL_HRTIM_TIMER_B
6595 * @arg @ref LL_HRTIM_TIMER_C
6596 * @arg @ref LL_HRTIM_TIMER_D
6597 * @arg @ref LL_HRTIM_TIMER_E
6598 * @arg @ref LL_HRTIM_TIMER_F
6599 * @param Mode This parameter can be one of the following values:
6600 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6601 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6602 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6603 * @retval None
6604 */
LL_HRTIM_TIM_SetBMRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6605 __STATIC_INLINE void LL_HRTIM_TIM_SetBMRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6606 {
6607 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6608 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6609 REG_OFFSET_TAB_TIMER[iTimer]));
6610 MODIFY_REG(* pReg, HRTIM_TIMCR2_BMROM, (Mode << HRTIM_TIMCR2_BMROM_Pos));
6611 }
6612
6613 /**
6614 * @brief Get selected Burst mode roll-over mode.
6615 * @rmtoll TIMxCR2 ROM LL_HRTIM_TIM_GetBMRollOverMode
6616 * @param HRTIMx High Resolution Timer instance
6617 * @param Timer This parameter can be one of the following values:
6618 * @arg @ref LL_HRTIM_TIMER_A
6619 * @arg @ref LL_HRTIM_TIMER_B
6620 * @arg @ref LL_HRTIM_TIMER_C
6621 * @arg @ref LL_HRTIM_TIMER_D
6622 * @arg @ref LL_HRTIM_TIMER_E
6623 * @arg @ref LL_HRTIM_TIMER_F
6624 * @retval Mode returned value can be one of the following values:
6625 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6626 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6627 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6628 */
LL_HRTIM_TIM_GetBMRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6629 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBMRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6630 {
6631 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6632 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6633 REG_OFFSET_TAB_TIMER[iTimer]));
6634 return (READ_BIT(*pReg, HRTIM_TIMCR2_BMROM) >> HRTIM_TIMCR2_BMROM_Pos);
6635 }
6636
6637 /**
6638 * @brief Select the ADC roll-over mode.
6639 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6640 * @note Only concerns the Roll-over event used to trigger the ADC.
6641 * @rmtoll TIMxCR2 BMROM LL_HRTIM_TIM_SetADCRollOverMode
6642 * @param HRTIMx High Resolution Timer instance
6643 * @param Timer This parameter can be one of the following values:
6644 * @arg @ref LL_HRTIM_TIMER_A
6645 * @arg @ref LL_HRTIM_TIMER_B
6646 * @arg @ref LL_HRTIM_TIMER_C
6647 * @arg @ref LL_HRTIM_TIMER_D
6648 * @arg @ref LL_HRTIM_TIMER_E
6649 * @arg @ref LL_HRTIM_TIMER_F
6650 * @param Mode This parameter can be one of the following values:
6651 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6652 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6653 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6654 * @retval None
6655 */
LL_HRTIM_TIM_SetADCRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6656 __STATIC_INLINE void LL_HRTIM_TIM_SetADCRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6657 {
6658 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6659 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6660 REG_OFFSET_TAB_TIMER[iTimer]));
6661 MODIFY_REG(* pReg, HRTIM_TIMCR2_ADROM, (Mode << HRTIM_TIMCR2_ADROM_Pos));
6662 }
6663
6664 /**
6665 * @brief Get selected ADC roll-over mode.
6666 * @rmtoll TIMxCR2 BMROM LL_HRTIM_TIM_GetADCRollOverMode
6667 * @param HRTIMx High Resolution Timer instance
6668 * @param Timer This parameter can be one of the following values:
6669 * @arg @ref LL_HRTIM_TIMER_A
6670 * @arg @ref LL_HRTIM_TIMER_B
6671 * @arg @ref LL_HRTIM_TIMER_C
6672 * @arg @ref LL_HRTIM_TIMER_D
6673 * @arg @ref LL_HRTIM_TIMER_E
6674 * @arg @ref LL_HRTIM_TIMER_F
6675 * @retval Mode returned value can be one of the following values:
6676 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6677 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6678 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6679 */
LL_HRTIM_TIM_GetADCRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6680 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetADCRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6681 {
6682 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6683 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6684 REG_OFFSET_TAB_TIMER[iTimer]));
6685 return (READ_BIT(*pReg, HRTIM_TIMCR2_ADROM) >> HRTIM_TIMCR2_ADROM_Pos);
6686 }
6687
6688 /**
6689 * @brief Select the ADC roll-over mode.
6690 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6691 * @note Only concerns concerns the Roll-over event which sets and/or resets the outputs,
6692 * as per HRTIM_SETxyR and HRTIM_RSTxyR settings (see function @ref LL_HRTIM_OUT_SetOutputSetSrc()
6693 * and function @ref LL_HRTIM_OUT_SetOutputResetSrc() respectively).
6694 * @rmtoll TIMxCR2 OUTROM LL_HRTIM_TIM_SetOutputRollOverMode
6695 * @param HRTIMx High Resolution Timer instance
6696 * @param Timer This parameter can be one of the following values:
6697 * @arg @ref LL_HRTIM_TIMER_A
6698 * @arg @ref LL_HRTIM_TIMER_B
6699 * @arg @ref LL_HRTIM_TIMER_C
6700 * @arg @ref LL_HRTIM_TIMER_D
6701 * @arg @ref LL_HRTIM_TIMER_E
6702 * @arg @ref LL_HRTIM_TIMER_F
6703 * @param Mode This parameter can be one of the following values:
6704 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6705 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6706 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6707 * @retval None
6708 */
LL_HRTIM_TIM_SetOutputRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6709 __STATIC_INLINE void LL_HRTIM_TIM_SetOutputRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6710 {
6711 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6712 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6713 REG_OFFSET_TAB_TIMER[iTimer]));
6714 MODIFY_REG(* pReg, HRTIM_TIMCR2_OUTROM, (Mode << HRTIM_TIMCR2_OUTROM_Pos));
6715 }
6716
6717 /**
6718 * @brief Get selected ADC roll-over mode.
6719 * @rmtoll TIMxCR2 OUTROM LL_HRTIM_TIM_GetOutputRollOverMode
6720 * @param HRTIMx High Resolution Timer instance
6721 * @param Timer This parameter can be one of the following values:
6722 * @arg @ref LL_HRTIM_TIMER_A
6723 * @arg @ref LL_HRTIM_TIMER_B
6724 * @arg @ref LL_HRTIM_TIMER_C
6725 * @arg @ref LL_HRTIM_TIMER_D
6726 * @arg @ref LL_HRTIM_TIMER_E
6727 * @arg @ref LL_HRTIM_TIMER_F
6728 * @retval Mode returned value can be one of the following values:
6729 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6730 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6731 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6732 */
LL_HRTIM_TIM_GetOutputRollOverMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6733 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetOutputRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6734 {
6735 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6736 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6737 REG_OFFSET_TAB_TIMER[iTimer]));
6738 return (READ_BIT(*pReg, HRTIM_TIMCR2_OUTROM) >> HRTIM_TIMCR2_OUTROM_Pos);
6739 }
6740
6741 /**
6742 * @brief Select the counting mode.
6743 * @note The up-down counting mode is available for both continuous and single-shot
6744 * (retriggerable and nonretriggerable) operating modes
6745 * (see function @ref LL_HRTIM_TIM_SetCounterMode()).
6746 * @note The counter roll-over event is defined differently in-up-down counting mode to
6747 * support various operating condition.
6748 * See @ref LL_HRTIM_TIM_SetCounterMode()
6749 * @rmtoll TIMxCR2 UDM LL_HRTIM_TIM_SetCountingMode
6750 * @param HRTIMx High Resolution Timer instance
6751 * @param Timer This parameter can be one of the following values:
6752 * @arg @ref LL_HRTIM_TIMER_A
6753 * @arg @ref LL_HRTIM_TIMER_B
6754 * @arg @ref LL_HRTIM_TIMER_C
6755 * @arg @ref LL_HRTIM_TIMER_D
6756 * @arg @ref LL_HRTIM_TIMER_E
6757 * @arg @ref LL_HRTIM_TIMER_F
6758 * @param Mode This parameter can be one of the following values:
6759 * @arg @ref LL_HRTIM_COUNTING_MODE_UP
6760 * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
6761 * @retval None
6762 */
LL_HRTIM_TIM_SetCountingMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6763 __STATIC_INLINE void LL_HRTIM_TIM_SetCountingMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6764 {
6765 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6766 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6767 REG_OFFSET_TAB_TIMER[iTimer]));
6768 MODIFY_REG(* pReg, HRTIM_TIMCR2_UDM, Mode);
6769 }
6770
6771 /**
6772 * @brief Get selected counting mode.
6773 * @rmtoll TIMxCR2 UDM LL_HRTIM_TIM_GetCountingMode
6774 * @param HRTIMx High Resolution Timer instance
6775 * @param Timer This parameter can be one of the following values:
6776 * @arg @ref LL_HRTIM_TIMER_A
6777 * @arg @ref LL_HRTIM_TIMER_B
6778 * @arg @ref LL_HRTIM_TIMER_C
6779 * @arg @ref LL_HRTIM_TIMER_D
6780 * @arg @ref LL_HRTIM_TIMER_E
6781 * @arg @ref LL_HRTIM_TIMER_F
6782 * @retval Mode returned value can be one of the following values:
6783 * @arg @ref LL_HRTIM_COUNTING_MODE_UP
6784 * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
6785 * @retval None
6786 */
LL_HRTIM_TIM_GetCountingMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6787 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCountingMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6788 {
6789 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6790 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6791 REG_OFFSET_TAB_TIMER[iTimer]));
6792 return (READ_BIT(*pReg, HRTIM_TIMCR2_UDM));
6793 }
6794
6795 /**
6796 * @brief Select Dual Channel DAC Reset trigger.
6797 * @note Significant only when Dual channel DAC trigger is enabled
6798 * (see function @ref LL_HRTIM_TIM_EnableDualDacTrigger()).
6799 * @rmtoll TIMxCR2 DCDR LL_HRTIM_TIM_SetDualDacResetTrigger
6800 * @param HRTIMx High Resolution Timer instance
6801 * @param Timer This parameter can be one of the following values:
6802 * @arg @ref LL_HRTIM_TIMER_A
6803 * @arg @ref LL_HRTIM_TIMER_B
6804 * @arg @ref LL_HRTIM_TIMER_C
6805 * @arg @ref LL_HRTIM_TIMER_D
6806 * @arg @ref LL_HRTIM_TIMER_E
6807 * @arg @ref LL_HRTIM_TIMER_F
6808 * @param Mode This parameter can be one of the following values:
6809 * @arg @ref LL_HRTIM_DCDR_COUNTER
6810 * @arg @ref LL_HRTIM_DCDR_OUT1SET
6811 * @retval None
6812 */
LL_HRTIM_TIM_SetDualDacResetTrigger(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6813 __STATIC_INLINE void LL_HRTIM_TIM_SetDualDacResetTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6814 {
6815 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6816 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6817 REG_OFFSET_TAB_TIMER[iTimer]));
6818 MODIFY_REG(* pReg, HRTIM_TIMCR2_DCDR, Mode);
6819 }
6820
6821 /**
6822 * @brief Get selected Dual Channel DAC Reset trigger.
6823 * @rmtoll TIMxCR2 DCDR LL_HRTIM_TIM_GetDualDacResetTrigger
6824 * @param HRTIMx High Resolution Timer instance
6825 * @param Timer This parameter can be one of the following values:
6826 * @arg @ref LL_HRTIM_TIMER_A
6827 * @arg @ref LL_HRTIM_TIMER_B
6828 * @arg @ref LL_HRTIM_TIMER_C
6829 * @arg @ref LL_HRTIM_TIMER_D
6830 * @arg @ref LL_HRTIM_TIMER_E
6831 * @arg @ref LL_HRTIM_TIMER_F
6832 * @retval Trigger returned value can be one of the following values:
6833 * @arg @ref LL_HRTIM_DCDR_COUNTER
6834 * @arg @ref LL_HRTIM_DCDR_OUT1SET
6835 */
LL_HRTIM_TIM_GetDualDacResetTrigger(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6836 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacResetTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6837 {
6838 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6839 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6840 REG_OFFSET_TAB_TIMER[iTimer]));
6841 return (READ_BIT(*pReg, HRTIM_TIMCR2_DCDR));
6842 }
6843
6844 /**
6845 * @brief Select Dual Channel DAC Reset trigger.
6846 * @rmtoll TIMxCR2 DCDS LL_HRTIM_TIM_SetDualDacStepTrigger
6847 * @param HRTIMx High Resolution Timer instance
6848 * @param Timer This parameter can be one of the following values:
6849 * @arg @ref LL_HRTIM_TIMER_A
6850 * @arg @ref LL_HRTIM_TIMER_B
6851 * @arg @ref LL_HRTIM_TIMER_C
6852 * @arg @ref LL_HRTIM_TIMER_D
6853 * @arg @ref LL_HRTIM_TIMER_E
6854 * @arg @ref LL_HRTIM_TIMER_F
6855 * @param Mode This parameter can be one of the following values:
6856 * @arg @ref LL_HRTIM_DCDS_CMP2
6857 * @arg @ref LL_HRTIM_DCDS_OUT1RST
6858 * @retval None
6859 */
LL_HRTIM_TIM_SetDualDacStepTrigger(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)6860 __STATIC_INLINE void LL_HRTIM_TIM_SetDualDacStepTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6861 {
6862 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6863 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6864 REG_OFFSET_TAB_TIMER[iTimer]));
6865 MODIFY_REG(* pReg, HRTIM_TIMCR2_DCDS, Mode);
6866 }
6867
6868 /**
6869 * @brief Get selected Dual Channel DAC Reset trigger.
6870 * @rmtoll TIMxCR2 DCDS LL_HRTIM_TIM_GetDualDacStepTrigger
6871 * @param HRTIMx High Resolution Timer instance
6872 * @param Timer This parameter can be one of the following values:
6873 * @arg @ref LL_HRTIM_TIMER_A
6874 * @arg @ref LL_HRTIM_TIMER_B
6875 * @arg @ref LL_HRTIM_TIMER_C
6876 * @arg @ref LL_HRTIM_TIMER_D
6877 * @arg @ref LL_HRTIM_TIMER_E
6878 * @arg @ref LL_HRTIM_TIMER_F
6879 * @retval Trigger returned value can be one of the following values:
6880 * @arg @ref LL_HRTIM_DCDS_CMP2
6881 * @arg @ref LL_HRTIM_DCDS_OUT1RST
6882 */
LL_HRTIM_TIM_GetDualDacStepTrigger(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6883 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacStepTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6884 {
6885 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6886 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6887 REG_OFFSET_TAB_TIMER[iTimer]));
6888 return (READ_BIT(*pReg, HRTIM_TIMCR2_DCDS));
6889 }
6890
6891 /**
6892 * @brief Enable Dual Channel DAC trigger.
6893 * @note Only significant when balanced Idle mode is enabled (see function @ref LL_HRTIM_TIM_SetDLYPRTMode()).
6894 * @rmtoll TIMxCR2 DCDE LL_HRTIM_TIM_EnableDualDacTrigger
6895 * @param HRTIMx High Resolution Timer instance
6896 * @param Timer This parameter can be one of the following values:
6897 * @arg @ref LL_HRTIM_TIMER_A
6898 * @arg @ref LL_HRTIM_TIMER_B
6899 * @arg @ref LL_HRTIM_TIMER_C
6900 * @arg @ref LL_HRTIM_TIMER_D
6901 * @arg @ref LL_HRTIM_TIMER_E
6902 * @arg @ref LL_HRTIM_TIMER_F
6903 * @retval None
6904 */
LL_HRTIM_TIM_EnableDualDacTrigger(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6905 __STATIC_INLINE void LL_HRTIM_TIM_EnableDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6906 {
6907 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6908 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6909 REG_OFFSET_TAB_TIMER[iTimer]));
6910 SET_BIT(* pReg, HRTIM_TIMCR2_DCDE);
6911 }
6912
6913 /**
6914 * @brief Disable Dual Channel DAC trigger.
6915 * @rmtoll TIMxCR2 DCDE LL_HRTIM_TIM_DisableDualDacTrigger
6916 * @param HRTIMx High Resolution Timer instance
6917 * @param Timer This parameter can be one of the following values:
6918 * @arg @ref LL_HRTIM_TIMER_A
6919 * @arg @ref LL_HRTIM_TIMER_B
6920 * @arg @ref LL_HRTIM_TIMER_C
6921 * @arg @ref LL_HRTIM_TIMER_D
6922 * @arg @ref LL_HRTIM_TIMER_E
6923 * @arg @ref LL_HRTIM_TIMER_F
6924 * @retval None
6925 */
LL_HRTIM_TIM_DisableDualDacTrigger(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6926 __STATIC_INLINE void LL_HRTIM_TIM_DisableDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6927 {
6928 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6929 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6930 REG_OFFSET_TAB_TIMER[iTimer]));
6931 CLEAR_BIT(* pReg, HRTIM_TIMCR2_DCDE);
6932 }
6933
6934 /**
6935 * @brief Indicate whether Dual Channel DAC trigger is enabled for a given timer.
6936 * @rmtoll TIMxCR2 DCDE LL_HRTIM_TIM_IsEnabledDualDacTrigger
6937 * @param HRTIMx High Resolution Timer instance
6938 * @param Timer This parameter can be one of the following values:
6939 * @arg @ref LL_HRTIM_TIMER_A
6940 * @arg @ref LL_HRTIM_TIMER_B
6941 * @arg @ref LL_HRTIM_TIMER_C
6942 * @arg @ref LL_HRTIM_TIMER_D
6943 * @arg @ref LL_HRTIM_TIMER_E
6944 * @arg @ref LL_HRTIM_TIMER_F
6945 * @retval State of DCDE bit in HRTIM_TIMxCR2 register (1 or 0).
6946 */
LL_HRTIM_TIM_IsEnabledDualDacTrigger(HRTIM_TypeDef * HRTIMx,uint32_t Timer)6947 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6948 {
6949 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6950 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6951 REG_OFFSET_TAB_TIMER[iTimer]));
6952
6953 return ((READ_BIT(* pReg, HRTIM_TIMCR2_DCDE) == (HRTIM_TIMCR2_DCDE)) ? 1UL : 0UL);
6954 }
6955
6956
6957 /**
6958 * @brief Set the external event counter threshold.
6959 * @note The external event is propagated to the timer only if the number
6960 * of active edges is greater than the external event counter threshold.
6961 * @rmtoll EEFxR3 EEVBCNT LL_HRTIM_TIM_SetEventCounterThreshold\n
6962 * EEFxR3 EEVACNT LL_HRTIM_TIM_SetEventCounterThreshold
6963 * @param HRTIMx High Resolution Timer instance
6964 * @param Timer This parameter can be one of the following values:
6965 * @arg @ref LL_HRTIM_TIMER_A
6966 * @arg @ref LL_HRTIM_TIMER_B
6967 * @arg @ref LL_HRTIM_TIMER_C
6968 * @arg @ref LL_HRTIM_TIMER_D
6969 * @arg @ref LL_HRTIM_TIMER_E
6970 * @arg @ref LL_HRTIM_TIMER_F
6971 * @param EventCounter This parameter can be one of the following values:
6972 * @arg @ref LL_HRTIM_EE_COUNTER_A
6973 * @arg @ref LL_HRTIM_EE_COUNTER_B
6974 * @param Threshold This parameter can be a number between Min_Data=0 and Max_Data=63
6975 * @retval None
6976 */
LL_HRTIM_TIM_SetEventCounterThreshold(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter,uint32_t Threshold)6977 __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
6978 uint32_t Threshold)
6979 {
6980 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
6981 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
6982
6983 MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVACNT << EventCounter), Threshold << (HRTIM_EEFR3_EEVACNT_Pos + EventCounter));
6984 }
6985
6986 /**
6987 * @brief Get the programmed external event counter threshold.
6988 * @rmtoll EEFxR3 EEVBCNT LL_HRTIM_TIM_GetEventCounterThreshold\n
6989 * EEFxR3 EEVACNT LL_HRTIM_TIM_GetEventCounterThreshold
6990 * @param HRTIMx High Resolution Timer instance
6991 * @param Timer This parameter can be one of the following values:
6992 * @arg @ref LL_HRTIM_TIMER_A
6993 * @arg @ref LL_HRTIM_TIMER_B
6994 * @arg @ref LL_HRTIM_TIMER_C
6995 * @arg @ref LL_HRTIM_TIMER_D
6996 * @arg @ref LL_HRTIM_TIMER_E
6997 * @arg @ref LL_HRTIM_TIMER_F
6998 * @param EventCounter This parameter can be one of the following values:
6999 * @arg @ref LL_HRTIM_EE_COUNTER_A
7000 * @arg @ref LL_HRTIM_EE_COUNTER_B
7001 * @retval Threshold Value between Min_Data=0 and Max_Data=63
7002 */
LL_HRTIM_TIM_GetEventCounterThreshold(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7003 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Timer,
7004 uint32_t EventCounter)
7005 {
7006 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7007 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7008
7009 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACNT) << EventCounter)) >> ((HRTIM_EEFR3_EEVACNT_Pos + EventCounter))) ;
7010 }
7011
7012 /**
7013 * @brief Select the external event counter source.
7014 * @note External event counting is only valid for edge-sensitive
7015 * external events (See function LL_HRTIM_EE_Config() and function
7016 * LL_HRTIM_EE_SetSensitivity()).
7017 * @rmtoll EEFxR3 EEVBSEL LL_HRTIM_TIM_SetEventCounterSource\n
7018 * EEFxR3 EEVASEL LL_HRTIM_TIM_SetEventCounterSource
7019 * @param HRTIMx High Resolution Timer instance
7020 * @param Timer This parameter can be one of the following values:
7021 * @arg @ref LL_HRTIM_TIMER_A
7022 * @arg @ref LL_HRTIM_TIMER_B
7023 * @arg @ref LL_HRTIM_TIMER_C
7024 * @arg @ref LL_HRTIM_TIMER_D
7025 * @arg @ref LL_HRTIM_TIMER_E
7026 * @arg @ref LL_HRTIM_TIMER_F
7027 * @param EventCounter This parameter can be one of the following values:
7028 * @arg @ref LL_HRTIM_EE_COUNTER_A
7029 * @arg @ref LL_HRTIM_EE_COUNTER_B
7030 * @param Event This parameter can be one of the following values:
7031 * @arg @ref LL_HRTIM_EVENT_1
7032 * @arg @ref LL_HRTIM_EVENT_2
7033 * @arg @ref LL_HRTIM_EVENT_3
7034 * @arg @ref LL_HRTIM_EVENT_4
7035 * @arg @ref LL_HRTIM_EVENT_5
7036 * @arg @ref LL_HRTIM_EVENT_6
7037 * @arg @ref LL_HRTIM_EVENT_7
7038 * @arg @ref LL_HRTIM_EVENT_8
7039 * @arg @ref LL_HRTIM_EVENT_9
7040 * @arg @ref LL_HRTIM_EVENT_10
7041 * @retval None
7042 */
LL_HRTIM_TIM_SetEventCounterSource(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter,uint32_t Event)7043 __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterSource(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
7044 uint32_t Event)
7045 {
7046 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7047 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7048 uint32_t iEvent = (uint32_t)(POSITION_VAL(Event));
7049
7050 /* register SEL value is 0 if LL_HRTIM_EVENT_1, 1 if LL_HRTIM_EVENT_1, etc
7051 and 9 if LL_HRTIM_EVENT_10 */
7052 MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVASEL << EventCounter), iEvent << (HRTIM_EEFR3_EEVASEL_Pos + EventCounter));
7053 }
7054
7055 /**
7056 * @brief get the selected external event counter source.
7057 * LL_HRTIM_EE_SetSensitivity()).
7058 * @rmtoll EEFxR3 EEVBSEL LL_HRTIM_TIM_GetEventCounterSource\n
7059 * EEFxR3 EEVASEL LL_HRTIM_TIM_GetEventCounterSource
7060 * @param HRTIMx High Resolution Timer instance
7061 * @param Timer This parameter can be one of the following values:
7062 * @arg @ref LL_HRTIM_TIMER_A
7063 * @arg @ref LL_HRTIM_TIMER_B
7064 * @arg @ref LL_HRTIM_TIMER_C
7065 * @arg @ref LL_HRTIM_TIMER_D
7066 * @arg @ref LL_HRTIM_TIMER_E
7067 * @arg @ref LL_HRTIM_TIMER_F
7068 * @param EventCounter This parameter can be one of the following values:
7069 * @arg @ref LL_HRTIM_EE_COUNTER_A
7070 * @arg @ref LL_HRTIM_EE_COUNTER_B
7071 * @retval Event This parameter can be one of the following values:
7072 * @arg @ref LL_HRTIM_EVENT_1
7073 * @arg @ref LL_HRTIM_EVENT_2
7074 * @arg @ref LL_HRTIM_EVENT_3
7075 * @arg @ref LL_HRTIM_EVENT_4
7076 * @arg @ref LL_HRTIM_EVENT_5
7077 * @arg @ref LL_HRTIM_EVENT_6
7078 * @arg @ref LL_HRTIM_EVENT_7
7079 * @arg @ref LL_HRTIM_EVENT_8
7080 * @arg @ref LL_HRTIM_EVENT_9
7081 * @arg @ref LL_HRTIM_EVENT_10
7082 */
LL_HRTIM_TIM_GetEventCounterSource(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7083 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterSource(HRTIM_TypeDef *HRTIMx, uint32_t Timer,
7084 uint32_t EventCounter)
7085 {
7086 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7087 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7088
7089 uint32_t iEvent = (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVASEL) << (EventCounter))) >> ((HRTIM_EEFR3_EEVASEL_Pos + EventCounter));
7090
7091 /* returned value is 0 if SEL is LL_HRTIM_EVENT_1, 1 if SEL is LL_HRTIM_EVENT_1, etc
7092 and 9 if SEL is LL_HRTIM_EVENT_10 */
7093 return ((uint32_t)0x1U << iEvent) ;
7094 }
7095
7096 /**
7097 * @brief Select the external event counter reset mode.
7098 * @rmtoll EEFxR3 EEVBRSTM LL_HRTIM_TIM_SetEventCounterResetMode\n
7099 * EEFxR3 EEVARSTM LL_HRTIM_TIM_SetEventCounterResetMode
7100 * @param HRTIMx High Resolution Timer instance
7101 * @param Timer This parameter can be one of the following values:
7102 * @arg @ref LL_HRTIM_TIMER_A
7103 * @arg @ref LL_HRTIM_TIMER_B
7104 * @arg @ref LL_HRTIM_TIMER_C
7105 * @arg @ref LL_HRTIM_TIMER_D
7106 * @arg @ref LL_HRTIM_TIMER_E
7107 * @arg @ref LL_HRTIM_TIMER_F
7108 * @param EventCounter This parameter can be one of the following values:
7109 * @arg @ref LL_HRTIM_EE_COUNTER_A
7110 * @arg @ref LL_HRTIM_EE_COUNTER_B
7111 * @param Mode This parameter can be one of the following values:
7112 * @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL
7113 * @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL
7114 * @retval None
7115 */
LL_HRTIM_TIM_SetEventCounterResetMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter,uint32_t Mode)7116 __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
7117 uint32_t Mode)
7118 {
7119 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7120 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7121
7122 MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVARSTM << (EventCounter)), Mode << (EventCounter));
7123 }
7124
7125 /**
7126 * @brief Get selected external event counter reset mode.
7127 * @rmtoll EEFxR3 EEVBRSTM LL_HRTIM_TIM_GetEventCounterResetMode\n
7128 * EEFxR3 EEVARSTM LL_HRTIM_TIM_GetEventCounterResetMode
7129 * @param HRTIMx High Resolution Timer instance
7130 * @param Timer This parameter can be one of the following values:
7131 * @arg @ref LL_HRTIM_TIMER_A
7132 * @arg @ref LL_HRTIM_TIMER_B
7133 * @arg @ref LL_HRTIM_TIMER_C
7134 * @arg @ref LL_HRTIM_TIMER_D
7135 * @arg @ref LL_HRTIM_TIMER_E
7136 * @arg @ref LL_HRTIM_TIMER_F
7137 * @param EventCounter This parameter can be one of the following values:
7138 * @arg @ref LL_HRTIM_EE_COUNTER_A
7139 * @arg @ref LL_HRTIM_EE_COUNTER_B
7140 * @retval Mode This parameter can be one of the following values:
7141 * @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL
7142 * @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL
7143 */
LL_HRTIM_TIM_GetEventCounterResetMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7144 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer,
7145 uint32_t EventCounter)
7146 {
7147 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7148 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7149
7150 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVARSTM) << (EventCounter))) >> (EventCounter)) ;
7151 }
7152
7153 /**
7154 * @brief Reset the external event counter.
7155 * @rmtoll EEFxR3 EEVACRES LL_HRTIM_TIM_ResetEventCounter\n
7156 * EEFxR3 EEVBCRES LL_HRTIM_TIM_ResetEventCounter
7157 * @param HRTIMx High Resolution Timer instance
7158 * @param Timer This parameter can be one of the following values:
7159 * @arg @ref LL_HRTIM_TIMER_A
7160 * @arg @ref LL_HRTIM_TIMER_B
7161 * @arg @ref LL_HRTIM_TIMER_C
7162 * @arg @ref LL_HRTIM_TIMER_D
7163 * @arg @ref LL_HRTIM_TIMER_E
7164 * @arg @ref LL_HRTIM_TIMER_F
7165 * @param EventCounter This parameter can be one of the following values:
7166 * @arg @ref LL_HRTIM_EE_COUNTER_A
7167 * @arg @ref LL_HRTIM_EE_COUNTER_B
7168 * @retval None
7169 */
LL_HRTIM_TIM_ResetEventCounter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7170 __STATIC_INLINE void LL_HRTIM_TIM_ResetEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
7171 {
7172 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7173 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7174
7175 SET_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACRES) << EventCounter);
7176 }
7177
7178 /**
7179 * @brief Enable the external event counter.
7180 * @rmtoll EEFxR3 EEVACE LL_HRTIM_TIM_EnableEventCounter\n
7181 * EEFxR3 EEVBCE LL_HRTIM_TIM_EnableEventCounter
7182 * @param HRTIMx High Resolution Timer instance
7183 * @param Timer This parameter can be one of the following values:
7184 * @arg @ref LL_HRTIM_TIMER_A
7185 * @arg @ref LL_HRTIM_TIMER_B
7186 * @arg @ref LL_HRTIM_TIMER_C
7187 * @arg @ref LL_HRTIM_TIMER_D
7188 * @arg @ref LL_HRTIM_TIMER_E
7189 * @arg @ref LL_HRTIM_TIMER_F
7190 * @param EventCounter This parameter can be one of the following values:
7191 * @arg @ref LL_HRTIM_EE_COUNTER_A
7192 * @arg @ref LL_HRTIM_EE_COUNTER_B
7193 * @retval None
7194 */
LL_HRTIM_TIM_EnableEventCounter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7195 __STATIC_INLINE void LL_HRTIM_TIM_EnableEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
7196 {
7197 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7198 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7199
7200 SET_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter);
7201 }
7202
7203 /**
7204 * @brief Disable the external event counter.
7205 * @rmtoll EEFxR3 EEVACE LL_HRTIM_TIM_DisableEventCounter\n
7206 * EEFxR3 EEVBCE LL_HRTIM_TIM_DisableEventCounter
7207 * @param HRTIMx High Resolution Timer instance
7208 * @param Timer This parameter can be one of the following values:
7209 * @arg @ref LL_HRTIM_TIMER_A
7210 * @arg @ref LL_HRTIM_TIMER_B
7211 * @arg @ref LL_HRTIM_TIMER_C
7212 * @arg @ref LL_HRTIM_TIMER_D
7213 * @arg @ref LL_HRTIM_TIMER_E
7214 * @arg @ref LL_HRTIM_TIMER_F
7215 * @param EventCounter This parameter can be one of the following values:
7216 * @arg @ref LL_HRTIM_EE_COUNTER_A
7217 * @arg @ref LL_HRTIM_EE_COUNTER_B
7218 * @retval None
7219 */
LL_HRTIM_TIM_DisableEventCounter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7220 __STATIC_INLINE void LL_HRTIM_TIM_DisableEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
7221 {
7222 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7223 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7224
7225 CLEAR_BIT(*pReg, (HRTIM_EEFR3_EEVACE << EventCounter));
7226 }
7227
7228
7229 /**
7230 * @brief Indicate whether the external event counter is enabled for a given timer.
7231 * @rmtoll EEFxR3 EEVACE LL_HRTIM_TIM_IsEnabledEventCounter\n
7232 * EEFxR3 EEVBCE LL_HRTIM_TIM_IsEnabledEventCounter
7233 * @param HRTIMx High Resolution Timer instance
7234 * @param Timer This parameter can be one of the following values:
7235 * @arg @ref LL_HRTIM_TIMER_A
7236 * @arg @ref LL_HRTIM_TIMER_B
7237 * @arg @ref LL_HRTIM_TIMER_C
7238 * @arg @ref LL_HRTIM_TIMER_D
7239 * @arg @ref LL_HRTIM_TIMER_E
7240 * @arg @ref LL_HRTIM_TIMER_F
7241 * @param EventCounter This parameter can be one of the following values:
7242 * @arg @ref LL_HRTIM_EE_COUNTER_A
7243 * @arg @ref LL_HRTIM_EE_COUNTER_B
7244 * @retval State of EEVxCE bit in RTIM_EEFxR3 register (1 or 0).
7245 */
LL_HRTIM_TIM_IsEnabledEventCounter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t EventCounter)7246 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer,
7247 uint32_t EventCounter)
7248 {
7249 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
7250 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7251
7252 uint32_t temp; /* MISRAC-2012 compliance */
7253 temp = READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter);
7254
7255 return ((temp == ((uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter)) ? 1UL : 0UL);
7256 }
7257
7258 /**
7259 * @}
7260 */
7261
7262 /** @defgroup HRTIM_LL_EF_Dead_Time_Configuration Dead_Time_Configuration
7263 * @{
7264 */
7265
7266 /**
7267 * @brief Configure the dead time insertion feature for a given timer.
7268 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_Config\n
7269 * DTxR SDTF LL_HRTIM_DT_Config\n
7270 * DTxR SDRT LL_HRTIM_DT_Config
7271 * @param HRTIMx High Resolution Timer instance
7272 * @param Timer This parameter can be one of the following values:
7273 * @arg @ref LL_HRTIM_TIMER_A
7274 * @arg @ref LL_HRTIM_TIMER_B
7275 * @arg @ref LL_HRTIM_TIMER_C
7276 * @arg @ref LL_HRTIM_TIMER_D
7277 * @arg @ref LL_HRTIM_TIMER_E
7278 * @arg @ref LL_HRTIM_TIMER_F
7279 * @param Configuration This parameter must be a combination of all the following values:
7280 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 or ... or @ref LL_HRTIM_DT_PRESCALER_DIV16
7281 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE or @ref LL_HRTIM_DT_RISING_NEGATIVE
7282 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE
7283 * @retval None
7284 */
LL_HRTIM_DT_Config(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Configuration)7285 __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
7286 {
7287 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7288 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7289 REG_OFFSET_TAB_TIMER[iTimer]));
7290 MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration);
7291 }
7292
7293 /**
7294 * @brief Set the deadtime prescaler value.
7295 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_SetPrescaler
7296 * @param HRTIMx High Resolution Timer instance
7297 * @param Timer This parameter can be one of the following values:
7298 * @arg @ref LL_HRTIM_TIMER_A
7299 * @arg @ref LL_HRTIM_TIMER_B
7300 * @arg @ref LL_HRTIM_TIMER_C
7301 * @arg @ref LL_HRTIM_TIMER_D
7302 * @arg @ref LL_HRTIM_TIMER_E
7303 * @arg @ref LL_HRTIM_TIMER_F
7304 * @param Prescaler This parameter can be one of the following values:
7305 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
7306 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
7307 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
7308 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
7309 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
7310 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
7311 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
7312 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
7313 * @retval None
7314 */
LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Prescaler)7315 __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
7316 {
7317 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7318 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7319 REG_OFFSET_TAB_TIMER[iTimer]));
7320 MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler);
7321 }
7322
7323 /**
7324 * @brief Get actual deadtime prescaler value.
7325 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_GetPrescaler
7326 * @param HRTIMx High Resolution Timer instance
7327 * @param Timer This parameter can be one of the following values:
7328 * @arg @ref LL_HRTIM_TIMER_A
7329 * @arg @ref LL_HRTIM_TIMER_B
7330 * @arg @ref LL_HRTIM_TIMER_C
7331 * @arg @ref LL_HRTIM_TIMER_D
7332 * @arg @ref LL_HRTIM_TIMER_E
7333 * @arg @ref LL_HRTIM_TIMER_F
7334 * @retval Prescaler This parameter can be one of the following values:
7335 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
7336 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
7337 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
7338 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
7339 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
7340 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
7341 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
7342 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
7343 */
LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7344 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7345 {
7346 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7347 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7348 REG_OFFSET_TAB_TIMER[iTimer]));
7349 return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC));
7350 }
7351
7352 /**
7353 * @brief Set the deadtime rising value.
7354 * @rmtoll DTxR DTR LL_HRTIM_DT_SetRisingValue
7355 * @param HRTIMx High Resolution Timer instance
7356 * @param Timer This parameter can be one of the following values:
7357 * @arg @ref LL_HRTIM_TIMER_A
7358 * @arg @ref LL_HRTIM_TIMER_B
7359 * @arg @ref LL_HRTIM_TIMER_C
7360 * @arg @ref LL_HRTIM_TIMER_D
7361 * @arg @ref LL_HRTIM_TIMER_E
7362 * @arg @ref LL_HRTIM_TIMER_F
7363 * @param RisingValue Value between 0 and 0x1FF
7364 * @retval None
7365 */
LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t RisingValue)7366 __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue)
7367 {
7368 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7369 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7370 REG_OFFSET_TAB_TIMER[iTimer]));
7371 MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue);
7372 }
7373
7374 /**
7375 * @brief Get actual deadtime rising value.
7376 * @rmtoll DTxR DTR LL_HRTIM_DT_GetRisingValue
7377 * @param HRTIMx High Resolution Timer instance
7378 * @param Timer This parameter can be one of the following values:
7379 * @arg @ref LL_HRTIM_TIMER_A
7380 * @arg @ref LL_HRTIM_TIMER_B
7381 * @arg @ref LL_HRTIM_TIMER_C
7382 * @arg @ref LL_HRTIM_TIMER_D
7383 * @arg @ref LL_HRTIM_TIMER_E
7384 * @arg @ref LL_HRTIM_TIMER_F
7385 * @retval RisingValue Value between 0 and 0x1FF
7386 */
LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7387 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7388 {
7389 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7390 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7391 REG_OFFSET_TAB_TIMER[iTimer]));
7392 return (READ_BIT(*pReg, HRTIM_DTR_DTR));
7393 }
7394
7395 /**
7396 * @brief Set the deadtime sign on rising edge.
7397 * @rmtoll DTxR SDTR LL_HRTIM_DT_SetRisingSign
7398 * @param HRTIMx High Resolution Timer instance
7399 * @param Timer This parameter can be one of the following values:
7400 * @arg @ref LL_HRTIM_TIMER_A
7401 * @arg @ref LL_HRTIM_TIMER_B
7402 * @arg @ref LL_HRTIM_TIMER_C
7403 * @arg @ref LL_HRTIM_TIMER_D
7404 * @arg @ref LL_HRTIM_TIMER_E
7405 * @arg @ref LL_HRTIM_TIMER_F
7406 * @param RisingSign This parameter can be one of the following values:
7407 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE
7408 * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
7409 * @retval None
7410 */
LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t RisingSign)7411 __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign)
7412 {
7413 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7414 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7415 REG_OFFSET_TAB_TIMER[iTimer]));
7416 MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign);
7417 }
7418
7419 /**
7420 * @brief Get actual deadtime sign on rising edge.
7421 * @rmtoll DTxR SDTR LL_HRTIM_DT_GetRisingSign
7422 * @param HRTIMx High Resolution Timer instance
7423 * @param Timer This parameter can be one of the following values:
7424 * @arg @ref LL_HRTIM_TIMER_A
7425 * @arg @ref LL_HRTIM_TIMER_B
7426 * @arg @ref LL_HRTIM_TIMER_C
7427 * @arg @ref LL_HRTIM_TIMER_D
7428 * @arg @ref LL_HRTIM_TIMER_E
7429 * @arg @ref LL_HRTIM_TIMER_F
7430 * @retval RisingSign This parameter can be one of the following values:
7431 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE
7432 * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
7433 */
LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7434 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7435 {
7436 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7437 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7438 REG_OFFSET_TAB_TIMER[iTimer]));
7439 return (READ_BIT(*pReg, HRTIM_DTR_SDTR));
7440 }
7441
7442 /**
7443 * @brief Set the deadime falling value.
7444 * @rmtoll DTxR DTF LL_HRTIM_DT_SetFallingValue
7445 * @param HRTIMx High Resolution Timer instance
7446 * @param Timer This parameter can be one of the following values:
7447 * @arg @ref LL_HRTIM_TIMER_A
7448 * @arg @ref LL_HRTIM_TIMER_B
7449 * @arg @ref LL_HRTIM_TIMER_C
7450 * @arg @ref LL_HRTIM_TIMER_D
7451 * @arg @ref LL_HRTIM_TIMER_E
7452 * @arg @ref LL_HRTIM_TIMER_F
7453 * @param FallingValue Value between 0 and 0x1FF
7454 * @retval None
7455 */
LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t FallingValue)7456 __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue)
7457 {
7458 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7459 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7460 REG_OFFSET_TAB_TIMER[iTimer]));
7461 MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos);
7462 }
7463
7464 /**
7465 * @brief Get actual deadtime falling value
7466 * @rmtoll DTxR DTF LL_HRTIM_DT_GetFallingValue
7467 * @param HRTIMx High Resolution Timer instance
7468 * @param Timer This parameter can be one of the following values:
7469 * @arg @ref LL_HRTIM_TIMER_A
7470 * @arg @ref LL_HRTIM_TIMER_B
7471 * @arg @ref LL_HRTIM_TIMER_C
7472 * @arg @ref LL_HRTIM_TIMER_D
7473 * @arg @ref LL_HRTIM_TIMER_E
7474 * @arg @ref LL_HRTIM_TIMER_F
7475 * @retval FallingValue Value between 0 and 0x1FF
7476 */
LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7477 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7478 {
7479 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7480 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7481 REG_OFFSET_TAB_TIMER[iTimer]));
7482 return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos);
7483 }
7484
7485 /**
7486 * @brief Set the deadtime sign on falling edge.
7487 * @rmtoll DTxR SDTF LL_HRTIM_DT_SetFallingSign
7488 * @param HRTIMx High Resolution Timer instance
7489 * @param Timer This parameter can be one of the following values:
7490 * @arg @ref LL_HRTIM_TIMER_A
7491 * @arg @ref LL_HRTIM_TIMER_B
7492 * @arg @ref LL_HRTIM_TIMER_C
7493 * @arg @ref LL_HRTIM_TIMER_D
7494 * @arg @ref LL_HRTIM_TIMER_E
7495 * @arg @ref LL_HRTIM_TIMER_F
7496 * @param FallingSign This parameter can be one of the following values:
7497 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
7498 * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
7499 * @retval None
7500 */
LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t FallingSign)7501 __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign)
7502 {
7503 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7504 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7505 REG_OFFSET_TAB_TIMER[iTimer]));
7506 MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign);
7507 }
7508
7509 /**
7510 * @brief Get actual deadtime sign on falling edge.
7511 * @rmtoll DTxR SDTF LL_HRTIM_DT_GetFallingSign
7512 * @param HRTIMx High Resolution Timer instance
7513 * @param Timer This parameter can be one of the following values:
7514 * @arg @ref LL_HRTIM_TIMER_A
7515 * @arg @ref LL_HRTIM_TIMER_B
7516 * @arg @ref LL_HRTIM_TIMER_C
7517 * @arg @ref LL_HRTIM_TIMER_D
7518 * @arg @ref LL_HRTIM_TIMER_E
7519 * @arg @ref LL_HRTIM_TIMER_F
7520 * @retval FallingSign This parameter can be one of the following values:
7521 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
7522 * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
7523 */
LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7524 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7525 {
7526 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7527 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7528 REG_OFFSET_TAB_TIMER[iTimer]));
7529 return (READ_BIT(*pReg, HRTIM_DTR_SDTF));
7530 }
7531
7532 /**
7533 * @brief Lock the deadtime value and sign on rising edge.
7534 * @rmtoll DTxR DTRLK LL_HRTIM_DT_LockRising
7535 * @param HRTIMx High Resolution Timer instance
7536 * @param Timer This parameter can be one of the following values:
7537 * @arg @ref LL_HRTIM_TIMER_A
7538 * @arg @ref LL_HRTIM_TIMER_B
7539 * @arg @ref LL_HRTIM_TIMER_C
7540 * @arg @ref LL_HRTIM_TIMER_D
7541 * @arg @ref LL_HRTIM_TIMER_E
7542 * @arg @ref LL_HRTIM_TIMER_F
7543 * @retval None
7544 */
LL_HRTIM_DT_LockRising(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7545 __STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7546 {
7547 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7548 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7549 REG_OFFSET_TAB_TIMER[iTimer]));
7550 SET_BIT(*pReg, HRTIM_DTR_DTRLK);
7551 }
7552
7553 /**
7554 * @brief Lock the deadtime sign on rising edge.
7555 * @rmtoll DTxR DTRSLK LL_HRTIM_DT_LockRisingSign
7556 * @param HRTIMx High Resolution Timer instance
7557 * @param Timer This parameter can be one of the following values:
7558 * @arg @ref LL_HRTIM_TIMER_A
7559 * @arg @ref LL_HRTIM_TIMER_B
7560 * @arg @ref LL_HRTIM_TIMER_C
7561 * @arg @ref LL_HRTIM_TIMER_D
7562 * @arg @ref LL_HRTIM_TIMER_E
7563 * @arg @ref LL_HRTIM_TIMER_F
7564 * @retval None
7565 */
LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7566 __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7567 {
7568 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7569 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7570 REG_OFFSET_TAB_TIMER[iTimer]));
7571 SET_BIT(*pReg, HRTIM_DTR_DTRSLK);
7572 }
7573
7574 /**
7575 * @brief Lock the deadtime value and sign on falling edge.
7576 * @rmtoll DTxR DTFLK LL_HRTIM_DT_LockFalling
7577 * @param HRTIMx High Resolution Timer instance
7578 * @param Timer This parameter can be one of the following values:
7579 * @arg @ref LL_HRTIM_TIMER_A
7580 * @arg @ref LL_HRTIM_TIMER_B
7581 * @arg @ref LL_HRTIM_TIMER_C
7582 * @arg @ref LL_HRTIM_TIMER_D
7583 * @arg @ref LL_HRTIM_TIMER_E
7584 * @arg @ref LL_HRTIM_TIMER_F
7585 * @retval None
7586 */
LL_HRTIM_DT_LockFalling(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7587 __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7588 {
7589 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7590 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7591 REG_OFFSET_TAB_TIMER[iTimer]));
7592 SET_BIT(*pReg, HRTIM_DTR_DTFLK);
7593 }
7594
7595 /**
7596 * @brief Lock the deadtime sign on falling edge.
7597 * @rmtoll DTxR DTFSLK LL_HRTIM_DT_LockFallingSign
7598 * @param HRTIMx High Resolution Timer instance
7599 * @param Timer This parameter can be one of the following values:
7600 * @arg @ref LL_HRTIM_TIMER_A
7601 * @arg @ref LL_HRTIM_TIMER_B
7602 * @arg @ref LL_HRTIM_TIMER_C
7603 * @arg @ref LL_HRTIM_TIMER_D
7604 * @arg @ref LL_HRTIM_TIMER_E
7605 * @arg @ref LL_HRTIM_TIMER_F
7606 * @retval None
7607 */
LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7608 __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7609 {
7610 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7611 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7612 REG_OFFSET_TAB_TIMER[iTimer]));
7613 SET_BIT(*pReg, HRTIM_DTR_DTFSLK);
7614 }
7615
7616 /**
7617 * @}
7618 */
7619
7620 /** @defgroup HRTIM_LL_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration
7621 * @{
7622 */
7623
7624 /**
7625 * @brief Configure the chopper stage for a given timer.
7626 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_Config\n
7627 * CHPxR CARDTY LL_HRTIM_CHP_Config\n
7628 * CHPxR STRTPW LL_HRTIM_CHP_Config
7629 * @note This function must not be called if the chopper mode is already
7630 * enabled for one of the timer outputs.
7631 * @param HRTIMx High Resolution Timer instance
7632 * @param Timer This parameter can be one of the following values:
7633 * @arg @ref LL_HRTIM_TIMER_A
7634 * @arg @ref LL_HRTIM_TIMER_B
7635 * @arg @ref LL_HRTIM_TIMER_C
7636 * @arg @ref LL_HRTIM_TIMER_D
7637 * @arg @ref LL_HRTIM_TIMER_E
7638 * @arg @ref LL_HRTIM_TIMER_F
7639 * @param Configuration This parameter must be a combination of all the following values:
7640 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 or ... or @ref LL_HRTIM_CHP_PRESCALER_DIV256
7641 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 or ... or @ref LL_HRTIM_CHP_DUTYCYCLE_875
7642 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256
7643 * @retval None
7644 */
LL_HRTIM_CHP_Config(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Configuration)7645 __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
7646 {
7647 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7648 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7649 REG_OFFSET_TAB_TIMER[iTimer]));
7650 MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration);
7651 }
7652
7653 /**
7654 * @brief Set prescaler determining the carrier frequency to be added on top
7655 * of the timer output signals when chopper mode is enabled.
7656 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_SetPrescaler
7657 * @note This function must not be called if the chopper mode is already
7658 * enabled for one of the timer outputs.
7659 * @param HRTIMx High Resolution Timer instance
7660 * @param Timer This parameter can be one of the following values:
7661 * @arg @ref LL_HRTIM_TIMER_A
7662 * @arg @ref LL_HRTIM_TIMER_B
7663 * @arg @ref LL_HRTIM_TIMER_C
7664 * @arg @ref LL_HRTIM_TIMER_D
7665 * @arg @ref LL_HRTIM_TIMER_E
7666 * @arg @ref LL_HRTIM_TIMER_F
7667 * @param Prescaler This parameter can be one of the following values:
7668 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
7669 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
7670 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
7671 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
7672 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
7673 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
7674 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
7675 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
7676 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
7677 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
7678 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
7679 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
7680 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
7681 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
7682 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
7683 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
7684 * @retval None
7685 */
LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Prescaler)7686 __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
7687 {
7688 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7689 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7690 REG_OFFSET_TAB_TIMER[iTimer]));
7691 MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler);
7692 }
7693
7694 /**
7695 * @brief Get actual chopper stage prescaler value.
7696 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_GetPrescaler
7697 * @param HRTIMx High Resolution Timer instance
7698 * @param Timer This parameter can be one of the following values:
7699 * @arg @ref LL_HRTIM_TIMER_A
7700 * @arg @ref LL_HRTIM_TIMER_B
7701 * @arg @ref LL_HRTIM_TIMER_C
7702 * @arg @ref LL_HRTIM_TIMER_D
7703 * @arg @ref LL_HRTIM_TIMER_E
7704 * @arg @ref LL_HRTIM_TIMER_F
7705 * @retval Prescaler This parameter can be one of the following values:
7706 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
7707 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
7708 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
7709 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
7710 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
7711 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
7712 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
7713 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
7714 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
7715 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
7716 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
7717 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
7718 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
7719 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
7720 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
7721 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
7722 */
LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7723 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7724 {
7725 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7726 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7727 REG_OFFSET_TAB_TIMER[iTimer]));
7728 return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ));
7729 }
7730
7731 /**
7732 * @brief Set the chopper duty cycle.
7733 * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_SetDutyCycle
7734 * @note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
7735 * @note This function must not be called if the chopper mode is already
7736 * enabled for one of the timer outputs.
7737 * @param HRTIMx High Resolution Timer instance
7738 * @param Timer This parameter can be one of the following values:
7739 * @arg @ref LL_HRTIM_TIMER_A
7740 * @arg @ref LL_HRTIM_TIMER_B
7741 * @arg @ref LL_HRTIM_TIMER_C
7742 * @arg @ref LL_HRTIM_TIMER_D
7743 * @arg @ref LL_HRTIM_TIMER_E
7744 * @arg @ref LL_HRTIM_TIMER_F
7745 * @param DutyCycle This parameter can be one of the following values:
7746 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
7747 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
7748 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
7749 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
7750 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
7751 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
7752 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
7753 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
7754 * @retval None
7755 */
LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t DutyCycle)7756 __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle)
7757 {
7758 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7759 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7760 REG_OFFSET_TAB_TIMER[iTimer]));
7761 MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle);
7762 }
7763
7764 /**
7765 * @brief Get actual chopper duty cycle.
7766 * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_GetDutyCycle
7767 * @param HRTIMx High Resolution Timer instance
7768 * @param Timer This parameter can be one of the following values:
7769 * @arg @ref LL_HRTIM_TIMER_A
7770 * @arg @ref LL_HRTIM_TIMER_B
7771 * @arg @ref LL_HRTIM_TIMER_C
7772 * @arg @ref LL_HRTIM_TIMER_D
7773 * @arg @ref LL_HRTIM_TIMER_E
7774 * @arg @ref LL_HRTIM_TIMER_F
7775 * @retval DutyCycle This parameter can be one of the following values:
7776 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
7777 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
7778 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
7779 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
7780 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
7781 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
7782 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
7783 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
7784 */
LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7785 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7786 {
7787 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7788 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7789 REG_OFFSET_TAB_TIMER[iTimer]));
7790 return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY));
7791 }
7792
7793 /**
7794 * @brief Set the start pulse width.
7795 * @rmtoll CHPxR STRPW LL_HRTIM_CHP_SetPulseWidth
7796 * @note This function must not be called if the chopper mode is already
7797 * enabled for one of the timer outputs.
7798 * @param HRTIMx High Resolution Timer instance
7799 * @param Timer This parameter can be one of the following values:
7800 * @arg @ref LL_HRTIM_TIMER_A
7801 * @arg @ref LL_HRTIM_TIMER_B
7802 * @arg @ref LL_HRTIM_TIMER_C
7803 * @arg @ref LL_HRTIM_TIMER_D
7804 * @arg @ref LL_HRTIM_TIMER_E
7805 * @arg @ref LL_HRTIM_TIMER_F
7806 * @param PulseWidth This parameter can be one of the following values:
7807 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
7808 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
7809 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
7810 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
7811 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
7812 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
7813 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
7814 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
7815 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
7816 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
7817 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
7818 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
7819 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
7820 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
7821 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
7822 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
7823 * @retval None
7824 */
LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t PulseWidth)7825 __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth)
7826 {
7827 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7828 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7829 REG_OFFSET_TAB_TIMER[iTimer]));
7830 MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth);
7831 }
7832
7833 /**
7834 * @brief Get actual start pulse width.
7835 * @rmtoll CHPxR STRPW LL_HRTIM_CHP_GetPulseWidth
7836 * @param HRTIMx High Resolution Timer instance
7837 * @param Timer This parameter can be one of the following values:
7838 * @arg @ref LL_HRTIM_TIMER_A
7839 * @arg @ref LL_HRTIM_TIMER_B
7840 * @arg @ref LL_HRTIM_TIMER_C
7841 * @arg @ref LL_HRTIM_TIMER_D
7842 * @arg @ref LL_HRTIM_TIMER_E
7843 * @arg @ref LL_HRTIM_TIMER_F
7844 * @retval PulseWidth This parameter can be one of the following values:
7845 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
7846 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
7847 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
7848 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
7849 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
7850 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
7851 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
7852 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
7853 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
7854 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
7855 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
7856 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
7857 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
7858 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
7859 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
7860 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
7861 */
LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7862 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7863 {
7864 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
7865 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7866 REG_OFFSET_TAB_TIMER[iTimer]));
7867 return (READ_BIT(*pReg, HRTIM_CHPR_STRPW));
7868 }
7869
7870 /**
7871 * @}
7872 */
7873
7874 /** @defgroup HRTIM_LL_EF_Output_Management Output_Management
7875 * @{
7876 */
7877
7878 /**
7879 * @brief Set the timer output set source.
7880 * @rmtoll SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
7881 * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
7882 * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
7883 * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
7884 * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
7885 * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
7886 * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
7887 * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
7888 * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
7889 * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
7890 * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
7891 * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
7892 * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
7893 * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
7894 * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
7895 * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
7896 * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
7897 * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
7898 * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
7899 * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
7900 * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
7901 * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
7902 * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
7903 * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
7904 * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
7905 * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
7906 * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
7907 * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
7908 * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
7909 * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
7910 * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
7911 * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc\n
7912 * SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
7913 * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
7914 * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
7915 * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
7916 * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
7917 * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
7918 * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
7919 * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
7920 * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
7921 * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
7922 * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
7923 * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
7924 * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
7925 * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
7926 * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
7927 * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
7928 * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
7929 * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
7930 * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
7931 * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
7932 * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
7933 * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
7934 * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
7935 * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
7936 * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
7937 * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
7938 * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
7939 * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
7940 * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
7941 * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
7942 * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
7943 * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc
7944 * @param HRTIMx High Resolution Timer instance
7945 * @param Output This parameter can be one of the following values:
7946 * @arg @ref LL_HRTIM_OUTPUT_TA1
7947 * @arg @ref LL_HRTIM_OUTPUT_TA2
7948 * @arg @ref LL_HRTIM_OUTPUT_TB1
7949 * @arg @ref LL_HRTIM_OUTPUT_TB2
7950 * @arg @ref LL_HRTIM_OUTPUT_TC1
7951 * @arg @ref LL_HRTIM_OUTPUT_TC2
7952 * @arg @ref LL_HRTIM_OUTPUT_TD1
7953 * @arg @ref LL_HRTIM_OUTPUT_TD2
7954 * @arg @ref LL_HRTIM_OUTPUT_TE1
7955 * @arg @ref LL_HRTIM_OUTPUT_TE2
7956 * @arg @ref LL_HRTIM_OUTPUT_TF1
7957 * @arg @ref LL_HRTIM_OUTPUT_TF2
7958 * @param SetSrc This parameter can be a combination of the following values:
7959 * @arg @ref LL_HRTIM_OUTPUTSET_NONE
7960 * @arg @ref LL_HRTIM_OUTPUTSET_RESYNC
7961 * @arg @ref LL_HRTIM_OUTPUTSET_TIMPER
7962 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1
7963 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2
7964 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3
7965 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4
7966 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER
7967 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1
7968 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2
7969 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3
7970 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4
7971 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
7972 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
7973 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2
7974 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3
7975 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1
7976 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2
7977 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3
7978 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4
7979 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4
7980 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
7981 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
7982 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3
7983 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4
7984 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3
7985 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4
7986 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1
7987 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2
7988 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3
7989 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
7990 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
7991 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
7992 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
7993 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
7994 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
7995 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3
7996 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4
7997 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2
7998 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
7999 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
8000 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
8001 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
8002 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4
8003 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1
8004 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4
8005 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1
8006 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3
8007 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4
8008 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3
8009 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4
8010 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1
8011 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2
8012 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1
8013 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2
8014 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3
8015 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
8016 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
8017 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
8018 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
8019 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
8020 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
8021 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
8022 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
8023 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
8024 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
8025 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_1
8026 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_2
8027 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_3
8028 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_4
8029 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_5
8030 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_6
8031 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_7
8032 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_8
8033 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
8034 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
8035 * @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
8036 * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
8037 * @retval None
8038 */
LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t SetSrc)8039 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
8040 {
8041 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8042 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
8043 REG_OFFSET_TAB_SETxR[iOutput]));
8044 WRITE_REG(*pReg, SetSrc);
8045 }
8046
8047 /**
8048 * @brief Get the timer output set source.
8049 * @rmtoll SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
8050 * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
8051 * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
8052 * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
8053 * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
8054 * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
8055 * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
8056 * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
8057 * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
8058 * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
8059 * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
8060 * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
8061 * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
8062 * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
8063 * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
8064 * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
8065 * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
8066 * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
8067 * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
8068 * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
8069 * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
8070 * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
8071 * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
8072 * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
8073 * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
8074 * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
8075 * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
8076 * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
8077 * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
8078 * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
8079 * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
8080 * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc\n
8081 * SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
8082 * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
8083 * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
8084 * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
8085 * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
8086 * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
8087 * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
8088 * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
8089 * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
8090 * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
8091 * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
8092 * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
8093 * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
8094 * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
8095 * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
8096 * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
8097 * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
8098 * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
8099 * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
8100 * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
8101 * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
8102 * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
8103 * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
8104 * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
8105 * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
8106 * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
8107 * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
8108 * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
8109 * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
8110 * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
8111 * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
8112 * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc
8113 * @param HRTIMx High Resolution Timer instance
8114 * @param Output This parameter can be one of the following values:
8115 * @arg @ref LL_HRTIM_OUTPUT_TA1
8116 * @arg @ref LL_HRTIM_OUTPUT_TA2
8117 * @arg @ref LL_HRTIM_OUTPUT_TB1
8118 * @arg @ref LL_HRTIM_OUTPUT_TB2
8119 * @arg @ref LL_HRTIM_OUTPUT_TC1
8120 * @arg @ref LL_HRTIM_OUTPUT_TC2
8121 * @arg @ref LL_HRTIM_OUTPUT_TD1
8122 * @arg @ref LL_HRTIM_OUTPUT_TD2
8123 * @arg @ref LL_HRTIM_OUTPUT_TE1
8124 * @arg @ref LL_HRTIM_OUTPUT_TE2
8125 * @arg @ref LL_HRTIM_OUTPUT_TF1
8126 * @arg @ref LL_HRTIM_OUTPUT_TF2
8127 * @retval SetSrc This parameter can be a combination of the following values:
8128 * @arg @ref LL_HRTIM_OUTPUTSET_NONE
8129 * @arg @ref LL_HRTIM_OUTPUTSET_RESYNC
8130 * @arg @ref LL_HRTIM_OUTPUTSET_TIMPER
8131 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1
8132 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2
8133 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3
8134 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4
8135 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER
8136 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1
8137 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2
8138 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3
8139 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4
8140 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
8141 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
8142 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2
8143 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3
8144 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1
8145 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2
8146 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3
8147 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4
8148 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4
8149 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
8150 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
8151 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3
8152 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4
8153 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3
8154 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4
8155 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1
8156 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2
8157 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3
8158 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
8159 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
8160 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
8161 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
8162 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
8163 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
8164 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3
8165 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4
8166 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2
8167 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
8168 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
8169 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
8170 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
8171 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4
8172 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1
8173 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4
8174 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1
8175 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3
8176 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4
8177 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3
8178 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4
8179 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1
8180 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2
8181 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1
8182 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2
8183 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3
8184 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
8185 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
8186 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
8187 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
8188 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
8189 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
8190 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
8191 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
8192 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
8193 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
8194 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_1
8195 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_2
8196 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_3
8197 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_4
8198 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_5
8199 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_6
8200 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_7
8201 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_8
8202 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
8203 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
8204 * @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
8205 * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
8206 */
LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Output)8207 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8208 {
8209 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8210 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
8211 REG_OFFSET_TAB_SETxR[iOutput]));
8212 return (uint32_t) READ_REG(*pReg);
8213 }
8214
8215 /**
8216 * @brief Set the timer output reset source.
8217 * @rmtoll RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
8218 * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
8219 * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
8220 * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
8221 * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
8222 * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
8223 * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
8224 * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
8225 * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
8226 * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
8227 * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
8228 * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
8229 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
8230 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
8231 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
8232 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
8233 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
8234 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
8235 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
8236 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
8237 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
8238 * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
8239 * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
8240 * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
8241 * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
8242 * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
8243 * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
8244 * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
8245 * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
8246 * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
8247 * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
8248 * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc\n
8249 * RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
8250 * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
8251 * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
8252 * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
8253 * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
8254 * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
8255 * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
8256 * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
8257 * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
8258 * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
8259 * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
8260 * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
8261 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
8262 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
8263 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
8264 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
8265 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
8266 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
8267 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
8268 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
8269 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
8270 * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
8271 * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
8272 * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
8273 * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
8274 * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
8275 * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
8276 * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
8277 * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
8278 * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
8279 * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
8280 * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc
8281 * @param HRTIMx High Resolution Timer instance
8282 * @param Output This parameter can be one of the following values:
8283 * @arg @ref LL_HRTIM_OUTPUT_TA1
8284 * @arg @ref LL_HRTIM_OUTPUT_TA2
8285 * @arg @ref LL_HRTIM_OUTPUT_TB1
8286 * @arg @ref LL_HRTIM_OUTPUT_TB2
8287 * @arg @ref LL_HRTIM_OUTPUT_TC1
8288 * @arg @ref LL_HRTIM_OUTPUT_TC2
8289 * @arg @ref LL_HRTIM_OUTPUT_TD1
8290 * @arg @ref LL_HRTIM_OUTPUT_TD2
8291 * @arg @ref LL_HRTIM_OUTPUT_TE1
8292 * @arg @ref LL_HRTIM_OUTPUT_TE2
8293 * @arg @ref LL_HRTIM_OUTPUT_TF1
8294 * @arg @ref LL_HRTIM_OUTPUT_TF2
8295 * @param ResetSrc This parameter can be a combination of the following values:
8296 * @arg @ref LL_HRTIM_OUTPUTRESET_NONE
8297 * @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC
8298 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER
8299 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1
8300 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2
8301 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3
8302 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4
8303 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER
8304 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1
8305 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2
8306 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3
8307 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4
8308 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
8309 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
8310 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
8311 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
8312 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
8313 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
8314 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
8315 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
8316 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
8317 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
8318 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
8319 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
8320 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
8321 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
8322 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
8323 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
8324 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
8325 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
8326 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
8327 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
8328 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
8329 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
8330 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
8331 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
8332 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
8333 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
8334 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
8335 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
8336 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
8337 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
8338 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
8339 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
8340 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
8341 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
8342 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
8343 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
8344 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
8345 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
8346 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
8347 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
8348 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
8349 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
8350 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
8351 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
8352 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
8353 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
8354 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
8355 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
8356 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
8357 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
8358 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
8359 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
8360 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
8361 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
8362 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1
8363 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2
8364 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3
8365 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4
8366 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5
8367 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6
8368 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7
8369 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8
8370 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
8371 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
8372 * @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
8373 * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
8374 * @retval None
8375 */
LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t ResetSrc)8376 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc)
8377 {
8378 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8379 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
8380 REG_OFFSET_TAB_SETxR[iOutput]));
8381 WRITE_REG(*pReg, ResetSrc);
8382 }
8383
8384 /**
8385 * @brief Get the timer output set source.
8386 * @rmtoll RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
8387 * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
8388 * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
8389 * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
8390 * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
8391 * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
8392 * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
8393 * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
8394 * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
8395 * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
8396 * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
8397 * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
8398 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
8399 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
8400 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
8401 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
8402 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
8403 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
8404 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
8405 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
8406 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
8407 * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
8408 * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
8409 * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
8410 * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
8411 * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
8412 * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
8413 * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
8414 * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
8415 * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
8416 * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
8417 * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc\n
8418 * RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
8419 * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
8420 * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
8421 * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
8422 * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
8423 * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
8424 * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
8425 * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
8426 * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
8427 * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
8428 * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
8429 * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
8430 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
8431 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
8432 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
8433 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
8434 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
8435 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
8436 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
8437 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
8438 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
8439 * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
8440 * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
8441 * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
8442 * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
8443 * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
8444 * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
8445 * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
8446 * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
8447 * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
8448 * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
8449 * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc
8450 * @param HRTIMx High Resolution Timer instance
8451 * @param Output This parameter can be one of the following values:
8452 * @arg @ref LL_HRTIM_OUTPUT_TA1
8453 * @arg @ref LL_HRTIM_OUTPUT_TA2
8454 * @arg @ref LL_HRTIM_OUTPUT_TB1
8455 * @arg @ref LL_HRTIM_OUTPUT_TB2
8456 * @arg @ref LL_HRTIM_OUTPUT_TC1
8457 * @arg @ref LL_HRTIM_OUTPUT_TC2
8458 * @arg @ref LL_HRTIM_OUTPUT_TD1
8459 * @arg @ref LL_HRTIM_OUTPUT_TD2
8460 * @arg @ref LL_HRTIM_OUTPUT_TE1
8461 * @arg @ref LL_HRTIM_OUTPUT_TE2
8462 * @arg @ref LL_HRTIM_OUTPUT_TF1
8463 * @arg @ref LL_HRTIM_OUTPUT_TF2
8464 * @retval ResetSrc This parameter can be a combination of the following values:
8465 * @arg @ref LL_HRTIM_OUTPUTRESET_NONE
8466 * @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC
8467 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER
8468 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1
8469 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2
8470 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3
8471 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4
8472 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER
8473 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1
8474 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2
8475 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3
8476 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4
8477 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
8478 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
8479 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
8480 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
8481 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
8482 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
8483 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
8484 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
8485 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
8486 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
8487 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
8488 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
8489 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
8490 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
8491 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
8492 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
8493 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
8494 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
8495 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
8496 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
8497 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
8498 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
8499 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
8500 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
8501 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
8502 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
8503 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
8504 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
8505 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
8506 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
8507 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
8508 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
8509 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
8510 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
8511 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
8512 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
8513 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
8514 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
8515 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
8516 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
8517 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
8518 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
8519 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
8520 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
8521 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
8522 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
8523 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
8524 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
8525 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
8526 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
8527 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
8528 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
8529 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
8530 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
8531 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1
8532 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2
8533 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3
8534 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4
8535 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5
8536 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6
8537 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7
8538 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8
8539 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
8540 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
8541 * @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
8542 * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
8543 */
LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Output)8544 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8545 {
8546 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8547 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
8548 REG_OFFSET_TAB_SETxR[iOutput]));
8549 return (uint32_t) READ_REG(*pReg);
8550 }
8551
8552 /**
8553 * @brief Configure a timer output.
8554 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_Config\n
8555 * OUTxR IDLEM1 LL_HRTIM_OUT_Config\n
8556 * OUTxR IDLES1 LL_HRTIM_OUT_Config\n
8557 * OUTxR FAULT1 LL_HRTIM_OUT_Config\n
8558 * OUTxR CHP1 LL_HRTIM_OUT_Config\n
8559 * OUTxR DIDL1 LL_HRTIM_OUT_Config\n
8560 * OUTxR POL2 LL_HRTIM_OUT_Config\n
8561 * OUTxR IDLEM2 LL_HRTIM_OUT_Config\n
8562 * OUTxR IDLES2 LL_HRTIM_OUT_Config\n
8563 * OUTxR FAULT2 LL_HRTIM_OUT_Config\n
8564 * OUTxR CHP2 LL_HRTIM_OUT_Config\n
8565 * OUTxR DIDL2 LL_HRTIM_OUT_Config
8566 * @param HRTIMx High Resolution Timer instance
8567 * @param Output This parameter can be one of the following values:
8568 * @arg @ref LL_HRTIM_OUTPUT_TA1
8569 * @arg @ref LL_HRTIM_OUTPUT_TA2
8570 * @arg @ref LL_HRTIM_OUTPUT_TB1
8571 * @arg @ref LL_HRTIM_OUTPUT_TB2
8572 * @arg @ref LL_HRTIM_OUTPUT_TC1
8573 * @arg @ref LL_HRTIM_OUTPUT_TC2
8574 * @arg @ref LL_HRTIM_OUTPUT_TD1
8575 * @arg @ref LL_HRTIM_OUTPUT_TD2
8576 * @arg @ref LL_HRTIM_OUTPUT_TE1
8577 * @arg @ref LL_HRTIM_OUTPUT_TE2
8578 * @arg @ref LL_HRTIM_OUTPUT_TF1
8579 * @arg @ref LL_HRTIM_OUTPUT_TF2
8580 * @param Configuration This parameter must be a combination of all the following values:
8581 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY or @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
8582 * @arg @ref LL_HRTIM_OUT_NO_IDLE or @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
8583 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE or @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
8584 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION or @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
8585 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED or @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
8586 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
8587 * @retval None
8588 */
LL_HRTIM_OUT_Config(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t Configuration)8589 __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration)
8590 {
8591 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8592 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8593 REG_OFFSET_TAB_OUTxR[iOutput]));
8594 MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]),
8595 (Configuration << REG_SHIFT_TAB_OUTxR[iOutput]));
8596 }
8597
8598 /**
8599 * @brief Set the polarity of a timer output.
8600 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_SetPolarity\n
8601 * OUTxR POL2 LL_HRTIM_OUT_SetPolarity
8602 * @param HRTIMx High Resolution Timer instance
8603 * @param Output This parameter can be one of the following values:
8604 * @arg @ref LL_HRTIM_OUTPUT_TA1
8605 * @arg @ref LL_HRTIM_OUTPUT_TA2
8606 * @arg @ref LL_HRTIM_OUTPUT_TB1
8607 * @arg @ref LL_HRTIM_OUTPUT_TB2
8608 * @arg @ref LL_HRTIM_OUTPUT_TC1
8609 * @arg @ref LL_HRTIM_OUTPUT_TC2
8610 * @arg @ref LL_HRTIM_OUTPUT_TD1
8611 * @arg @ref LL_HRTIM_OUTPUT_TD2
8612 * @arg @ref LL_HRTIM_OUTPUT_TE1
8613 * @arg @ref LL_HRTIM_OUTPUT_TE2
8614 * @arg @ref LL_HRTIM_OUTPUT_TF1
8615 * @arg @ref LL_HRTIM_OUTPUT_TF2
8616 * @param Polarity This parameter can be one of the following values:
8617 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
8618 * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
8619 * @retval None
8620 */
LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t Polarity)8621 __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity)
8622 {
8623 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8624 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8625 REG_OFFSET_TAB_OUTxR[iOutput]));
8626 MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput]));
8627 }
8628
8629 /**
8630 * @brief Get actual polarity of the timer output.
8631 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_GetPolarity\n
8632 * OUTxR POL2 LL_HRTIM_OUT_GetPolarity
8633 * @param HRTIMx High Resolution Timer instance
8634 * @param Output This parameter can be one of the following values:
8635 * @arg @ref LL_HRTIM_OUTPUT_TA1
8636 * @arg @ref LL_HRTIM_OUTPUT_TA2
8637 * @arg @ref LL_HRTIM_OUTPUT_TB1
8638 * @arg @ref LL_HRTIM_OUTPUT_TB2
8639 * @arg @ref LL_HRTIM_OUTPUT_TC1
8640 * @arg @ref LL_HRTIM_OUTPUT_TC2
8641 * @arg @ref LL_HRTIM_OUTPUT_TD1
8642 * @arg @ref LL_HRTIM_OUTPUT_TD2
8643 * @arg @ref LL_HRTIM_OUTPUT_TE1
8644 * @arg @ref LL_HRTIM_OUTPUT_TE2
8645 * @arg @ref LL_HRTIM_OUTPUT_TF1
8646 * @arg @ref LL_HRTIM_OUTPUT_TF2
8647 * @retval Polarity This parameter can be one of the following values:
8648 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
8649 * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
8650 */
LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Output)8651 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8652 {
8653 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8654 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8655 REG_OFFSET_TAB_OUTxR[iOutput]));
8656 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8657 }
8658
8659 /**
8660 * @brief Set the output IDLE mode.
8661 * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_SetIdleMode\n
8662 * OUTxR IDLEM2 LL_HRTIM_OUT_SetIdleMode
8663 * @note This function must not be called when the burst mode is active
8664 * @param HRTIMx High Resolution Timer instance
8665 * @param Output This parameter can be one of the following values:
8666 * @arg @ref LL_HRTIM_OUTPUT_TA1
8667 * @arg @ref LL_HRTIM_OUTPUT_TA2
8668 * @arg @ref LL_HRTIM_OUTPUT_TB1
8669 * @arg @ref LL_HRTIM_OUTPUT_TB2
8670 * @arg @ref LL_HRTIM_OUTPUT_TC1
8671 * @arg @ref LL_HRTIM_OUTPUT_TC2
8672 * @arg @ref LL_HRTIM_OUTPUT_TD1
8673 * @arg @ref LL_HRTIM_OUTPUT_TD2
8674 * @arg @ref LL_HRTIM_OUTPUT_TE1
8675 * @arg @ref LL_HRTIM_OUTPUT_TE2
8676 * @arg @ref LL_HRTIM_OUTPUT_TF1
8677 * @arg @ref LL_HRTIM_OUTPUT_TF2
8678 * @param IdleMode This parameter can be one of the following values:
8679 * @arg @ref LL_HRTIM_OUT_NO_IDLE
8680 * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
8681 * @retval None
8682 */
LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t IdleMode)8683 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode)
8684 {
8685 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8686 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8687 REG_OFFSET_TAB_OUTxR[iOutput]));
8688 MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput])));
8689 }
8690
8691 /**
8692 * @brief Get actual output IDLE mode.
8693 * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_GetIdleMode\n
8694 * OUTxR IDLEM2 LL_HRTIM_OUT_GetIdleMode
8695 * @param HRTIMx High Resolution Timer instance
8696 * @param Output This parameter can be one of the following values:
8697 * @arg @ref LL_HRTIM_OUTPUT_TA1
8698 * @arg @ref LL_HRTIM_OUTPUT_TA2
8699 * @arg @ref LL_HRTIM_OUTPUT_TB1
8700 * @arg @ref LL_HRTIM_OUTPUT_TB2
8701 * @arg @ref LL_HRTIM_OUTPUT_TC1
8702 * @arg @ref LL_HRTIM_OUTPUT_TC2
8703 * @arg @ref LL_HRTIM_OUTPUT_TD1
8704 * @arg @ref LL_HRTIM_OUTPUT_TD2
8705 * @arg @ref LL_HRTIM_OUTPUT_TE1
8706 * @arg @ref LL_HRTIM_OUTPUT_TE2
8707 * @arg @ref LL_HRTIM_OUTPUT_TF1
8708 * @arg @ref LL_HRTIM_OUTPUT_TF2
8709 * @retval IdleMode This parameter can be one of the following values:
8710 * @arg @ref LL_HRTIM_OUT_NO_IDLE
8711 * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
8712 */
LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef * HRTIMx,uint32_t Output)8713 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8714 {
8715 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8716 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8717 REG_OFFSET_TAB_OUTxR[iOutput]));
8718 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8719 }
8720
8721 /**
8722 * @brief Set the output IDLE level.
8723 * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_SetIdleLevel\n
8724 * OUTxR IDLES2 LL_HRTIM_OUT_SetIdleLevel
8725 * @note This function must be called prior enabling the timer.
8726 * @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE.
8727 * @param HRTIMx High Resolution Timer instance
8728 * @param Output This parameter can be one of the following values:
8729 * @arg @ref LL_HRTIM_OUTPUT_TA1
8730 * @arg @ref LL_HRTIM_OUTPUT_TA2
8731 * @arg @ref LL_HRTIM_OUTPUT_TB1
8732 * @arg @ref LL_HRTIM_OUTPUT_TB2
8733 * @arg @ref LL_HRTIM_OUTPUT_TC1
8734 * @arg @ref LL_HRTIM_OUTPUT_TC2
8735 * @arg @ref LL_HRTIM_OUTPUT_TD1
8736 * @arg @ref LL_HRTIM_OUTPUT_TD2
8737 * @arg @ref LL_HRTIM_OUTPUT_TE1
8738 * @arg @ref LL_HRTIM_OUTPUT_TE2
8739 * @arg @ref LL_HRTIM_OUTPUT_TF1
8740 * @arg @ref LL_HRTIM_OUTPUT_TF2
8741 * @param IdleLevel This parameter can be one of the following values:
8742 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
8743 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
8744 * @retval None
8745 */
LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t IdleLevel)8746 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel)
8747 {
8748 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8749 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8750 REG_OFFSET_TAB_OUTxR[iOutput]));
8751 MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput]));
8752 }
8753
8754 /**
8755 * @brief Get actual output IDLE level.
8756 * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_GetIdleLevel\n
8757 * OUTxR IDLES2 LL_HRTIM_OUT_GetIdleLevel
8758 * @param HRTIMx High Resolution Timer instance
8759 * @param Output This parameter can be one of the following values:
8760 * @arg @ref LL_HRTIM_OUTPUT_TA1
8761 * @arg @ref LL_HRTIM_OUTPUT_TA2
8762 * @arg @ref LL_HRTIM_OUTPUT_TB1
8763 * @arg @ref LL_HRTIM_OUTPUT_TB2
8764 * @arg @ref LL_HRTIM_OUTPUT_TC1
8765 * @arg @ref LL_HRTIM_OUTPUT_TC2
8766 * @arg @ref LL_HRTIM_OUTPUT_TD1
8767 * @arg @ref LL_HRTIM_OUTPUT_TD2
8768 * @arg @ref LL_HRTIM_OUTPUT_TE1
8769 * @arg @ref LL_HRTIM_OUTPUT_TE2
8770 * @arg @ref LL_HRTIM_OUTPUT_TF1
8771 * @arg @ref LL_HRTIM_OUTPUT_TF2
8772 * @retval IdleLevel This parameter can be one of the following values:
8773 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
8774 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
8775 */
LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef * HRTIMx,uint32_t Output)8776 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8777 {
8778 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8779 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8780 REG_OFFSET_TAB_OUTxR[iOutput]));
8781 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8782 }
8783
8784 /**
8785 * @brief Set the output FAULT state.
8786 * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_SetFaultState\n
8787 * OUTxR FAULT2 LL_HRTIM_OUT_SetFaultState
8788 * @note This function must not called when the timer is enabled and a fault
8789 * channel is enabled at timer level.
8790 * @param HRTIMx High Resolution Timer instance
8791 * @param Output This parameter can be one of the following values:
8792 * @arg @ref LL_HRTIM_OUTPUT_TA1
8793 * @arg @ref LL_HRTIM_OUTPUT_TA2
8794 * @arg @ref LL_HRTIM_OUTPUT_TB1
8795 * @arg @ref LL_HRTIM_OUTPUT_TB2
8796 * @arg @ref LL_HRTIM_OUTPUT_TC1
8797 * @arg @ref LL_HRTIM_OUTPUT_TC2
8798 * @arg @ref LL_HRTIM_OUTPUT_TD1
8799 * @arg @ref LL_HRTIM_OUTPUT_TD2
8800 * @arg @ref LL_HRTIM_OUTPUT_TE1
8801 * @arg @ref LL_HRTIM_OUTPUT_TE2
8802 * @arg @ref LL_HRTIM_OUTPUT_TF1
8803 * @arg @ref LL_HRTIM_OUTPUT_TF2
8804 * @param FaultState This parameter can be one of the following values:
8805 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
8806 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
8807 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
8808 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
8809 * @retval None
8810 */
LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t FaultState)8811 __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState)
8812 {
8813 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8814 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8815 REG_OFFSET_TAB_OUTxR[iOutput]));
8816 MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput]));
8817 }
8818
8819 /**
8820 * @brief Get actual FAULT state.
8821 * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_GetFaultState\n
8822 * OUTxR FAULT2 LL_HRTIM_OUT_GetFaultState
8823 * @param HRTIMx High Resolution Timer instance
8824 * @param Output This parameter can be one of the following values:
8825 * @arg @ref LL_HRTIM_OUTPUT_TA1
8826 * @arg @ref LL_HRTIM_OUTPUT_TA2
8827 * @arg @ref LL_HRTIM_OUTPUT_TB1
8828 * @arg @ref LL_HRTIM_OUTPUT_TB2
8829 * @arg @ref LL_HRTIM_OUTPUT_TC1
8830 * @arg @ref LL_HRTIM_OUTPUT_TC2
8831 * @arg @ref LL_HRTIM_OUTPUT_TD1
8832 * @arg @ref LL_HRTIM_OUTPUT_TD2
8833 * @arg @ref LL_HRTIM_OUTPUT_TE1
8834 * @arg @ref LL_HRTIM_OUTPUT_TE2
8835 * @arg @ref LL_HRTIM_OUTPUT_TF1
8836 * @arg @ref LL_HRTIM_OUTPUT_TF2
8837 * @retval FaultState This parameter can be one of the following values:
8838 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
8839 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
8840 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
8841 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
8842 */
LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef * HRTIMx,uint32_t Output)8843 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8844 {
8845 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8846 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8847 REG_OFFSET_TAB_OUTxR[iOutput]));
8848 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8849 }
8850
8851 /**
8852 * @brief Set the output chopper mode.
8853 * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_SetChopperMode\n
8854 * OUTxR CHP2 LL_HRTIM_OUT_SetChopperMode
8855 * @note This function must not called when the timer is enabled.
8856 * @param HRTIMx High Resolution Timer instance
8857 * @param Output This parameter can be one of the following values:
8858 * @arg @ref LL_HRTIM_OUTPUT_TA1
8859 * @arg @ref LL_HRTIM_OUTPUT_TA2
8860 * @arg @ref LL_HRTIM_OUTPUT_TB1
8861 * @arg @ref LL_HRTIM_OUTPUT_TB2
8862 * @arg @ref LL_HRTIM_OUTPUT_TC1
8863 * @arg @ref LL_HRTIM_OUTPUT_TC2
8864 * @arg @ref LL_HRTIM_OUTPUT_TD1
8865 * @arg @ref LL_HRTIM_OUTPUT_TD2
8866 * @arg @ref LL_HRTIM_OUTPUT_TE1
8867 * @arg @ref LL_HRTIM_OUTPUT_TE2
8868 * @arg @ref LL_HRTIM_OUTPUT_TF1
8869 * @arg @ref LL_HRTIM_OUTPUT_TF2
8870 * @param ChopperMode This parameter can be one of the following values:
8871 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
8872 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
8873 * @retval None
8874 */
LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t ChopperMode)8875 __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode)
8876 {
8877 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8878 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8879 REG_OFFSET_TAB_OUTxR[iOutput]));
8880 MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput]));
8881 }
8882
8883 /**
8884 * @brief Get actual output chopper mode
8885 * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_GetChopperMode\n
8886 * OUTxR CHP2 LL_HRTIM_OUT_GetChopperMode
8887 * @param HRTIMx High Resolution Timer instance
8888 * @param Output This parameter can be one of the following values:
8889 * @arg @ref LL_HRTIM_OUTPUT_TA1
8890 * @arg @ref LL_HRTIM_OUTPUT_TA2
8891 * @arg @ref LL_HRTIM_OUTPUT_TB1
8892 * @arg @ref LL_HRTIM_OUTPUT_TB2
8893 * @arg @ref LL_HRTIM_OUTPUT_TC1
8894 * @arg @ref LL_HRTIM_OUTPUT_TC2
8895 * @arg @ref LL_HRTIM_OUTPUT_TD1
8896 * @arg @ref LL_HRTIM_OUTPUT_TD2
8897 * @arg @ref LL_HRTIM_OUTPUT_TE1
8898 * @arg @ref LL_HRTIM_OUTPUT_TE2
8899 * @arg @ref LL_HRTIM_OUTPUT_TF1
8900 * @arg @ref LL_HRTIM_OUTPUT_TF2
8901 * @retval ChopperMode This parameter can be one of the following values:
8902 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
8903 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
8904 */
LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef * HRTIMx,uint32_t Output)8905 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8906 {
8907 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8908 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8909 REG_OFFSET_TAB_OUTxR[iOutput]));
8910 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8911 }
8912
8913 /**
8914 * @brief Set the output burst mode entry mode.
8915 * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_SetBMEntryMode\n
8916 * OUTxR DIDL2 LL_HRTIM_OUT_SetBMEntryMode
8917 * @note This function must not called when the timer is enabled.
8918 * @param HRTIMx High Resolution Timer instance
8919 * @param Output This parameter can be one of the following values:
8920 * @arg @ref LL_HRTIM_OUTPUT_TA1
8921 * @arg @ref LL_HRTIM_OUTPUT_TA2
8922 * @arg @ref LL_HRTIM_OUTPUT_TB1
8923 * @arg @ref LL_HRTIM_OUTPUT_TB2
8924 * @arg @ref LL_HRTIM_OUTPUT_TC1
8925 * @arg @ref LL_HRTIM_OUTPUT_TC2
8926 * @arg @ref LL_HRTIM_OUTPUT_TD1
8927 * @arg @ref LL_HRTIM_OUTPUT_TD2
8928 * @arg @ref LL_HRTIM_OUTPUT_TE1
8929 * @arg @ref LL_HRTIM_OUTPUT_TE2
8930 * @arg @ref LL_HRTIM_OUTPUT_TF1
8931 * @arg @ref LL_HRTIM_OUTPUT_TF2
8932 * @param BMEntryMode This parameter can be one of the following values:
8933 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
8934 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
8935 * @retval None
8936 */
LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t BMEntryMode)8937 __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode)
8938 {
8939 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8940 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8941 REG_OFFSET_TAB_OUTxR[iOutput]));
8942 MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput]));
8943 }
8944
8945 /**
8946 * @brief Get actual output burst mode entry mode.
8947 * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_GetBMEntryMode\n
8948 * OUTxR DIDL2 LL_HRTIM_OUT_GetBMEntryMode
8949 * @param HRTIMx High Resolution Timer instance
8950 * @param Output This parameter can be one of the following values:
8951 * @arg @ref LL_HRTIM_OUTPUT_TA1
8952 * @arg @ref LL_HRTIM_OUTPUT_TA2
8953 * @arg @ref LL_HRTIM_OUTPUT_TB1
8954 * @arg @ref LL_HRTIM_OUTPUT_TB2
8955 * @arg @ref LL_HRTIM_OUTPUT_TC1
8956 * @arg @ref LL_HRTIM_OUTPUT_TC2
8957 * @arg @ref LL_HRTIM_OUTPUT_TD1
8958 * @arg @ref LL_HRTIM_OUTPUT_TD2
8959 * @arg @ref LL_HRTIM_OUTPUT_TE1
8960 * @arg @ref LL_HRTIM_OUTPUT_TE2
8961 * @arg @ref LL_HRTIM_OUTPUT_TF1
8962 * @arg @ref LL_HRTIM_OUTPUT_TF2
8963 * @retval BMEntryMode This parameter can be one of the following values:
8964 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
8965 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
8966 */
LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef * HRTIMx,uint32_t Output)8967 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8968 {
8969 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8970 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8971 REG_OFFSET_TAB_OUTxR[iOutput]));
8972 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8973 }
8974
8975 /**
8976 * @brief Get the level (active or inactive) of the designated output when the
8977 * delayed protection was triggered.
8978 * @rmtoll TIMxISR O1SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus\n
8979 * TIMxISR O2SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus
8980 * @param HRTIMx High Resolution Timer instance
8981 * @param Output This parameter can be one of the following values:
8982 * @arg @ref LL_HRTIM_OUTPUT_TA1
8983 * @arg @ref LL_HRTIM_OUTPUT_TA2
8984 * @arg @ref LL_HRTIM_OUTPUT_TB1
8985 * @arg @ref LL_HRTIM_OUTPUT_TB2
8986 * @arg @ref LL_HRTIM_OUTPUT_TC1
8987 * @arg @ref LL_HRTIM_OUTPUT_TC2
8988 * @arg @ref LL_HRTIM_OUTPUT_TD1
8989 * @arg @ref LL_HRTIM_OUTPUT_TD2
8990 * @arg @ref LL_HRTIM_OUTPUT_TE1
8991 * @arg @ref LL_HRTIM_OUTPUT_TE2
8992 * @arg @ref LL_HRTIM_OUTPUT_TF1
8993 * @arg @ref LL_HRTIM_OUTPUT_TF2
8994 * @retval OutputLevel This parameter can be one of the following values:
8995 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
8996 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
8997 */
LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef * HRTIMx,uint32_t Output)8998 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8999 {
9000 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
9001 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
9002 REG_OFFSET_TAB_OUTxR[iOutput]));
9003 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
9004 HRTIM_TIMISR_O1STAT_Pos);
9005 }
9006
9007 /**
9008 * @brief Force the timer output to its active or inactive level.
9009 * @rmtoll SETx1R SST LL_HRTIM_OUT_ForceLevel\n
9010 * RSTx1R SRT LL_HRTIM_OUT_ForceLevel\n
9011 * SETx2R SST LL_HRTIM_OUT_ForceLevel\n
9012 * RSTx2R SRT LL_HRTIM_OUT_ForceLevel
9013 * @param HRTIMx High Resolution Timer instance
9014 * @param Output This parameter can be one of the following values:
9015 * @arg @ref LL_HRTIM_OUTPUT_TA1
9016 * @arg @ref LL_HRTIM_OUTPUT_TA2
9017 * @arg @ref LL_HRTIM_OUTPUT_TB1
9018 * @arg @ref LL_HRTIM_OUTPUT_TB2
9019 * @arg @ref LL_HRTIM_OUTPUT_TC1
9020 * @arg @ref LL_HRTIM_OUTPUT_TC2
9021 * @arg @ref LL_HRTIM_OUTPUT_TD1
9022 * @arg @ref LL_HRTIM_OUTPUT_TD2
9023 * @arg @ref LL_HRTIM_OUTPUT_TE1
9024 * @arg @ref LL_HRTIM_OUTPUT_TE2
9025 * @arg @ref LL_HRTIM_OUTPUT_TF1
9026 * @arg @ref LL_HRTIM_OUTPUT_TF2
9027 * @param OutputLevel This parameter can be one of the following values:
9028 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
9029 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
9030 * @retval None
9031 */
LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t OutputLevel)9032 __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel)
9033 {
9034 const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] =
9035 {
9036 0x04U, /* 0: LL_HRTIM_OUT_LEVEL_INACTIVE */
9037 0x00U /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE */
9038 };
9039
9040 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
9041 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
9042 REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel]));
9043 SET_BIT(*pReg, HRTIM_SET1R_SST);
9044 }
9045
9046 /**
9047 * @brief Get actual output level, before the output stage (chopper, polarity).
9048 * @rmtoll TIMxISR O1CPY LL_HRTIM_OUT_GetLevel\n
9049 * TIMxISR O2CPY LL_HRTIM_OUT_GetLevel
9050 * @param HRTIMx High Resolution Timer instance
9051 * @param Output This parameter can be one of the following values:
9052 * @arg @ref LL_HRTIM_OUTPUT_TA1
9053 * @arg @ref LL_HRTIM_OUTPUT_TA2
9054 * @arg @ref LL_HRTIM_OUTPUT_TB1
9055 * @arg @ref LL_HRTIM_OUTPUT_TB2
9056 * @arg @ref LL_HRTIM_OUTPUT_TC1
9057 * @arg @ref LL_HRTIM_OUTPUT_TC2
9058 * @arg @ref LL_HRTIM_OUTPUT_TD1
9059 * @arg @ref LL_HRTIM_OUTPUT_TD2
9060 * @arg @ref LL_HRTIM_OUTPUT_TE1
9061 * @arg @ref LL_HRTIM_OUTPUT_TE2
9062 * @arg @ref LL_HRTIM_OUTPUT_TF1
9063 * @arg @ref LL_HRTIM_OUTPUT_TF2
9064 * @retval OutputLevel This parameter can be one of the following values:
9065 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
9066 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
9067 */
LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef * HRTIMx,uint32_t Output)9068 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
9069 {
9070 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
9071 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
9072 REG_OFFSET_TAB_OUTxR[iOutput]));
9073 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
9074 HRTIM_TIMISR_O1CPY_Pos);
9075 }
9076
9077 /**
9078 * @}
9079 */
9080
9081 /** @defgroup HRTIM_LL_EF_External_Event_management External_Event_management
9082 * @{
9083 */
9084
9085 /**
9086 * @brief Configure external event conditioning.
9087 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_Config\n
9088 * EECR1 EE1POL LL_HRTIM_EE_Config\n
9089 * EECR1 EE1SNS LL_HRTIM_EE_Config\n
9090 * EECR1 EE1FAST LL_HRTIM_EE_Config\n
9091 * EECR1 EE2SRC LL_HRTIM_EE_Config\n
9092 * EECR1 EE2POL LL_HRTIM_EE_Config\n
9093 * EECR1 EE2SNS LL_HRTIM_EE_Config\n
9094 * EECR1 EE2FAST LL_HRTIM_EE_Config\n
9095 * EECR1 EE3SRC LL_HRTIM_EE_Config\n
9096 * EECR1 EE3POL LL_HRTIM_EE_Config\n
9097 * EECR1 EE3SNS LL_HRTIM_EE_Config\n
9098 * EECR1 EE3FAST LL_HRTIM_EE_Config\n
9099 * EECR1 EE4SRC LL_HRTIM_EE_Config\n
9100 * EECR1 EE4POL LL_HRTIM_EE_Config\n
9101 * EECR1 EE4SNS LL_HRTIM_EE_Config\n
9102 * EECR1 EE4FAST LL_HRTIM_EE_Config\n
9103 * EECR1 EE5SRC LL_HRTIM_EE_Config\n
9104 * EECR1 EE5POL LL_HRTIM_EE_Config\n
9105 * EECR1 EE5SNS LL_HRTIM_EE_Config\n
9106 * EECR1 EE5FAST LL_HRTIM_EE_Config\n
9107 * EECR2 EE6SRC LL_HRTIM_EE_Config\n
9108 * EECR2 EE6POL LL_HRTIM_EE_Config\n
9109 * EECR2 EE6SNS LL_HRTIM_EE_Config\n
9110 * EECR2 EE6FAST LL_HRTIM_EE_Config\n
9111 * EECR2 EE7SRC LL_HRTIM_EE_Config\n
9112 * EECR2 EE7POL LL_HRTIM_EE_Config\n
9113 * EECR2 EE7SNS LL_HRTIM_EE_Config\n
9114 * EECR2 EE7FAST LL_HRTIM_EE_Config\n
9115 * EECR2 EE8SRC LL_HRTIM_EE_Config\n
9116 * EECR2 EE8POL LL_HRTIM_EE_Config\n
9117 * EECR2 EE8SNS LL_HRTIM_EE_Config\n
9118 * EECR2 EE8FAST LL_HRTIM_EE_Config\n
9119 * EECR2 EE9SRC LL_HRTIM_EE_Config\n
9120 * EECR2 EE9POL LL_HRTIM_EE_Config\n
9121 * EECR2 EE9SNS LL_HRTIM_EE_Config\n
9122 * EECR2 EE9FAST LL_HRTIM_EE_Config\n
9123 * EECR2 EE10SRC LL_HRTIM_EE_Config\n
9124 * EECR2 EE10POL LL_HRTIM_EE_Config\n
9125 * EECR2 EE10SNS LL_HRTIM_EE_Config\n
9126 * EECR2 EE10FAST LL_HRTIM_EE_Config
9127 * @note This function must not be called when the timer counter is enabled.
9128 * @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel.
9129 * @note Fast mode is available only for LL_HRTIM_EVENT_1..5.
9130 * @param HRTIMx High Resolution Timer instance
9131 * @param Event This parameter can be one of the following values:
9132 * @arg @ref LL_HRTIM_EVENT_1
9133 * @arg @ref LL_HRTIM_EVENT_2
9134 * @arg @ref LL_HRTIM_EVENT_3
9135 * @arg @ref LL_HRTIM_EVENT_4
9136 * @arg @ref LL_HRTIM_EVENT_5
9137 * @arg @ref LL_HRTIM_EVENT_6
9138 * @arg @ref LL_HRTIM_EVENT_7
9139 * @arg @ref LL_HRTIM_EVENT_8
9140 * @arg @ref LL_HRTIM_EVENT_9
9141 * @arg @ref LL_HRTIM_EVENT_10
9142 * @param Configuration This parameter must be a combination of all the following values:
9143 * @arg External event source 1 or External event source 2 or External event source 3 or External event source 4
9144 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW
9145 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
9146 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE
9147 * @retval None
9148 */
LL_HRTIM_EE_Config(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Configuration)9149 __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration)
9150 {
9151 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9152 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9153 REG_OFFSET_TAB_EECR[iEvent]));
9154 MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]),
9155 (Configuration << REG_SHIFT_TAB_EExSRC[iEvent]));
9156 }
9157
9158 /**
9159 * @brief Set the external event source.
9160 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_SetSrc\n
9161 * EECR1 EE2SRC LL_HRTIM_EE_SetSrc\n
9162 * EECR1 EE3SRC LL_HRTIM_EE_SetSrc\n
9163 * EECR1 EE4SRC LL_HRTIM_EE_SetSrc\n
9164 * EECR1 EE5SRC LL_HRTIM_EE_SetSrc\n
9165 * EECR2 EE6SRC LL_HRTIM_EE_SetSrc\n
9166 * EECR2 EE7SRC LL_HRTIM_EE_SetSrc\n
9167 * EECR2 EE8SRC LL_HRTIM_EE_SetSrc\n
9168 * EECR2 EE9SRC LL_HRTIM_EE_SetSrc\n
9169 * EECR2 EE10SRC LL_HRTIM_EE_SetSrc
9170 * @param HRTIMx High Resolution Timer instance
9171 * @param Event This parameter can be one of the following values:
9172 * @arg @ref LL_HRTIM_EVENT_1
9173 * @arg @ref LL_HRTIM_EVENT_2
9174 * @arg @ref LL_HRTIM_EVENT_3
9175 * @arg @ref LL_HRTIM_EVENT_4
9176 * @arg @ref LL_HRTIM_EVENT_5
9177 * @arg @ref LL_HRTIM_EVENT_6
9178 * @arg @ref LL_HRTIM_EVENT_7
9179 * @arg @ref LL_HRTIM_EVENT_8
9180 * @arg @ref LL_HRTIM_EVENT_9
9181 * @arg @ref LL_HRTIM_EVENT_10
9182 * @param Src This parameter can be one of the following values:
9183 * @arg External event source 1
9184 * @arg External event source 2
9185 * @arg External event source 3
9186 * @arg External event source 4
9187 * @retval None
9188 */
LL_HRTIM_EE_SetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Src)9189 __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src)
9190 {
9191 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9192 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9193 REG_OFFSET_TAB_EECR[iEvent]));
9194 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent]));
9195 }
9196
9197 /**
9198 * @brief Get actual external event source.
9199 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_GetSrc\n
9200 * EECR1 EE2SRC LL_HRTIM_EE_GetSrc\n
9201 * EECR1 EE3SRC LL_HRTIM_EE_GetSrc\n
9202 * EECR1 EE4SRC LL_HRTIM_EE_GetSrc\n
9203 * EECR1 EE5SRC LL_HRTIM_EE_GetSrc\n
9204 * EECR2 EE6SRC LL_HRTIM_EE_GetSrc\n
9205 * EECR2 EE7SRC LL_HRTIM_EE_GetSrc\n
9206 * EECR2 EE8SRC LL_HRTIM_EE_GetSrc\n
9207 * EECR2 EE9SRC LL_HRTIM_EE_GetSrc\n
9208 * EECR2 EE10SRC LL_HRTIM_EE_GetSrc
9209 * @param HRTIMx High Resolution Timer instance
9210 * @param Event This parameter can be one of the following values:
9211 * @arg @ref LL_HRTIM_EVENT_1
9212 * @arg @ref LL_HRTIM_EVENT_2
9213 * @arg @ref LL_HRTIM_EVENT_3
9214 * @arg @ref LL_HRTIM_EVENT_4
9215 * @arg @ref LL_HRTIM_EVENT_5
9216 * @arg @ref LL_HRTIM_EVENT_6
9217 * @arg @ref LL_HRTIM_EVENT_7
9218 * @arg @ref LL_HRTIM_EVENT_8
9219 * @arg @ref LL_HRTIM_EVENT_9
9220 * @arg @ref LL_HRTIM_EVENT_10
9221 * @retval EventSrc This parameter can be one of the following values:
9222 * @arg External event source 1
9223 * @arg External event source 2
9224 * @arg External event source 3
9225 * @arg External event source 4
9226 */
LL_HRTIM_EE_GetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Event)9227 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event)
9228 {
9229 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9230 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9231 REG_OFFSET_TAB_EECR[iEvent]));
9232 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9233 }
9234
9235 /**
9236 * @brief Set the polarity of an external event.
9237 * @rmtoll EECR1 EE1POL LL_HRTIM_EE_SetPolarity\n
9238 * EECR1 EE2POL LL_HRTIM_EE_SetPolarity\n
9239 * EECR1 EE3POL LL_HRTIM_EE_SetPolarity\n
9240 * EECR1 EE4POL LL_HRTIM_EE_SetPolarity\n
9241 * EECR1 EE5POL LL_HRTIM_EE_SetPolarity\n
9242 * EECR2 EE6POL LL_HRTIM_EE_SetPolarity\n
9243 * EECR2 EE7POL LL_HRTIM_EE_SetPolarity\n
9244 * EECR2 EE8POL LL_HRTIM_EE_SetPolarity\n
9245 * EECR2 EE9POL LL_HRTIM_EE_SetPolarity\n
9246 * EECR2 EE10POL LL_HRTIM_EE_SetPolarity
9247 * @note This function must not be called when the timer counter is enabled.
9248 * @note Event polarity is only significant when event detection is level-sensitive.
9249 * @param HRTIMx High Resolution Timer instance
9250 * @param Event This parameter can be one of the following values:
9251 * @arg @ref LL_HRTIM_EVENT_1
9252 * @arg @ref LL_HRTIM_EVENT_2
9253 * @arg @ref LL_HRTIM_EVENT_3
9254 * @arg @ref LL_HRTIM_EVENT_4
9255 * @arg @ref LL_HRTIM_EVENT_5
9256 * @arg @ref LL_HRTIM_EVENT_6
9257 * @arg @ref LL_HRTIM_EVENT_7
9258 * @arg @ref LL_HRTIM_EVENT_8
9259 * @arg @ref LL_HRTIM_EVENT_9
9260 * @arg @ref LL_HRTIM_EVENT_10
9261 * @param Polarity This parameter can be one of the following values:
9262 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH
9263 * @arg @ref LL_HRTIM_EE_POLARITY_LOW
9264 * @retval None
9265 */
LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Polarity)9266 __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity)
9267 {
9268 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9269 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9270 REG_OFFSET_TAB_EECR[iEvent]));
9271 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent]));
9272 }
9273
9274 /**
9275 * @brief Get actual polarity setting of an external event.
9276 * @rmtoll EECR1 EE1POL LL_HRTIM_EE_GetPolarity\n
9277 * EECR1 EE2POL LL_HRTIM_EE_GetPolarity\n
9278 * EECR1 EE3POL LL_HRTIM_EE_GetPolarity\n
9279 * EECR1 EE4POL LL_HRTIM_EE_GetPolarity\n
9280 * EECR1 EE5POL LL_HRTIM_EE_GetPolarity\n
9281 * EECR2 EE6POL LL_HRTIM_EE_GetPolarity\n
9282 * EECR2 EE7POL LL_HRTIM_EE_GetPolarity\n
9283 * EECR2 EE8POL LL_HRTIM_EE_GetPolarity\n
9284 * EECR2 EE9POL LL_HRTIM_EE_GetPolarity\n
9285 * EECR2 EE10POL LL_HRTIM_EE_GetPolarity
9286 * @param HRTIMx High Resolution Timer instance
9287 * @param Event This parameter can be one of the following values:
9288 * @arg @ref LL_HRTIM_EVENT_1
9289 * @arg @ref LL_HRTIM_EVENT_2
9290 * @arg @ref LL_HRTIM_EVENT_3
9291 * @arg @ref LL_HRTIM_EVENT_4
9292 * @arg @ref LL_HRTIM_EVENT_5
9293 * @arg @ref LL_HRTIM_EVENT_6
9294 * @arg @ref LL_HRTIM_EVENT_7
9295 * @arg @ref LL_HRTIM_EVENT_8
9296 * @arg @ref LL_HRTIM_EVENT_9
9297 * @arg @ref LL_HRTIM_EVENT_10
9298 * @retval Polarity This parameter can be one of the following values:
9299 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH
9300 * @arg @ref LL_HRTIM_EE_POLARITY_LOW
9301 */
LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Event)9302 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
9303 {
9304 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9305 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9306 REG_OFFSET_TAB_EECR[iEvent]));
9307 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9308 }
9309
9310 /**
9311 * @brief Set the sensitivity of an external event.
9312 * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_SetSensitivity\n
9313 * EECR1 EE2SNS LL_HRTIM_EE_SetSensitivity\n
9314 * EECR1 EE3SNS LL_HRTIM_EE_SetSensitivity\n
9315 * EECR1 EE4SNS LL_HRTIM_EE_SetSensitivity\n
9316 * EECR1 EE5SNS LL_HRTIM_EE_SetSensitivity\n
9317 * EECR2 EE6SNS LL_HRTIM_EE_SetSensitivity\n
9318 * EECR2 EE7SNS LL_HRTIM_EE_SetSensitivity\n
9319 * EECR2 EE8SNS LL_HRTIM_EE_SetSensitivity\n
9320 * EECR2 EE9SNS LL_HRTIM_EE_SetSensitivity\n
9321 * EECR2 EE10SNS LL_HRTIM_EE_SetSensitivity
9322 * @param HRTIMx High Resolution Timer instance
9323 * @param Event This parameter can be one of the following values:
9324 * @arg @ref LL_HRTIM_EVENT_1
9325 * @arg @ref LL_HRTIM_EVENT_2
9326 * @arg @ref LL_HRTIM_EVENT_3
9327 * @arg @ref LL_HRTIM_EVENT_4
9328 * @arg @ref LL_HRTIM_EVENT_5
9329 * @arg @ref LL_HRTIM_EVENT_6
9330 * @arg @ref LL_HRTIM_EVENT_7
9331 * @arg @ref LL_HRTIM_EVENT_8
9332 * @arg @ref LL_HRTIM_EVENT_9
9333 * @arg @ref LL_HRTIM_EVENT_10
9334 * @param Sensitivity This parameter can be one of the following values:
9335 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
9336 * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
9337 * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
9338 * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
9339 * @retval None
9340 */
9341
LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Sensitivity)9342 __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity)
9343 {
9344 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9345 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9346 REG_OFFSET_TAB_EECR[iEvent]));
9347 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent]));
9348 }
9349
9350 /**
9351 * @brief Get actual sensitivity setting of an external event.
9352 * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_GetSensitivity\n
9353 * EECR1 EE2SNS LL_HRTIM_EE_GetSensitivity\n
9354 * EECR1 EE3SNS LL_HRTIM_EE_GetSensitivity\n
9355 * EECR1 EE4SNS LL_HRTIM_EE_GetSensitivity\n
9356 * EECR1 EE5SNS LL_HRTIM_EE_GetSensitivity\n
9357 * EECR2 EE6SNS LL_HRTIM_EE_GetSensitivity\n
9358 * EECR2 EE7SNS LL_HRTIM_EE_GetSensitivity\n
9359 * EECR2 EE8SNS LL_HRTIM_EE_GetSensitivity\n
9360 * EECR2 EE9SNS LL_HRTIM_EE_GetSensitivity\n
9361 * EECR2 EE10SNS LL_HRTIM_EE_GetSensitivity
9362 * @param HRTIMx High Resolution Timer instance
9363 * @param Event This parameter can be one of the following values:
9364 * @arg @ref LL_HRTIM_EVENT_1
9365 * @arg @ref LL_HRTIM_EVENT_2
9366 * @arg @ref LL_HRTIM_EVENT_3
9367 * @arg @ref LL_HRTIM_EVENT_4
9368 * @arg @ref LL_HRTIM_EVENT_5
9369 * @arg @ref LL_HRTIM_EVENT_6
9370 * @arg @ref LL_HRTIM_EVENT_7
9371 * @arg @ref LL_HRTIM_EVENT_8
9372 * @arg @ref LL_HRTIM_EVENT_9
9373 * @arg @ref LL_HRTIM_EVENT_10
9374 * @retval Polarity This parameter can be one of the following values:
9375 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
9376 * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
9377 * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
9378 * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
9379 */
LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef * HRTIMx,uint32_t Event)9380 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
9381 {
9382 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9383 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9384 REG_OFFSET_TAB_EECR[iEvent]));
9385 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9386 }
9387
9388 /**
9389 * @brief Set the fast mode of an external event.
9390 * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_SetFastMode\n
9391 * EECR1 EE2FAST LL_HRTIM_EE_SetFastMode\n
9392 * EECR1 EE3FAST LL_HRTIM_EE_SetFastMode\n
9393 * EECR1 EE4FAST LL_HRTIM_EE_SetFastMode\n
9394 * EECR1 EE5FAST LL_HRTIM_EE_SetFastMode\n
9395 * EECR2 EE6FAST LL_HRTIM_EE_SetFastMode\n
9396 * EECR2 EE7FAST LL_HRTIM_EE_SetFastMode\n
9397 * EECR2 EE8FAST LL_HRTIM_EE_SetFastMode\n
9398 * EECR2 EE9FAST LL_HRTIM_EE_SetFastMode\n
9399 * EECR2 EE10FAST LL_HRTIM_EE_SetFastMode
9400 * @note This function must not be called when the timer counter is enabled.
9401 * @param HRTIMx High Resolution Timer instance
9402 * @param Event This parameter can be one of the following values:
9403 * @arg @ref LL_HRTIM_EVENT_1
9404 * @arg @ref LL_HRTIM_EVENT_2
9405 * @arg @ref LL_HRTIM_EVENT_3
9406 * @arg @ref LL_HRTIM_EVENT_4
9407 * @arg @ref LL_HRTIM_EVENT_5
9408 * @param FastMode This parameter can be one of the following values:
9409 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
9410 * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
9411 * @retval None
9412 */
LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t FastMode)9413 __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode)
9414 {
9415 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9416 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9417 REG_OFFSET_TAB_EECR[iEvent]));
9418 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent]));
9419 }
9420
9421 /**
9422 * @brief Get actual fast mode setting of an external event.
9423 * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_GetFastMode\n
9424 * EECR1 EE2FAST LL_HRTIM_EE_GetFastMode\n
9425 * EECR1 EE3FAST LL_HRTIM_EE_GetFastMode\n
9426 * EECR1 EE4FAST LL_HRTIM_EE_GetFastMode\n
9427 * EECR1 EE5FAST LL_HRTIM_EE_GetFastMode\n
9428 * EECR2 EE6FAST LL_HRTIM_EE_GetFastMode\n
9429 * EECR2 EE7FAST LL_HRTIM_EE_GetFastMode\n
9430 * EECR2 EE8FAST LL_HRTIM_EE_GetFastMode\n
9431 * EECR2 EE9FAST LL_HRTIM_EE_GetFastMode\n
9432 * EECR2 EE10FAST LL_HRTIM_EE_GetFastMode
9433 * @param HRTIMx High Resolution Timer instance
9434 * @param Event This parameter can be one of the following values:
9435 * @arg @ref LL_HRTIM_EVENT_1
9436 * @arg @ref LL_HRTIM_EVENT_2
9437 * @arg @ref LL_HRTIM_EVENT_3
9438 * @arg @ref LL_HRTIM_EVENT_4
9439 * @arg @ref LL_HRTIM_EVENT_5
9440 * @retval FastMode This parameter can be one of the following values:
9441 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
9442 * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
9443 */
LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef * HRTIMx,uint32_t Event)9444 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event)
9445 {
9446 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9447 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9448 REG_OFFSET_TAB_EECR[iEvent]));
9449 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9450 }
9451
9452 /**
9453 * @brief Set the digital noise filter of a external event.
9454 * @rmtoll EECR3 EE6F LL_HRTIM_EE_SetFilter\n
9455 * EECR3 EE7F LL_HRTIM_EE_SetFilter\n
9456 * EECR3 EE8F LL_HRTIM_EE_SetFilter\n
9457 * EECR3 EE9F LL_HRTIM_EE_SetFilter\n
9458 * EECR3 EE10F LL_HRTIM_EE_SetFilter
9459 * @param HRTIMx High Resolution Timer instance
9460 * @param Event This parameter can be one of the following values:
9461 * @arg @ref LL_HRTIM_EVENT_6
9462 * @arg @ref LL_HRTIM_EVENT_7
9463 * @arg @ref LL_HRTIM_EVENT_8
9464 * @arg @ref LL_HRTIM_EVENT_9
9465 * @arg @ref LL_HRTIM_EVENT_10
9466 * @param Filter This parameter can be one of the following values:
9467 * @arg @ref LL_HRTIM_EE_FILTER_NONE
9468 * @arg @ref LL_HRTIM_EE_FILTER_1
9469 * @arg @ref LL_HRTIM_EE_FILTER_2
9470 * @arg @ref LL_HRTIM_EE_FILTER_3
9471 * @arg @ref LL_HRTIM_EE_FILTER_4
9472 * @arg @ref LL_HRTIM_EE_FILTER_5
9473 * @arg @ref LL_HRTIM_EE_FILTER_6
9474 * @arg @ref LL_HRTIM_EE_FILTER_7
9475 * @arg @ref LL_HRTIM_EE_FILTER_8
9476 * @arg @ref LL_HRTIM_EE_FILTER_9
9477 * @arg @ref LL_HRTIM_EE_FILTER_10
9478 * @arg @ref LL_HRTIM_EE_FILTER_11
9479 * @arg @ref LL_HRTIM_EE_FILTER_12
9480 * @arg @ref LL_HRTIM_EE_FILTER_13
9481 * @arg @ref LL_HRTIM_EE_FILTER_14
9482 * @arg @ref LL_HRTIM_EE_FILTER_15
9483 * @retval None
9484 */
LL_HRTIM_EE_SetFilter(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Filter)9485 __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter)
9486 {
9487 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
9488 MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]),
9489 (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
9490 }
9491
9492 /**
9493 * @brief Get actual digital noise filter setting of a external event.
9494 * @rmtoll EECR3 EE6F LL_HRTIM_EE_GetFilter\n
9495 * EECR3 EE7F LL_HRTIM_EE_GetFilter\n
9496 * EECR3 EE8F LL_HRTIM_EE_GetFilter\n
9497 * EECR3 EE9F LL_HRTIM_EE_GetFilter\n
9498 * EECR3 EE10F LL_HRTIM_EE_GetFilter
9499 * @param HRTIMx High Resolution Timer instance
9500 * @param Event This parameter can be one of the following values:
9501 * @arg @ref LL_HRTIM_EVENT_6
9502 * @arg @ref LL_HRTIM_EVENT_7
9503 * @arg @ref LL_HRTIM_EVENT_8
9504 * @arg @ref LL_HRTIM_EVENT_9
9505 * @arg @ref LL_HRTIM_EVENT_10
9506 * @retval Filter This parameter can be one of the following values:
9507 * @arg @ref LL_HRTIM_EE_FILTER_NONE
9508 * @arg @ref LL_HRTIM_EE_FILTER_1
9509 * @arg @ref LL_HRTIM_EE_FILTER_2
9510 * @arg @ref LL_HRTIM_EE_FILTER_3
9511 * @arg @ref LL_HRTIM_EE_FILTER_4
9512 * @arg @ref LL_HRTIM_EE_FILTER_5
9513 * @arg @ref LL_HRTIM_EE_FILTER_6
9514 * @arg @ref LL_HRTIM_EE_FILTER_7
9515 * @arg @ref LL_HRTIM_EE_FILTER_8
9516 * @arg @ref LL_HRTIM_EE_FILTER_9
9517 * @arg @ref LL_HRTIM_EE_FILTER_10
9518 * @arg @ref LL_HRTIM_EE_FILTER_11
9519 * @arg @ref LL_HRTIM_EE_FILTER_12
9520 * @arg @ref LL_HRTIM_EE_FILTER_13
9521 * @arg @ref LL_HRTIM_EE_FILTER_14
9522 * @arg @ref LL_HRTIM_EE_FILTER_15
9523 */
LL_HRTIM_EE_GetFilter(HRTIM_TypeDef * HRTIMx,uint32_t Event)9524 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event)
9525 {
9526 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6));
9527 return (READ_BIT(HRTIMx->sCommonRegs.EECR3,
9528 (uint32_t)(HRTIM_EECR3_EE6F) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9529 }
9530
9531 /**
9532 * @brief Set the external event prescaler.
9533 * @rmtoll EECR3 EEVSD LL_HRTIM_EE_SetPrescaler
9534 * @param HRTIMx High Resolution Timer instance
9535 * @param Prescaler This parameter can be one of the following values:
9536 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
9537 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
9538 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
9539 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
9540 * @retval None
9541 */
9542
LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Prescaler)9543 __STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
9544 {
9545 MODIFY_REG(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, Prescaler);
9546 }
9547
9548 /**
9549 * @brief Get actual external event prescaler setting.
9550 * @rmtoll EECR3 EEVSD LL_HRTIM_EE_GetPrescaler
9551 * @param HRTIMx High Resolution Timer instance
9552 * @retval Prescaler This parameter can be one of the following values:
9553 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
9554 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
9555 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
9556 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
9557 */
9558
LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef * HRTIMx)9559 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef *HRTIMx)
9560 {
9561 return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD));
9562 }
9563
9564 /**
9565 * @}
9566 */
9567
9568 /** @defgroup HRTIM_LL_EF_Fault_management Fault_management
9569 * @{
9570 */
9571 /**
9572 * @brief Configure fault signal conditioning Polarity and Source.
9573 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_Config\n
9574 * FLTINR1 FLT1SRC LL_HRTIM_FLT_Config\n
9575 * FLTINR1 FLT2P LL_HRTIM_FLT_Config\n
9576 * FLTINR1 FLT2SRC LL_HRTIM_FLT_Config\n
9577 * FLTINR1 FLT3P LL_HRTIM_FLT_Config\n
9578 * FLTINR1 FLT3SRC LL_HRTIM_FLT_Config\n
9579 * FLTINR1 FLT4P LL_HRTIM_FLT_Config\n
9580 * FLTINR1 FLT4SRC LL_HRTIM_FLT_Config\n
9581 * FLTINR2 FLT5P LL_HRTIM_FLT_Config\n
9582 * FLTINR2 FLT5SRC LL_HRTIM_FLT_Config\n
9583 * FLTINR2 FLT6P LL_HRTIM_FLT_Config\n
9584 * FLTINR2 FLT6SRC LL_HRTIM_FLT_Config
9585 * @note This function must not be called when the fault channel is enabled.
9586 * @param HRTIMx High Resolution Timer instance
9587 * @param Fault This parameter can be one of the following values:
9588 * @arg @ref LL_HRTIM_FAULT_1
9589 * @arg @ref LL_HRTIM_FAULT_2
9590 * @arg @ref LL_HRTIM_FAULT_3
9591 * @arg @ref LL_HRTIM_FAULT_4
9592 * @arg @ref LL_HRTIM_FAULT_5
9593 * @arg @ref LL_HRTIM_FAULT_6
9594 * @param Configuration This parameter must be a combination of all the following values:
9595 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT..LL_HRTIM_FLT_SRC_EEVINPUT
9596 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW..LL_HRTIM_FLT_POLARITY_HIGH
9597 * @retval None
9598 */
LL_HRTIM_FLT_Config(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Configuration)9599 __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration)
9600 {
9601 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9602 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9603 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9604
9605 uint64_t cfg;
9606 uint64_t mask;
9607
9608 cfg = ((uint64_t)((uint64_t)Configuration & (uint64_t)HRTIM_FLT_CONFIG_MASK) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 and polarity bits */
9609 (((uint64_t)((uint64_t)Configuration & (uint64_t)HRTIM_FLT_SRC_1_MASK) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe 1 bit */
9610
9611 mask = ((uint64_t)(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 and polarity bits */
9612 ((uint64_t)(HRTIM_FLT_SRC_1_MASK) << 32U); /* this for SouRCe bit 1 */
9613
9614 MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
9615 MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg >> 32U));
9616
9617 }
9618
9619 /**
9620 * @brief Set the source of a fault signal.
9621 * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_SetSrc\n
9622 * FLTINR1 FLT2SRC LL_HRTIM_FLT_SetSrc\n
9623 * FLTINR1 FLT3SRC LL_HRTIM_FLT_SetSrc\n
9624 * FLTINR1 FLT4SRC LL_HRTIM_FLT_SetSrc\n
9625 * FLTINR2 FLT5SRC LL_HRTIM_FLT_SetSrc\n
9626 * FLTINR2 FLT6SRC LL_HRTIM_FLT_SetSrc
9627 * @note This function must not be called when the fault channel is enabled.
9628 * @param HRTIMx High Resolution Timer instance
9629 * @param Fault This parameter can be one of the following values:
9630 * @arg @ref LL_HRTIM_FAULT_1
9631 * @arg @ref LL_HRTIM_FAULT_2
9632 * @arg @ref LL_HRTIM_FAULT_3
9633 * @arg @ref LL_HRTIM_FAULT_4
9634 * @arg @ref LL_HRTIM_FAULT_5
9635 * @arg @ref LL_HRTIM_FAULT_6
9636 * @param Src This parameter can be one of the following values:
9637 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
9638 * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
9639 * @arg @ref LL_HRTIM_FLT_SRC_EEVINPUT
9640 * @retval None
9641 */
LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Src)9642 __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src)
9643 {
9644 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9645 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9646 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9647
9648 uint64_t cfg = ( (uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 bit */
9649 (((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLT_SRC_1_MASK) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe 1 bit */
9650 uint64_t mask = ( (uint64_t)(HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe bit 0 */
9651 (((uint64_t)(HRTIM_FLTINR2_FLT1SRC_1) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe bit 1 */
9652
9653 MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
9654 MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg >> 32U));
9655 }
9656
9657 /**
9658 * @brief Get actual source of a fault signal.
9659 * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_GetSrc\n
9660 * FLTINR1 FLT2SRC LL_HRTIM_FLT_GetSrc\n
9661 * FLTINR1 FLT3SRC LL_HRTIM_FLT_GetSrc\n
9662 * FLTINR1 FLT4SRC LL_HRTIM_FLT_GetSrc\n
9663 * FLTINR2 FLT5SRC LL_HRTIM_FLT_GetSrc\n
9664 * FLTINR2 FLT6SRC LL_HRTIM_FLT_GetSrc
9665 * @param HRTIMx High Resolution Timer instance
9666 * @param Fault This parameter can be one of the following values:
9667 * @arg @ref LL_HRTIM_FAULT_1
9668 * @arg @ref LL_HRTIM_FAULT_2
9669 * @arg @ref LL_HRTIM_FAULT_3
9670 * @arg @ref LL_HRTIM_FAULT_4
9671 * @arg @ref LL_HRTIM_FAULT_5
9672 * @arg @ref LL_HRTIM_FAULT_6
9673 * @retval Source This parameter can be one of the following values:
9674 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
9675 * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
9676 * @arg @ref LL_HRTIM_FLT_SRC_EEVINPUT
9677 */
LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Fault)9678 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
9679 {
9680 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9681 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9682 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9683
9684 uint64_t Src0;
9685 uint32_t Src1;
9686 uint32_t temp1, temp2; /* temp variables used for MISRA-C */
9687
9688 /* this for SouRCe bit 1 */
9689 Src1 = READ_BIT(*pReg2, HRTIM_FLT_SRC_1_MASK) >> REG_SHIFT_TAB_FLTx[iFault] ;
9690 temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5SRC_0 | HRTIM_FLTINR2_FLT6SRC_0));
9691 temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1SRC_0 | HRTIM_FLTINR1_FLT2SRC_0 | HRTIM_FLTINR1_FLT3SRC_0 | HRTIM_FLTINR1_FLT4SRC_0));
9692
9693 /* this for SouRCe bit 0 */
9694 Src0 = (uint64_t)temp1 << 32U;
9695 Src0 |= (uint64_t)temp2;
9696 Src0 = (Src0 >> REG_SHIFT_TAB_FLTxF[iFault]) ;
9697
9698 return ((uint32_t)(Src0 | Src1));
9699 }
9700
9701 /**
9702 * @brief Set the polarity of a fault signal.
9703 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_SetPolarity\n
9704 * FLTINR1 FLT2P LL_HRTIM_FLT_SetPolarity\n
9705 * FLTINR1 FLT3P LL_HRTIM_FLT_SetPolarity\n
9706 * FLTINR1 FLT4P LL_HRTIM_FLT_SetPolarity\n
9707 * FLTINR2 FLT5P LL_HRTIM_FLT_SetPolarity\n
9708 * FLTINR2 FLT6P LL_HRTIM_FLT_SetPolarity
9709 * @note This function must not be called when the fault channel is enabled.
9710 * @param HRTIMx High Resolution Timer instance
9711 * @param Fault This parameter can be one of the following values:
9712 * @arg @ref LL_HRTIM_FAULT_1
9713 * @arg @ref LL_HRTIM_FAULT_2
9714 * @arg @ref LL_HRTIM_FAULT_3
9715 * @arg @ref LL_HRTIM_FAULT_4
9716 * @arg @ref LL_HRTIM_FAULT_5
9717 * @arg @ref LL_HRTIM_FAULT_6
9718 * @param Polarity This parameter can be one of the following values:
9719 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW
9720 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
9721 * @retval None
9722 */
LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Polarity)9723 __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity)
9724 {
9725 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9726 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9727 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9728
9729 uint64_t cfg = (uint64_t)((uint64_t)Polarity & (uint64_t)(HRTIM_FLTINR1_FLT1P)) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for Polarity bit */
9730 uint64_t mask = (uint64_t)(HRTIM_FLTINR1_FLT1P) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for Polarity bit */
9731
9732 /* for Polarity bit */
9733 MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
9734 MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg >> 32U));
9735 }
9736
9737 /**
9738 * @brief Get actual polarity of a fault signal.
9739 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_GetPolarity\n
9740 * FLTINR1 FLT2P LL_HRTIM_FLT_GetPolarity\n
9741 * FLTINR1 FLT3P LL_HRTIM_FLT_GetPolarity\n
9742 * FLTINR1 FLT4P LL_HRTIM_FLT_GetPolarity\n
9743 * FLTINR2 FLT5P LL_HRTIM_FLT_GetPolarity\n
9744 * FLTINR2 FLT6P LL_HRTIM_FLT_GetPolarity
9745 * @param HRTIMx High Resolution Timer instance
9746 * @param Fault This parameter can be one of the following values:
9747 * @arg @ref LL_HRTIM_FAULT_1
9748 * @arg @ref LL_HRTIM_FAULT_2
9749 * @arg @ref LL_HRTIM_FAULT_3
9750 * @arg @ref LL_HRTIM_FAULT_4
9751 * @arg @ref LL_HRTIM_FAULT_5
9752 * @arg @ref LL_HRTIM_FAULT_6
9753 * @retval Polarity This parameter can be one of the following values:
9754 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW
9755 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
9756 */
LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Fault)9757 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
9758 {
9759 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9760 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9761 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9762 uint32_t temp1, temp2; /* temp variables used for MISRA-C */
9763 uint64_t cfg;
9764
9765 temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT6P));
9766 temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT4P));
9767
9768 cfg = (uint64_t)temp1 << 32 ;
9769 cfg |= (uint64_t)temp2;
9770 cfg = (cfg >> REG_SHIFT_TAB_FLTxF[iFault]) ;
9771
9772 return (uint32_t)(cfg);
9773
9774 }
9775
9776 /**
9777 * @brief Set the digital noise filter of a fault signal.
9778 * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_SetFilter\n
9779 * FLTINR1 FLT2F LL_HRTIM_FLT_SetFilter\n
9780 * FLTINR1 FLT3F LL_HRTIM_FLT_SetFilter\n
9781 * FLTINR1 FLT4F LL_HRTIM_FLT_SetFilter\n
9782 * FLTINR2 FLT5F LL_HRTIM_FLT_SetFilter\n
9783 * FLTINR2 FLT6F LL_HRTIM_FLT_SetFilter
9784 * @note This function must not be called when the fault channel is enabled.
9785 * @param HRTIMx High Resolution Timer instance
9786 * @param Fault This parameter can be one of the following values:
9787 * @arg @ref LL_HRTIM_FAULT_1
9788 * @arg @ref LL_HRTIM_FAULT_2
9789 * @arg @ref LL_HRTIM_FAULT_3
9790 * @arg @ref LL_HRTIM_FAULT_4
9791 * @arg @ref LL_HRTIM_FAULT_5
9792 * @arg @ref LL_HRTIM_FAULT_6
9793 * @param Filter This parameter can be one of the following values:
9794 * @arg @ref LL_HRTIM_FLT_FILTER_NONE
9795 * @arg @ref LL_HRTIM_FLT_FILTER_1
9796 * @arg @ref LL_HRTIM_FLT_FILTER_2
9797 * @arg @ref LL_HRTIM_FLT_FILTER_3
9798 * @arg @ref LL_HRTIM_FLT_FILTER_4
9799 * @arg @ref LL_HRTIM_FLT_FILTER_5
9800 * @arg @ref LL_HRTIM_FLT_FILTER_6
9801 * @arg @ref LL_HRTIM_FLT_FILTER_7
9802 * @arg @ref LL_HRTIM_FLT_FILTER_8
9803 * @arg @ref LL_HRTIM_FLT_FILTER_9
9804 * @arg @ref LL_HRTIM_FLT_FILTER_10
9805 * @arg @ref LL_HRTIM_FLT_FILTER_11
9806 * @arg @ref LL_HRTIM_FLT_FILTER_12
9807 * @arg @ref LL_HRTIM_FLT_FILTER_13
9808 * @arg @ref LL_HRTIM_FLT_FILTER_14
9809 * @arg @ref LL_HRTIM_FLT_FILTER_15
9810 * @retval None
9811 */
LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Filter)9812 __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter)
9813 {
9814 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9815 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9816 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9817
9818 uint64_t flt = (uint64_t)((uint64_t)Filter & (uint64_t)HRTIM_FLTINR1_FLT1F) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for filter bits */
9819 uint64_t mask = (uint64_t)(HRTIM_FLTINR1_FLT1F) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for Polarity bit */
9820
9821 MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(flt));
9822 MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(flt >> 32U));
9823 }
9824
9825 /**
9826 * @brief Get actual digital noise filter setting of a fault signal.
9827 * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_GetFilter\n
9828 * FLTINR1 FLT2F LL_HRTIM_FLT_GetFilter\n
9829 * FLTINR1 FLT3F LL_HRTIM_FLT_GetFilter\n
9830 * FLTINR1 FLT4F LL_HRTIM_FLT_GetFilter\n
9831 * FLTINR2 FLT5F LL_HRTIM_FLT_GetFilter\n
9832 * FLTINR2 FLT6F LL_HRTIM_FLT_GetFilter
9833 * @param HRTIMx High Resolution Timer instance
9834 * @param Fault This parameter can be one of the following values:
9835 * @arg @ref LL_HRTIM_FAULT_1
9836 * @arg @ref LL_HRTIM_FAULT_2
9837 * @arg @ref LL_HRTIM_FAULT_3
9838 * @arg @ref LL_HRTIM_FAULT_4
9839 * @arg @ref LL_HRTIM_FAULT_5
9840 * @arg @ref LL_HRTIM_FAULT_6
9841 * @retval Filter This parameter can be one of the following values:
9842 * @arg @ref LL_HRTIM_FLT_FILTER_NONE
9843 * @arg @ref LL_HRTIM_FLT_FILTER_1
9844 * @arg @ref LL_HRTIM_FLT_FILTER_2
9845 * @arg @ref LL_HRTIM_FLT_FILTER_3
9846 * @arg @ref LL_HRTIM_FLT_FILTER_4
9847 * @arg @ref LL_HRTIM_FLT_FILTER_5
9848 * @arg @ref LL_HRTIM_FLT_FILTER_6
9849 * @arg @ref LL_HRTIM_FLT_FILTER_7
9850 * @arg @ref LL_HRTIM_FLT_FILTER_8
9851 * @arg @ref LL_HRTIM_FLT_FILTER_9
9852 * @arg @ref LL_HRTIM_FLT_FILTER_10
9853 * @arg @ref LL_HRTIM_FLT_FILTER_11
9854 * @arg @ref LL_HRTIM_FLT_FILTER_12
9855 * @arg @ref LL_HRTIM_FLT_FILTER_13
9856 * @arg @ref LL_HRTIM_FLT_FILTER_14
9857 * @arg @ref LL_HRTIM_FLT_FILTER_15
9858 */
LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef * HRTIMx,uint32_t Fault)9859 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
9860 {
9861 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9862 __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9863 __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9864 uint32_t temp1, temp2; /* temp variables used for MISRA-C */
9865 uint64_t flt;
9866 temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT6F));
9867 temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT4F));
9868
9869 flt = (uint64_t)temp1 << 32U;
9870 flt |= (uint64_t)temp2;
9871 flt = (flt >> REG_SHIFT_TAB_FLTxF[iFault]) ;
9872
9873 return (uint32_t)(flt);
9874
9875 }
9876
9877 /**
9878 * @brief Set the fault circuitry prescaler.
9879 * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_SetPrescaler
9880 * @param HRTIMx High Resolution Timer instance
9881 * @param Prescaler This parameter can be one of the following values:
9882 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
9883 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
9884 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
9885 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
9886 * @retval None
9887 */
LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Prescaler)9888 __STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
9889 {
9890 MODIFY_REG(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, Prescaler);
9891 }
9892
9893 /**
9894 * @brief Get actual fault circuitry prescaler setting.
9895 * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_GetPrescaler
9896 * @param HRTIMx High Resolution Timer instance
9897 * @retval Prescaler This parameter can be one of the following values:
9898 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
9899 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
9900 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
9901 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
9902 */
LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef * HRTIMx)9903 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef *HRTIMx)
9904 {
9905 return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD));
9906 }
9907
9908 /**
9909 * @brief Lock the fault signal conditioning settings.
9910 * @rmtoll FLTINR1 FLT1LCK LL_HRTIM_FLT_Lock\n
9911 * FLTINR1 FLT2LCK LL_HRTIM_FLT_Lock\n
9912 * FLTINR1 FLT3LCK LL_HRTIM_FLT_Lock\n
9913 * FLTINR1 FLT4LCK LL_HRTIM_FLT_Lock\n
9914 * FLTINR2 FLT5LCK LL_HRTIM_FLT_Lock\n
9915 * FLTINR2 FLT6LCK LL_HRTIM_FLT_Lock
9916 * @param HRTIMx High Resolution Timer instance
9917 * @param Fault This parameter can be one of the following values:
9918 * @arg @ref LL_HRTIM_FAULT_1
9919 * @arg @ref LL_HRTIM_FAULT_2
9920 * @arg @ref LL_HRTIM_FAULT_3
9921 * @arg @ref LL_HRTIM_FAULT_4
9922 * @arg @ref LL_HRTIM_FAULT_5
9923 * @arg @ref LL_HRTIM_FAULT_6
9924 * @retval None
9925 */
LL_HRTIM_FLT_Lock(HRTIM_TypeDef * HRTIMx,uint32_t Fault)9926 __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
9927 {
9928 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9929 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
9930 REG_OFFSET_TAB_FLTINR[iFault]));
9931 SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault]));
9932 }
9933
9934 /**
9935 * @brief Enable the fault circuitry for the designated fault input.
9936 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Enable\n
9937 * FLTINR1 FLT2E LL_HRTIM_FLT_Enable\n
9938 * FLTINR1 FLT3E LL_HRTIM_FLT_Enable\n
9939 * FLTINR1 FLT4E LL_HRTIM_FLT_Enable\n
9940 * FLTINR2 FLT5E LL_HRTIM_FLT_Enable\n
9941 * FLTINR2 FLT6E LL_HRTIM_FLT_Enable
9942 * @param HRTIMx High Resolution Timer instance
9943 * @param Fault This parameter can be one of the following values:
9944 * @arg @ref LL_HRTIM_FAULT_1
9945 * @arg @ref LL_HRTIM_FAULT_2
9946 * @arg @ref LL_HRTIM_FAULT_3
9947 * @arg @ref LL_HRTIM_FAULT_4
9948 * @arg @ref LL_HRTIM_FAULT_5
9949 * @arg @ref LL_HRTIM_FAULT_6
9950 * @retval None
9951 */
LL_HRTIM_FLT_Enable(HRTIM_TypeDef * HRTIMx,uint32_t Fault)9952 __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
9953 {
9954 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9955 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
9956 REG_OFFSET_TAB_FLTINR[iFault]));
9957 SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
9958 }
9959
9960 /**
9961 * @brief Disable the fault circuitry for for the designated fault input.
9962 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Disable\n
9963 * FLTINR1 FLT2E LL_HRTIM_FLT_Disable\n
9964 * FLTINR1 FLT3E LL_HRTIM_FLT_Disable\n
9965 * FLTINR1 FLT4E LL_HRTIM_FLT_Disable\n
9966 * FLTINR2 FLT5E LL_HRTIM_FLT_Disable\n
9967 * FLTINR2 FLT6E LL_HRTIM_FLT_Disable
9968 * @param HRTIMx High Resolution Timer instance
9969 * @param Fault This parameter can be one of the following values:
9970 * @arg @ref LL_HRTIM_FAULT_1
9971 * @arg @ref LL_HRTIM_FAULT_2
9972 * @arg @ref LL_HRTIM_FAULT_3
9973 * @arg @ref LL_HRTIM_FAULT_4
9974 * @arg @ref LL_HRTIM_FAULT_5
9975 * @arg @ref LL_HRTIM_FAULT_6
9976 * @retval None
9977 */
LL_HRTIM_FLT_Disable(HRTIM_TypeDef * HRTIMx,uint32_t Fault)9978 __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
9979 {
9980 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
9981 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
9982 REG_OFFSET_TAB_FLTINR[iFault]));
9983 CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
9984
9985 }
9986
9987 /**
9988 * @brief Indicate whether the fault circuitry is enabled for a given fault input.
9989 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_IsEnabled\n
9990 * FLTINR1 FLT2E LL_HRTIM_FLT_IsEnabled\n
9991 * FLTINR1 FLT3E LL_HRTIM_FLT_IsEnabled\n
9992 * FLTINR1 FLT4E LL_HRTIM_FLT_IsEnabled\n
9993 * FLTINR2 FLT5E LL_HRTIM_FLT_IsEnabled\n
9994 * FLTINR2 FLT6E LL_HRTIM_FLT_IsEnabled
9995 * @param HRTIMx High Resolution Timer instance
9996 * @param Fault This parameter can be one of the following values:
9997 * @arg @ref LL_HRTIM_FAULT_1
9998 * @arg @ref LL_HRTIM_FAULT_2
9999 * @arg @ref LL_HRTIM_FAULT_3
10000 * @arg @ref LL_HRTIM_FAULT_4
10001 * @arg @ref LL_HRTIM_FAULT_5
10002 * @arg @ref LL_HRTIM_FAULT_6
10003 * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0).
10004 */
LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10005 __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10006 {
10007 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10008 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
10009 REG_OFFSET_TAB_FLTINR[iFault]));
10010 return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) ==
10011 (HRTIM_FLTINR1_FLT1E)) ? 1UL : 0UL);
10012 }
10013
10014 /**
10015 * @brief Enable the Blanking of the fault circuitry for the designated fault input.
10016 * @rmtoll FLTINR1 FLT1BLKE LL_HRTIM_FLT_EnableBlanking\n
10017 * FLTINR1 FLT2BLKE LL_HRTIM_FLT_EnableBlanking\n
10018 * FLTINR1 FLT3BLKE LL_HRTIM_FLT_EnableBlanking\n
10019 * FLTINR1 FLT4BLKE LL_HRTIM_FLT_EnableBlanking\n
10020 * FLTINR2 FLT5BLKE LL_HRTIM_FLT_EnableBlanking\n
10021 * FLTINR2 FLT6BLKE LL_HRTIM_FLT_EnableBlanking
10022 * @param HRTIMx High Resolution Timer instance
10023 * @param Fault This parameter can be one of the following values:
10024 * @arg @ref LL_HRTIM_FAULT_1
10025 * @arg @ref LL_HRTIM_FAULT_2
10026 * @arg @ref LL_HRTIM_FAULT_3
10027 * @arg @ref LL_HRTIM_FAULT_4
10028 * @arg @ref LL_HRTIM_FAULT_5
10029 * @arg @ref LL_HRTIM_FAULT_6
10030 * @retval None
10031 */
LL_HRTIM_FLT_EnableBlanking(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10032 __STATIC_INLINE void LL_HRTIM_FLT_EnableBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10033 {
10034 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10035 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10036 REG_OFFSET_TAB_FLTINR[iFault]));
10037 SET_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKE) << REG_SHIFT_TAB_FLTxE[iFault]);
10038 }
10039
10040 /**
10041 * @brief Disable the Blanking of the fault circuitry for the designated fault input.
10042 * @rmtoll FLTINR1 FLT1BLKE LL_HRTIM_FLT_DisableBlanking\n
10043 * FLTINR1 FLT2BLKE LL_HRTIM_FLT_DisableBlanking\n
10044 * FLTINR1 FLT3BLKE LL_HRTIM_FLT_DisableBlanking\n
10045 * FLTINR1 FLT4BLKE LL_HRTIM_FLT_DisableBlanking\n
10046 * FLTINR2 FLT5BLKE LL_HRTIM_FLT_DisableBlanking\n
10047 * FLTINR2 FLT6BLKE LL_HRTIM_FLT_DisableBlanking
10048 * @param HRTIMx High Resolution Timer instance
10049 * @param Fault This parameter can be one of the following values:
10050 * @arg @ref LL_HRTIM_FAULT_1
10051 * @arg @ref LL_HRTIM_FAULT_2
10052 * @arg @ref LL_HRTIM_FAULT_3
10053 * @arg @ref LL_HRTIM_FAULT_4
10054 * @arg @ref LL_HRTIM_FAULT_5
10055 * @arg @ref LL_HRTIM_FAULT_6
10056 * @retval None
10057 */
LL_HRTIM_FLT_DisableBlanking(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10058 __STATIC_INLINE void LL_HRTIM_FLT_DisableBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10059 {
10060 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10061 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10062 REG_OFFSET_TAB_FLTINR[iFault]));
10063 CLEAR_BIT(*pReg, (HRTIM_FLTINR3_FLT1BLKE << REG_SHIFT_TAB_FLTxE[iFault]));
10064 }
10065
10066 /**
10067 * @brief Indicate whether the Blanking of the fault circuitry is enabled for a given fault input.
10068 * @rmtoll FLTINR1 FLT1BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10069 * FLTINR1 FLT2BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10070 * FLTINR1 FLT3BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10071 * FLTINR1 FLT4BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10072 * FLTINR2 FLT5BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10073 * FLTINR2 FLT6BLKE LL_HRTIM_FLT_IsEnabledBlanking
10074 * @param HRTIMx High Resolution Timer instance
10075 * @param Fault This parameter can be one of the following values:
10076 * @arg @ref LL_HRTIM_FAULT_1
10077 * @arg @ref LL_HRTIM_FAULT_2
10078 * @arg @ref LL_HRTIM_FAULT_3
10079 * @arg @ref LL_HRTIM_FAULT_4
10080 * @arg @ref LL_HRTIM_FAULT_5
10081 * @arg @ref LL_HRTIM_FAULT_6
10082 * @retval State of FLTxBLKE bit in HRTIM_FLTINRx register (1 or 0).
10083 */
LL_HRTIM_FLT_IsEnabledBlanking(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10084 __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabledBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10085 {
10086 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10087 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10088 REG_OFFSET_TAB_FLTINR[iFault]));
10089 uint32_t temp; /* MISRAC-2012 compliance */
10090 temp = READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKE) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault];
10091
10092 return ((temp == (HRTIM_FLTINR3_FLT1BLKE)) ? 1UL : 0UL);
10093 }
10094
10095 /**
10096 * @brief Set the Blanking Source of the fault circuitry for a given fault input.
10097 * @note Fault inputs can be temporary disabled to blank spurious fault events.
10098 * @note This function allows for selection amongst 2 possible blanking sources.
10099 * @note Events triggering blanking window start and blanking window end depend
10100 * on both the selected blanking source and the fault input.
10101 * @rmtoll FLTINR3 FLT1BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10102 * FLTINR3 FLT2BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10103 * FLTINR3 FLT3BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10104 * FLTINR3 FLT4BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10105 * FLTINR4 FLT5BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10106 * FLTINR4 FLT6BLKS LL_HRTIM_FLT_SetBlankingSrc
10107 * @param HRTIMx High Resolution Timer instance
10108 * @param Fault This parameter can be one of the following values:
10109 * @arg @ref LL_HRTIM_FAULT_1
10110 * @arg @ref LL_HRTIM_FAULT_2
10111 * @arg @ref LL_HRTIM_FAULT_3
10112 * @arg @ref LL_HRTIM_FAULT_4
10113 * @arg @ref LL_HRTIM_FAULT_5
10114 * @arg @ref LL_HRTIM_FAULT_6
10115 * @param Source parameter can be one of the following values:
10116 * @arg @ref LL_HRTIM_FLT_BLANKING_RSTALIGNED
10117 * @arg @ref LL_HRTIM_FLT_BLANKING_MOVING
10118 * @retval None
10119 */
LL_HRTIM_FLT_SetBlankingSrc(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Source)10120 __STATIC_INLINE void LL_HRTIM_FLT_SetBlankingSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Source)
10121 {
10122 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10123 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10124 REG_OFFSET_TAB_FLTINR[iFault]));
10125 MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1BLKS << REG_SHIFT_TAB_FLTxE[iFault]), (Source << REG_SHIFT_TAB_FLTxE[iFault]));
10126
10127 }
10128
10129 /**
10130 * @brief Get the Blanking Source of the fault circuitry is enabled for a given fault input.
10131 * @rmtoll FLTINR3 FLT1BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10132 * FLTINR3 FLT2BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10133 * FLTINR3 FLT3BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10134 * FLTINR3 FLT4BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10135 * FLTINR4 FLT5BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10136 * FLTINR4 FLT6BLKS LL_HRTIM_FLT_GetBlankingSrc
10137 * @param HRTIMx High Resolution Timer instance
10138 * @param Fault This parameter can be one of the following values:
10139 * @arg @ref LL_HRTIM_FAULT_1
10140 * @arg @ref LL_HRTIM_FAULT_2
10141 * @arg @ref LL_HRTIM_FAULT_3
10142 * @arg @ref LL_HRTIM_FAULT_4
10143 * @arg @ref LL_HRTIM_FAULT_5
10144 * @arg @ref LL_HRTIM_FAULT_6
10145 */
LL_HRTIM_FLT_GetBlankingSrc(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10146 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetBlankingSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10147 {
10148 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10149 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10150 REG_OFFSET_TAB_FLTINR[iFault]));
10151 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKS) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]));
10152 }
10153
10154 /**
10155 * @brief Set the Counter threshold value of a fault counter.
10156 * @rmtoll FLTINR3 FLT1CNT LL_HRTIM_FLT_SetCounterThreshold\n
10157 * FLTINR3 FLT2CNT LL_HRTIM_FLT_SetCounterThreshold\n
10158 * FLTINR3 FLT3CNT LL_HRTIM_FLT_SetCounterThreshold\n
10159 * FLTINR3 FLT4CNT LL_HRTIM_FLT_SetCounterThreshold\n
10160 * FLTINR4 FLT5CNT LL_HRTIM_FLT_SetCounterThreshold\n
10161 * FLTINR4 FLT6CNT LL_HRTIM_FLT_SetCounterThreshold
10162 * @note This function must not be called when the fault channel is enabled.
10163 * @param HRTIMx High Resolution Timer instance
10164 * @param Fault This parameter can be one of the following values:
10165 * @arg @ref LL_HRTIM_FAULT_1
10166 * @arg @ref LL_HRTIM_FAULT_2
10167 * @arg @ref LL_HRTIM_FAULT_3
10168 * @arg @ref LL_HRTIM_FAULT_4
10169 * @arg @ref LL_HRTIM_FAULT_5
10170 * @arg @ref LL_HRTIM_FAULT_6
10171 * @param Threshold This parameter can be a number between Min_Data=0 and Max_Data=15
10172 * @retval None
10173 */
LL_HRTIM_FLT_SetCounterThreshold(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Threshold)10174 __STATIC_INLINE void LL_HRTIM_FLT_SetCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Threshold)
10175 {
10176 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10177 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10178 REG_OFFSET_TAB_FLTINR[iFault]));
10179 MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1CNT << REG_SHIFT_TAB_FLTxE[iFault]), (Threshold << REG_SHIFT_TAB_FLTxE[iFault]));
10180 }
10181
10182 /**
10183 * @brief Get actual the Counter threshold value of a fault counter.
10184 * @rmtoll FLTINR3 FLT1CNT LL_HRTIM_FLT_GetCounterThreshold\n
10185 * FLTINR3 FLT2CNT LL_HRTIM_FLT_GetCounterThreshold\n
10186 * FLTINR3 FLT3CNT LL_HRTIM_FLT_GetCounterThreshold\n
10187 * FLTINR3 FLT4CNT LL_HRTIM_FLT_GetCounterThreshold\n
10188 * FLTINR4 FLT5CNT LL_HRTIM_FLT_GetCounterThreshold\n
10189 * FLTINR4 FLT6CNT LL_HRTIM_FLT_GetCounterThreshold
10190 * @param HRTIMx High Resolution Timer instance
10191 * @param Fault This parameter can be one of the following values:
10192 * @arg @ref LL_HRTIM_FAULT_1
10193 * @arg @ref LL_HRTIM_FAULT_2
10194 * @arg @ref LL_HRTIM_FAULT_3
10195 * @arg @ref LL_HRTIM_FAULT_4
10196 * @arg @ref LL_HRTIM_FAULT_5
10197 * @arg @ref LL_HRTIM_FAULT_6
10198 * @retval Threshold This parameter can be a number between Min_Data=0 and Max_Data=15
10199 */
LL_HRTIM_FLT_GetCounterThreshold(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10200 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10201 {
10202 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10203 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10204 REG_OFFSET_TAB_FLTINR[iFault]));
10205 return (READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CNT) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]);
10206 }
10207
10208 /**
10209 * @brief Set the mode of reset of a fault counter to 'always reset'.
10210 * @rmtoll FLTINR3 FLT1RSTM LL_HRTIM_FLT_SetResetMode\n
10211 * FLTINR3 FLT2RSTM LL_HRTIM_FLT_SetResetMode\n
10212 * FLTINR3 FLT3RSTM LL_HRTIM_FLT_SetResetMode\n
10213 * FLTINR3 FLT4RSTM LL_HRTIM_FLT_SetResetMode\n
10214 * FLTINR4 FLT5RSTM LL_HRTIM_FLT_SetResetMode\n
10215 * FLTINR4 FLT6RSTM LL_HRTIM_FLT_SetResetMode
10216 * @param HRTIMx High Resolution Timer instance
10217 * @param Fault This parameter can be one of the following values:
10218 * @arg @ref LL_HRTIM_FAULT_1
10219 * @arg @ref LL_HRTIM_FAULT_2
10220 * @arg @ref LL_HRTIM_FAULT_3
10221 * @arg @ref LL_HRTIM_FAULT_4
10222 * @arg @ref LL_HRTIM_FAULT_5
10223 * @arg @ref LL_HRTIM_FAULT_6
10224 * @param Mode This parameter can be one of the following values:
10225 * @arg @ref LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL
10226 * @arg @ref LL_HRTIM_FLT_COUNTERRST_CONDITIONAL
10227 * @retval None
10228 */
LL_HRTIM_FLT_SetResetMode(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Mode)10229 __STATIC_INLINE void LL_HRTIM_FLT_SetResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Mode)
10230 {
10231 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10232 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10233 REG_OFFSET_TAB_FLTINR[iFault]));
10234 MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1RSTM << REG_SHIFT_TAB_FLTxE[iFault]), Mode << REG_SHIFT_TAB_FLTxE[iFault]);
10235
10236 }
10237
10238 /**
10239 * @brief Get the mode of reset of a fault counter to 'reset on event'.
10240 * @rmtoll FLTINR3 FLT1RSTM LL_HRTIM_FLT_GetResetMode\n
10241 * FLTINR3 FLT2RSTM LL_HRTIM_FLT_GetResetMode\n
10242 * FLTINR3 FLT3RSTM LL_HRTIM_FLT_GetResetMode\n
10243 * FLTINR3 FLT4RSTM LL_HRTIM_FLT_GetResetMode\n
10244 * FLTINR4 FLT5RSTM LL_HRTIM_FLT_GetResetMode\n
10245 * FLTINR4 FLT6RSTM LL_HRTIM_FLT_GetResetMode
10246 * @param HRTIMx High Resolution Timer instance
10247 * @param Fault This parameter can be one of the following values:
10248 * @arg @ref LL_HRTIM_FAULT_1
10249 * @arg @ref LL_HRTIM_FAULT_2
10250 * @arg @ref LL_HRTIM_FAULT_3
10251 * @arg @ref LL_HRTIM_FAULT_4
10252 * @arg @ref LL_HRTIM_FAULT_5
10253 * @arg @ref LL_HRTIM_FAULT_6
10254 * @retval Mode This parameter can be one of the following values:
10255 * @arg @ref LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL
10256 * @arg @ref LL_HRTIM_FLT_COUNTERRST_CONDITIONAL
10257 */
LL_HRTIM_FLT_GetResetMode(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10258 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10259 {
10260 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10261 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10262 REG_OFFSET_TAB_FLTINR[iFault]));
10263 return READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1RSTM) << REG_SHIFT_TAB_FLTxE[iFault]);
10264 }
10265
10266 /**
10267 * @brief Reset the fault counter for a fault circuitry
10268 * @rmtoll FLTINR3 FLT1RSTM LL_HRTIM_FLT_ResetCounter\n
10269 * FLTINR3 FLT2RSTM LL_HRTIM_FLT_ResetCounter\n
10270 * FLTINR3 FLT3RSTM LL_HRTIM_FLT_ResetCounter\n
10271 * FLTINR3 FLT4RSTM LL_HRTIM_FLT_ResetCounter\n
10272 * FLTINR4 FLT5RSTM LL_HRTIM_FLT_ResetCounter\n
10273 * FLTINR4 FLT6RSTM LL_HRTIM_FLT_ResetCounter
10274 * @param HRTIMx High Resolution Timer instance
10275 * @param Fault This parameter can be one of the following values:
10276 * @arg @ref LL_HRTIM_FAULT_1
10277 * @arg @ref LL_HRTIM_FAULT_2
10278 * @arg @ref LL_HRTIM_FAULT_3
10279 * @arg @ref LL_HRTIM_FAULT_4
10280 * @arg @ref LL_HRTIM_FAULT_5
10281 * @arg @ref LL_HRTIM_FAULT_6
10282 * @retval None
10283 */
LL_HRTIM_FLT_ResetCounter(HRTIM_TypeDef * HRTIMx,uint32_t Fault)10284 __STATIC_INLINE void LL_HRTIM_FLT_ResetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10285 {
10286 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
10287 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10288 REG_OFFSET_TAB_FLTINR[iFault]));
10289 SET_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CRES) << REG_SHIFT_TAB_FLTxE[iFault]);
10290
10291 }
10292
10293 /**
10294 * @}
10295 */
10296
10297 /** @defgroup HRTIM_LL_EF_Burst_Mode_management Burst_Mode_management
10298 * @{
10299 */
10300
10301 /**
10302 * @brief Configure the burst mode controller.
10303 * @rmtoll BMCR BMOM LL_HRTIM_BM_Config\n
10304 * BMCR BMCLK LL_HRTIM_BM_Config\n
10305 * BMCR BMPRSC LL_HRTIM_BM_Config
10306 * @param HRTIMx High Resolution Timer instance
10307 * @param Configuration This parameter must be a combination of all the following values:
10308 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS
10309 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER or ... or @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10310 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 or ... @ref LL_HRTIM_BM_PRESCALER_DIV32768
10311 * @retval None
10312 */
LL_HRTIM_BM_Config(HRTIM_TypeDef * HRTIMx,uint32_t Configuration)10313 __STATIC_INLINE void LL_HRTIM_BM_Config(HRTIM_TypeDef *HRTIMx, uint32_t Configuration)
10314 {
10315 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BM_CONFIG_MASK, Configuration);
10316 }
10317
10318 /**
10319 * @brief Set the burst mode controller operating mode.
10320 * @rmtoll BMCR BMOM LL_HRTIM_BM_SetMode
10321 * @param HRTIMx High Resolution Timer instance
10322 * @param Mode This parameter can be one of the following values:
10323 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
10324 * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
10325 * @retval None
10326 */
LL_HRTIM_BM_SetMode(HRTIM_TypeDef * HRTIMx,uint32_t Mode)10327 __STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode)
10328 {
10329 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM, Mode);
10330 }
10331
10332 /**
10333 * @brief Get actual burst mode controller operating mode.
10334 * @rmtoll BMCR BMOM LL_HRTIM_BM_GetMode
10335 * @param HRTIMx High Resolution Timer instance
10336 * @retval Mode This parameter can be one of the following values:
10337 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
10338 * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
10339 */
LL_HRTIM_BM_GetMode(HRTIM_TypeDef * HRTIMx)10340 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(HRTIM_TypeDef *HRTIMx)
10341 {
10342 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM);
10343 }
10344
10345 /**
10346 * @brief Set the burst mode controller clock source.
10347 * @rmtoll BMCR BMCLK LL_HRTIM_BM_SetClockSrc
10348 * @param HRTIMx High Resolution Timer instance
10349 * @param ClockSrc This parameter can be one of the following values:
10350 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
10351 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
10352 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
10353 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
10354 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
10355 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
10356 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
10357 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
10358 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
10359 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10360 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_F
10361 * @retval None
10362 */
LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef * HRTIMx,uint32_t ClockSrc)10363 __STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t ClockSrc)
10364 {
10365 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK, ClockSrc);
10366 }
10367
10368 /**
10369 * @brief Get actual burst mode controller clock source.
10370 * @rmtoll BMCR BMCLK LL_HRTIM_BM_GetClockSrc
10371 * @param HRTIMx High Resolution Timer instance
10372 * @retval ClockSrc This parameter can be one of the following values:
10373 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
10374 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
10375 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
10376 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
10377 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
10378 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
10379 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
10380 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
10381 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
10382 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10383 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_F
10384 * @retval ClockSrc This parameter can be one of the following values:
10385 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
10386 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
10387 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
10388 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
10389 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
10390 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
10391 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
10392 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
10393 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
10394 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10395 */
LL_HRTIM_BM_GetClockSrc(HRTIM_TypeDef * HRTIMx)10396 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(HRTIM_TypeDef *HRTIMx)
10397 {
10398 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK);
10399 }
10400
10401 /**
10402 * @brief Set the burst mode controller prescaler.
10403 * @rmtoll BMCR BMPRSC LL_HRTIM_BM_SetPrescaler
10404 * @param HRTIMx High Resolution Timer instance
10405 * @param Prescaler This parameter can be one of the following values:
10406 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
10407 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
10408 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
10409 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
10410 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
10411 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
10412 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
10413 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
10414 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
10415 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
10416 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
10417 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
10418 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
10419 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
10420 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
10421 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
10422 * @retval None
10423 */
LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Prescaler)10424 __STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
10425 {
10426 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC, Prescaler);
10427 }
10428
10429 /**
10430 * @brief Get actual burst mode controller prescaler setting.
10431 * @rmtoll BMCR BMPRSC LL_HRTIM_BM_GetPrescaler
10432 * @param HRTIMx High Resolution Timer instance
10433 * @retval Prescaler This parameter can be one of the following values:
10434 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
10435 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
10436 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
10437 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
10438 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
10439 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
10440 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
10441 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
10442 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
10443 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
10444 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
10445 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
10446 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
10447 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
10448 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
10449 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
10450 */
LL_HRTIM_BM_GetPrescaler(HRTIM_TypeDef * HRTIMx)10451 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(HRTIM_TypeDef *HRTIMx)
10452 {
10453 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC);
10454 }
10455
10456 /**
10457 * @brief Enable burst mode compare and period registers preload.
10458 * @rmtoll BMCR BMPREN LL_HRTIM_BM_EnablePreload
10459 * @param HRTIMx High Resolution Timer instance
10460 * @retval None
10461 */
LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef * HRTIMx)10462 __STATIC_INLINE void LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef *HRTIMx)
10463 {
10464 SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
10465 }
10466
10467 /**
10468 * @brief Disable burst mode compare and period registers preload.
10469 * @rmtoll BMCR BMPREN LL_HRTIM_BM_DisablePreload
10470 * @param HRTIMx High Resolution Timer instance
10471 * @retval None
10472 */
LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef * HRTIMx)10473 __STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx)
10474 {
10475 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
10476 }
10477
10478 /**
10479 * @brief Indicate whether burst mode compare and period registers are preloaded.
10480 * @rmtoll BMCR BMPREN LL_HRTIM_BM_IsEnabledPreload
10481 * @param HRTIMx High Resolution Timer instance
10482 * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0).
10483 */
LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef * HRTIMx)10484 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx)
10485 {
10486 uint32_t temp; /* MISRAC-2012 compliance */
10487 temp = READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
10488
10489 return ((temp == (HRTIM_BMCR_BMPREN)) ? 1UL : 0UL);
10490 }
10491
10492 /**
10493 * @brief Set the burst mode controller trigger
10494 * @rmtoll BMTRGR SW LL_HRTIM_BM_SetTrig\n
10495 * BMTRGR MSTRST LL_HRTIM_BM_SetTrig\n
10496 * BMTRGR MSTREP LL_HRTIM_BM_SetTrig\n
10497 * BMTRGR MSTCMP1 LL_HRTIM_BM_SetTrig\n
10498 * BMTRGR MSTCMP2 LL_HRTIM_BM_SetTrig\n
10499 * BMTRGR MSTCMP3 LL_HRTIM_BM_SetTrig\n
10500 * BMTRGR MSTCMP4 LL_HRTIM_BM_SetTrig\n
10501 * BMTRGR TARST LL_HRTIM_BM_SetTrig\n
10502 * BMTRGR TAREP LL_HRTIM_BM_SetTrig\n
10503 * BMTRGR TACMP1 LL_HRTIM_BM_SetTrig\n
10504 * BMTRGR TACMP2 LL_HRTIM_BM_SetTrig\n
10505 * BMTRGR TBRST LL_HRTIM_BM_SetTrig\n
10506 * BMTRGR TBREP LL_HRTIM_BM_SetTrig\n
10507 * BMTRGR TBCMP1 LL_HRTIM_BM_SetTrig\n
10508 * BMTRGR TBCMP2 LL_HRTIM_BM_SetTrig\n
10509 * BMTRGR TCRST LL_HRTIM_BM_SetTrig\n
10510 * BMTRGR TCREP LL_HRTIM_BM_SetTrig\n
10511 * BMTRGR TCCMP1 LL_HRTIM_BM_SetTrig\n
10512 * BMTRGR TDRST LL_HRTIM_BM_SetTrig\n
10513 * BMTRGR TDREP LL_HRTIM_BM_SetTrig\n
10514 * BMTRGR TDCMP2 LL_HRTIM_BM_SetTrig\n
10515 * BMTRGR TEREP LL_HRTIM_BM_SetTrig\n
10516 * BMTRGR TECMP1 LL_HRTIM_BM_SetTrig\n
10517 * BMTRGR TECMP2 LL_HRTIM_BM_SetTrig\n
10518 * BMTRGR TFREP LL_HRTIM_BM_SetTrig\n
10519 * BMTRGR TFRST LL_HRTIM_BM_SetTrig\n
10520 * BMTRGR TFCMP1 LL_HRTIM_BM_SetTrig\n
10521 * BMTRGR TAEEV7 LL_HRTIM_BM_SetTrig\n
10522 * BMTRGR TAEEV8 LL_HRTIM_BM_SetTrig\n
10523 * BMTRGR EEV7 LL_HRTIM_BM_SetTrig\n
10524 * BMTRGR EEV8 LL_HRTIM_BM_SetTrig\n
10525 * BMTRGR OCHIPEV LL_HRTIM_BM_SetTrig
10526 * @param HRTIMx High Resolution Timer instance
10527 * @param Trig This parameter can be a combination of the following values:
10528 * @arg @ref LL_HRTIM_BM_TRIG_NONE
10529 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
10530 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
10531 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
10532 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
10533 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
10534 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
10535 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
10536 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
10537 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
10538 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
10539 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
10540 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
10541 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
10542 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
10543 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
10544 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
10545 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
10546 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
10547 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
10548 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
10549 * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
10550 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
10551 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
10552 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_RESET
10553 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_REPETITION
10554 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_CMP1
10555 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
10556 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
10557 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
10558 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
10559 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
10560 * @retval None
10561 */
LL_HRTIM_BM_SetTrig(HRTIM_TypeDef * HRTIMx,uint32_t Trig)10562 __STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig)
10563 {
10564 WRITE_REG(HRTIMx->sCommonRegs.BMTRGR, Trig);
10565 }
10566
10567 /**
10568 * @brief Get actual burst mode controller trigger.
10569 * @rmtoll BMTRGR SW LL_HRTIM_BM_GetTrig\n
10570 * BMTRGR MSTRST LL_HRTIM_BM_GetTrig\n
10571 * BMTRGR MSTREP LL_HRTIM_BM_GetTrig\n
10572 * BMTRGR MSTCMP1 LL_HRTIM_BM_GetTrig\n
10573 * BMTRGR MSTCMP2 LL_HRTIM_BM_GetTrig\n
10574 * BMTRGR MSTCMP3 LL_HRTIM_BM_GetTrig\n
10575 * BMTRGR MSTCMP4 LL_HRTIM_BM_GetTrig\n
10576 * BMTRGR TARST LL_HRTIM_BM_GetTrig\n
10577 * BMTRGR TAREP LL_HRTIM_BM_GetTrig\n
10578 * BMTRGR TACMP1 LL_HRTIM_BM_GetTrig\n
10579 * BMTRGR TACMP2 LL_HRTIM_BM_GetTrig\n
10580 * BMTRGR TBRST LL_HRTIM_BM_GetTrig\n
10581 * BMTRGR TBREP LL_HRTIM_BM_GetTrig\n
10582 * BMTRGR TBCMP1 LL_HRTIM_BM_GetTrig\n
10583 * BMTRGR TBCMP2 LL_HRTIM_BM_GetTrig\n
10584 * BMTRGR TCRST LL_HRTIM_BM_GetTrig\n
10585 * BMTRGR TCREP LL_HRTIM_BM_GetTrig\n
10586 * BMTRGR TCCMP1 LL_HRTIM_BM_GetTrig\n
10587 * BMTRGR TDRST LL_HRTIM_BM_GetTrig\n
10588 * BMTRGR TDREP LL_HRTIM_BM_GetTrig\n
10589 * BMTRGR TDCMP2 LL_HRTIM_BM_GetTrig\n
10590 * BMTRGR TEREP LL_HRTIM_BM_GetTrig\n
10591 * BMTRGR TECMP1 LL_HRTIM_BM_GetTrig\n
10592 * BMTRGR TECMP2 LL_HRTIM_BM_GetTrig\n
10593 * BMTRGR TFREP LL_HRTIM_BM_GetTrig\n
10594 * BMTRGR TFRST LL_HRTIM_BM_GetTrig\n
10595 * BMTRGR TFCMP1 LL_HRTIM_BM_GetTrig\n
10596 * BMTRGR TAEEV7 LL_HRTIM_BM_GetTrig\n
10597 * BMTRGR TAEEV8 LL_HRTIM_BM_GetTrig\n
10598 * BMTRGR EEV7 LL_HRTIM_BM_GetTrig\n
10599 * BMTRGR EEV8 LL_HRTIM_BM_GetTrig\n
10600 * BMTRGR OCHIPEV LL_HRTIM_BM_GetTrig
10601 * @param HRTIMx High Resolution Timer instance
10602 * @retval Trig This parameter can be a combination of the following values:
10603 * @arg @ref LL_HRTIM_BM_TRIG_NONE
10604 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
10605 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
10606 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
10607 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
10608 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
10609 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
10610 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
10611 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
10612 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
10613 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
10614 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
10615 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
10616 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
10617 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
10618 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
10619 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
10620 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
10621 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
10622 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
10623 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
10624 * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
10625 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
10626 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
10627 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_RESET
10628 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_REPETITION
10629 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_CMP1
10630 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
10631 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
10632 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
10633 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
10634 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
10635 */
LL_HRTIM_BM_GetTrig(HRTIM_TypeDef * HRTIMx)10636 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(HRTIM_TypeDef *HRTIMx)
10637 {
10638 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR);
10639 }
10640
10641 /**
10642 * @brief Set the burst mode controller compare value.
10643 * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_SetCompare
10644 * @param HRTIMx High Resolution Timer instance
10645 * @param CompareValue Compare value must be above or equal to 3
10646 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
10647 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10648 * @retval None
10649 */
LL_HRTIM_BM_SetCompare(HRTIM_TypeDef * HRTIMx,uint32_t CompareValue)10650 __STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t CompareValue)
10651 {
10652 WRITE_REG(HRTIMx->sCommonRegs.BMCMPR, CompareValue);
10653 }
10654
10655 /**
10656 * @brief Get actual burst mode controller compare value.
10657 * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_GetCompare
10658 * @param HRTIMx High Resolution Timer instance
10659 * @retval CompareValue Compare value must be above or equal to 3
10660 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
10661 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10662 */
LL_HRTIM_BM_GetCompare(HRTIM_TypeDef * HRTIMx)10663 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(HRTIM_TypeDef *HRTIMx)
10664 {
10665 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR);
10666 }
10667
10668 /**
10669 * @brief Set the burst mode controller period.
10670 * @rmtoll BMPER BMPER LL_HRTIM_BM_SetPeriod
10671 * @param HRTIMx High Resolution Timer instance
10672 * @param Period The period value must be above or equal to 3 periods of the fHRTIM clock,
10673 * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10674 * The maximum value is 0x0000 FFDF.
10675 * @retval None
10676 */
LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef * HRTIMx,uint32_t Period)10677 __STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Period)
10678 {
10679 WRITE_REG(HRTIMx->sCommonRegs.BMPER, Period);
10680 }
10681
10682 /**
10683 * @brief Get actual burst mode controller period.
10684 * @rmtoll BMPER BMPER LL_HRTIM_BM_GetPeriod
10685 * @param HRTIMx High Resolution Timer instance
10686 * @retval The period value must be above or equal to 3 periods of the fHRTIM clock,
10687 * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10688 * The maximum value is 0x0000 FFDF.
10689 */
LL_HRTIM_BM_GetPeriod(HRTIM_TypeDef * HRTIMx)10690 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(HRTIM_TypeDef *HRTIMx)
10691 {
10692 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER);
10693 }
10694
10695 /**
10696 * @brief Enable the burst mode controller
10697 * @rmtoll BMCR BME LL_HRTIM_BM_Enable
10698 * @param HRTIMx High Resolution Timer instance
10699 * @retval None
10700 */
LL_HRTIM_BM_Enable(HRTIM_TypeDef * HRTIMx)10701 __STATIC_INLINE void LL_HRTIM_BM_Enable(HRTIM_TypeDef *HRTIMx)
10702 {
10703 SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
10704 }
10705
10706 /**
10707 * @brief Disable the burst mode controller
10708 * @rmtoll BMCR BME LL_HRTIM_BM_Disable
10709 * @param HRTIMx High Resolution Timer instance
10710 * @retval None
10711 */
LL_HRTIM_BM_Disable(HRTIM_TypeDef * HRTIMx)10712 __STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx)
10713 {
10714 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
10715 }
10716
10717 /**
10718 * @brief Indicate whether the burst mode controller is enabled.
10719 * @rmtoll BMCR BME LL_HRTIM_BM_IsEnabled
10720 * @param HRTIMx High Resolution Timer instance
10721 * @retval State of BME bit in HRTIM_BMCR register (1 or 0).
10722 */
LL_HRTIM_BM_IsEnabled(HRTIM_TypeDef * HRTIMx)10723 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(HRTIM_TypeDef *HRTIMx)
10724 {
10725 return ((READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == (HRTIM_BMCR_BME)) ? 1UL : 0UL);
10726 }
10727
10728 /**
10729 * @brief Trigger the burst operation (software trigger)
10730 * @rmtoll BMTRGR SW LL_HRTIM_BM_Start
10731 * @param HRTIMx High Resolution Timer instance
10732 * @retval None
10733 */
LL_HRTIM_BM_Start(HRTIM_TypeDef * HRTIMx)10734 __STATIC_INLINE void LL_HRTIM_BM_Start(HRTIM_TypeDef *HRTIMx)
10735 {
10736 SET_BIT(HRTIMx->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
10737 }
10738
10739 /**
10740 * @brief Stop the burst mode operation.
10741 * @rmtoll BMCR BMSTAT LL_HRTIM_BM_Stop
10742 * @note Causes a burst mode early termination.
10743 * @param HRTIMx High Resolution Timer instance
10744 * @retval None
10745 */
LL_HRTIM_BM_Stop(HRTIM_TypeDef * HRTIMx)10746 __STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx)
10747 {
10748 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT);
10749 }
10750
10751 /**
10752 * @brief Get actual burst mode status
10753 * @rmtoll BMCR BMSTAT LL_HRTIM_BM_GetStatus
10754 * @param HRTIMx High Resolution Timer instance
10755 * @retval Status This parameter can be one of the following values:
10756 * @arg @ref LL_HRTIM_BM_STATUS_NORMAL
10757 * @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING
10758 */
LL_HRTIM_BM_GetStatus(HRTIM_TypeDef * HRTIMx)10759 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(HRTIM_TypeDef *HRTIMx)
10760 {
10761 return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT));
10762 }
10763
10764 /**
10765 * @}
10766 */
10767
10768 /** @defgroup HRTIM_LL_EF_FLAG_Management FLAG_Management
10769 * @{
10770 */
10771
10772 /**
10773 * @brief Clear the Fault 1 interrupt flag.
10774 * @rmtoll ICR FLT1C LL_HRTIM_ClearFlag_FLT1
10775 * @param HRTIMx High Resolution Timer instance
10776 * @retval None
10777 */
LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef * HRTIMx)10778 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx)
10779 {
10780 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT1C);
10781 }
10782
10783 /**
10784 * @brief Indicate whether Fault 1 interrupt occurred.
10785 * @rmtoll ICR FLT1 LL_HRTIM_IsActiveFlag_FLT1
10786 * @param HRTIMx High Resolution Timer instance
10787 * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0).
10788 */
LL_HRTIM_IsActiveFlag_FLT1(HRTIM_TypeDef * HRTIMx)10789 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(HRTIM_TypeDef *HRTIMx)
10790 {
10791 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1)) ? 1UL : 0UL);
10792 }
10793
10794 /**
10795 * @brief Clear the Fault 2 interrupt flag.
10796 * @rmtoll ICR FLT2C LL_HRTIM_ClearFlag_FLT2
10797 * @param HRTIMx High Resolution Timer instance
10798 * @retval None
10799 */
LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef * HRTIMx)10800 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx)
10801 {
10802 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT2C);
10803 }
10804
10805 /**
10806 * @brief Indicate whether Fault 2 interrupt occurred.
10807 * @rmtoll ICR FLT2 LL_HRTIM_IsActiveFlag_FLT2
10808 * @param HRTIMx High Resolution Timer instance
10809 * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0).
10810 */
LL_HRTIM_IsActiveFlag_FLT2(HRTIM_TypeDef * HRTIMx)10811 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(HRTIM_TypeDef *HRTIMx)
10812 {
10813 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2)) ? 1UL : 0UL);
10814 }
10815
10816 /**
10817 * @brief Clear the Fault 3 interrupt flag.
10818 * @rmtoll ICR FLT3C LL_HRTIM_ClearFlag_FLT3
10819 * @param HRTIMx High Resolution Timer instance
10820 * @retval None
10821 */
LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef * HRTIMx)10822 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx)
10823 {
10824 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT3C);
10825 }
10826
10827 /**
10828 * @brief Indicate whether Fault 3 interrupt occurred.
10829 * @rmtoll ICR FLT3 LL_HRTIM_IsActiveFlag_FLT3
10830 * @param HRTIMx High Resolution Timer instance
10831 * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0).
10832 */
LL_HRTIM_IsActiveFlag_FLT3(HRTIM_TypeDef * HRTIMx)10833 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(HRTIM_TypeDef *HRTIMx)
10834 {
10835 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3)) ? 1UL : 0UL);
10836 }
10837
10838 /**
10839 * @brief Clear the Fault 4 interrupt flag.
10840 * @rmtoll ICR FLT4C LL_HRTIM_ClearFlag_FLT4
10841 * @param HRTIMx High Resolution Timer instance
10842 * @retval None
10843 */
LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef * HRTIMx)10844 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx)
10845 {
10846 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT4C);
10847 }
10848
10849 /**
10850 * @brief Indicate whether Fault 4 interrupt occurred.
10851 * @rmtoll ICR FLT4 LL_HRTIM_IsActiveFlag_FLT4
10852 * @param HRTIMx High Resolution Timer instance
10853 * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0).
10854 */
LL_HRTIM_IsActiveFlag_FLT4(HRTIM_TypeDef * HRTIMx)10855 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(HRTIM_TypeDef *HRTIMx)
10856 {
10857 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4)) ? 1UL : 0UL);
10858 }
10859
10860 /**
10861 * @brief Clear the Fault 5 interrupt flag.
10862 * @rmtoll ICR FLT5C LL_HRTIM_ClearFlag_FLT5
10863 * @param HRTIMx High Resolution Timer instance
10864 * @retval None
10865 */
LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef * HRTIMx)10866 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx)
10867 {
10868 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT5C);
10869 }
10870
10871 /**
10872 * @brief Indicate whether Fault 5 interrupt occurred.
10873 * @rmtoll ICR FLT5 LL_HRTIM_IsActiveFlag_FLT5
10874 * @param HRTIMx High Resolution Timer instance
10875 * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0).
10876 */
LL_HRTIM_IsActiveFlag_FLT5(HRTIM_TypeDef * HRTIMx)10877 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(HRTIM_TypeDef *HRTIMx)
10878 {
10879 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5)) ? 1UL : 0UL);
10880 }
10881
10882 /**
10883 * @brief Clear the Fault 6 interrupt flag.
10884 * @rmtoll ICR FLT6C LL_HRTIM_ClearFlag_FLT6
10885 * @param HRTIMx High Resolution Timer instance
10886 * @retval None
10887 */
LL_HRTIM_ClearFlag_FLT6(HRTIM_TypeDef * HRTIMx)10888 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT6(HRTIM_TypeDef *HRTIMx)
10889 {
10890 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT6C);
10891 }
10892
10893 /**
10894 * @brief Indicate whether Fault 6 interrupt occurred.
10895 * @rmtoll ICR FLT6 LL_HRTIM_IsActiveFlag_FLT6
10896 * @param HRTIMx High Resolution Timer instance
10897 * @retval State of FLT6 bit in HRTIM_ISR register (1 or 0).
10898 */
LL_HRTIM_IsActiveFlag_FLT6(HRTIM_TypeDef * HRTIMx)10899 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT6(HRTIM_TypeDef *HRTIMx)
10900 {
10901 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT6) == (HRTIM_ISR_FLT6)) ? 1UL : 0UL);
10902 }
10903
10904 /**
10905 * @brief Clear the System Fault interrupt flag.
10906 * @rmtoll ICR SYSFLTC LL_HRTIM_ClearFlag_SYSFLT
10907 * @param HRTIMx High Resolution Timer instance
10908 * @retval None
10909 */
LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef * HRTIMx)10910 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
10911 {
10912 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_SYSFLTC);
10913 }
10914
10915 /**
10916 * @brief Indicate whether System Fault interrupt occurred.
10917 * @rmtoll ISR SYSFLT LL_HRTIM_IsActiveFlag_SYSFLT
10918 * @param HRTIMx High Resolution Timer instance
10919 * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0).
10920 */
LL_HRTIM_IsActiveFlag_SYSFLT(HRTIM_TypeDef * HRTIMx)10921 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
10922 {
10923 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT)) ? 1UL : 0UL);
10924 }
10925
10926 /**
10927 * @brief Clear the DLL ready interrupt flag.
10928 * @rmtoll ICR DLLRDYC LL_HRTIM_ClearFlag_DLLRDY
10929 * @param HRTIMx High Resolution Timer instance
10930 * @retval None
10931 */
LL_HRTIM_ClearFlag_DLLRDY(HRTIM_TypeDef * HRTIMx)10932 __STATIC_INLINE void LL_HRTIM_ClearFlag_DLLRDY(HRTIM_TypeDef *HRTIMx)
10933 {
10934 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_DLLRDYC);
10935 }
10936
10937 /**
10938 * @brief Indicate whether DLL ready interrupt occurred.
10939 * @rmtoll ISR DLLRDY LL_HRTIM_IsActiveFlag_DLLRDY
10940 * @param HRTIMx High Resolution Timer instance
10941 * @retval State of DLLRDY bit in HRTIM_ISR register (1 or 0).
10942 */
LL_HRTIM_IsActiveFlag_DLLRDY(HRTIM_TypeDef * HRTIMx)10943 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLLRDY(HRTIM_TypeDef *HRTIMx)
10944 {
10945 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_DLLRDY) == (HRTIM_ISR_DLLRDY)) ? 1UL : 0UL);
10946 }
10947
10948 /**
10949 * @brief Clear the Burst Mode period interrupt flag.
10950 * @rmtoll ICR BMPERC LL_HRTIM_ClearFlag_BMPER
10951 * @param HRTIMx High Resolution Timer instance
10952 * @retval None
10953 */
LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef * HRTIMx)10954 __STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx)
10955 {
10956 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_BMPERC);
10957 }
10958
10959 /**
10960 * @brief Indicate whether Burst Mode period interrupt occurred.
10961 * @rmtoll ISR BMPER LL_HRTIM_IsActiveFlag_BMPER
10962 * @param HRTIMx High Resolution Timer instance
10963 * @retval State of BMPER bit in HRTIM_ISR register (1 or 0).
10964 */
LL_HRTIM_IsActiveFlag_BMPER(HRTIM_TypeDef * HRTIMx)10965 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(HRTIM_TypeDef *HRTIMx)
10966 {
10967 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER)) ? 1UL : 0UL);
10968 }
10969
10970 /**
10971 * @brief Clear the Synchronization Input interrupt flag.
10972 * @rmtoll MICR SYNCC LL_HRTIM_ClearFlag_SYNC
10973 * @param HRTIMx High Resolution Timer instance
10974 * @retval None
10975 */
LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef * HRTIMx)10976 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx)
10977 {
10978 SET_BIT(HRTIMx->sMasterRegs.MICR, HRTIM_MICR_SYNC);
10979 }
10980
10981 /**
10982 * @brief Indicate whether the Synchronization Input interrupt occurred.
10983 * @rmtoll MISR SYNC LL_HRTIM_IsActiveFlag_SYNC
10984 * @param HRTIMx High Resolution Timer instance
10985 * @retval State of SYNC bit in HRTIM_MISR register (1 or 0).
10986 */
LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef * HRTIMx)10987 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef *HRTIMx)
10988 {
10989 return ((READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC)) ? 1UL : 0UL);
10990 }
10991
10992 /**
10993 * @brief Clear the update interrupt flag for a given timer (including the master timer) .
10994 * @rmtoll MICR MUPDC LL_HRTIM_ClearFlag_UPDATE\n
10995 * TIMxICR UPDC LL_HRTIM_ClearFlag_UPDATE
10996 * @param HRTIMx High Resolution Timer instance
10997 * @param Timer This parameter can be one of the following values:
10998 * @arg @ref LL_HRTIM_TIMER_MASTER
10999 * @arg @ref LL_HRTIM_TIMER_A
11000 * @arg @ref LL_HRTIM_TIMER_B
11001 * @arg @ref LL_HRTIM_TIMER_C
11002 * @arg @ref LL_HRTIM_TIMER_D
11003 * @arg @ref LL_HRTIM_TIMER_E
11004 * @arg @ref LL_HRTIM_TIMER_F
11005 * @retval None
11006 */
LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11007 __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11008 {
11009 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11010 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11011 REG_OFFSET_TAB_TIMER[iTimer]));
11012 SET_BIT(*pReg, HRTIM_MICR_MUPD);
11013 }
11014
11015 /**
11016 * @brief Indicate whether the update interrupt has occurred for a given timer (including the master timer) .
11017 * @rmtoll MISR MUPD LL_HRTIM_IsActiveFlag_UPDATE\n
11018 * TIMxISR UPD LL_HRTIM_IsActiveFlag_UPDATE
11019 * @param HRTIMx High Resolution Timer instance
11020 * @param Timer This parameter can be one of the following values:
11021 * @arg @ref LL_HRTIM_TIMER_MASTER
11022 * @arg @ref LL_HRTIM_TIMER_A
11023 * @arg @ref LL_HRTIM_TIMER_B
11024 * @arg @ref LL_HRTIM_TIMER_C
11025 * @arg @ref LL_HRTIM_TIMER_D
11026 * @arg @ref LL_HRTIM_TIMER_E
11027 * @arg @ref LL_HRTIM_TIMER_F
11028 * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11029 */
LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11030 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11031 {
11032 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11033 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11034 REG_OFFSET_TAB_TIMER[iTimer]));
11035
11036 return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL);
11037 }
11038
11039 /**
11040 * @brief Clear the repetition interrupt flag for a given timer (including the master timer) .
11041 * @rmtoll MICR MREPC LL_HRTIM_ClearFlag_REP\n
11042 * TIMxICR REPC LL_HRTIM_ClearFlag_REP
11043 * @param HRTIMx High Resolution Timer instance
11044 * @param Timer This parameter can be one of the following values:
11045 * @arg @ref LL_HRTIM_TIMER_MASTER
11046 * @arg @ref LL_HRTIM_TIMER_A
11047 * @arg @ref LL_HRTIM_TIMER_B
11048 * @arg @ref LL_HRTIM_TIMER_C
11049 * @arg @ref LL_HRTIM_TIMER_D
11050 * @arg @ref LL_HRTIM_TIMER_E
11051 * @arg @ref LL_HRTIM_TIMER_F
11052 * @retval None
11053 */
LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11054 __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11055 {
11056 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11057 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11058 REG_OFFSET_TAB_TIMER[iTimer]));
11059 SET_BIT(*pReg, HRTIM_MICR_MREP);
11060
11061 }
11062
11063 /**
11064 * @brief Indicate whether the repetition interrupt has occurred for a given timer (including the master timer) .
11065 * @rmtoll MISR MREP LL_HRTIM_IsActiveFlag_REP\n
11066 * TIMxISR REP LL_HRTIM_IsActiveFlag_REP
11067 * @param HRTIMx High Resolution Timer instance
11068 * @param Timer This parameter can be one of the following values:
11069 * @arg @ref LL_HRTIM_TIMER_MASTER
11070 * @arg @ref LL_HRTIM_TIMER_A
11071 * @arg @ref LL_HRTIM_TIMER_B
11072 * @arg @ref LL_HRTIM_TIMER_C
11073 * @arg @ref LL_HRTIM_TIMER_D
11074 * @arg @ref LL_HRTIM_TIMER_E
11075 * @arg @ref LL_HRTIM_TIMER_F
11076 * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11077 */
LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11078 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11079 {
11080 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11081 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11082 REG_OFFSET_TAB_TIMER[iTimer]));
11083
11084 return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL);
11085 }
11086
11087 /**
11088 * @brief Clear the compare 1 match interrupt for a given timer (including the master timer).
11089 * @rmtoll MICR MCMP1C LL_HRTIM_ClearFlag_CMP1\n
11090 * TIMxICR CMP1C LL_HRTIM_ClearFlag_CMP1
11091 * @param HRTIMx High Resolution Timer instance
11092 * @param Timer This parameter can be one of the following values:
11093 * @arg @ref LL_HRTIM_TIMER_MASTER
11094 * @arg @ref LL_HRTIM_TIMER_A
11095 * @arg @ref LL_HRTIM_TIMER_B
11096 * @arg @ref LL_HRTIM_TIMER_C
11097 * @arg @ref LL_HRTIM_TIMER_D
11098 * @arg @ref LL_HRTIM_TIMER_E
11099 * @arg @ref LL_HRTIM_TIMER_F
11100 * @retval None
11101 */
LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11102 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11103 {
11104 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11105 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11106 REG_OFFSET_TAB_TIMER[iTimer]));
11107 SET_BIT(*pReg, HRTIM_MICR_MCMP1);
11108 }
11109
11110 /**
11111 * @brief Indicate whether the compare match 1 interrupt has occurred for a given timer (including the master timer) .
11112 * @rmtoll MISR MCMP1 LL_HRTIM_IsActiveFlag_CMP1\n
11113 * TIMxISR CMP1 LL_HRTIM_IsActiveFlag_CMP1
11114 * @param HRTIMx High Resolution Timer instance
11115 * @param Timer This parameter can be one of the following values:
11116 * @arg @ref LL_HRTIM_TIMER_MASTER
11117 * @arg @ref LL_HRTIM_TIMER_A
11118 * @arg @ref LL_HRTIM_TIMER_B
11119 * @arg @ref LL_HRTIM_TIMER_C
11120 * @arg @ref LL_HRTIM_TIMER_D
11121 * @arg @ref LL_HRTIM_TIMER_E
11122 * @arg @ref LL_HRTIM_TIMER_F
11123 * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11124 */
LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11125 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11126 {
11127 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11128 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11129 REG_OFFSET_TAB_TIMER[iTimer]));
11130
11131 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL);
11132 }
11133
11134 /**
11135 * @brief Clear the compare 2 match interrupt for a given timer (including the master timer).
11136 * @rmtoll MICR MCMP2C LL_HRTIM_ClearFlag_CMP2\n
11137 * TIMxICR CMP2C LL_HRTIM_ClearFlag_CMP2
11138 * @param HRTIMx High Resolution Timer instance
11139 * @param Timer This parameter can be one of the following values:
11140 * @arg @ref LL_HRTIM_TIMER_MASTER
11141 * @arg @ref LL_HRTIM_TIMER_A
11142 * @arg @ref LL_HRTIM_TIMER_B
11143 * @arg @ref LL_HRTIM_TIMER_C
11144 * @arg @ref LL_HRTIM_TIMER_D
11145 * @arg @ref LL_HRTIM_TIMER_E
11146 * @arg @ref LL_HRTIM_TIMER_F
11147 * @retval None
11148 */
LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11149 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11150 {
11151 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11152 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11153 REG_OFFSET_TAB_TIMER[iTimer]));
11154 SET_BIT(*pReg, HRTIM_MICR_MCMP2);
11155 }
11156
11157 /**
11158 * @brief Indicate whether the compare match 2 interrupt has occurred for a given timer (including the master timer) .
11159 * @rmtoll MISR MCMP2 LL_HRTIM_IsActiveFlag_CMP2\n
11160 * TIMxISR CMP2 LL_HRTIM_IsActiveFlag_CMP2
11161 * @param HRTIMx High Resolution Timer instance
11162 * @param Timer This parameter can be one of the following values:
11163 * @arg @ref LL_HRTIM_TIMER_MASTER
11164 * @arg @ref LL_HRTIM_TIMER_A
11165 * @arg @ref LL_HRTIM_TIMER_B
11166 * @arg @ref LL_HRTIM_TIMER_C
11167 * @arg @ref LL_HRTIM_TIMER_D
11168 * @arg @ref LL_HRTIM_TIMER_E
11169 * @arg @ref LL_HRTIM_TIMER_F
11170 * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11171 */
LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11172 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11173 {
11174 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11175 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11176 REG_OFFSET_TAB_TIMER[iTimer]));
11177
11178 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL);
11179 }
11180
11181 /**
11182 * @brief Clear the compare 3 match interrupt for a given timer (including the master timer).
11183 * @rmtoll MICR MCMP3C LL_HRTIM_ClearFlag_CMP3\n
11184 * TIMxICR CMP3C LL_HRTIM_ClearFlag_CMP3
11185 * @param HRTIMx High Resolution Timer instance
11186 * @param Timer This parameter can be one of the following values:
11187 * @arg @ref LL_HRTIM_TIMER_MASTER
11188 * @arg @ref LL_HRTIM_TIMER_A
11189 * @arg @ref LL_HRTIM_TIMER_B
11190 * @arg @ref LL_HRTIM_TIMER_C
11191 * @arg @ref LL_HRTIM_TIMER_D
11192 * @arg @ref LL_HRTIM_TIMER_E
11193 * @arg @ref LL_HRTIM_TIMER_F
11194 * @retval None
11195 */
LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11196 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11197 {
11198 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11199 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11200 REG_OFFSET_TAB_TIMER[iTimer]));
11201 SET_BIT(*pReg, HRTIM_MICR_MCMP3);
11202 }
11203
11204 /**
11205 * @brief Indicate whether the compare match 3 interrupt has occurred for a given timer (including the master timer) .
11206 * @rmtoll MISR MCMP3 LL_HRTIM_IsActiveFlag_CMP3\n
11207 * TIMxISR CMP3 LL_HRTIM_IsActiveFlag_CMP3
11208 * @param HRTIMx High Resolution Timer instance
11209 * @param Timer This parameter can be one of the following values:
11210 * @arg @ref LL_HRTIM_TIMER_MASTER
11211 * @arg @ref LL_HRTIM_TIMER_A
11212 * @arg @ref LL_HRTIM_TIMER_B
11213 * @arg @ref LL_HRTIM_TIMER_C
11214 * @arg @ref LL_HRTIM_TIMER_D
11215 * @arg @ref LL_HRTIM_TIMER_E
11216 * @arg @ref LL_HRTIM_TIMER_F
11217 * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11218 */
LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11219 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11220 {
11221 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11222 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11223 REG_OFFSET_TAB_TIMER[iTimer]));
11224
11225 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL);
11226 }
11227
11228 /**
11229 * @brief Clear the compare 4 match interrupt for a given timer (including the master timer).
11230 * @rmtoll MICR MCMP4C LL_HRTIM_ClearFlag_CMP4\n
11231 * TIMxICR CMP4C LL_HRTIM_ClearFlag_CMP4
11232 * @param HRTIMx High Resolution Timer instance
11233 * @param Timer This parameter can be one of the following values:
11234 * @arg @ref LL_HRTIM_TIMER_MASTER
11235 * @arg @ref LL_HRTIM_TIMER_A
11236 * @arg @ref LL_HRTIM_TIMER_B
11237 * @arg @ref LL_HRTIM_TIMER_C
11238 * @arg @ref LL_HRTIM_TIMER_D
11239 * @arg @ref LL_HRTIM_TIMER_E
11240 * @arg @ref LL_HRTIM_TIMER_F
11241 * @retval None
11242 */
LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11243 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11244 {
11245 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11246 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11247 REG_OFFSET_TAB_TIMER[iTimer]));
11248 SET_BIT(*pReg, HRTIM_MICR_MCMP4);
11249 }
11250
11251 /**
11252 * @brief Indicate whether the compare match 4 interrupt has occurred for a given timer (including the master timer) .
11253 * @rmtoll MISR MCMP4 LL_HRTIM_IsActiveFlag_CMP4\n
11254 * TIMxISR CMP4 LL_HRTIM_IsActiveFlag_CMP4
11255 * @param HRTIMx High Resolution Timer instance
11256 * @param Timer This parameter can be one of the following values:
11257 * @arg @ref LL_HRTIM_TIMER_MASTER
11258 * @arg @ref LL_HRTIM_TIMER_A
11259 * @arg @ref LL_HRTIM_TIMER_B
11260 * @arg @ref LL_HRTIM_TIMER_C
11261 * @arg @ref LL_HRTIM_TIMER_D
11262 * @arg @ref LL_HRTIM_TIMER_E
11263 * @arg @ref LL_HRTIM_TIMER_F
11264 * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11265 */
LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11266 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11267 {
11268 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11269 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11270 REG_OFFSET_TAB_TIMER[iTimer]));
11271
11272 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL);
11273 }
11274
11275 /**
11276 * @brief Clear the capture 1 interrupt flag for a given timer.
11277 * @rmtoll TIMxICR CPT1C LL_HRTIM_ClearFlag_CPT1
11278 * @param HRTIMx High Resolution Timer instance
11279 * @param Timer This parameter can be one of the following values:
11280 * @arg @ref LL_HRTIM_TIMER_A
11281 * @arg @ref LL_HRTIM_TIMER_B
11282 * @arg @ref LL_HRTIM_TIMER_C
11283 * @arg @ref LL_HRTIM_TIMER_D
11284 * @arg @ref LL_HRTIM_TIMER_E
11285 * @arg @ref LL_HRTIM_TIMER_F
11286 * @retval None
11287 */
LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11288 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11289 {
11290 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11291 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11292 REG_OFFSET_TAB_TIMER[iTimer]));
11293 SET_BIT(*pReg, HRTIM_TIMICR_CPT1C);
11294 }
11295
11296 /**
11297 * @brief Indicate whether the capture 1 interrupt occurred for a given timer.
11298 * @rmtoll TIMxISR CPT1 LL_HRTIM_IsActiveFlag_CPT1
11299 * @param HRTIMx High Resolution Timer instance
11300 * @param Timer This parameter can be one of the following values:
11301 * @arg @ref LL_HRTIM_TIMER_A
11302 * @arg @ref LL_HRTIM_TIMER_B
11303 * @arg @ref LL_HRTIM_TIMER_C
11304 * @arg @ref LL_HRTIM_TIMER_D
11305 * @arg @ref LL_HRTIM_TIMER_E
11306 * @arg @ref LL_HRTIM_TIMER_F
11307 * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0).
11308 */
LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11309 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11310 {
11311 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11312 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11313 REG_OFFSET_TAB_TIMER[iTimer]));
11314
11315 return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL);
11316 }
11317
11318 /**
11319 * @brief Clear the capture 2 interrupt flag for a given timer.
11320 * @rmtoll TIMxICR CPT2C LL_HRTIM_ClearFlag_CPT2
11321 * @param HRTIMx High Resolution Timer instance
11322 * @param Timer This parameter can be one of the following values:
11323 * @arg @ref LL_HRTIM_TIMER_A
11324 * @arg @ref LL_HRTIM_TIMER_B
11325 * @arg @ref LL_HRTIM_TIMER_C
11326 * @arg @ref LL_HRTIM_TIMER_D
11327 * @arg @ref LL_HRTIM_TIMER_E
11328 * @arg @ref LL_HRTIM_TIMER_F
11329 * @retval None
11330 */
LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11331 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11332 {
11333 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11334 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11335 REG_OFFSET_TAB_TIMER[iTimer]));
11336 SET_BIT(*pReg, HRTIM_TIMICR_CPT2C);
11337 }
11338
11339 /**
11340 * @brief Indicate whether the capture 2 interrupt occurred for a given timer.
11341 * @rmtoll TIMxISR CPT2 LL_HRTIM_IsActiveFlag_CPT2
11342 * @param HRTIMx High Resolution Timer instance
11343 * @param Timer This parameter can be one of the following values:
11344 * @arg @ref LL_HRTIM_TIMER_A
11345 * @arg @ref LL_HRTIM_TIMER_B
11346 * @arg @ref LL_HRTIM_TIMER_C
11347 * @arg @ref LL_HRTIM_TIMER_D
11348 * @arg @ref LL_HRTIM_TIMER_E
11349 * @arg @ref LL_HRTIM_TIMER_F
11350 * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0).
11351 */
LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11352 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11353 {
11354 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11355 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11356 REG_OFFSET_TAB_TIMER[iTimer]));
11357
11358 return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL);
11359 }
11360
11361 /**
11362 * @brief Clear the output 1 set interrupt flag for a given timer.
11363 * @rmtoll TIMxICR SET1C LL_HRTIM_ClearFlag_SET1
11364 * @param HRTIMx High Resolution Timer instance
11365 * @param Timer This parameter can be one of the following values:
11366 * @arg @ref LL_HRTIM_TIMER_A
11367 * @arg @ref LL_HRTIM_TIMER_B
11368 * @arg @ref LL_HRTIM_TIMER_C
11369 * @arg @ref LL_HRTIM_TIMER_D
11370 * @arg @ref LL_HRTIM_TIMER_E
11371 * @arg @ref LL_HRTIM_TIMER_F
11372 * @retval None
11373 */
LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11374 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11375 {
11376 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11377 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11378 REG_OFFSET_TAB_TIMER[iTimer]));
11379 SET_BIT(*pReg, HRTIM_TIMICR_SET1C);
11380 }
11381
11382 /**
11383 * @brief Indicate whether the output 1 set interrupt occurred for a given timer.
11384 * @rmtoll TIMxISR SET1 LL_HRTIM_IsActiveFlag_SET1
11385 * @param HRTIMx High Resolution Timer instance
11386 * @param Timer This parameter can be one of the following values:
11387 * @arg @ref LL_HRTIM_TIMER_A
11388 * @arg @ref LL_HRTIM_TIMER_B
11389 * @arg @ref LL_HRTIM_TIMER_C
11390 * @arg @ref LL_HRTIM_TIMER_D
11391 * @arg @ref LL_HRTIM_TIMER_E
11392 * @arg @ref LL_HRTIM_TIMER_F
11393 * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0).
11394 */
LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11395 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11396 {
11397 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11398 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11399 REG_OFFSET_TAB_TIMER[iTimer]));
11400
11401 return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL);
11402 }
11403
11404 /**
11405 * @brief Clear the output 1 reset interrupt flag for a given timer.
11406 * @rmtoll TIMxICR RST1C LL_HRTIM_ClearFlag_RST1
11407 * @param HRTIMx High Resolution Timer instance
11408 * @param Timer This parameter can be one of the following values:
11409 * @arg @ref LL_HRTIM_TIMER_A
11410 * @arg @ref LL_HRTIM_TIMER_B
11411 * @arg @ref LL_HRTIM_TIMER_C
11412 * @arg @ref LL_HRTIM_TIMER_D
11413 * @arg @ref LL_HRTIM_TIMER_E
11414 * @arg @ref LL_HRTIM_TIMER_F
11415 * @retval None
11416 */
LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11417 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11418 {
11419 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11420 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11421 REG_OFFSET_TAB_TIMER[iTimer]));
11422 SET_BIT(*pReg, HRTIM_TIMICR_RST1C);
11423 }
11424
11425 /**
11426 * @brief Indicate whether the output 1 reset interrupt occurred for a given timer.
11427 * @rmtoll TIMxISR RST1 LL_HRTIM_IsActiveFlag_RST1
11428 * @param HRTIMx High Resolution Timer instance
11429 * @param Timer This parameter can be one of the following values:
11430 * @arg @ref LL_HRTIM_TIMER_A
11431 * @arg @ref LL_HRTIM_TIMER_B
11432 * @arg @ref LL_HRTIM_TIMER_C
11433 * @arg @ref LL_HRTIM_TIMER_D
11434 * @arg @ref LL_HRTIM_TIMER_E
11435 * @arg @ref LL_HRTIM_TIMER_F
11436 * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0).
11437 */
LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11438 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11439 {
11440 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11441 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11442 REG_OFFSET_TAB_TIMER[iTimer]));
11443
11444 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL);
11445 }
11446
11447 /**
11448 * @brief Clear the output 2 set interrupt flag for a given timer.
11449 * @rmtoll TIMxICR SET2C LL_HRTIM_ClearFlag_SET2
11450 * @param HRTIMx High Resolution Timer instance
11451 * @param Timer This parameter can be one of the following values:
11452 * @arg @ref LL_HRTIM_TIMER_A
11453 * @arg @ref LL_HRTIM_TIMER_B
11454 * @arg @ref LL_HRTIM_TIMER_C
11455 * @arg @ref LL_HRTIM_TIMER_D
11456 * @arg @ref LL_HRTIM_TIMER_E
11457 * @arg @ref LL_HRTIM_TIMER_F
11458 * @retval None
11459 */
LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11460 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11461 {
11462 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11463 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11464 REG_OFFSET_TAB_TIMER[iTimer]));
11465 SET_BIT(*pReg, HRTIM_TIMICR_SET2C);
11466 }
11467
11468 /**
11469 * @brief Indicate whether the output 2 set interrupt occurred for a given timer.
11470 * @rmtoll TIMxISR SET2 LL_HRTIM_IsActiveFlag_SET2
11471 * @param HRTIMx High Resolution Timer instance
11472 * @param Timer This parameter can be one of the following values:
11473 * @arg @ref LL_HRTIM_TIMER_A
11474 * @arg @ref LL_HRTIM_TIMER_B
11475 * @arg @ref LL_HRTIM_TIMER_C
11476 * @arg @ref LL_HRTIM_TIMER_D
11477 * @arg @ref LL_HRTIM_TIMER_E
11478 * @arg @ref LL_HRTIM_TIMER_F
11479 * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0).
11480 */
LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11481 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11482 {
11483 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11484 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11485 REG_OFFSET_TAB_TIMER[iTimer]));
11486
11487 return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL);
11488 }
11489
11490 /**
11491 * @brief Clear the output 2reset interrupt flag for a given timer.
11492 * @rmtoll TIMxICR RST2C LL_HRTIM_ClearFlag_RST2
11493 * @param HRTIMx High Resolution Timer instance
11494 * @param Timer This parameter can be one of the following values:
11495 * @arg @ref LL_HRTIM_TIMER_A
11496 * @arg @ref LL_HRTIM_TIMER_B
11497 * @arg @ref LL_HRTIM_TIMER_C
11498 * @arg @ref LL_HRTIM_TIMER_D
11499 * @arg @ref LL_HRTIM_TIMER_E
11500 * @arg @ref LL_HRTIM_TIMER_F
11501 * @retval None
11502 */
LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11503 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11504 {
11505 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11506 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11507 REG_OFFSET_TAB_TIMER[iTimer]));
11508 SET_BIT(*pReg, HRTIM_TIMICR_RST2C);
11509 }
11510
11511 /**
11512 * @brief Indicate whether the output 2 reset interrupt occurred for a given timer.
11513 * @rmtoll TIMxISR RST2 LL_HRTIM_IsActiveFlag_RST2
11514 * @param HRTIMx High Resolution Timer instance
11515 * @param Timer This parameter can be one of the following values:
11516 * @arg @ref LL_HRTIM_TIMER_A
11517 * @arg @ref LL_HRTIM_TIMER_B
11518 * @arg @ref LL_HRTIM_TIMER_C
11519 * @arg @ref LL_HRTIM_TIMER_D
11520 * @arg @ref LL_HRTIM_TIMER_E
11521 * @arg @ref LL_HRTIM_TIMER_F
11522 * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0).
11523 */
LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11524 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11525 {
11526 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11527 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11528 REG_OFFSET_TAB_TIMER[iTimer]));
11529
11530 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL);
11531 }
11532
11533 /**
11534 * @brief Clear the reset and/or roll-over interrupt flag for a given timer.
11535 * @rmtoll TIMxICR RSTC LL_HRTIM_ClearFlag_RST
11536 * @param HRTIMx High Resolution Timer instance
11537 * @param Timer This parameter can be one of the following values:
11538 * @arg @ref LL_HRTIM_TIMER_A
11539 * @arg @ref LL_HRTIM_TIMER_B
11540 * @arg @ref LL_HRTIM_TIMER_C
11541 * @arg @ref LL_HRTIM_TIMER_D
11542 * @arg @ref LL_HRTIM_TIMER_E
11543 * @arg @ref LL_HRTIM_TIMER_F
11544 * @retval None
11545 */
LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11546 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11547 {
11548 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11549 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11550 REG_OFFSET_TAB_TIMER[iTimer]));
11551 SET_BIT(*pReg, HRTIM_TIMICR_RSTC);
11552 }
11553
11554 /**
11555 * @brief Indicate whether the reset and/or roll-over interrupt occurred for a given timer.
11556 * @rmtoll TIMxISR RST LL_HRTIM_IsActiveFlag_RST
11557 * @param HRTIMx High Resolution Timer instance
11558 * @param Timer This parameter can be one of the following values:
11559 * @arg @ref LL_HRTIM_TIMER_A
11560 * @arg @ref LL_HRTIM_TIMER_B
11561 * @arg @ref LL_HRTIM_TIMER_C
11562 * @arg @ref LL_HRTIM_TIMER_D
11563 * @arg @ref LL_HRTIM_TIMER_E
11564 * @arg @ref LL_HRTIM_TIMER_F
11565 * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0).
11566 */
LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11567 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11568 {
11569 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11570 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11571 REG_OFFSET_TAB_TIMER[iTimer]));
11572
11573 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL);
11574 }
11575
11576 /**
11577 * @brief Clear the delayed protection interrupt flag for a given timer.
11578 * @rmtoll TIMxICR DLYPRTC LL_HRTIM_ClearFlag_DLYPRT
11579 * @param HRTIMx High Resolution Timer instance
11580 * @param Timer This parameter can be one of the following values:
11581 * @arg @ref LL_HRTIM_TIMER_A
11582 * @arg @ref LL_HRTIM_TIMER_B
11583 * @arg @ref LL_HRTIM_TIMER_C
11584 * @arg @ref LL_HRTIM_TIMER_D
11585 * @arg @ref LL_HRTIM_TIMER_E
11586 * @arg @ref LL_HRTIM_TIMER_F
11587 * @retval None
11588 */
LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11589 __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11590 {
11591 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11592 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11593 REG_OFFSET_TAB_TIMER[iTimer]));
11594 SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC);
11595 }
11596
11597 /**
11598 * @brief Indicate whether the delayed protection interrupt occurred for a given timer.
11599 * @rmtoll TIMxISR DLYPRT LL_HRTIM_IsActiveFlag_DLYPRT
11600 * @param HRTIMx High Resolution Timer instance
11601 * @param Timer This parameter can be one of the following values:
11602 * @arg @ref LL_HRTIM_TIMER_A
11603 * @arg @ref LL_HRTIM_TIMER_B
11604 * @arg @ref LL_HRTIM_TIMER_C
11605 * @arg @ref LL_HRTIM_TIMER_D
11606 * @arg @ref LL_HRTIM_TIMER_E
11607 * @arg @ref LL_HRTIM_TIMER_F
11608 * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0).
11609 */
LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11610 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11611 {
11612 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11613 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11614 REG_OFFSET_TAB_TIMER[iTimer]));
11615
11616 return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL);
11617 }
11618
11619 /**
11620 * @}
11621 */
11622
11623 /** @defgroup HRTIM_LL_EF_IT_Management IT_Management
11624 * @{
11625 */
11626
11627 /**
11628 * @brief Enable the fault 1 interrupt.
11629 * @rmtoll IER FLT1IE LL_HRTIM_EnableIT_FLT1
11630 * @param HRTIMx High Resolution Timer instance
11631 * @retval None
11632 */
LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef * HRTIMx)11633 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef *HRTIMx)
11634 {
11635 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
11636 }
11637
11638 /**
11639 * @brief Disable the fault 1 interrupt.
11640 * @rmtoll IER FLT1IE LL_HRTIM_DisableIT_FLT1
11641 * @param HRTIMx High Resolution Timer instance
11642 * @retval None
11643 */
LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef * HRTIMx)11644 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx)
11645 {
11646 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
11647 }
11648
11649 /**
11650 * @brief Indicate whether the fault 1 interrupt is enabled.
11651 * @rmtoll IER FLT1IE LL_HRTIM_IsEnabledIT_FLT1
11652 * @param HRTIMx High Resolution Timer instance
11653 * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0).
11654 */
LL_HRTIM_IsEnabledIT_FLT1(HRTIM_TypeDef * HRTIMx)11655 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(HRTIM_TypeDef *HRTIMx)
11656 {
11657 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1)) ? 1UL : 0UL);
11658 }
11659
11660 /**
11661 * @brief Enable the fault 2 interrupt.
11662 * @rmtoll IER FLT2IE LL_HRTIM_EnableIT_FLT2
11663 * @param HRTIMx High Resolution Timer instance
11664 * @retval None
11665 */
LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef * HRTIMx)11666 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef *HRTIMx)
11667 {
11668 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
11669 }
11670
11671 /**
11672 * @brief Disable the fault 2 interrupt.
11673 * @rmtoll IER FLT2IE LL_HRTIM_DisableIT_FLT2
11674 * @param HRTIMx High Resolution Timer instance
11675 * @retval None
11676 */
LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef * HRTIMx)11677 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx)
11678 {
11679 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
11680 }
11681
11682 /**
11683 * @brief Indicate whether the fault 2 interrupt is enabled.
11684 * @rmtoll IER FLT2IE LL_HRTIM_IsEnabledIT_FLT2
11685 * @param HRTIMx High Resolution Timer instance
11686 * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0).
11687 */
LL_HRTIM_IsEnabledIT_FLT2(HRTIM_TypeDef * HRTIMx)11688 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(HRTIM_TypeDef *HRTIMx)
11689 {
11690 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2)) ? 1UL : 0UL);
11691 }
11692
11693 /**
11694 * @brief Enable the fault 3 interrupt.
11695 * @rmtoll IER FLT3IE LL_HRTIM_EnableIT_FLT3
11696 * @param HRTIMx High Resolution Timer instance
11697 * @retval None
11698 */
LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef * HRTIMx)11699 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef *HRTIMx)
11700 {
11701 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
11702 }
11703
11704 /**
11705 * @brief Disable the fault 3 interrupt.
11706 * @rmtoll IER FLT3IE LL_HRTIM_DisableIT_FLT3
11707 * @param HRTIMx High Resolution Timer instance
11708 * @retval None
11709 */
LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef * HRTIMx)11710 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx)
11711 {
11712 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
11713 }
11714
11715 /**
11716 * @brief Indicate whether the fault 3 interrupt is enabled.
11717 * @rmtoll IER FLT3IE LL_HRTIM_IsEnabledIT_FLT3
11718 * @param HRTIMx High Resolution Timer instance
11719 * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0).
11720 */
LL_HRTIM_IsEnabledIT_FLT3(HRTIM_TypeDef * HRTIMx)11721 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(HRTIM_TypeDef *HRTIMx)
11722 {
11723 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3)) ? 1UL : 0UL);
11724 }
11725
11726 /**
11727 * @brief Enable the fault 4 interrupt.
11728 * @rmtoll IER FLT4IE LL_HRTIM_EnableIT_FLT4
11729 * @param HRTIMx High Resolution Timer instance
11730 * @retval None
11731 */
LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef * HRTIMx)11732 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef *HRTIMx)
11733 {
11734 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
11735 }
11736
11737 /**
11738 * @brief Disable the fault 4 interrupt.
11739 * @rmtoll IER FLT4IE LL_HRTIM_DisableIT_FLT4
11740 * @param HRTIMx High Resolution Timer instance
11741 * @retval None
11742 */
LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef * HRTIMx)11743 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx)
11744 {
11745 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
11746 }
11747
11748 /**
11749 * @brief Indicate whether the fault 4 interrupt is enabled.
11750 * @rmtoll IER FLT4IE LL_HRTIM_IsEnabledIT_FLT4
11751 * @param HRTIMx High Resolution Timer instance
11752 * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0).
11753 */
LL_HRTIM_IsEnabledIT_FLT4(HRTIM_TypeDef * HRTIMx)11754 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(HRTIM_TypeDef *HRTIMx)
11755 {
11756 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4)) ? 1UL : 0UL);
11757 }
11758
11759 /**
11760 * @brief Enable the fault 5 interrupt.
11761 * @rmtoll IER FLT5IE LL_HRTIM_EnableIT_FLT5
11762 * @param HRTIMx High Resolution Timer instance
11763 * @retval None
11764 */
LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef * HRTIMx)11765 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef *HRTIMx)
11766 {
11767 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
11768 }
11769
11770 /**
11771 * @brief Disable the fault 5 interrupt.
11772 * @rmtoll IER FLT5IE LL_HRTIM_DisableIT_FLT5
11773 * @param HRTIMx High Resolution Timer instance
11774 * @retval None
11775 */
LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef * HRTIMx)11776 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx)
11777 {
11778 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
11779 }
11780
11781 /**
11782 * @brief Indicate whether the fault 5 interrupt is enabled.
11783 * @rmtoll IER FLT5IE LL_HRTIM_IsEnabledIT_FLT5
11784 * @param HRTIMx High Resolution Timer instance
11785 * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0).
11786 */
LL_HRTIM_IsEnabledIT_FLT5(HRTIM_TypeDef * HRTIMx)11787 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(HRTIM_TypeDef *HRTIMx)
11788 {
11789 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5)) ? 1UL : 0UL);
11790 }
11791
11792 /**
11793 * @brief Enable the fault 6 interrupt.
11794 * @rmtoll IER FLT6IE LL_HRTIM_EnableIT_FLT6
11795 * @param HRTIMx High Resolution Timer instance
11796 * @retval None
11797 */
LL_HRTIM_EnableIT_FLT6(HRTIM_TypeDef * HRTIMx)11798 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT6(HRTIM_TypeDef *HRTIMx)
11799 {
11800 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6);
11801 }
11802
11803 /**
11804 * @brief Disable the fault 6 interrupt.
11805 * @rmtoll IER FLT6IE LL_HRTIM_DisableIT_FLT6
11806 * @param HRTIMx High Resolution Timer instance
11807 * @retval None
11808 */
LL_HRTIM_DisableIT_FLT6(HRTIM_TypeDef * HRTIMx)11809 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT6(HRTIM_TypeDef *HRTIMx)
11810 {
11811 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6);
11812 }
11813
11814 /**
11815 * @brief Indicate whether the fault 6 interrupt is enabled.
11816 * @rmtoll IER FLT6IE LL_HRTIM_IsEnabledIT_FLT6
11817 * @param HRTIMx High Resolution Timer instance
11818 * @retval State of FLT6IE bit in HRTIM_IER register (1 or 0).
11819 */
LL_HRTIM_IsEnabledIT_FLT6(HRTIM_TypeDef * HRTIMx)11820 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT6(HRTIM_TypeDef *HRTIMx)
11821 {
11822 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6) == (HRTIM_IER_FLT6)) ? 1UL : 0UL);
11823 }
11824
11825 /**
11826 * @brief Enable the system fault interrupt.
11827 * @rmtoll IER SYSFLTIE LL_HRTIM_EnableIT_SYSFLT
11828 * @param HRTIMx High Resolution Timer instance
11829 * @retval None
11830 */
LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef * HRTIMx)11831 __STATIC_INLINE void LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
11832 {
11833 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
11834 }
11835
11836 /**
11837 * @brief Disable the system fault interrupt.
11838 * @rmtoll IER SYSFLTIE LL_HRTIM_DisableIT_SYSFLT
11839 * @param HRTIMx High Resolution Timer instance
11840 * @retval None
11841 */
LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef * HRTIMx)11842 __STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
11843 {
11844 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
11845 }
11846
11847 /**
11848 * @brief Indicate whether the system fault interrupt is enabled.
11849 * @rmtoll IER SYSFLTIE LL_HRTIM_IsEnabledIT_SYSFLT
11850 * @param HRTIMx High Resolution Timer instance
11851 * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0).
11852 */
LL_HRTIM_IsEnabledIT_SYSFLT(HRTIM_TypeDef * HRTIMx)11853 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
11854 {
11855 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT)) ? 1UL : 0UL);
11856 }
11857
11858 /**
11859 * @brief Enable the DLL ready interrupt.
11860 * @rmtoll IER DLLRDYIE LL_HRTIM_EnableIT_DLLRDY
11861 * @param HRTIMx High Resolution Timer instance
11862 * @retval None
11863 */
LL_HRTIM_EnableIT_DLLRDY(HRTIM_TypeDef * HRTIMx)11864 __STATIC_INLINE void LL_HRTIM_EnableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
11865 {
11866 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
11867 }
11868
11869 /**
11870 * @brief Disable the DLL ready interrupt.
11871 * @rmtoll IER DLLRDYIE LL_HRTIM_DisableIT_DLLRDY
11872 * @param HRTIMx High Resolution Timer instance
11873 * @retval None
11874 */
LL_HRTIM_DisableIT_DLLRDY(HRTIM_TypeDef * HRTIMx)11875 __STATIC_INLINE void LL_HRTIM_DisableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
11876 {
11877 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
11878 }
11879
11880 /**
11881 * @brief Indicate whether the DLL ready interrupt is enabled.
11882 * @rmtoll IER DLLRDYIE LL_HRTIM_IsEnabledIT_DLLRDY
11883 * @param HRTIMx High Resolution Timer instance
11884 * @retval State of DLLRDYIE bit in HRTIM_IER register (1 or 0).
11885 */
LL_HRTIM_IsEnabledIT_DLLRDY(HRTIM_TypeDef * HRTIMx)11886 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
11887 {
11888 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY) == (HRTIM_IER_DLLRDY)) ? 1UL : 0UL);
11889 }
11890
11891 /**
11892 * @brief Enable the burst mode period interrupt.
11893 * @rmtoll IER BMPERIE LL_HRTIM_EnableIT_BMPER
11894 * @param HRTIMx High Resolution Timer instance
11895 * @retval None
11896 */
LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef * HRTIMx)11897 __STATIC_INLINE void LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef *HRTIMx)
11898 {
11899 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
11900 }
11901
11902 /**
11903 * @brief Disable the burst mode period interrupt.
11904 * @rmtoll IER BMPERIE LL_HRTIM_DisableIT_BMPER
11905 * @param HRTIMx High Resolution Timer instance
11906 * @retval None
11907 */
LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef * HRTIMx)11908 __STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx)
11909 {
11910 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
11911 }
11912
11913 /**
11914 * @brief Indicate whether the burst mode period interrupt is enabled.
11915 * @rmtoll IER BMPERIE LL_HRTIM_IsEnabledIT_BMPER
11916 * @param HRTIMx High Resolution Timer instance
11917 * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0).
11918 */
LL_HRTIM_IsEnabledIT_BMPER(HRTIM_TypeDef * HRTIMx)11919 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(HRTIM_TypeDef *HRTIMx)
11920 {
11921 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER)) ? 1UL : 0UL);
11922 }
11923
11924 /**
11925 * @brief Enable the synchronization input interrupt.
11926 * @rmtoll MDIER SYNCIE LL_HRTIM_EnableIT_SYNC
11927 * @param HRTIMx High Resolution Timer instance
11928 * @retval None
11929 */
LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef * HRTIMx)11930 __STATIC_INLINE void LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef *HRTIMx)
11931 {
11932 SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
11933 }
11934
11935 /**
11936 * @brief Disable the synchronization input interrupt.
11937 * @rmtoll MDIER SYNCIE LL_HRTIM_DisableIT_SYNC
11938 * @param HRTIMx High Resolution Timer instance
11939 * @retval None
11940 */
LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef * HRTIMx)11941 __STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx)
11942 {
11943 CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
11944 }
11945
11946 /**
11947 * @brief Indicate whether the synchronization input interrupt is enabled.
11948 * @rmtoll MDIER SYNCIE LL_HRTIM_IsEnabledIT_SYNC
11949 * @param HRTIMx High Resolution Timer instance
11950 * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0).
11951 */
LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef * HRTIMx)11952 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef *HRTIMx)
11953 {
11954 return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : 0UL);
11955 }
11956
11957 /**
11958 * @brief Enable the update interrupt for a given timer.
11959 * @rmtoll MDIER MUPDIE LL_HRTIM_EnableIT_UPDATE\n
11960 * TIMxDIER UPDIE LL_HRTIM_EnableIT_UPDATE
11961 * @param HRTIMx High Resolution Timer instance
11962 * @param Timer This parameter can be one of the following values:
11963 * @arg @ref LL_HRTIM_TIMER_MASTER
11964 * @arg @ref LL_HRTIM_TIMER_A
11965 * @arg @ref LL_HRTIM_TIMER_B
11966 * @arg @ref LL_HRTIM_TIMER_C
11967 * @arg @ref LL_HRTIM_TIMER_D
11968 * @arg @ref LL_HRTIM_TIMER_E
11969 * @arg @ref LL_HRTIM_TIMER_F
11970 * @retval None
11971 */
LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11972 __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11973 {
11974 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11975 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
11976 REG_OFFSET_TAB_TIMER[iTimer]));
11977 SET_BIT(*pReg, HRTIM_MDIER_MUPDIE);
11978 }
11979
11980 /**
11981 * @brief Disable the update interrupt for a given timer.
11982 * @rmtoll MDIER MUPDIE LL_HRTIM_DisableIT_UPDATE\n
11983 * TIMxDIER UPDIE LL_HRTIM_DisableIT_UPDATE
11984 * @param HRTIMx High Resolution Timer instance
11985 * @param Timer This parameter can be one of the following values:
11986 * @arg @ref LL_HRTIM_TIMER_MASTER
11987 * @arg @ref LL_HRTIM_TIMER_A
11988 * @arg @ref LL_HRTIM_TIMER_B
11989 * @arg @ref LL_HRTIM_TIMER_C
11990 * @arg @ref LL_HRTIM_TIMER_D
11991 * @arg @ref LL_HRTIM_TIMER_E
11992 * @arg @ref LL_HRTIM_TIMER_F
11993 * @retval None
11994 */
LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)11995 __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
11996 {
11997 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
11998 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
11999 REG_OFFSET_TAB_TIMER[iTimer]));
12000 CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE);
12001 }
12002
12003 /**
12004 * @brief Indicate whether the update interrupt is enabled for a given timer.
12005 * @rmtoll MDIER MUPDIE LL_HRTIM_IsEnabledIT_UPDATE\n
12006 * TIMxDIER UPDIE LL_HRTIM_IsEnabledIT_UPDATE
12007 * @param HRTIMx High Resolution Timer instance
12008 * @param Timer This parameter can be one of the following values:
12009 * @arg @ref LL_HRTIM_TIMER_MASTER
12010 * @arg @ref LL_HRTIM_TIMER_A
12011 * @arg @ref LL_HRTIM_TIMER_B
12012 * @arg @ref LL_HRTIM_TIMER_C
12013 * @arg @ref LL_HRTIM_TIMER_D
12014 * @arg @ref LL_HRTIM_TIMER_E
12015 * @arg @ref LL_HRTIM_TIMER_F
12016 * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12017 */
LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12018 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12019 {
12020 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12021 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12022 REG_OFFSET_TAB_TIMER[iTimer]));
12023
12024 return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL);
12025 }
12026
12027 /**
12028 * @brief Enable the repetition interrupt for a given timer.
12029 * @rmtoll MDIER MREPIE LL_HRTIM_EnableIT_REP\n
12030 * TIMxDIER REPIE LL_HRTIM_EnableIT_REP
12031 * @param HRTIMx High Resolution Timer instance
12032 * @param Timer This parameter can be one of the following values:
12033 * @arg @ref LL_HRTIM_TIMER_MASTER
12034 * @arg @ref LL_HRTIM_TIMER_A
12035 * @arg @ref LL_HRTIM_TIMER_B
12036 * @arg @ref LL_HRTIM_TIMER_C
12037 * @arg @ref LL_HRTIM_TIMER_D
12038 * @arg @ref LL_HRTIM_TIMER_E
12039 * @arg @ref LL_HRTIM_TIMER_F
12040 * @retval None
12041 */
LL_HRTIM_EnableIT_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12042 __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12043 {
12044 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12045 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12046 REG_OFFSET_TAB_TIMER[iTimer]));
12047 SET_BIT(*pReg, HRTIM_MDIER_MREPIE);
12048 }
12049
12050 /**
12051 * @brief Disable the repetition interrupt for a given timer.
12052 * @rmtoll MDIER MREPIE LL_HRTIM_DisableIT_REP\n
12053 * TIMxDIER REPIE LL_HRTIM_DisableIT_REP
12054 * @param HRTIMx High Resolution Timer instance
12055 * @param Timer This parameter can be one of the following values:
12056 * @arg @ref LL_HRTIM_TIMER_MASTER
12057 * @arg @ref LL_HRTIM_TIMER_A
12058 * @arg @ref LL_HRTIM_TIMER_B
12059 * @arg @ref LL_HRTIM_TIMER_C
12060 * @arg @ref LL_HRTIM_TIMER_D
12061 * @arg @ref LL_HRTIM_TIMER_E
12062 * @arg @ref LL_HRTIM_TIMER_F
12063 * @retval None
12064 */
LL_HRTIM_DisableIT_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12065 __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12066 {
12067 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12068 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12069 REG_OFFSET_TAB_TIMER[iTimer]));
12070 CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE);
12071 }
12072
12073 /**
12074 * @brief Indicate whether the repetition interrupt is enabled for a given timer.
12075 * @rmtoll MDIER MREPIE LL_HRTIM_IsEnabledIT_REP\n
12076 * TIMxDIER REPIE LL_HRTIM_IsEnabledIT_REP
12077 * @param HRTIMx High Resolution Timer instance
12078 * @param Timer This parameter can be one of the following values:
12079 * @arg @ref LL_HRTIM_TIMER_MASTER
12080 * @arg @ref LL_HRTIM_TIMER_A
12081 * @arg @ref LL_HRTIM_TIMER_B
12082 * @arg @ref LL_HRTIM_TIMER_C
12083 * @arg @ref LL_HRTIM_TIMER_D
12084 * @arg @ref LL_HRTIM_TIMER_E
12085 * @arg @ref LL_HRTIM_TIMER_F
12086 * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12087 */
LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12088 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12089 {
12090 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12091 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12092 REG_OFFSET_TAB_TIMER[iTimer]));
12093
12094 return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL);
12095 }
12096
12097 /**
12098 * @brief Enable the compare 1 interrupt for a given timer.
12099 * @rmtoll MDIER MCMP1IE LL_HRTIM_EnableIT_CMP1\n
12100 * TIMxDIER CMP1IE LL_HRTIM_EnableIT_CMP1
12101 * @param HRTIMx High Resolution Timer instance
12102 * @param Timer This parameter can be one of the following values:
12103 * @arg @ref LL_HRTIM_TIMER_MASTER
12104 * @arg @ref LL_HRTIM_TIMER_A
12105 * @arg @ref LL_HRTIM_TIMER_B
12106 * @arg @ref LL_HRTIM_TIMER_C
12107 * @arg @ref LL_HRTIM_TIMER_D
12108 * @arg @ref LL_HRTIM_TIMER_E
12109 * @arg @ref LL_HRTIM_TIMER_F
12110 * @retval None
12111 */
LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12112 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12113 {
12114 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12115 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12116 REG_OFFSET_TAB_TIMER[iTimer]));
12117 SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
12118 }
12119
12120 /**
12121 * @brief Disable the compare 1 interrupt for a given timer.
12122 * @rmtoll MDIER MCMP1IE LL_HRTIM_DisableIT_CMP1\n
12123 * TIMxDIER CMP1IE LL_HRTIM_DisableIT_CMP1
12124 * @param HRTIMx High Resolution Timer instance
12125 * @param Timer This parameter can be one of the following values:
12126 * @arg @ref LL_HRTIM_TIMER_MASTER
12127 * @arg @ref LL_HRTIM_TIMER_A
12128 * @arg @ref LL_HRTIM_TIMER_B
12129 * @arg @ref LL_HRTIM_TIMER_C
12130 * @arg @ref LL_HRTIM_TIMER_D
12131 * @arg @ref LL_HRTIM_TIMER_E
12132 * @arg @ref LL_HRTIM_TIMER_F
12133 * @retval None
12134 */
LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12135 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12136 {
12137 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12138 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12139 REG_OFFSET_TAB_TIMER[iTimer]));
12140 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
12141 }
12142
12143 /**
12144 * @brief Indicate whether the compare 1 interrupt is enabled for a given timer.
12145 * @rmtoll MDIER MCMP1IE LL_HRTIM_IsEnabledIT_CMP1\n
12146 * TIMxDIER CMP1IE LL_HRTIM_IsEnabledIT_CMP1
12147 * @param HRTIMx High Resolution Timer instance
12148 * @param Timer This parameter can be one of the following values:
12149 * @arg @ref LL_HRTIM_TIMER_MASTER
12150 * @arg @ref LL_HRTIM_TIMER_A
12151 * @arg @ref LL_HRTIM_TIMER_B
12152 * @arg @ref LL_HRTIM_TIMER_C
12153 * @arg @ref LL_HRTIM_TIMER_D
12154 * @arg @ref LL_HRTIM_TIMER_E
12155 * @arg @ref LL_HRTIM_TIMER_F
12156 * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12157 */
LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12158 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12159 {
12160 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12161 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12162 REG_OFFSET_TAB_TIMER[iTimer]));
12163
12164 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL);
12165 }
12166
12167 /**
12168 * @brief Enable the compare 2 interrupt for a given timer.
12169 * @rmtoll MDIER MCMP2IE LL_HRTIM_EnableIT_CMP2\n
12170 * TIMxDIER CMP2IE LL_HRTIM_EnableIT_CMP2
12171 * @param HRTIMx High Resolution Timer instance
12172 * @param Timer This parameter can be one of the following values:
12173 * @arg @ref LL_HRTIM_TIMER_MASTER
12174 * @arg @ref LL_HRTIM_TIMER_A
12175 * @arg @ref LL_HRTIM_TIMER_B
12176 * @arg @ref LL_HRTIM_TIMER_C
12177 * @arg @ref LL_HRTIM_TIMER_D
12178 * @arg @ref LL_HRTIM_TIMER_E
12179 * @arg @ref LL_HRTIM_TIMER_F
12180 * @retval None
12181 */
LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12182 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12183 {
12184 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12185 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12186 REG_OFFSET_TAB_TIMER[iTimer]));
12187 SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
12188 }
12189
12190 /**
12191 * @brief Disable the compare 2 interrupt for a given timer.
12192 * @rmtoll MDIER MCMP2IE LL_HRTIM_DisableIT_CMP2\n
12193 * TIMxDIER CMP2IE LL_HRTIM_DisableIT_CMP2
12194 * @param HRTIMx High Resolution Timer instance
12195 * @param Timer This parameter can be one of the following values:
12196 * @arg @ref LL_HRTIM_TIMER_MASTER
12197 * @arg @ref LL_HRTIM_TIMER_A
12198 * @arg @ref LL_HRTIM_TIMER_B
12199 * @arg @ref LL_HRTIM_TIMER_C
12200 * @arg @ref LL_HRTIM_TIMER_D
12201 * @arg @ref LL_HRTIM_TIMER_E
12202 * @arg @ref LL_HRTIM_TIMER_F
12203 * @retval None
12204 */
LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12205 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12206 {
12207 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12208 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12209 REG_OFFSET_TAB_TIMER[iTimer]));
12210 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
12211 }
12212
12213 /**
12214 * @brief Indicate whether the compare 2 interrupt is enabled for a given timer.
12215 * @rmtoll MDIER MCMP2IE LL_HRTIM_IsEnabledIT_CMP2\n
12216 * TIMxDIER CMP2IE LL_HRTIM_IsEnabledIT_CMP2
12217 * @param HRTIMx High Resolution Timer instance
12218 * @param Timer This parameter can be one of the following values:
12219 * @arg @ref LL_HRTIM_TIMER_MASTER
12220 * @arg @ref LL_HRTIM_TIMER_A
12221 * @arg @ref LL_HRTIM_TIMER_B
12222 * @arg @ref LL_HRTIM_TIMER_C
12223 * @arg @ref LL_HRTIM_TIMER_D
12224 * @arg @ref LL_HRTIM_TIMER_E
12225 * @arg @ref LL_HRTIM_TIMER_F
12226 * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12227 */
LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12228 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12229 {
12230 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12231 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12232 REG_OFFSET_TAB_TIMER[iTimer]));
12233
12234 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL);
12235 }
12236
12237 /**
12238 * @brief Enable the compare 3 interrupt for a given timer.
12239 * @rmtoll MDIER MCMP3IE LL_HRTIM_EnableIT_CMP3\n
12240 * TIMxDIER CMP3IE LL_HRTIM_EnableIT_CMP3
12241 * @param HRTIMx High Resolution Timer instance
12242 * @param Timer This parameter can be one of the following values:
12243 * @arg @ref LL_HRTIM_TIMER_MASTER
12244 * @arg @ref LL_HRTIM_TIMER_A
12245 * @arg @ref LL_HRTIM_TIMER_B
12246 * @arg @ref LL_HRTIM_TIMER_C
12247 * @arg @ref LL_HRTIM_TIMER_D
12248 * @arg @ref LL_HRTIM_TIMER_E
12249 * @arg @ref LL_HRTIM_TIMER_F
12250 * @retval None
12251 */
LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12252 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12253 {
12254 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12255 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12256 REG_OFFSET_TAB_TIMER[iTimer]));
12257 SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
12258 }
12259
12260 /**
12261 * @brief Disable the compare 3 interrupt for a given timer.
12262 * @rmtoll MDIER MCMP3IE LL_HRTIM_DisableIT_CMP3\n
12263 * TIMxDIER CMP3IE LL_HRTIM_DisableIT_CMP3
12264 * @param HRTIMx High Resolution Timer instance
12265 * @param Timer This parameter can be one of the following values:
12266 * @arg @ref LL_HRTIM_TIMER_MASTER
12267 * @arg @ref LL_HRTIM_TIMER_A
12268 * @arg @ref LL_HRTIM_TIMER_B
12269 * @arg @ref LL_HRTIM_TIMER_C
12270 * @arg @ref LL_HRTIM_TIMER_D
12271 * @arg @ref LL_HRTIM_TIMER_E
12272 * @arg @ref LL_HRTIM_TIMER_F
12273 * @retval None
12274 */
LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12275 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12276 {
12277 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12278 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12279 REG_OFFSET_TAB_TIMER[iTimer]));
12280 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
12281 }
12282
12283 /**
12284 * @brief Indicate whether the compare 3 interrupt is enabled for a given timer.
12285 * @rmtoll MDIER MCMP3IE LL_HRTIM_IsEnabledIT_CMP3\n
12286 * TIMxDIER CMP3IE LL_HRTIM_IsEnabledIT_CMP3
12287 * @param HRTIMx High Resolution Timer instance
12288 * @param Timer This parameter can be one of the following values:
12289 * @arg @ref LL_HRTIM_TIMER_MASTER
12290 * @arg @ref LL_HRTIM_TIMER_A
12291 * @arg @ref LL_HRTIM_TIMER_B
12292 * @arg @ref LL_HRTIM_TIMER_C
12293 * @arg @ref LL_HRTIM_TIMER_D
12294 * @arg @ref LL_HRTIM_TIMER_E
12295 * @arg @ref LL_HRTIM_TIMER_F
12296 * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12297 */
LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12298 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12299 {
12300 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12301 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12302 REG_OFFSET_TAB_TIMER[iTimer]));
12303
12304 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL);
12305 }
12306
12307 /**
12308 * @brief Enable the compare 4 interrupt for a given timer.
12309 * @rmtoll MDIER MCMP4IE LL_HRTIM_EnableIT_CMP4\n
12310 * TIMxDIER CMP4IE LL_HRTIM_EnableIT_CMP4
12311 * @param HRTIMx High Resolution Timer instance
12312 * @param Timer This parameter can be one of the following values:
12313 * @arg @ref LL_HRTIM_TIMER_MASTER
12314 * @arg @ref LL_HRTIM_TIMER_A
12315 * @arg @ref LL_HRTIM_TIMER_B
12316 * @arg @ref LL_HRTIM_TIMER_C
12317 * @arg @ref LL_HRTIM_TIMER_D
12318 * @arg @ref LL_HRTIM_TIMER_E
12319 * @arg @ref LL_HRTIM_TIMER_F
12320 * @retval None
12321 */
LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12322 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12323 {
12324 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12325 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12326 REG_OFFSET_TAB_TIMER[iTimer]));
12327 SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
12328 }
12329
12330 /**
12331 * @brief Disable the compare 4 interrupt for a given timer.
12332 * @rmtoll MDIER MCMP4IE LL_HRTIM_DisableIT_CMP4\n
12333 * TIMxDIER CMP4IE LL_HRTIM_DisableIT_CMP4
12334 * @param HRTIMx High Resolution Timer instance
12335 * @param Timer This parameter can be one of the following values:
12336 * @arg @ref LL_HRTIM_TIMER_MASTER
12337 * @arg @ref LL_HRTIM_TIMER_A
12338 * @arg @ref LL_HRTIM_TIMER_B
12339 * @arg @ref LL_HRTIM_TIMER_C
12340 * @arg @ref LL_HRTIM_TIMER_D
12341 * @arg @ref LL_HRTIM_TIMER_E
12342 * @arg @ref LL_HRTIM_TIMER_F
12343 * @retval None
12344 */
LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12345 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12346 {
12347 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12348 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12349 REG_OFFSET_TAB_TIMER[iTimer]));
12350 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
12351 }
12352
12353 /**
12354 * @brief Indicate whether the compare 4 interrupt is enabled for a given timer.
12355 * @rmtoll MDIER MCMP4IE LL_HRTIM_IsEnabledIT_CMP4\n
12356 * TIMxDIER CMP4IE LL_HRTIM_IsEnabledIT_CMP4
12357 * @param HRTIMx High Resolution Timer instance
12358 * @param Timer This parameter can be one of the following values:
12359 * @arg @ref LL_HRTIM_TIMER_MASTER
12360 * @arg @ref LL_HRTIM_TIMER_A
12361 * @arg @ref LL_HRTIM_TIMER_B
12362 * @arg @ref LL_HRTIM_TIMER_C
12363 * @arg @ref LL_HRTIM_TIMER_D
12364 * @arg @ref LL_HRTIM_TIMER_E
12365 * @arg @ref LL_HRTIM_TIMER_F
12366 * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12367 */
LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12368 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12369 {
12370 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12371 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12372 REG_OFFSET_TAB_TIMER[iTimer]));
12373
12374 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL);
12375 }
12376
12377 /**
12378 * @brief Enable the capture 1 interrupt for a given timer.
12379 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_EnableIT_CPT1
12380 * @param HRTIMx High Resolution Timer instance
12381 * @param Timer This parameter can be one of the following values:
12382 * @arg @ref LL_HRTIM_TIMER_A
12383 * @arg @ref LL_HRTIM_TIMER_B
12384 * @arg @ref LL_HRTIM_TIMER_C
12385 * @arg @ref LL_HRTIM_TIMER_D
12386 * @arg @ref LL_HRTIM_TIMER_E
12387 * @arg @ref LL_HRTIM_TIMER_F
12388 * @retval None
12389 */
LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12390 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12391 {
12392 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12393 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12394 REG_OFFSET_TAB_TIMER[iTimer]));
12395 SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
12396 }
12397
12398 /**
12399 * @brief Enable the capture 1 interrupt for a given timer.
12400 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_DisableIT_CPT1
12401 * @param HRTIMx High Resolution Timer instance
12402 * @param Timer This parameter can be one of the following values:
12403 * @arg @ref LL_HRTIM_TIMER_A
12404 * @arg @ref LL_HRTIM_TIMER_B
12405 * @arg @ref LL_HRTIM_TIMER_C
12406 * @arg @ref LL_HRTIM_TIMER_D
12407 * @arg @ref LL_HRTIM_TIMER_E
12408 * @arg @ref LL_HRTIM_TIMER_F
12409 * @retval None
12410 */
LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12411 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12412 {
12413 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12414 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12415 REG_OFFSET_TAB_TIMER[iTimer]));
12416 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
12417 }
12418
12419 /**
12420 * @brief Indicate whether the capture 1 interrupt is enabled for a given timer.
12421 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_IsEnabledIT_CPT1
12422 * @param HRTIMx High Resolution Timer instance
12423 * @param Timer This parameter can be one of the following values:
12424 * @arg @ref LL_HRTIM_TIMER_A
12425 * @arg @ref LL_HRTIM_TIMER_B
12426 * @arg @ref LL_HRTIM_TIMER_C
12427 * @arg @ref LL_HRTIM_TIMER_D
12428 * @arg @ref LL_HRTIM_TIMER_E
12429 * @arg @ref LL_HRTIM_TIMER_F
12430 * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0).
12431 */
LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12432 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12433 {
12434 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12435 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12436 REG_OFFSET_TAB_TIMER[iTimer]));
12437
12438 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL);
12439 }
12440
12441 /**
12442 * @brief Enable the capture 2 interrupt for a given timer.
12443 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_EnableIT_CPT2
12444 * @param HRTIMx High Resolution Timer instance
12445 * @param Timer This parameter can be one of the following values:
12446 * @arg @ref LL_HRTIM_TIMER_A
12447 * @arg @ref LL_HRTIM_TIMER_B
12448 * @arg @ref LL_HRTIM_TIMER_C
12449 * @arg @ref LL_HRTIM_TIMER_D
12450 * @arg @ref LL_HRTIM_TIMER_E
12451 * @arg @ref LL_HRTIM_TIMER_F
12452 * @retval None
12453 */
LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12454 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12455 {
12456 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12457 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12458 REG_OFFSET_TAB_TIMER[iTimer]));
12459 SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
12460 }
12461
12462 /**
12463 * @brief Enable the capture 2 interrupt for a given timer.
12464 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_DisableIT_CPT2
12465 * @param HRTIMx High Resolution Timer instance
12466 * @param Timer This parameter can be one of the following values:
12467 * @arg @ref LL_HRTIM_TIMER_A
12468 * @arg @ref LL_HRTIM_TIMER_B
12469 * @arg @ref LL_HRTIM_TIMER_C
12470 * @arg @ref LL_HRTIM_TIMER_D
12471 * @arg @ref LL_HRTIM_TIMER_E
12472 * @arg @ref LL_HRTIM_TIMER_F
12473 * @retval None
12474 */
LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12475 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12476 {
12477 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12478 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12479 REG_OFFSET_TAB_TIMER[iTimer]));
12480 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
12481 }
12482
12483 /**
12484 * @brief Indicate whether the capture 2 interrupt is enabled for a given timer.
12485 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_IsEnabledIT_CPT2
12486 * @param HRTIMx High Resolution Timer instance
12487 * @param Timer This parameter can be one of the following values:
12488 * @arg @ref LL_HRTIM_TIMER_A
12489 * @arg @ref LL_HRTIM_TIMER_B
12490 * @arg @ref LL_HRTIM_TIMER_C
12491 * @arg @ref LL_HRTIM_TIMER_D
12492 * @arg @ref LL_HRTIM_TIMER_E
12493 * @arg @ref LL_HRTIM_TIMER_F
12494 * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0).
12495 */
LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12496 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12497 {
12498 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12499 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12500 REG_OFFSET_TAB_TIMER[iTimer]));
12501
12502 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL);
12503 }
12504
12505 /**
12506 * @brief Enable the output 1 set interrupt for a given timer.
12507 * @rmtoll TIMxDIER SET1IE LL_HRTIM_EnableIT_SET1
12508 * @param HRTIMx High Resolution Timer instance
12509 * @param Timer This parameter can be one of the following values:
12510 * @arg @ref LL_HRTIM_TIMER_A
12511 * @arg @ref LL_HRTIM_TIMER_B
12512 * @arg @ref LL_HRTIM_TIMER_C
12513 * @arg @ref LL_HRTIM_TIMER_D
12514 * @arg @ref LL_HRTIM_TIMER_E
12515 * @arg @ref LL_HRTIM_TIMER_F
12516 * @retval None
12517 */
LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12518 __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12519 {
12520 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12521 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12522 REG_OFFSET_TAB_TIMER[iTimer]));
12523 SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
12524 }
12525
12526 /**
12527 * @brief Disable the output 1 set interrupt for a given timer.
12528 * @rmtoll TIMxDIER SET1IE LL_HRTIM_DisableIT_SET1
12529 * @param HRTIMx High Resolution Timer instance
12530 * @param Timer This parameter can be one of the following values:
12531 * @arg @ref LL_HRTIM_TIMER_A
12532 * @arg @ref LL_HRTIM_TIMER_B
12533 * @arg @ref LL_HRTIM_TIMER_C
12534 * @arg @ref LL_HRTIM_TIMER_D
12535 * @arg @ref LL_HRTIM_TIMER_E
12536 * @arg @ref LL_HRTIM_TIMER_F
12537 * @retval None
12538 */
LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12539 __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12540 {
12541 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12542 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12543 REG_OFFSET_TAB_TIMER[iTimer]));
12544 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
12545 }
12546
12547 /**
12548 * @brief Indicate whether the output 1 set interrupt is enabled for a given timer.
12549 * @rmtoll TIMxDIER SET1IE LL_HRTIM_IsEnabledIT_SET1
12550 * @param HRTIMx High Resolution Timer instance
12551 * @param Timer This parameter can be one of the following values:
12552 * @arg @ref LL_HRTIM_TIMER_A
12553 * @arg @ref LL_HRTIM_TIMER_B
12554 * @arg @ref LL_HRTIM_TIMER_C
12555 * @arg @ref LL_HRTIM_TIMER_D
12556 * @arg @ref LL_HRTIM_TIMER_E
12557 * @arg @ref LL_HRTIM_TIMER_F
12558 * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0).
12559 */
LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12560 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12561 {
12562 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12563 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12564 REG_OFFSET_TAB_TIMER[iTimer]));
12565
12566 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL);
12567 }
12568
12569 /**
12570 * @brief Enable the output 1 reset interrupt for a given timer.
12571 * @rmtoll TIMxDIER RST1IE LL_HRTIM_EnableIT_RST1
12572 * @param HRTIMx High Resolution Timer instance
12573 * @param Timer This parameter can be one of the following values:
12574 * @arg @ref LL_HRTIM_TIMER_A
12575 * @arg @ref LL_HRTIM_TIMER_B
12576 * @arg @ref LL_HRTIM_TIMER_C
12577 * @arg @ref LL_HRTIM_TIMER_D
12578 * @arg @ref LL_HRTIM_TIMER_E
12579 * @arg @ref LL_HRTIM_TIMER_F
12580 * @retval None
12581 */
LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12582 __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12583 {
12584 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12585 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12586 REG_OFFSET_TAB_TIMER[iTimer]));
12587 SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
12588 }
12589
12590 /**
12591 * @brief Disable the output 1 reset interrupt for a given timer.
12592 * @rmtoll TIMxDIER RST1IE LL_HRTIM_DisableIT_RST1
12593 * @param HRTIMx High Resolution Timer instance
12594 * @param Timer This parameter can be one of the following values:
12595 * @arg @ref LL_HRTIM_TIMER_A
12596 * @arg @ref LL_HRTIM_TIMER_B
12597 * @arg @ref LL_HRTIM_TIMER_C
12598 * @arg @ref LL_HRTIM_TIMER_D
12599 * @arg @ref LL_HRTIM_TIMER_E
12600 * @arg @ref LL_HRTIM_TIMER_F
12601 * @retval None
12602 */
LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12603 __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12604 {
12605 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12606 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12607 REG_OFFSET_TAB_TIMER[iTimer]));
12608 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
12609 }
12610
12611 /**
12612 * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
12613 * @rmtoll TIMxDIER RST1IE LL_HRTIM_IsEnabledIT_RST1
12614 * @param HRTIMx High Resolution Timer instance
12615 * @param Timer This parameter can be one of the following values:
12616 * @arg @ref LL_HRTIM_TIMER_A
12617 * @arg @ref LL_HRTIM_TIMER_B
12618 * @arg @ref LL_HRTIM_TIMER_C
12619 * @arg @ref LL_HRTIM_TIMER_D
12620 * @arg @ref LL_HRTIM_TIMER_E
12621 * @arg @ref LL_HRTIM_TIMER_F
12622 * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0).
12623 */
LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12624 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12625 {
12626 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12627 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12628 REG_OFFSET_TAB_TIMER[iTimer]));
12629
12630 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL);
12631 }
12632
12633 /**
12634 * @brief Enable the output 2 set interrupt for a given timer.
12635 * @rmtoll TIMxDIER SET2IE LL_HRTIM_EnableIT_SET2
12636 * @param HRTIMx High Resolution Timer instance
12637 * @param Timer This parameter can be one of the following values:
12638 * @arg @ref LL_HRTIM_TIMER_A
12639 * @arg @ref LL_HRTIM_TIMER_B
12640 * @arg @ref LL_HRTIM_TIMER_C
12641 * @arg @ref LL_HRTIM_TIMER_D
12642 * @arg @ref LL_HRTIM_TIMER_E
12643 * @arg @ref LL_HRTIM_TIMER_F
12644 * @retval None
12645 */
LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12646 __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12647 {
12648 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12649 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12650 REG_OFFSET_TAB_TIMER[iTimer]));
12651 SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
12652 }
12653
12654 /**
12655 * @brief Disable the output 2 set interrupt for a given timer.
12656 * @rmtoll TIMxDIER SET2IE LL_HRTIM_DisableIT_SET2
12657 * @param HRTIMx High Resolution Timer instance
12658 * @param Timer This parameter can be one of the following values:
12659 * @arg @ref LL_HRTIM_TIMER_A
12660 * @arg @ref LL_HRTIM_TIMER_B
12661 * @arg @ref LL_HRTIM_TIMER_C
12662 * @arg @ref LL_HRTIM_TIMER_D
12663 * @arg @ref LL_HRTIM_TIMER_E
12664 * @arg @ref LL_HRTIM_TIMER_F
12665 * @retval None
12666 */
LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12667 __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12668 {
12669 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12670 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12671 REG_OFFSET_TAB_TIMER[iTimer]));
12672 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
12673 }
12674
12675 /**
12676 * @brief Indicate whether the output 2 set interrupt is enabled for a given timer.
12677 * @rmtoll TIMxDIER SET2IE LL_HRTIM_IsEnabledIT_SET2
12678 * @param HRTIMx High Resolution Timer instance
12679 * @param Timer This parameter can be one of the following values:
12680 * @arg @ref LL_HRTIM_TIMER_A
12681 * @arg @ref LL_HRTIM_TIMER_B
12682 * @arg @ref LL_HRTIM_TIMER_C
12683 * @arg @ref LL_HRTIM_TIMER_D
12684 * @arg @ref LL_HRTIM_TIMER_E
12685 * @arg @ref LL_HRTIM_TIMER_F
12686 * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0).
12687 */
LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12688 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12689 {
12690 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12691 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12692 REG_OFFSET_TAB_TIMER[iTimer]));
12693
12694 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL);
12695 }
12696
12697 /**
12698 * @brief Enable the output 2 reset interrupt for a given timer.
12699 * @rmtoll TIMxDIER RST2IE LL_HRTIM_EnableIT_RST2
12700 * @param HRTIMx High Resolution Timer instance
12701 * @param Timer This parameter can be one of the following values:
12702 * @arg @ref LL_HRTIM_TIMER_A
12703 * @arg @ref LL_HRTIM_TIMER_B
12704 * @arg @ref LL_HRTIM_TIMER_C
12705 * @arg @ref LL_HRTIM_TIMER_D
12706 * @arg @ref LL_HRTIM_TIMER_E
12707 * @arg @ref LL_HRTIM_TIMER_F
12708 * @retval None
12709 */
LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12710 __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12711 {
12712 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12713 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12714 REG_OFFSET_TAB_TIMER[iTimer]));
12715 SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
12716 }
12717
12718 /**
12719 * @brief Disable the output 2 reset interrupt for a given timer.
12720 * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
12721 * @param HRTIMx High Resolution Timer instance
12722 * @param Timer This parameter can be one of the following values:
12723 * @arg @ref LL_HRTIM_TIMER_A
12724 * @arg @ref LL_HRTIM_TIMER_B
12725 * @arg @ref LL_HRTIM_TIMER_C
12726 * @arg @ref LL_HRTIM_TIMER_D
12727 * @arg @ref LL_HRTIM_TIMER_E
12728 * @arg @ref LL_HRTIM_TIMER_F
12729 * @retval None
12730 */
LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12731 __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12732 {
12733 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12734 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12735 REG_OFFSET_TAB_TIMER[iTimer]));
12736 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
12737 }
12738
12739 /**
12740 * @brief Indicate whether the output 2 reset LL_HRTIM_IsEnabledIT_RST2 is enabled for a given timer.
12741 * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
12742 * @param HRTIMx High Resolution Timer instance
12743 * @param Timer This parameter can be one of the following values:
12744 * @arg @ref LL_HRTIM_TIMER_A
12745 * @arg @ref LL_HRTIM_TIMER_B
12746 * @arg @ref LL_HRTIM_TIMER_C
12747 * @arg @ref LL_HRTIM_TIMER_D
12748 * @arg @ref LL_HRTIM_TIMER_E
12749 * @arg @ref LL_HRTIM_TIMER_F
12750 * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0).
12751 */
LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12752 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12753 {
12754 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12755 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12756 REG_OFFSET_TAB_TIMER[iTimer]));
12757
12758 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL);
12759 }
12760
12761 /**
12762 * @brief Enable the reset/roll-over interrupt for a given timer.
12763 * @rmtoll TIMxDIER RSTIE LL_HRTIM_EnableIT_RST
12764 * @param HRTIMx High Resolution Timer instance
12765 * @param Timer This parameter can be one of the following values:
12766 * @arg @ref LL_HRTIM_TIMER_A
12767 * @arg @ref LL_HRTIM_TIMER_B
12768 * @arg @ref LL_HRTIM_TIMER_C
12769 * @arg @ref LL_HRTIM_TIMER_D
12770 * @arg @ref LL_HRTIM_TIMER_E
12771 * @arg @ref LL_HRTIM_TIMER_F
12772 * @retval None
12773 */
LL_HRTIM_EnableIT_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12774 __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12775 {
12776 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12777 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12778 REG_OFFSET_TAB_TIMER[iTimer]));
12779 SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
12780 }
12781
12782 /**
12783 * @brief Disable the reset/roll-over interrupt for a given timer.
12784 * @rmtoll TIMxDIER RSTIE LL_HRTIM_DisableIT_RST
12785 * @param HRTIMx High Resolution Timer instance
12786 * @param Timer This parameter can be one of the following values:
12787 * @arg @ref LL_HRTIM_TIMER_A
12788 * @arg @ref LL_HRTIM_TIMER_B
12789 * @arg @ref LL_HRTIM_TIMER_C
12790 * @arg @ref LL_HRTIM_TIMER_D
12791 * @arg @ref LL_HRTIM_TIMER_E
12792 * @arg @ref LL_HRTIM_TIMER_F
12793 * @retval None
12794 */
LL_HRTIM_DisableIT_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12795 __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12796 {
12797 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12798 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12799 REG_OFFSET_TAB_TIMER[iTimer]));
12800 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
12801 }
12802
12803 /**
12804 * @brief Indicate whether the reset/roll-over interrupt is enabled for a given timer.
12805 * @rmtoll TIMxDIER RSTIE LL_HRTIM_IsEnabledIT_RST
12806 * @param HRTIMx High Resolution Timer instance
12807 * @param Timer This parameter can be one of the following values:
12808 * @arg @ref LL_HRTIM_TIMER_A
12809 * @arg @ref LL_HRTIM_TIMER_B
12810 * @arg @ref LL_HRTIM_TIMER_C
12811 * @arg @ref LL_HRTIM_TIMER_D
12812 * @arg @ref LL_HRTIM_TIMER_E
12813 * @arg @ref LL_HRTIM_TIMER_F
12814 * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0).
12815 */
LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12816 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12817 {
12818 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12819 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12820 REG_OFFSET_TAB_TIMER[iTimer]));
12821
12822 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL);
12823 }
12824
12825 /**
12826 * @brief Enable the delayed protection interrupt for a given timer.
12827 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_EnableIT_DLYPRT
12828 * @param HRTIMx High Resolution Timer instance
12829 * @param Timer This parameter can be one of the following values:
12830 * @arg @ref LL_HRTIM_TIMER_A
12831 * @arg @ref LL_HRTIM_TIMER_B
12832 * @arg @ref LL_HRTIM_TIMER_C
12833 * @arg @ref LL_HRTIM_TIMER_D
12834 * @arg @ref LL_HRTIM_TIMER_E
12835 * @arg @ref LL_HRTIM_TIMER_F
12836 * @retval None
12837 */
LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12838 __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12839 {
12840 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12841 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12842 REG_OFFSET_TAB_TIMER[iTimer]));
12843 SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
12844 }
12845
12846 /**
12847 * @brief Disable the delayed protection interrupt for a given timer.
12848 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_DisableIT_DLYPRT
12849 * @param HRTIMx High Resolution Timer instance
12850 * @param Timer This parameter can be one of the following values:
12851 * @arg @ref LL_HRTIM_TIMER_A
12852 * @arg @ref LL_HRTIM_TIMER_B
12853 * @arg @ref LL_HRTIM_TIMER_C
12854 * @arg @ref LL_HRTIM_TIMER_D
12855 * @arg @ref LL_HRTIM_TIMER_E
12856 * @arg @ref LL_HRTIM_TIMER_F
12857 * @retval None
12858 */
LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12859 __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12860 {
12861 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12862 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12863 REG_OFFSET_TAB_TIMER[iTimer]));
12864 CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
12865 }
12866
12867 /**
12868 * @brief Indicate whether the delayed protection interrupt is enabled for a given timer.
12869 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_IsEnabledIT_DLYPRT
12870 * @param HRTIMx High Resolution Timer instance
12871 * @param Timer This parameter can be one of the following values:
12872 * @arg @ref LL_HRTIM_TIMER_A
12873 * @arg @ref LL_HRTIM_TIMER_B
12874 * @arg @ref LL_HRTIM_TIMER_C
12875 * @arg @ref LL_HRTIM_TIMER_D
12876 * @arg @ref LL_HRTIM_TIMER_E
12877 * @arg @ref LL_HRTIM_TIMER_F
12878 * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0).
12879 */
LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12880 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12881 {
12882 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12883 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12884 REG_OFFSET_TAB_TIMER[iTimer]));
12885
12886 return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL);
12887 }
12888
12889 /**
12890 * @}
12891 */
12892
12893 /** @defgroup HRTIM_LL_EF_DMA_Management DMA_Management
12894 * @{
12895 */
12896
12897 /**
12898 * @brief Enable the synchronization input DMA request.
12899 * @rmtoll MDIER SYNCDE LL_HRTIM_EnableDMAReq_SYNC
12900 * @param HRTIMx High Resolution Timer instance
12901 * @retval None
12902 */
LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef * HRTIMx)12903 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
12904 {
12905 SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
12906 }
12907
12908 /**
12909 * @brief Disable the synchronization input DMA request
12910 * @rmtoll MDIER SYNCDE LL_HRTIM_DisableDMAReq_SYNC
12911 * @param HRTIMx High Resolution Timer instance
12912 * @retval None
12913 */
LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef * HRTIMx)12914 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
12915 {
12916 CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
12917 }
12918
12919 /**
12920 * @brief Indicate whether the synchronization input DMA request is enabled.
12921 * @rmtoll MDIER SYNCDE LL_HRTIM_IsEnabledDMAReq_SYNC
12922 * @param HRTIMx High Resolution Timer instance
12923 * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0).
12924 */
LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef * HRTIMx)12925 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
12926 {
12927 return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE)) ? 1UL : 0UL);
12928 }
12929
12930 /**
12931 * @brief Enable the update DMA request for a given timer.
12932 * @rmtoll MDIER MUPDDE LL_HRTIM_EnableDMAReq_UPDATE\n
12933 * TIMxDIER UPDDE LL_HRTIM_EnableDMAReq_UPDATE
12934 * @param HRTIMx High Resolution Timer instance
12935 * @param Timer This parameter can be one of the following values:
12936 * @arg @ref LL_HRTIM_TIMER_MASTER
12937 * @arg @ref LL_HRTIM_TIMER_A
12938 * @arg @ref LL_HRTIM_TIMER_B
12939 * @arg @ref LL_HRTIM_TIMER_C
12940 * @arg @ref LL_HRTIM_TIMER_D
12941 * @arg @ref LL_HRTIM_TIMER_E
12942 * @arg @ref LL_HRTIM_TIMER_F
12943 * @retval None
12944 */
LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12945 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12946 {
12947 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12948 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12949 REG_OFFSET_TAB_TIMER[iTimer]));
12950 SET_BIT(*pReg, HRTIM_MDIER_MUPDDE);
12951 }
12952
12953 /**
12954 * @brief Disable the update DMA request for a given timer.
12955 * @rmtoll MDIER MUPDDE LL_HRTIM_DisableDMAReq_UPDATE\n
12956 * TIMxDIER UPDDE LL_HRTIM_DisableDMAReq_UPDATE
12957 * @param HRTIMx High Resolution Timer instance
12958 * @param Timer This parameter can be one of the following values:
12959 * @arg @ref LL_HRTIM_TIMER_MASTER
12960 * @arg @ref LL_HRTIM_TIMER_A
12961 * @arg @ref LL_HRTIM_TIMER_B
12962 * @arg @ref LL_HRTIM_TIMER_C
12963 * @arg @ref LL_HRTIM_TIMER_D
12964 * @arg @ref LL_HRTIM_TIMER_E
12965 * @arg @ref LL_HRTIM_TIMER_F
12966 * @retval None
12967 */
LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12968 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12969 {
12970 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12971 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12972 REG_OFFSET_TAB_TIMER[iTimer]));
12973 CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE);
12974 }
12975
12976 /**
12977 * @brief Indicate whether the update DMA request is enabled for a given timer.
12978 * @rmtoll MDIER MUPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE\n
12979 * TIMxDIER UPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE
12980 * @param HRTIMx High Resolution Timer instance
12981 * @param Timer This parameter can be one of the following values:
12982 * @arg @ref LL_HRTIM_TIMER_MASTER
12983 * @arg @ref LL_HRTIM_TIMER_A
12984 * @arg @ref LL_HRTIM_TIMER_B
12985 * @arg @ref LL_HRTIM_TIMER_C
12986 * @arg @ref LL_HRTIM_TIMER_D
12987 * @arg @ref LL_HRTIM_TIMER_E
12988 * @arg @ref LL_HRTIM_TIMER_F
12989 * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12990 */
LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)12991 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
12992 {
12993 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
12994 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12995 REG_OFFSET_TAB_TIMER[iTimer]));
12996
12997 return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL);
12998 }
12999
13000 /**
13001 * @brief Enable the repetition DMA request for a given timer.
13002 * @rmtoll MDIER MREPDE LL_HRTIM_EnableDMAReq_REP\n
13003 * TIMxDIER REPDE LL_HRTIM_EnableDMAReq_REP
13004 * @param HRTIMx High Resolution Timer instance
13005 * @param Timer This parameter can be one of the following values:
13006 * @arg @ref LL_HRTIM_TIMER_MASTER
13007 * @arg @ref LL_HRTIM_TIMER_A
13008 * @arg @ref LL_HRTIM_TIMER_B
13009 * @arg @ref LL_HRTIM_TIMER_C
13010 * @arg @ref LL_HRTIM_TIMER_D
13011 * @arg @ref LL_HRTIM_TIMER_E
13012 * @arg @ref LL_HRTIM_TIMER_F
13013 * @retval None
13014 */
LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13015 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13016 {
13017 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13018 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13019 REG_OFFSET_TAB_TIMER[iTimer]));
13020 SET_BIT(*pReg, HRTIM_MDIER_MREPDE);
13021 }
13022
13023 /**
13024 * @brief Disable the repetition DMA request for a given timer.
13025 * @rmtoll MDIER MREPDE LL_HRTIM_DisableDMAReq_REP\n
13026 * TIMxDIER REPDE LL_HRTIM_DisableDMAReq_REP
13027 * @param HRTIMx High Resolution Timer instance
13028 * @param Timer This parameter can be one of the following values:
13029 * @arg @ref LL_HRTIM_TIMER_MASTER
13030 * @arg @ref LL_HRTIM_TIMER_A
13031 * @arg @ref LL_HRTIM_TIMER_B
13032 * @arg @ref LL_HRTIM_TIMER_C
13033 * @arg @ref LL_HRTIM_TIMER_D
13034 * @arg @ref LL_HRTIM_TIMER_E
13035 * @arg @ref LL_HRTIM_TIMER_F
13036 * @retval None
13037 */
LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13038 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13039 {
13040 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13041 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13042 REG_OFFSET_TAB_TIMER[iTimer]));
13043 CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE);
13044 }
13045
13046 /**
13047 * @brief Indicate whether the repetition DMA request is enabled for a given timer.
13048 * @rmtoll MDIER MREPDE LL_HRTIM_IsEnabledDMAReq_REP\n
13049 * TIMxDIER REPDE LL_HRTIM_IsEnabledDMAReq_REP
13050 * @param HRTIMx High Resolution Timer instance
13051 * @param Timer This parameter can be one of the following values:
13052 * @arg @ref LL_HRTIM_TIMER_MASTER
13053 * @arg @ref LL_HRTIM_TIMER_A
13054 * @arg @ref LL_HRTIM_TIMER_B
13055 * @arg @ref LL_HRTIM_TIMER_C
13056 * @arg @ref LL_HRTIM_TIMER_D
13057 * @arg @ref LL_HRTIM_TIMER_E
13058 * @arg @ref LL_HRTIM_TIMER_F
13059 * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13060 */
LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13061 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13062 {
13063 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13064 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13065 REG_OFFSET_TAB_TIMER[iTimer]));
13066
13067 return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL);
13068 }
13069
13070 /**
13071 * @brief Enable the compare 1 DMA request for a given timer.
13072 * @rmtoll MDIER MCMP1DE LL_HRTIM_EnableDMAReq_CMP1\n
13073 * TIMxDIER CMP1DE LL_HRTIM_EnableDMAReq_CMP1
13074 * @param HRTIMx High Resolution Timer instance
13075 * @param Timer This parameter can be one of the following values:
13076 * @arg @ref LL_HRTIM_TIMER_MASTER
13077 * @arg @ref LL_HRTIM_TIMER_A
13078 * @arg @ref LL_HRTIM_TIMER_B
13079 * @arg @ref LL_HRTIM_TIMER_C
13080 * @arg @ref LL_HRTIM_TIMER_D
13081 * @arg @ref LL_HRTIM_TIMER_E
13082 * @arg @ref LL_HRTIM_TIMER_F
13083 * @retval None
13084 */
LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13085 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13086 {
13087 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13088 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13089 REG_OFFSET_TAB_TIMER[iTimer]));
13090 SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
13091 }
13092
13093 /**
13094 * @brief Disable the compare 1 DMA request for a given timer.
13095 * @rmtoll MDIER MCMP1DE LL_HRTIM_DisableDMAReq_CMP1\n
13096 * TIMxDIER CMP1DE LL_HRTIM_DisableDMAReq_CMP1
13097 * @param HRTIMx High Resolution Timer instance
13098 * @param Timer This parameter can be one of the following values:
13099 * @arg @ref LL_HRTIM_TIMER_MASTER
13100 * @arg @ref LL_HRTIM_TIMER_A
13101 * @arg @ref LL_HRTIM_TIMER_B
13102 * @arg @ref LL_HRTIM_TIMER_C
13103 * @arg @ref LL_HRTIM_TIMER_D
13104 * @arg @ref LL_HRTIM_TIMER_E
13105 * @arg @ref LL_HRTIM_TIMER_F
13106 * @retval None
13107 */
LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13108 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13109 {
13110 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13111 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13112 REG_OFFSET_TAB_TIMER[iTimer]));
13113 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
13114 }
13115
13116 /**
13117 * @brief Indicate whether the compare 1 DMA request is enabled for a given timer.
13118 * @rmtoll MDIER MCMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1\n
13119 * TIMxDIER CMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1
13120 * @param HRTIMx High Resolution Timer instance
13121 * @param Timer This parameter can be one of the following values:
13122 * @arg @ref LL_HRTIM_TIMER_MASTER
13123 * @arg @ref LL_HRTIM_TIMER_A
13124 * @arg @ref LL_HRTIM_TIMER_B
13125 * @arg @ref LL_HRTIM_TIMER_C
13126 * @arg @ref LL_HRTIM_TIMER_D
13127 * @arg @ref LL_HRTIM_TIMER_E
13128 * @arg @ref LL_HRTIM_TIMER_F
13129 * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13130 */
LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13131 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13132 {
13133 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13134 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13135 REG_OFFSET_TAB_TIMER[iTimer]));
13136
13137 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL);
13138 }
13139
13140 /**
13141 * @brief Enable the compare 2 DMA request for a given timer.
13142 * @rmtoll MDIER MCMP2DE LL_HRTIM_EnableDMAReq_CMP2\n
13143 * TIMxDIER CMP2DE LL_HRTIM_EnableDMAReq_CMP2
13144 * @param HRTIMx High Resolution Timer instance
13145 * @param Timer This parameter can be one of the following values:
13146 * @arg @ref LL_HRTIM_TIMER_MASTER
13147 * @arg @ref LL_HRTIM_TIMER_A
13148 * @arg @ref LL_HRTIM_TIMER_B
13149 * @arg @ref LL_HRTIM_TIMER_C
13150 * @arg @ref LL_HRTIM_TIMER_D
13151 * @arg @ref LL_HRTIM_TIMER_E
13152 * @arg @ref LL_HRTIM_TIMER_F
13153 * @retval None
13154 */
LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13155 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13156 {
13157 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13158 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13159 REG_OFFSET_TAB_TIMER[iTimer]));
13160 SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
13161 }
13162
13163 /**
13164 * @brief Disable the compare 2 DMA request for a given timer.
13165 * @rmtoll MDIER MCMP2DE LL_HRTIM_DisableDMAReq_CMP2\n
13166 * TIMxDIER CMP2DE LL_HRTIM_DisableDMAReq_CMP2
13167 * @param HRTIMx High Resolution Timer instance
13168 * @param Timer This parameter can be one of the following values:
13169 * @arg @ref LL_HRTIM_TIMER_MASTER
13170 * @arg @ref LL_HRTIM_TIMER_A
13171 * @arg @ref LL_HRTIM_TIMER_B
13172 * @arg @ref LL_HRTIM_TIMER_C
13173 * @arg @ref LL_HRTIM_TIMER_D
13174 * @arg @ref LL_HRTIM_TIMER_E
13175 * @arg @ref LL_HRTIM_TIMER_F
13176 * @retval None
13177 */
LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13178 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13179 {
13180 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13181 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13182 REG_OFFSET_TAB_TIMER[iTimer]));
13183 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
13184 }
13185
13186 /**
13187 * @brief Indicate whether the compare 2 DMA request is enabled for a given timer.
13188 * @rmtoll MDIER MCMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2\n
13189 * TIMxDIER CMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2
13190 * @param HRTIMx High Resolution Timer instance
13191 * @param Timer This parameter can be one of the following values:
13192 * @arg @ref LL_HRTIM_TIMER_MASTER
13193 * @arg @ref LL_HRTIM_TIMER_A
13194 * @arg @ref LL_HRTIM_TIMER_B
13195 * @arg @ref LL_HRTIM_TIMER_C
13196 * @arg @ref LL_HRTIM_TIMER_D
13197 * @arg @ref LL_HRTIM_TIMER_E
13198 * @arg @ref LL_HRTIM_TIMER_F
13199 * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13200 */
LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13201 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13202 {
13203 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13204 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13205 REG_OFFSET_TAB_TIMER[iTimer]));
13206
13207 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL);
13208 }
13209
13210 /**
13211 * @brief Enable the compare 3 DMA request for a given timer.
13212 * @rmtoll MDIER MCMP3DE LL_HRTIM_EnableDMAReq_CMP3\n
13213 * TIMxDIER CMP3DE LL_HRTIM_EnableDMAReq_CMP3
13214 * @param HRTIMx High Resolution Timer instance
13215 * @param Timer This parameter can be one of the following values:
13216 * @arg @ref LL_HRTIM_TIMER_MASTER
13217 * @arg @ref LL_HRTIM_TIMER_A
13218 * @arg @ref LL_HRTIM_TIMER_B
13219 * @arg @ref LL_HRTIM_TIMER_C
13220 * @arg @ref LL_HRTIM_TIMER_D
13221 * @arg @ref LL_HRTIM_TIMER_E
13222 * @arg @ref LL_HRTIM_TIMER_F
13223 * @retval None
13224 */
LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13225 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13226 {
13227 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13228 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13229 REG_OFFSET_TAB_TIMER[iTimer]));
13230 SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
13231 }
13232
13233 /**
13234 * @brief Disable the compare 3 DMA request for a given timer.
13235 * @rmtoll MDIER MCMP3DE LL_HRTIM_DisableDMAReq_CMP3\n
13236 * TIMxDIER CMP3DE LL_HRTIM_DisableDMAReq_CMP3
13237 * @param HRTIMx High Resolution Timer instance
13238 * @param Timer This parameter can be one of the following values:
13239 * @arg @ref LL_HRTIM_TIMER_MASTER
13240 * @arg @ref LL_HRTIM_TIMER_A
13241 * @arg @ref LL_HRTIM_TIMER_B
13242 * @arg @ref LL_HRTIM_TIMER_C
13243 * @arg @ref LL_HRTIM_TIMER_D
13244 * @arg @ref LL_HRTIM_TIMER_E
13245 * @arg @ref LL_HRTIM_TIMER_F
13246 * @retval None
13247 */
LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13248 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13249 {
13250 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13251 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13252 REG_OFFSET_TAB_TIMER[iTimer]));
13253 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
13254 }
13255
13256 /**
13257 * @brief Indicate whether the compare 3 DMA request is enabled for a given timer.
13258 * @rmtoll MDIER MCMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3\n
13259 * TIMxDIER CMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3
13260 * @param HRTIMx High Resolution Timer instance
13261 * @param Timer This parameter can be one of the following values:
13262 * @arg @ref LL_HRTIM_TIMER_MASTER
13263 * @arg @ref LL_HRTIM_TIMER_A
13264 * @arg @ref LL_HRTIM_TIMER_B
13265 * @arg @ref LL_HRTIM_TIMER_C
13266 * @arg @ref LL_HRTIM_TIMER_D
13267 * @arg @ref LL_HRTIM_TIMER_E
13268 * @arg @ref LL_HRTIM_TIMER_F
13269 * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13270 */
LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13271 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13272 {
13273 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13274 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13275 REG_OFFSET_TAB_TIMER[iTimer]));
13276
13277 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL);
13278 }
13279
13280 /**
13281 * @brief Enable the compare 4 DMA request for a given timer.
13282 * @rmtoll MDIER MCMP4DE LL_HRTIM_EnableDMAReq_CMP4\n
13283 * TIMxDIER CMP4DE LL_HRTIM_EnableDMAReq_CMP4
13284 * @param HRTIMx High Resolution Timer instance
13285 * @param Timer This parameter can be one of the following values:
13286 * @arg @ref LL_HRTIM_TIMER_MASTER
13287 * @arg @ref LL_HRTIM_TIMER_A
13288 * @arg @ref LL_HRTIM_TIMER_B
13289 * @arg @ref LL_HRTIM_TIMER_C
13290 * @arg @ref LL_HRTIM_TIMER_D
13291 * @arg @ref LL_HRTIM_TIMER_E
13292 * @arg @ref LL_HRTIM_TIMER_F
13293 * @retval None
13294 */
LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13295 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13296 {
13297 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13298 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13299 REG_OFFSET_TAB_TIMER[iTimer]));
13300 SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
13301 }
13302
13303 /**
13304 * @brief Disable the compare 4 DMA request for a given timer.
13305 * @rmtoll MDIER MCMP4DE LL_HRTIM_DisableDMAReq_CMP4\n
13306 * TIMxDIER CMP4DE LL_HRTIM_DisableDMAReq_CMP4
13307 * @param HRTIMx High Resolution Timer instance
13308 * @param Timer This parameter can be one of the following values:
13309 * @arg @ref LL_HRTIM_TIMER_MASTER
13310 * @arg @ref LL_HRTIM_TIMER_A
13311 * @arg @ref LL_HRTIM_TIMER_B
13312 * @arg @ref LL_HRTIM_TIMER_C
13313 * @arg @ref LL_HRTIM_TIMER_D
13314 * @arg @ref LL_HRTIM_TIMER_E
13315 * @arg @ref LL_HRTIM_TIMER_F
13316 * @retval None
13317 */
LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13318 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13319 {
13320 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13321 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13322 REG_OFFSET_TAB_TIMER[iTimer]));
13323 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
13324 }
13325
13326 /**
13327 * @brief Indicate whether the compare 4 DMA request is enabled for a given timer.
13328 * @rmtoll MDIER MCMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4\n
13329 * TIMxDIER CMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4
13330 * @param HRTIMx High Resolution Timer instance
13331 * @param Timer This parameter can be one of the following values:
13332 * @arg @ref LL_HRTIM_TIMER_MASTER
13333 * @arg @ref LL_HRTIM_TIMER_A
13334 * @arg @ref LL_HRTIM_TIMER_B
13335 * @arg @ref LL_HRTIM_TIMER_C
13336 * @arg @ref LL_HRTIM_TIMER_D
13337 * @arg @ref LL_HRTIM_TIMER_E
13338 * @arg @ref LL_HRTIM_TIMER_F
13339 * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13340 */
LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13341 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13342 {
13343 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13344 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13345 REG_OFFSET_TAB_TIMER[iTimer]));
13346
13347 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL);
13348 }
13349
13350 /**
13351 * @brief Enable the capture 1 DMA request for a given timer.
13352 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_EnableDMAReq_CPT1
13353 * @param HRTIMx High Resolution Timer instance
13354 * @param Timer This parameter can be one of the following values:
13355 * @arg @ref LL_HRTIM_TIMER_A
13356 * @arg @ref LL_HRTIM_TIMER_B
13357 * @arg @ref LL_HRTIM_TIMER_C
13358 * @arg @ref LL_HRTIM_TIMER_D
13359 * @arg @ref LL_HRTIM_TIMER_E
13360 * @arg @ref LL_HRTIM_TIMER_F
13361 * @retval None
13362 */
LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13363 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13364 {
13365 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13366 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13367 REG_OFFSET_TAB_TIMER[iTimer]));
13368 SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
13369 }
13370
13371 /**
13372 * @brief Disable the capture 1 DMA request for a given timer.
13373 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_DisableDMAReq_CPT1
13374 * @param HRTIMx High Resolution Timer instance
13375 * @param Timer This parameter can be one of the following values:
13376 * @arg @ref LL_HRTIM_TIMER_A
13377 * @arg @ref LL_HRTIM_TIMER_B
13378 * @arg @ref LL_HRTIM_TIMER_C
13379 * @arg @ref LL_HRTIM_TIMER_D
13380 * @arg @ref LL_HRTIM_TIMER_E
13381 * @arg @ref LL_HRTIM_TIMER_F
13382 * @retval None
13383 */
LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13384 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13385 {
13386 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13387 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13388 REG_OFFSET_TAB_TIMER[iTimer]));
13389 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
13390 }
13391
13392 /**
13393 * @brief Indicate whether the capture 1 DMA request is enabled for a given timer.
13394 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_IsEnabledDMAReq_CPT1
13395 * @param HRTIMx High Resolution Timer instance
13396 * @param Timer This parameter can be one of the following values:
13397 * @arg @ref LL_HRTIM_TIMER_A
13398 * @arg @ref LL_HRTIM_TIMER_B
13399 * @arg @ref LL_HRTIM_TIMER_C
13400 * @arg @ref LL_HRTIM_TIMER_D
13401 * @arg @ref LL_HRTIM_TIMER_E
13402 * @arg @ref LL_HRTIM_TIMER_F
13403 * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0).
13404 */
LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13405 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13406 {
13407 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13408 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13409 REG_OFFSET_TAB_TIMER[iTimer]));
13410
13411 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL);
13412 }
13413
13414 /**
13415 * @brief Enable the capture 2 DMA request for a given timer.
13416 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_EnableDMAReq_CPT2
13417 * @param HRTIMx High Resolution Timer instance
13418 * @param Timer This parameter can be one of the following values:
13419 * @arg @ref LL_HRTIM_TIMER_A
13420 * @arg @ref LL_HRTIM_TIMER_B
13421 * @arg @ref LL_HRTIM_TIMER_C
13422 * @arg @ref LL_HRTIM_TIMER_D
13423 * @arg @ref LL_HRTIM_TIMER_E
13424 * @arg @ref LL_HRTIM_TIMER_F
13425 * @retval None
13426 */
LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13427 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13428 {
13429 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13430 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13431 REG_OFFSET_TAB_TIMER[iTimer]));
13432 SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
13433 }
13434
13435 /**
13436 * @brief Disable the capture 2 DMA request for a given timer.
13437 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_DisableDMAReq_CPT2
13438 * @param HRTIMx High Resolution Timer instance
13439 * @param Timer This parameter can be one of the following values:
13440 * @arg @ref LL_HRTIM_TIMER_A
13441 * @arg @ref LL_HRTIM_TIMER_B
13442 * @arg @ref LL_HRTIM_TIMER_C
13443 * @arg @ref LL_HRTIM_TIMER_D
13444 * @arg @ref LL_HRTIM_TIMER_E
13445 * @arg @ref LL_HRTIM_TIMER_F
13446 * @retval None
13447 */
LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13448 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13449 {
13450 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13451 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13452 REG_OFFSET_TAB_TIMER[iTimer]));
13453 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
13454 }
13455
13456 /**
13457 * @brief Indicate whether the capture 2 DMA request is enabled for a given timer.
13458 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_IsEnabledDMAReq_CPT2
13459 * @param HRTIMx High Resolution Timer instance
13460 * @param Timer This parameter can be one of the following values:
13461 * @arg @ref LL_HRTIM_TIMER_A
13462 * @arg @ref LL_HRTIM_TIMER_B
13463 * @arg @ref LL_HRTIM_TIMER_C
13464 * @arg @ref LL_HRTIM_TIMER_D
13465 * @arg @ref LL_HRTIM_TIMER_E
13466 * @arg @ref LL_HRTIM_TIMER_F
13467 * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0).
13468 */
LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13469 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13470 {
13471 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13472 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13473 REG_OFFSET_TAB_TIMER[iTimer]));
13474
13475 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL);
13476 }
13477
13478 /**
13479 * @brief Enable the output 1 set DMA request for a given timer.
13480 * @rmtoll TIMxDIER SET1DE LL_HRTIM_EnableDMAReq_SET1
13481 * @param HRTIMx High Resolution Timer instance
13482 * @param Timer This parameter can be one of the following values:
13483 * @arg @ref LL_HRTIM_TIMER_A
13484 * @arg @ref LL_HRTIM_TIMER_B
13485 * @arg @ref LL_HRTIM_TIMER_C
13486 * @arg @ref LL_HRTIM_TIMER_D
13487 * @arg @ref LL_HRTIM_TIMER_E
13488 * @arg @ref LL_HRTIM_TIMER_F
13489 * @retval None
13490 */
LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13491 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13492 {
13493 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13494 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13495 REG_OFFSET_TAB_TIMER[iTimer]));
13496 SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
13497 }
13498
13499 /**
13500 * @brief Disable the output 1 set DMA request for a given timer.
13501 * @rmtoll TIMxDIER SET1DE LL_HRTIM_DisableDMAReq_SET1
13502 * @param HRTIMx High Resolution Timer instance
13503 * @param Timer This parameter can be one of the following values:
13504 * @arg @ref LL_HRTIM_TIMER_A
13505 * @arg @ref LL_HRTIM_TIMER_B
13506 * @arg @ref LL_HRTIM_TIMER_C
13507 * @arg @ref LL_HRTIM_TIMER_D
13508 * @arg @ref LL_HRTIM_TIMER_E
13509 * @arg @ref LL_HRTIM_TIMER_F
13510 * @retval None
13511 */
LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13512 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13513 {
13514 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13515 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13516 REG_OFFSET_TAB_TIMER[iTimer]));
13517 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
13518 }
13519
13520 /**
13521 * @brief Indicate whether the output 1 set DMA request is enabled for a given timer.
13522 * @rmtoll TIMxDIER SET1DE LL_HRTIM_IsEnabledDMAReq_SET1
13523 * @param HRTIMx High Resolution Timer instance
13524 * @param Timer This parameter can be one of the following values:
13525 * @arg @ref LL_HRTIM_TIMER_A
13526 * @arg @ref LL_HRTIM_TIMER_B
13527 * @arg @ref LL_HRTIM_TIMER_C
13528 * @arg @ref LL_HRTIM_TIMER_D
13529 * @arg @ref LL_HRTIM_TIMER_E
13530 * @arg @ref LL_HRTIM_TIMER_F
13531 * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0).
13532 */
LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13533 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13534 {
13535 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13536 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13537 REG_OFFSET_TAB_TIMER[iTimer]));
13538
13539 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL);
13540 }
13541
13542 /**
13543 * @brief Enable the output 1 reset DMA request for a given timer.
13544 * @rmtoll TIMxDIER RST1DE LL_HRTIM_EnableDMAReq_RST1
13545 * @param HRTIMx High Resolution Timer instance
13546 * @param Timer This parameter can be one of the following values:
13547 * @arg @ref LL_HRTIM_TIMER_A
13548 * @arg @ref LL_HRTIM_TIMER_B
13549 * @arg @ref LL_HRTIM_TIMER_C
13550 * @arg @ref LL_HRTIM_TIMER_D
13551 * @arg @ref LL_HRTIM_TIMER_E
13552 * @arg @ref LL_HRTIM_TIMER_F
13553 * @retval None
13554 */
LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13555 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13556 {
13557 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13558 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13559 REG_OFFSET_TAB_TIMER[iTimer]));
13560 SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
13561 }
13562
13563 /**
13564 * @brief Disable the output 1 reset DMA request for a given timer.
13565 * @rmtoll TIMxDIER RST1DE LL_HRTIM_DisableDMAReq_RST1
13566 * @param HRTIMx High Resolution Timer instance
13567 * @param Timer This parameter can be one of the following values:
13568 * @arg @ref LL_HRTIM_TIMER_A
13569 * @arg @ref LL_HRTIM_TIMER_B
13570 * @arg @ref LL_HRTIM_TIMER_C
13571 * @arg @ref LL_HRTIM_TIMER_D
13572 * @arg @ref LL_HRTIM_TIMER_E
13573 * @arg @ref LL_HRTIM_TIMER_F
13574 * @retval None
13575 */
LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13576 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13577 {
13578 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13579 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13580 REG_OFFSET_TAB_TIMER[iTimer]));
13581 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
13582 }
13583
13584 /**
13585 * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
13586 * @rmtoll TIMxDIER RST1DE LL_HRTIM_IsEnabledDMAReq_RST1
13587 * @param HRTIMx High Resolution Timer instance
13588 * @param Timer This parameter can be one of the following values:
13589 * @arg @ref LL_HRTIM_TIMER_A
13590 * @arg @ref LL_HRTIM_TIMER_B
13591 * @arg @ref LL_HRTIM_TIMER_C
13592 * @arg @ref LL_HRTIM_TIMER_D
13593 * @arg @ref LL_HRTIM_TIMER_E
13594 * @arg @ref LL_HRTIM_TIMER_F
13595 * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0).
13596 */
LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13597 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13598 {
13599 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13600 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13601 REG_OFFSET_TAB_TIMER[iTimer]));
13602
13603 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL);
13604 }
13605
13606 /**
13607 * @brief Enable the output 2 set DMA request for a given timer.
13608 * @rmtoll TIMxDIER SET2DE LL_HRTIM_EnableDMAReq_SET2
13609 * @param HRTIMx High Resolution Timer instance
13610 * @param Timer This parameter can be one of the following values:
13611 * @arg @ref LL_HRTIM_TIMER_A
13612 * @arg @ref LL_HRTIM_TIMER_B
13613 * @arg @ref LL_HRTIM_TIMER_C
13614 * @arg @ref LL_HRTIM_TIMER_D
13615 * @arg @ref LL_HRTIM_TIMER_E
13616 * @arg @ref LL_HRTIM_TIMER_F
13617 * @retval None
13618 */
LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13619 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13620 {
13621 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13622 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13623 REG_OFFSET_TAB_TIMER[iTimer]));
13624 SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
13625 }
13626
13627 /**
13628 * @brief Disable the output 2 set DMA request for a given timer.
13629 * @rmtoll TIMxDIER SET2DE LL_HRTIM_DisableDMAReq_SET2
13630 * @param HRTIMx High Resolution Timer instance
13631 * @param Timer This parameter can be one of the following values:
13632 * @arg @ref LL_HRTIM_TIMER_A
13633 * @arg @ref LL_HRTIM_TIMER_B
13634 * @arg @ref LL_HRTIM_TIMER_C
13635 * @arg @ref LL_HRTIM_TIMER_D
13636 * @arg @ref LL_HRTIM_TIMER_E
13637 * @arg @ref LL_HRTIM_TIMER_F
13638 * @retval None
13639 */
LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13640 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13641 {
13642 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13643 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13644 REG_OFFSET_TAB_TIMER[iTimer]));
13645 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
13646 }
13647
13648 /**
13649 * @brief Indicate whether the output 2 set DMA request is enabled for a given timer.
13650 * @rmtoll TIMxDIER SET2DE LL_HRTIM_IsEnabledDMAReq_SET2
13651 * @param HRTIMx High Resolution Timer instance
13652 * @param Timer This parameter can be one of the following values:
13653 * @arg @ref LL_HRTIM_TIMER_A
13654 * @arg @ref LL_HRTIM_TIMER_B
13655 * @arg @ref LL_HRTIM_TIMER_C
13656 * @arg @ref LL_HRTIM_TIMER_D
13657 * @arg @ref LL_HRTIM_TIMER_E
13658 * @arg @ref LL_HRTIM_TIMER_F
13659 * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0).
13660 */
LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13661 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13662 {
13663 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13664 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13665 REG_OFFSET_TAB_TIMER[iTimer]));
13666
13667 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL);
13668 }
13669
13670 /**
13671 * @brief Enable the output 2 reset DMA request for a given timer.
13672 * @rmtoll TIMxDIER RST2DE LL_HRTIM_EnableDMAReq_RST2
13673 * @param HRTIMx High Resolution Timer instance
13674 * @param Timer This parameter can be one of the following values:
13675 * @arg @ref LL_HRTIM_TIMER_A
13676 * @arg @ref LL_HRTIM_TIMER_B
13677 * @arg @ref LL_HRTIM_TIMER_C
13678 * @arg @ref LL_HRTIM_TIMER_D
13679 * @arg @ref LL_HRTIM_TIMER_E
13680 * @arg @ref LL_HRTIM_TIMER_F
13681 * @retval None
13682 */
LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13683 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13684 {
13685 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13686 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13687 REG_OFFSET_TAB_TIMER[iTimer]));
13688 SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
13689 }
13690
13691 /**
13692 * @brief Disable the output 2 reset DMA request for a given timer.
13693 * @rmtoll TIMxDIER RST2DE LL_HRTIM_DisableDMAReq_RST2
13694 * @param HRTIMx High Resolution Timer instance
13695 * @param Timer This parameter can be one of the following values:
13696 * @arg @ref LL_HRTIM_TIMER_A
13697 * @arg @ref LL_HRTIM_TIMER_B
13698 * @arg @ref LL_HRTIM_TIMER_C
13699 * @arg @ref LL_HRTIM_TIMER_D
13700 * @arg @ref LL_HRTIM_TIMER_E
13701 * @arg @ref LL_HRTIM_TIMER_F
13702 * @retval None
13703 */
LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13704 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13705 {
13706 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13707 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13708 REG_OFFSET_TAB_TIMER[iTimer]));
13709 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
13710 }
13711
13712 /**
13713 * @brief Indicate whether the output 2 reset DMA request is enabled for a given timer.
13714 * @rmtoll TIMxDIER RST2DE LL_HRTIM_IsEnabledDMAReq_RST2
13715 * @param HRTIMx High Resolution Timer instance
13716 * @param Timer This parameter can be one of the following values:
13717 * @arg @ref LL_HRTIM_TIMER_A
13718 * @arg @ref LL_HRTIM_TIMER_B
13719 * @arg @ref LL_HRTIM_TIMER_C
13720 * @arg @ref LL_HRTIM_TIMER_D
13721 * @arg @ref LL_HRTIM_TIMER_E
13722 * @arg @ref LL_HRTIM_TIMER_F
13723 * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0).
13724 */
LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13725 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13726 {
13727 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13728 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13729 REG_OFFSET_TAB_TIMER[iTimer]));
13730
13731 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL);
13732 }
13733
13734 /**
13735 * @brief Enable the reset/roll-over DMA request for a given timer.
13736 * @rmtoll TIMxDIER RSTDE LL_HRTIM_EnableDMAReq_RST
13737 * @param HRTIMx High Resolution Timer instance
13738 * @param Timer This parameter can be one of the following values:
13739 * @arg @ref LL_HRTIM_TIMER_A
13740 * @arg @ref LL_HRTIM_TIMER_B
13741 * @arg @ref LL_HRTIM_TIMER_C
13742 * @arg @ref LL_HRTIM_TIMER_D
13743 * @arg @ref LL_HRTIM_TIMER_E
13744 * @arg @ref LL_HRTIM_TIMER_F
13745 * @retval None
13746 */
LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13747 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13748 {
13749 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13750 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13751 REG_OFFSET_TAB_TIMER[iTimer]));
13752 SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
13753 }
13754
13755 /**
13756 * @brief Disable the reset/roll-over DMA request for a given timer.
13757 * @rmtoll TIMxDIER RSTDE LL_HRTIM_DisableDMAReq_RST
13758 * @param HRTIMx High Resolution Timer instance
13759 * @param Timer This parameter can be one of the following values:
13760 * @arg @ref LL_HRTIM_TIMER_A
13761 * @arg @ref LL_HRTIM_TIMER_B
13762 * @arg @ref LL_HRTIM_TIMER_C
13763 * @arg @ref LL_HRTIM_TIMER_D
13764 * @arg @ref LL_HRTIM_TIMER_E
13765 * @arg @ref LL_HRTIM_TIMER_F
13766 * @retval None
13767 */
LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13768 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13769 {
13770 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13771 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13772 REG_OFFSET_TAB_TIMER[iTimer]));
13773 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
13774 }
13775
13776 /**
13777 * @brief Indicate whether the reset/roll-over DMA request is enabled for a given timer.
13778 * @rmtoll TIMxDIER RSTDE LL_HRTIM_IsEnabledDMAReq_RST
13779 * @param HRTIMx High Resolution Timer instance
13780 * @param Timer This parameter can be one of the following values:
13781 * @arg @ref LL_HRTIM_TIMER_A
13782 * @arg @ref LL_HRTIM_TIMER_B
13783 * @arg @ref LL_HRTIM_TIMER_C
13784 * @arg @ref LL_HRTIM_TIMER_D
13785 * @arg @ref LL_HRTIM_TIMER_E
13786 * @arg @ref LL_HRTIM_TIMER_F
13787 * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0).
13788 */
LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13789 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13790 {
13791 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13792 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13793 REG_OFFSET_TAB_TIMER[iTimer]));
13794
13795 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL);
13796 }
13797
13798 /**
13799 * @brief Enable the delayed protection DMA request for a given timer.
13800 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_EnableDMAReq_DLYPRT
13801 * @param HRTIMx High Resolution Timer instance
13802 * @param Timer This parameter can be one of the following values:
13803 * @arg @ref LL_HRTIM_TIMER_A
13804 * @arg @ref LL_HRTIM_TIMER_B
13805 * @arg @ref LL_HRTIM_TIMER_C
13806 * @arg @ref LL_HRTIM_TIMER_D
13807 * @arg @ref LL_HRTIM_TIMER_E
13808 * @arg @ref LL_HRTIM_TIMER_F
13809 * @retval None
13810 */
LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13811 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13812 {
13813 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13814 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13815 REG_OFFSET_TAB_TIMER[iTimer]));
13816 SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
13817 }
13818
13819 /**
13820 * @brief Disable the delayed protection DMA request for a given timer.
13821 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_DisableDMAReq_DLYPRT
13822 * @param HRTIMx High Resolution Timer instance
13823 * @param Timer This parameter can be one of the following values:
13824 * @arg @ref LL_HRTIM_TIMER_A
13825 * @arg @ref LL_HRTIM_TIMER_B
13826 * @arg @ref LL_HRTIM_TIMER_C
13827 * @arg @ref LL_HRTIM_TIMER_D
13828 * @arg @ref LL_HRTIM_TIMER_E
13829 * @arg @ref LL_HRTIM_TIMER_F
13830 * @retval None
13831 */
LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13832 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13833 {
13834 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13835 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13836 REG_OFFSET_TAB_TIMER[iTimer]));
13837 CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
13838 }
13839
13840 /**
13841 * @brief Indicate whether the delayed protection DMA request is enabled for a given timer.
13842 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_IsEnabledDMAReq_DLYPRT
13843 * @param HRTIMx High Resolution Timer instance
13844 * @param Timer This parameter can be one of the following values:
13845 * @arg @ref LL_HRTIM_TIMER_A
13846 * @arg @ref LL_HRTIM_TIMER_B
13847 * @arg @ref LL_HRTIM_TIMER_C
13848 * @arg @ref LL_HRTIM_TIMER_D
13849 * @arg @ref LL_HRTIM_TIMER_E
13850 * @arg @ref LL_HRTIM_TIMER_F
13851 * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0).
13852 */
LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)13853 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13854 {
13855 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
13856 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13857 REG_OFFSET_TAB_TIMER[iTimer]));
13858
13859 return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL);
13860 }
13861
13862 /**
13863 * @}
13864 */
13865
13866 #if defined(USE_FULL_LL_DRIVER)
13867 /** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions
13868 * @{
13869 */
13870 ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx);
13871 /**
13872 * @}
13873 */
13874 #endif /* USE_FULL_LL_DRIVER */
13875
13876 /**
13877 * @}
13878 */
13879
13880 /**
13881 * @}
13882 */
13883
13884 #endif /* HRTIM1 */
13885
13886 /**
13887 * @}
13888 */
13889
13890 #ifdef __cplusplus
13891 }
13892 #endif
13893
13894 #endif /* STM32G4xx_LL_HRTIM_H */
13895
13896
13897
