1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32G4xx_LL_DMA_H
21 #define __STM32G4xx_LL_DMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g4xx.h"
29 #include "stm32g4xx_ll_dmamux.h"
30
31 /** @addtogroup STM32G4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA1) || defined (DMA2)
36
37 /** @defgroup DMA_LL DMA
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
44 * @{
45 */
46 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
47 static const uint8_t CHANNEL_OFFSET_TAB[] =
48 {
49 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE)
55 #if defined (DMA1_Channel7)
56 ,
57 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
58 #endif /* DMA1_Channel7 */
59 #if defined (DMA1_Channel8)
60 ,
61 (uint8_t)(DMA1_Channel8_BASE - DMA1_BASE)
62 #endif /* DMA1_Channel8 */
63 };
64 /**
65 * @}
66 */
67
68 /* Private constants ---------------------------------------------------------*/
69 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
70 * @{
71 */
72 /* Define used to get CSELR register offset */
73 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
74
75 /* Defines used for the bit position in the register and perform offsets */
76 #define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
77 /**
78 * @}
79 */
80
81 /* Private macros ------------------------------------------------------------*/
82 #if defined(USE_FULL_LL_DRIVER)
83 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
84 * @{
85 */
86 /**
87 * @}
88 */
89 #endif /*USE_FULL_LL_DRIVER*/
90
91 /* Exported types ------------------------------------------------------------*/
92 #if defined(USE_FULL_LL_DRIVER)
93 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
94 * @{
95 */
96 typedef struct
97 {
98 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
99 or as Source base address in case of memory to memory transfer direction.
100
101 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
102
103 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
104 or as Destination base address in case of memory to memory transfer direction.
105
106 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
107
108 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
109 from memory to memory or from peripheral to memory.
110 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
111
112 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
113
114 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
115 This parameter can be a value of @ref DMA_LL_EC_MODE
116 @note: The circular buffer mode cannot be used if the memory to memory
117 data transfer direction is configured on the selected Channel
118
119 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
120
121 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
122 is incremented or not.
123 This parameter can be a value of @ref DMA_LL_EC_PERIPH
124
125 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
126
127 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
128 is incremented or not.
129 This parameter can be a value of @ref DMA_LL_EC_MEMORY
130
131 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
132
133 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
134 in case of memory to memory transfer direction.
135 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
136
137 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
138
139 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
140 in case of memory to memory transfer direction.
141 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
142
143 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
144
145 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
146 The data unit is equal to the source buffer configuration set in PeripheralSize
147 or MemorySize parameters depending in the transfer direction.
148 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
149
150 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
151
152 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
153 This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
154
155 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
156
157 uint32_t Priority; /*!< Specifies the channel priority level.
158 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
159
160 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
161
162 } LL_DMA_InitTypeDef;
163 /**
164 * @}
165 */
166 #endif /*USE_FULL_LL_DRIVER*/
167
168 /* Exported constants --------------------------------------------------------*/
169 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
170 * @{
171 */
172 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
173 * @brief Flags defines which can be used with LL_DMA_WriteReg function
174 * @{
175 */
176 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
177 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
178 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
179 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
180 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
181 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
182 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
183 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
184 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
185 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
186 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
187 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
188 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
189 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
190 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
191 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
192 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
193 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
194 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
195 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
196 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
197 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
198 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
199 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
200 #if defined (DMA1_Channel7)
201 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
202 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
203 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
204 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
205 #endif /* DMA1_Channel7 */
206 #if defined (DMA1_Channel8)
207 #define LL_DMA_IFCR_CGIF8 DMA_IFCR_CGIF8 /*!< Channel 8 global flag */
208 #define LL_DMA_IFCR_CTCIF8 DMA_IFCR_CTCIF8 /*!< Channel 8 transfer complete flag */
209 #define LL_DMA_IFCR_CHTIF8 DMA_IFCR_CHTIF8 /*!< Channel 8 half transfer flag */
210 #define LL_DMA_IFCR_CTEIF8 DMA_IFCR_CTEIF8 /*!< Channel 8 transfer error flag */
211 #endif /* DMA1_Channel8 */
212 /**
213 * @}
214 */
215
216 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
217 * @brief Flags defines which can be used with LL_DMA_ReadReg function
218 * @{
219 */
220 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
221 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
222 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
223 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
224 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
225 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
226 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
227 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
228 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
229 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
230 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
231 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
232 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
233 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
234 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
235 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
236 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
237 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
238 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
239 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
240 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
241 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
242 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
243 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
244 #if defined (DMA1_Channel7)
245 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
246 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
247 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
248 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
249 #endif /* DMA1_Channel7 */
250 #if defined (DMA1_Channel8)
251 #define LL_DMA_ISR_GIF8 DMA_ISR_GIF8 /*!< Channel 8 global flag */
252 #define LL_DMA_ISR_TCIF8 DMA_ISR_TCIF8 /*!< Channel 8 transfer complete flag */
253 #define LL_DMA_ISR_HTIF8 DMA_ISR_HTIF8 /*!< Channel 8 half transfer flag */
254 #define LL_DMA_ISR_TEIF8 DMA_ISR_TEIF8 /*!< Channel 8 transfer error flag */
255 #endif /* DMA1_Channel8 */
256 /**
257 * @}
258 */
259
260 /** @defgroup DMA_LL_EC_IT IT Defines
261 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
262 * @{
263 */
264 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
265 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
266 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
267 /**
268 * @}
269 */
270
271 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
272 * @{
273 */
274 #define LL_DMA_CHANNEL_1 0x00000000U /*!< DMA Channel 1 */
275 #define LL_DMA_CHANNEL_2 0x00000001U /*!< DMA Channel 2 */
276 #define LL_DMA_CHANNEL_3 0x00000002U /*!< DMA Channel 3 */
277 #define LL_DMA_CHANNEL_4 0x00000003U /*!< DMA Channel 4 */
278 #define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */
279 #define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */
280 #if defined (DMA1_Channel7)
281 #define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */
282 #endif /* DMA1_Channel7 */
283 #if defined (DMA1_Channel8)
284 #define LL_DMA_CHANNEL_8 0x00000007U /*!< DMA Channel 8 */
285 #endif /* DMA1_Channel8 */
286 #if defined(USE_FULL_LL_DRIVER)
287 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
288 #endif /*USE_FULL_LL_DRIVER*/
289 /**
290 * @}
291 */
292
293 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
294 * @{
295 */
296 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
297 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
298 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
299 /**
300 * @}
301 */
302
303 /** @defgroup DMA_LL_EC_MODE Transfer mode
304 * @{
305 */
306 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
307 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
308 /**
309 * @}
310 */
311
312 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
313 * @{
314 */
315 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
316 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
317 /**
318 * @}
319 */
320
321 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
322 * @{
323 */
324 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
325 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
326 /**
327 * @}
328 */
329
330 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
331 * @{
332 */
333 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
334 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
335 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
336 /**
337 * @}
338 */
339
340 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
341 * @{
342 */
343 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
344 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
345 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
346 /**
347 * @}
348 */
349
350 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
351 * @{
352 */
353 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
354 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
355 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
356 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
357 /**
358 * @}
359 */
360
361 /**
362 * @}
363 */
364
365 /* Exported macro ------------------------------------------------------------*/
366 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
367 * @{
368 */
369
370 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
371 * @{
372 */
373 /**
374 * @brief Write a value in DMA register
375 * @param __INSTANCE__ DMA Instance
376 * @param __REG__ Register to be written
377 * @param __VALUE__ Value to be written in the register
378 * @retval None
379 */
380 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
381
382 /**
383 * @brief Read a value in DMA register
384 * @param __INSTANCE__ DMA Instance
385 * @param __REG__ Register to be read
386 * @retval Register value
387 */
388 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
389 /**
390 * @}
391 */
392
393 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
394 * @{
395 */
396 /**
397 * @brief Convert DMAx_Channely into DMAx
398 * @param __CHANNEL_INSTANCE__ DMAx_Channely
399 * @retval DMAx
400 */
401 #if defined (DMA1_Channel8)
402 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
403 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel8)) ? DMA2 : DMA1)
404 #else
405 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
406 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel6)) ? DMA2 : DMA1)
407 #endif /* DMA1_Channel8 */
408 /**
409 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
410 * @param __CHANNEL_INSTANCE__ DMAx_Channely
411 * @retval LL_DMA_CHANNEL_y
412 */
413 #if defined (DMA1_Channel8)
414 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
415 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
416 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
417 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
418 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
419 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
420 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
421 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
422 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
423 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
424 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
425 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
426 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
427 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \
428 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel7)) ? LL_DMA_CHANNEL_7 : \
429 LL_DMA_CHANNEL_8)
430 #else
431 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
432 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
433 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
434 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
435 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
436 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
437 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
438 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
439 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
440 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
441 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
442 LL_DMA_CHANNEL_6)
443 #endif /* DMA1_Channel8 */
444
445 /**
446 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
447 * @param __DMA_INSTANCE__ DMAx
448 * @param __CHANNEL__ LL_DMA_CHANNEL_y
449 * @retval DMAx_Channely
450 */
451 #if defined (DMA1_Channel8)
452 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
453 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
458 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
459 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
460 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
461 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
462 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
463 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
464 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
465 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
466 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA2_Channel7 : \
467 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) ? DMA1_Channel8 : \
468 DMA2_Channel8)
469 #else
470 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
471 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
472 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
473 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
474 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
475 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
476 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
477 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
478 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
479 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
480 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
481 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
482 DMA2_Channel6)
483 #endif /* DMA1_Channel8 */
484
485 /**
486 * @}
487 */
488
489 /**
490 * @}
491 */
492
493 /* Exported functions --------------------------------------------------------*/
494 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
495 * @{
496 */
497
498 /** @defgroup DMA_LL_EF_Configuration Configuration
499 * @{
500 */
501 /**
502 * @brief Enable DMA channel.
503 * @rmtoll CCR EN LL_DMA_EnableChannel
504 * @param DMAx DMAx Instance
505 * @param Channel This parameter can be one of the following values:
506 * @arg @ref LL_DMA_CHANNEL_1
507 * @arg @ref LL_DMA_CHANNEL_2
508 * @arg @ref LL_DMA_CHANNEL_3
509 * @arg @ref LL_DMA_CHANNEL_4
510 * @arg @ref LL_DMA_CHANNEL_5
511 * @arg @ref LL_DMA_CHANNEL_6
512 * @arg @ref LL_DMA_CHANNEL_7 (*)
513 * @arg @ref LL_DMA_CHANNEL_8 (*)
514 * (*) Not on all G4 devices
515 * @retval None
516 */
LL_DMA_EnableChannel(DMA_TypeDef * DMAx,uint32_t Channel)517 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
518 {
519 uint32_t dma_base_addr = (uint32_t)DMAx;
520 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_EN);
521 }
522
523 /**
524 * @brief Disable DMA channel.
525 * @rmtoll CCR EN LL_DMA_DisableChannel
526 * @param DMAx DMAx Instance
527 * @param Channel This parameter can be one of the following values:
528 * @arg @ref LL_DMA_CHANNEL_1
529 * @arg @ref LL_DMA_CHANNEL_2
530 * @arg @ref LL_DMA_CHANNEL_3
531 * @arg @ref LL_DMA_CHANNEL_4
532 * @arg @ref LL_DMA_CHANNEL_5
533 * @arg @ref LL_DMA_CHANNEL_6
534 * @arg @ref LL_DMA_CHANNEL_7 (*)
535 * @arg @ref LL_DMA_CHANNEL_8 (*)
536 * (*) Not on all G4 devices
537 * @retval None
538 */
LL_DMA_DisableChannel(DMA_TypeDef * DMAx,uint32_t Channel)539 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
540 {
541 uint32_t dma_base_addr = (uint32_t)DMAx;
542 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_EN);
543 }
544
545 /**
546 * @brief Check if DMA channel is enabled or disabled.
547 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
548 * @param DMAx DMAx Instance
549 * @param Channel This parameter can be one of the following values:
550 * @arg @ref LL_DMA_CHANNEL_1
551 * @arg @ref LL_DMA_CHANNEL_2
552 * @arg @ref LL_DMA_CHANNEL_3
553 * @arg @ref LL_DMA_CHANNEL_4
554 * @arg @ref LL_DMA_CHANNEL_5
555 * @arg @ref LL_DMA_CHANNEL_6
556 * @arg @ref LL_DMA_CHANNEL_7 (*)
557 * @arg @ref LL_DMA_CHANNEL_8 (*)
558 * (*) Not on all G4 devices
559 * @retval State of bit (1 or 0).
560 */
LL_DMA_IsEnabledChannel(DMA_TypeDef * DMAx,uint32_t Channel)561 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
562 {
563 uint32_t dma_base_addr = (uint32_t)DMAx;
564 return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
565 DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
566 }
567
568 /**
569 * @brief Configure all parameters link to DMA transfer.
570 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
571 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
572 * CCR CIRC LL_DMA_ConfigTransfer\n
573 * CCR PINC LL_DMA_ConfigTransfer\n
574 * CCR MINC LL_DMA_ConfigTransfer\n
575 * CCR PSIZE LL_DMA_ConfigTransfer\n
576 * CCR MSIZE LL_DMA_ConfigTransfer\n
577 * CCR PL LL_DMA_ConfigTransfer
578 * @param DMAx DMAx Instance
579 * @param Channel This parameter can be one of the following values:
580 * @arg @ref LL_DMA_CHANNEL_1
581 * @arg @ref LL_DMA_CHANNEL_2
582 * @arg @ref LL_DMA_CHANNEL_3
583 * @arg @ref LL_DMA_CHANNEL_4
584 * @arg @ref LL_DMA_CHANNEL_5
585 * @arg @ref LL_DMA_CHANNEL_6
586 * @arg @ref LL_DMA_CHANNEL_7 (*)
587 * @arg @ref LL_DMA_CHANNEL_8 (*)
588 * (*) Not on all G4 devices
589 * @param Configuration This parameter must be a combination of all the following values:
590 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
591 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
592 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
593 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
594 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
595 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
596 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
597 * @retval None
598 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)599 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
600 {
601 uint32_t dma_base_addr = (uint32_t)DMAx;
602 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
603 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
604 Configuration);
605 }
606
607 /**
608 * @brief Set Data transfer direction (read from peripheral or from memory).
609 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
610 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
611 * @param DMAx DMAx Instance
612 * @param Channel This parameter can be one of the following values:
613 * @arg @ref LL_DMA_CHANNEL_1
614 * @arg @ref LL_DMA_CHANNEL_2
615 * @arg @ref LL_DMA_CHANNEL_3
616 * @arg @ref LL_DMA_CHANNEL_4
617 * @arg @ref LL_DMA_CHANNEL_5
618 * @arg @ref LL_DMA_CHANNEL_6
619 * @arg @ref LL_DMA_CHANNEL_7 (*)
620 * @arg @ref LL_DMA_CHANNEL_8 (*)
621 * (*) Not on all G4 devices
622 * @param Direction This parameter can be one of the following values:
623 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
624 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
625 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
626 * @retval None
627 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)628 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
629 {
630 uint32_t dma_base_addr = (uint32_t)DMAx;
631 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
632 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
633 }
634
635 /**
636 * @brief Get Data transfer direction (read from peripheral or from memory).
637 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
638 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
639 * @param DMAx DMAx Instance
640 * @param Channel This parameter can be one of the following values:
641 * @arg @ref LL_DMA_CHANNEL_1
642 * @arg @ref LL_DMA_CHANNEL_2
643 * @arg @ref LL_DMA_CHANNEL_3
644 * @arg @ref LL_DMA_CHANNEL_4
645 * @arg @ref LL_DMA_CHANNEL_5
646 * @arg @ref LL_DMA_CHANNEL_6
647 * @arg @ref LL_DMA_CHANNEL_7 (*)
648 * @arg @ref LL_DMA_CHANNEL_8 (*)
649 * (*) Not on all G4 devices
650 * @retval Returned value can be one of the following values:
651 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
652 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
653 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
654 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel)655 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
656 {
657 uint32_t dma_base_addr = (uint32_t)DMAx;
658 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
659 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
660 }
661
662 /**
663 * @brief Set DMA mode circular or normal.
664 * @note The circular buffer mode cannot be used if the memory-to-memory
665 * data transfer is configured on the selected Channel.
666 * @rmtoll CCR CIRC LL_DMA_SetMode
667 * @param DMAx DMAx Instance
668 * @param Channel This parameter can be one of the following values:
669 * @arg @ref LL_DMA_CHANNEL_1
670 * @arg @ref LL_DMA_CHANNEL_2
671 * @arg @ref LL_DMA_CHANNEL_3
672 * @arg @ref LL_DMA_CHANNEL_4
673 * @arg @ref LL_DMA_CHANNEL_5
674 * @arg @ref LL_DMA_CHANNEL_6
675 * @arg @ref LL_DMA_CHANNEL_7 (*)
676 * @arg @ref LL_DMA_CHANNEL_8 (*)
677 * (*) Not on all G4 devices
678 * @param Mode This parameter can be one of the following values:
679 * @arg @ref LL_DMA_MODE_NORMAL
680 * @arg @ref LL_DMA_MODE_CIRCULAR
681 * @retval None
682 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)683 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
684 {
685 uint32_t dma_base_addr = (uint32_t)DMAx;
686 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_CIRC,
687 Mode);
688 }
689
690 /**
691 * @brief Get DMA mode circular or normal.
692 * @rmtoll CCR CIRC LL_DMA_GetMode
693 * @param DMAx DMAx Instance
694 * @param Channel This parameter can be one of the following values:
695 * @arg @ref LL_DMA_CHANNEL_1
696 * @arg @ref LL_DMA_CHANNEL_2
697 * @arg @ref LL_DMA_CHANNEL_3
698 * @arg @ref LL_DMA_CHANNEL_4
699 * @arg @ref LL_DMA_CHANNEL_5
700 * @arg @ref LL_DMA_CHANNEL_6
701 * @arg @ref LL_DMA_CHANNEL_7 (*)
702 * @arg @ref LL_DMA_CHANNEL_8 (*)
703 * (*) Not on all G4 devices
704 * @retval Returned value can be one of the following values:
705 * @arg @ref LL_DMA_MODE_NORMAL
706 * @arg @ref LL_DMA_MODE_CIRCULAR
707 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Channel)708 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
709 {
710 uint32_t dma_base_addr = (uint32_t)DMAx;
711 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
712 DMA_CCR_CIRC));
713 }
714
715 /**
716 * @brief Set Peripheral increment mode.
717 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
718 * @param DMAx DMAx Instance
719 * @param Channel This parameter can be one of the following values:
720 * @arg @ref LL_DMA_CHANNEL_1
721 * @arg @ref LL_DMA_CHANNEL_2
722 * @arg @ref LL_DMA_CHANNEL_3
723 * @arg @ref LL_DMA_CHANNEL_4
724 * @arg @ref LL_DMA_CHANNEL_5
725 * @arg @ref LL_DMA_CHANNEL_6
726 * @arg @ref LL_DMA_CHANNEL_7 (*)
727 * @arg @ref LL_DMA_CHANNEL_8 (*)
728 * (*) Not on all G4 devices
729 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
730 * @arg @ref LL_DMA_PERIPH_INCREMENT
731 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
732 * @retval None
733 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)734 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
735 {
736 uint32_t dma_base_addr = (uint32_t)DMAx;
737 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PINC,
738 PeriphOrM2MSrcIncMode);
739 }
740
741 /**
742 * @brief Get Peripheral increment mode.
743 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
744 * @param DMAx DMAx Instance
745 * @param Channel This parameter can be one of the following values:
746 * @arg @ref LL_DMA_CHANNEL_1
747 * @arg @ref LL_DMA_CHANNEL_2
748 * @arg @ref LL_DMA_CHANNEL_3
749 * @arg @ref LL_DMA_CHANNEL_4
750 * @arg @ref LL_DMA_CHANNEL_5
751 * @arg @ref LL_DMA_CHANNEL_6
752 * @arg @ref LL_DMA_CHANNEL_7 (*)
753 * @arg @ref LL_DMA_CHANNEL_8 (*)
754 * (*) Not on all G4 devices
755 * @retval Returned value can be one of the following values:
756 * @arg @ref LL_DMA_PERIPH_INCREMENT
757 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
758 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel)759 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
760 {
761 uint32_t dma_base_addr = (uint32_t)DMAx;
762 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
763 DMA_CCR_PINC));
764 }
765
766 /**
767 * @brief Set Memory increment mode.
768 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
769 * @param DMAx DMAx Instance
770 * @param Channel This parameter can be one of the following values:
771 * @arg @ref LL_DMA_CHANNEL_1
772 * @arg @ref LL_DMA_CHANNEL_2
773 * @arg @ref LL_DMA_CHANNEL_3
774 * @arg @ref LL_DMA_CHANNEL_4
775 * @arg @ref LL_DMA_CHANNEL_5
776 * @arg @ref LL_DMA_CHANNEL_6
777 * @arg @ref LL_DMA_CHANNEL_7 (*)
778 * @arg @ref LL_DMA_CHANNEL_8 (*)
779 * (*) Not on all G4 devices
780 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
781 * @arg @ref LL_DMA_MEMORY_INCREMENT
782 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
783 * @retval None
784 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)785 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
786 {
787 uint32_t dma_base_addr = (uint32_t)DMAx;
788 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_MINC,
789 MemoryOrM2MDstIncMode);
790 }
791
792 /**
793 * @brief Get Memory increment mode.
794 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
795 * @param DMAx DMAx Instance
796 * @param Channel This parameter can be one of the following values:
797 * @arg @ref LL_DMA_CHANNEL_1
798 * @arg @ref LL_DMA_CHANNEL_2
799 * @arg @ref LL_DMA_CHANNEL_3
800 * @arg @ref LL_DMA_CHANNEL_4
801 * @arg @ref LL_DMA_CHANNEL_5
802 * @arg @ref LL_DMA_CHANNEL_6
803 * @arg @ref LL_DMA_CHANNEL_7 (*)
804 * @arg @ref LL_DMA_CHANNEL_8 (*)
805 * (*) Not on all G4 devices
806 * @retval Returned value can be one of the following values:
807 * @arg @ref LL_DMA_MEMORY_INCREMENT
808 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
809 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel)810 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
811 {
812 uint32_t dma_base_addr = (uint32_t)DMAx;
813 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
814 DMA_CCR_MINC));
815 }
816
817 /**
818 * @brief Set Peripheral size.
819 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
820 * @param DMAx DMAx Instance
821 * @param Channel This parameter can be one of the following values:
822 * @arg @ref LL_DMA_CHANNEL_1
823 * @arg @ref LL_DMA_CHANNEL_2
824 * @arg @ref LL_DMA_CHANNEL_3
825 * @arg @ref LL_DMA_CHANNEL_4
826 * @arg @ref LL_DMA_CHANNEL_5
827 * @arg @ref LL_DMA_CHANNEL_6
828 * @arg @ref LL_DMA_CHANNEL_7 (*)
829 * @arg @ref LL_DMA_CHANNEL_8 (*)
830 * (*) Not on all G4 devices
831 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
832 * @arg @ref LL_DMA_PDATAALIGN_BYTE
833 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
834 * @arg @ref LL_DMA_PDATAALIGN_WORD
835 * @retval None
836 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)837 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
838 {
839 uint32_t dma_base_addr = (uint32_t)DMAx;
840 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PSIZE,
841 PeriphOrM2MSrcDataSize);
842 }
843
844 /**
845 * @brief Get Peripheral size.
846 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
847 * @param DMAx DMAx Instance
848 * @param Channel This parameter can be one of the following values:
849 * @arg @ref LL_DMA_CHANNEL_1
850 * @arg @ref LL_DMA_CHANNEL_2
851 * @arg @ref LL_DMA_CHANNEL_3
852 * @arg @ref LL_DMA_CHANNEL_4
853 * @arg @ref LL_DMA_CHANNEL_5
854 * @arg @ref LL_DMA_CHANNEL_6
855 * @arg @ref LL_DMA_CHANNEL_7 (*)
856 * @arg @ref LL_DMA_CHANNEL_8 (*)
857 * (*) Not on all G4 devices
858 * @retval Returned value can be one of the following values:
859 * @arg @ref LL_DMA_PDATAALIGN_BYTE
860 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
861 * @arg @ref LL_DMA_PDATAALIGN_WORD
862 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel)863 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
864 {
865 uint32_t dma_base_addr = (uint32_t)DMAx;
866 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
867 DMA_CCR_PSIZE));
868 }
869
870 /**
871 * @brief Set Memory size.
872 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
873 * @param DMAx DMAx Instance
874 * @param Channel This parameter can be one of the following values:
875 * @arg @ref LL_DMA_CHANNEL_1
876 * @arg @ref LL_DMA_CHANNEL_2
877 * @arg @ref LL_DMA_CHANNEL_3
878 * @arg @ref LL_DMA_CHANNEL_4
879 * @arg @ref LL_DMA_CHANNEL_5
880 * @arg @ref LL_DMA_CHANNEL_6
881 * @arg @ref LL_DMA_CHANNEL_7 (*)
882 * @arg @ref LL_DMA_CHANNEL_8 (*)
883 * (*) Not on all G4 devices
884 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
885 * @arg @ref LL_DMA_MDATAALIGN_BYTE
886 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
887 * @arg @ref LL_DMA_MDATAALIGN_WORD
888 * @retval None
889 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)890 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
891 {
892 uint32_t dma_base_addr = (uint32_t)DMAx;
893 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_MSIZE,
894 MemoryOrM2MDstDataSize);
895 }
896
897 /**
898 * @brief Get Memory size.
899 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
900 * @param DMAx DMAx Instance
901 * @param Channel This parameter can be one of the following values:
902 * @arg @ref LL_DMA_CHANNEL_1
903 * @arg @ref LL_DMA_CHANNEL_2
904 * @arg @ref LL_DMA_CHANNEL_3
905 * @arg @ref LL_DMA_CHANNEL_4
906 * @arg @ref LL_DMA_CHANNEL_5
907 * @arg @ref LL_DMA_CHANNEL_6
908 * @arg @ref LL_DMA_CHANNEL_7 (*)
909 * @arg @ref LL_DMA_CHANNEL_8 (*)
910 * (*) Not on all G4 devices
911 * @retval Returned value can be one of the following values:
912 * @arg @ref LL_DMA_MDATAALIGN_BYTE
913 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
914 * @arg @ref LL_DMA_MDATAALIGN_WORD
915 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel)916 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
917 {
918 uint32_t dma_base_addr = (uint32_t)DMAx;
919 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
920 DMA_CCR_MSIZE));
921 }
922
923 /**
924 * @brief Set Channel priority level.
925 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
926 * @param DMAx DMAx Instance
927 * @param Channel This parameter can be one of the following values:
928 * @arg @ref LL_DMA_CHANNEL_1
929 * @arg @ref LL_DMA_CHANNEL_2
930 * @arg @ref LL_DMA_CHANNEL_3
931 * @arg @ref LL_DMA_CHANNEL_4
932 * @arg @ref LL_DMA_CHANNEL_5
933 * @arg @ref LL_DMA_CHANNEL_6
934 * @arg @ref LL_DMA_CHANNEL_7 (*)
935 * @arg @ref LL_DMA_CHANNEL_8 (*)
936 * (*) Not on all G4 devices
937 * @param Priority This parameter can be one of the following values:
938 * @arg @ref LL_DMA_PRIORITY_LOW
939 * @arg @ref LL_DMA_PRIORITY_MEDIUM
940 * @arg @ref LL_DMA_PRIORITY_HIGH
941 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
942 * @retval None
943 */
LL_DMA_SetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)944 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
945 {
946 uint32_t dma_base_addr = (uint32_t)DMAx;
947 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PL,
948 Priority);
949 }
950
951 /**
952 * @brief Get Channel priority level.
953 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
954 * @param DMAx DMAx Instance
955 * @param Channel This parameter can be one of the following values:
956 * @arg @ref LL_DMA_CHANNEL_1
957 * @arg @ref LL_DMA_CHANNEL_2
958 * @arg @ref LL_DMA_CHANNEL_3
959 * @arg @ref LL_DMA_CHANNEL_4
960 * @arg @ref LL_DMA_CHANNEL_5
961 * @arg @ref LL_DMA_CHANNEL_6
962 * @arg @ref LL_DMA_CHANNEL_7 (*)
963 * @arg @ref LL_DMA_CHANNEL_8 (*)
964 * (*) Not on all G4 devices
965 * @retval Returned value can be one of the following values:
966 * @arg @ref LL_DMA_PRIORITY_LOW
967 * @arg @ref LL_DMA_PRIORITY_MEDIUM
968 * @arg @ref LL_DMA_PRIORITY_HIGH
969 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
970 */
LL_DMA_GetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel)971 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
972 {
973 uint32_t dma_base_addr = (uint32_t)DMAx;
974 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
975 DMA_CCR_PL));
976 }
977
978 /**
979 * @brief Set Number of data to transfer.
980 * @note This action has no effect if
981 * channel is enabled.
982 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
983 * @param DMAx DMAx Instance
984 * @param Channel This parameter can be one of the following values:
985 * @arg @ref LL_DMA_CHANNEL_1
986 * @arg @ref LL_DMA_CHANNEL_2
987 * @arg @ref LL_DMA_CHANNEL_3
988 * @arg @ref LL_DMA_CHANNEL_4
989 * @arg @ref LL_DMA_CHANNEL_5
990 * @arg @ref LL_DMA_CHANNEL_6
991 * @arg @ref LL_DMA_CHANNEL_7 (*)
992 * @arg @ref LL_DMA_CHANNEL_8 (*)
993 * (*) Not on all G4 devices
994 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
995 * @retval None
996 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t NbData)997 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
998 {
999 uint32_t dma_base_addr = (uint32_t)DMAx;
1000 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CNDTR,
1001 DMA_CNDTR_NDT, NbData);
1002 }
1003
1004 /**
1005 * @brief Get Number of data to transfer.
1006 * @note Once the channel is enabled, the return value indicate the
1007 * remaining bytes to be transmitted.
1008 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
1009 * @param DMAx DMAx Instance
1010 * @param Channel This parameter can be one of the following values:
1011 * @arg @ref LL_DMA_CHANNEL_1
1012 * @arg @ref LL_DMA_CHANNEL_2
1013 * @arg @ref LL_DMA_CHANNEL_3
1014 * @arg @ref LL_DMA_CHANNEL_4
1015 * @arg @ref LL_DMA_CHANNEL_5
1016 * @arg @ref LL_DMA_CHANNEL_6
1017 * @arg @ref LL_DMA_CHANNEL_7 (*)
1018 * @arg @ref LL_DMA_CHANNEL_8 (*)
1019 * (*) Not on all G4 devices
1020 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1021 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Channel)1022 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
1023 {
1024 uint32_t dma_base_addr = (uint32_t)DMAx;
1025 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CNDTR,
1026 DMA_CNDTR_NDT));
1027 }
1028
1029 /**
1030 * @brief Configure the Source and Destination addresses.
1031 * @note This API must not be called when the DMA channel is enabled.
1032 * @note Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
1033 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
1034 * CMAR MA LL_DMA_ConfigAddresses
1035 * @param DMAx DMAx Instance
1036 * @param Channel This parameter can be one of the following values:
1037 * @arg @ref LL_DMA_CHANNEL_1
1038 * @arg @ref LL_DMA_CHANNEL_2
1039 * @arg @ref LL_DMA_CHANNEL_3
1040 * @arg @ref LL_DMA_CHANNEL_4
1041 * @arg @ref LL_DMA_CHANNEL_5
1042 * @arg @ref LL_DMA_CHANNEL_6
1043 * @arg @ref LL_DMA_CHANNEL_7 (*)
1044 * @arg @ref LL_DMA_CHANNEL_8 (*)
1045 * (*) Not on all G4 devices
1046 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1047 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1048 * @param Direction This parameter can be one of the following values:
1049 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1050 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1051 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1052 * @retval None
1053 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)1054 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
1055 uint32_t DstAddress, uint32_t Direction)
1056 {
1057 uint32_t dma_base_addr = (uint32_t)DMAx;
1058
1059 /* Direction Memory to Periph */
1060 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1061 {
1062 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, SrcAddress);
1063 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, DstAddress);
1064 }
1065 /* Direction Periph to Memory and Memory to Memory */
1066 else
1067 {
1068 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, SrcAddress);
1069 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, DstAddress);
1070 }
1071 }
1072
1073 /**
1074 * @brief Set the Memory address.
1075 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1076 * @note This API must not be called when the DMA channel is enabled.
1077 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
1078 * @param DMAx DMAx Instance
1079 * @param Channel This parameter can be one of the following values:
1080 * @arg @ref LL_DMA_CHANNEL_1
1081 * @arg @ref LL_DMA_CHANNEL_2
1082 * @arg @ref LL_DMA_CHANNEL_3
1083 * @arg @ref LL_DMA_CHANNEL_4
1084 * @arg @ref LL_DMA_CHANNEL_5
1085 * @arg @ref LL_DMA_CHANNEL_6
1086 * @arg @ref LL_DMA_CHANNEL_7 (*)
1087 * @arg @ref LL_DMA_CHANNEL_8 (*)
1088 * (*) Not on all G4 devices
1089 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1090 * @retval None
1091 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1092 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1093 {
1094 uint32_t dma_base_addr = (uint32_t)DMAx;
1095 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, MemoryAddress);
1096 }
1097
1098 /**
1099 * @brief Set the Peripheral address.
1100 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1101 * @note This API must not be called when the DMA channel is enabled.
1102 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
1103 * @param DMAx DMAx Instance
1104 * @param Channel This parameter can be one of the following values:
1105 * @arg @ref LL_DMA_CHANNEL_1
1106 * @arg @ref LL_DMA_CHANNEL_2
1107 * @arg @ref LL_DMA_CHANNEL_3
1108 * @arg @ref LL_DMA_CHANNEL_4
1109 * @arg @ref LL_DMA_CHANNEL_5
1110 * @arg @ref LL_DMA_CHANNEL_6
1111 * @arg @ref LL_DMA_CHANNEL_7 (*)
1112 * @arg @ref LL_DMA_CHANNEL_8 (*)
1113 * (*) Not on all G4 devices
1114 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1115 * @retval None
1116 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphAddress)1117 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1118 {
1119 uint32_t dma_base_addr = (uint32_t)DMAx;
1120 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, PeriphAddress);
1121 }
1122
1123 /**
1124 * @brief Get Memory address.
1125 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1126 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
1127 * @param DMAx DMAx Instance
1128 * @param Channel This parameter can be one of the following values:
1129 * @arg @ref LL_DMA_CHANNEL_1
1130 * @arg @ref LL_DMA_CHANNEL_2
1131 * @arg @ref LL_DMA_CHANNEL_3
1132 * @arg @ref LL_DMA_CHANNEL_4
1133 * @arg @ref LL_DMA_CHANNEL_5
1134 * @arg @ref LL_DMA_CHANNEL_6
1135 * @arg @ref LL_DMA_CHANNEL_7 (*)
1136 * @arg @ref LL_DMA_CHANNEL_8 (*)
1137 * (*) Not on all G4 devices
1138 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1139 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel)1140 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1141 {
1142 uint32_t dma_base_addr = (uint32_t)DMAx;
1143 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR));
1144 }
1145
1146 /**
1147 * @brief Get Peripheral address.
1148 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1149 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1150 * @param DMAx DMAx Instance
1151 * @param Channel This parameter can be one of the following values:
1152 * @arg @ref LL_DMA_CHANNEL_1
1153 * @arg @ref LL_DMA_CHANNEL_2
1154 * @arg @ref LL_DMA_CHANNEL_3
1155 * @arg @ref LL_DMA_CHANNEL_4
1156 * @arg @ref LL_DMA_CHANNEL_5
1157 * @arg @ref LL_DMA_CHANNEL_6
1158 * @arg @ref LL_DMA_CHANNEL_7 (*)
1159 * @arg @ref LL_DMA_CHANNEL_8 (*)
1160 * (*) Not on all G4 devices
1161 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1162 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel)1163 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1164 {
1165 uint32_t dma_base_addr = (uint32_t)DMAx;
1166 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR));
1167 }
1168
1169 /**
1170 * @brief Set the Memory to Memory Source address.
1171 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1172 * @note This API must not be called when the DMA channel is enabled.
1173 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1174 * @param DMAx DMAx Instance
1175 * @param Channel This parameter can be one of the following values:
1176 * @arg @ref LL_DMA_CHANNEL_1
1177 * @arg @ref LL_DMA_CHANNEL_2
1178 * @arg @ref LL_DMA_CHANNEL_3
1179 * @arg @ref LL_DMA_CHANNEL_4
1180 * @arg @ref LL_DMA_CHANNEL_5
1181 * @arg @ref LL_DMA_CHANNEL_6
1182 * @arg @ref LL_DMA_CHANNEL_7 (*)
1183 * @arg @ref LL_DMA_CHANNEL_8 (*)
1184 * (*) Not on all G4 devices
1185 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1186 * @retval None
1187 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1188 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1189 {
1190 uint32_t dma_base_addr = (uint32_t)DMAx;
1191 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, MemoryAddress);
1192 }
1193
1194 /**
1195 * @brief Set the Memory to Memory Destination address.
1196 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1197 * @note This API must not be called when the DMA channel is enabled.
1198 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1199 * @param DMAx DMAx Instance
1200 * @param Channel This parameter can be one of the following values:
1201 * @arg @ref LL_DMA_CHANNEL_1
1202 * @arg @ref LL_DMA_CHANNEL_2
1203 * @arg @ref LL_DMA_CHANNEL_3
1204 * @arg @ref LL_DMA_CHANNEL_4
1205 * @arg @ref LL_DMA_CHANNEL_5
1206 * @arg @ref LL_DMA_CHANNEL_6
1207 * @arg @ref LL_DMA_CHANNEL_7 (*)
1208 * @arg @ref LL_DMA_CHANNEL_8 (*)
1209 * (*) Not on all G4 devices
1210 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1211 * @retval None
1212 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1213 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1214 {
1215 uint32_t dma_base_addr = (uint32_t)DMAx;
1216 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, MemoryAddress);
1217 }
1218
1219 /**
1220 * @brief Get the Memory to Memory Source address.
1221 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1222 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1223 * @param DMAx DMAx Instance
1224 * @param Channel This parameter can be one of the following values:
1225 * @arg @ref LL_DMA_CHANNEL_1
1226 * @arg @ref LL_DMA_CHANNEL_2
1227 * @arg @ref LL_DMA_CHANNEL_3
1228 * @arg @ref LL_DMA_CHANNEL_4
1229 * @arg @ref LL_DMA_CHANNEL_5
1230 * @arg @ref LL_DMA_CHANNEL_6
1231 * @arg @ref LL_DMA_CHANNEL_7 (*)
1232 * @arg @ref LL_DMA_CHANNEL_8 (*)
1233 * (*) Not on all G4 devices
1234 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1235 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel)1236 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1237 {
1238 uint32_t dma_base_addr = (uint32_t)DMAx;
1239 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR));
1240 }
1241
1242 /**
1243 * @brief Get the Memory to Memory Destination address.
1244 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1245 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1246 * @param DMAx DMAx Instance
1247 * @param Channel This parameter can be one of the following values:
1248 * @arg @ref LL_DMA_CHANNEL_1
1249 * @arg @ref LL_DMA_CHANNEL_2
1250 * @arg @ref LL_DMA_CHANNEL_3
1251 * @arg @ref LL_DMA_CHANNEL_4
1252 * @arg @ref LL_DMA_CHANNEL_5
1253 * @arg @ref LL_DMA_CHANNEL_6
1254 * @arg @ref LL_DMA_CHANNEL_7 (*)
1255 * @arg @ref LL_DMA_CHANNEL_8 (*)
1256 * (*) Not on all G4 devices
1257 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1258 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel)1259 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1260 {
1261 uint32_t dma_base_addr = (uint32_t)DMAx;
1262 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR));
1263 }
1264
1265 /**
1266 * @brief Set DMA request for DMA instance on Channel x.
1267 * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
1268 * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
1269 * CSELR C2S LL_DMA_SetPeriphRequest\n
1270 * CSELR C3S LL_DMA_SetPeriphRequest\n
1271 * CSELR C4S LL_DMA_SetPeriphRequest\n
1272 * CSELR C5S LL_DMA_SetPeriphRequest\n
1273 * CSELR C6S LL_DMA_SetPeriphRequest\n
1274 * CSELR C7S LL_DMA_SetPeriphRequest
1275 * @param DMAx DMAx Instance
1276 * @param Channel This parameter can be one of the following values:
1277 * @arg @ref LL_DMA_CHANNEL_1
1278 * @arg @ref LL_DMA_CHANNEL_2
1279 * @arg @ref LL_DMA_CHANNEL_3
1280 * @arg @ref LL_DMA_CHANNEL_4
1281 * @arg @ref LL_DMA_CHANNEL_5
1282 * @arg @ref LL_DMA_CHANNEL_6
1283 * @arg @ref LL_DMA_CHANNEL_7 (*)
1284 * @arg @ref LL_DMA_CHANNEL_8 (*)
1285 * (*) Not on all G4 devices
1286 * @param PeriphRequest This parameter can be one of the following values:
1287 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1288 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1289 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1290 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1291 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1292 * @arg @ref LL_DMAMUX_REQ_ADC1
1293 * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
1294 * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
1295 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
1296 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
1297 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1298 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1299 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1300 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1301 * @arg @ref LL_DMAMUX_REQ_SPI3_RX
1302 * @arg @ref LL_DMAMUX_REQ_SPI3_TX
1303 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1304 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1305 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
1306 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
1307 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
1308 * @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
1309 * @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
1310 * @arg @ref LL_DMAMUX_REQ_I2C4_TX
1311 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1312 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1313 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1314 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1315 * @arg @ref LL_DMAMUX_REQ_USART3_RX
1316 * @arg @ref LL_DMAMUX_REQ_USART3_TX
1317 * @arg @ref LL_DMAMUX_REQ_UART4_RX
1318 * @arg @ref LL_DMAMUX_REQ_UART4_TX
1319 * @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
1320 * @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
1321 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1322 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1323 * @arg @ref LL_DMAMUX_REQ_ADC2
1324 * @arg @ref LL_DMAMUX_REQ_ADC3 (*)
1325 * @arg @ref LL_DMAMUX_REQ_ADC4 (*)
1326 * @arg @ref LL_DMAMUX_REQ_ADC5 (*)
1327 * @arg @ref LL_DMAMUX_REQ_QSPI (*)
1328 * @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
1329 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1330 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1331 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1332 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1333 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1334 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
1335 * @arg @ref LL_DMAMUX_REQ_TIM1_COM
1336 * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
1337 * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
1338 * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
1339 * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
1340 * @arg @ref LL_DMAMUX_REQ_TIM8_UP
1341 * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
1342 * @arg @ref LL_DMAMUX_REQ_TIM8_COM
1343 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1344 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1345 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1346 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1347 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1348 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
1349 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
1350 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
1351 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
1352 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
1353 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
1354 * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
1355 * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
1356 * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
1357 * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
1358 * @arg @ref LL_DMAMUX_REQ_TIM4_UP
1359 * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
1360 * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
1361 * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
1362 * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
1363 * @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
1364 * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
1365 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
1366 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
1367 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
1368 * @arg @ref LL_DMAMUX_REQ_TIM15_COM
1369 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1370 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1371 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1372 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1373 * @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
1374 * @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
1375 * @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
1376 * @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
1377 * @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
1378 * @arg @ref LL_DMAMUX_REQ_AES_IN
1379 * @arg @ref LL_DMAMUX_REQ_AES_OUT
1380 * @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
1381 * @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
1382 * @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
1383 * @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
1384 * @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
1385 * @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
1386 * @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
1387 * @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
1388 * @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
1389 * @arg @ref LL_DMAMUX_REQ_DAC3_CH1
1390 * @arg @ref LL_DMAMUX_REQ_DAC3_CH2
1391 * @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
1392 * @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
1393 * @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
1394 * @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
1395 * @arg @ref LL_DMAMUX_REQ_SAI1_A
1396 * @arg @ref LL_DMAMUX_REQ_SAI1_B
1397 * @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
1398 * @arg @ref LL_DMAMUX_REQ_FMAC_READ
1399 * @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
1400 * @arg @ref LL_DMAMUX_REQ_CORDIC_READ
1401 * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
1402 * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
1403 * (*) Not on all G4 devices
1404 * @retval None
1405 */
LL_DMA_SetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphRequest)1406 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
1407 {
1408 uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U);
1409 MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, PeriphRequest);
1410 }
1411
1412 /**
1413 * @brief Get DMA request for DMA instance on Channel x.
1414 * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
1415 * CSELR C2S LL_DMA_GetPeriphRequest\n
1416 * CSELR C3S LL_DMA_GetPeriphRequest\n
1417 * CSELR C4S LL_DMA_GetPeriphRequest\n
1418 * CSELR C5S LL_DMA_GetPeriphRequest\n
1419 * CSELR C6S LL_DMA_GetPeriphRequest\n
1420 * CSELR C7S LL_DMA_GetPeriphRequest
1421 * @param DMAx DMAx Instance
1422 * @param Channel This parameter can be one of the following values:
1423 * @arg @ref LL_DMA_CHANNEL_1
1424 * @arg @ref LL_DMA_CHANNEL_2
1425 * @arg @ref LL_DMA_CHANNEL_3
1426 * @arg @ref LL_DMA_CHANNEL_4
1427 * @arg @ref LL_DMA_CHANNEL_5
1428 * @arg @ref LL_DMA_CHANNEL_6
1429 * @arg @ref LL_DMA_CHANNEL_7 (*)
1430 * @arg @ref LL_DMA_CHANNEL_8 (*)
1431 * (*) Not on all G4 devices
1432 * @retval Returned value can be one of the following values:
1433 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1434 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1435 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1436 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1437 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1438 * @arg @ref LL_DMAMUX_REQ_ADC1
1439 * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
1440 * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
1441 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
1442 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
1443 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1444 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1445 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1446 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1447 * @arg @ref LL_DMAMUX_REQ_SPI3_RX
1448 * @arg @ref LL_DMAMUX_REQ_SPI3_TX
1449 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1450 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1451 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
1452 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
1453 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
1454 * @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
1455 * @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
1456 * @arg @ref LL_DMAMUX_REQ_I2C4_TX
1457 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1458 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1459 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1460 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1461 * @arg @ref LL_DMAMUX_REQ_USART3_RX
1462 * @arg @ref LL_DMAMUX_REQ_USART3_TX
1463 * @arg @ref LL_DMAMUX_REQ_UART4_RX
1464 * @arg @ref LL_DMAMUX_REQ_UART4_TX
1465 * @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
1466 * @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
1467 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1468 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1469 * @arg @ref LL_DMAMUX_REQ_ADC2
1470 * @arg @ref LL_DMAMUX_REQ_ADC3 (*)
1471 * @arg @ref LL_DMAMUX_REQ_ADC4 (*)
1472 * @arg @ref LL_DMAMUX_REQ_ADC5 (*)
1473 * @arg @ref LL_DMAMUX_REQ_QSPI (*)
1474 * @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
1475 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1476 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1477 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1478 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1479 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1480 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
1481 * @arg @ref LL_DMAMUX_REQ_TIM1_COM
1482 * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
1483 * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
1484 * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
1485 * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
1486 * @arg @ref LL_DMAMUX_REQ_TIM8_UP
1487 * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
1488 * @arg @ref LL_DMAMUX_REQ_TIM8_COM
1489 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1490 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1491 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1492 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1493 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1494 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
1495 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
1496 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
1497 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
1498 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
1499 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
1500 * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
1501 * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
1502 * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
1503 * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
1504 * @arg @ref LL_DMAMUX_REQ_TIM4_UP
1505 * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
1506 * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
1507 * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
1508 * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
1509 * @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
1510 * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
1511 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
1512 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
1513 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
1514 * @arg @ref LL_DMAMUX_REQ_TIM15_COM
1515 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1516 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1517 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1518 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1519 * @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
1520 * @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
1521 * @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
1522 * @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
1523 * @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
1524 * @arg @ref LL_DMAMUX_REQ_AES_IN
1525 * @arg @ref LL_DMAMUX_REQ_AES_OUT
1526 * @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
1527 * @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
1528 * @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
1529 * @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
1530 * @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
1531 * @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
1532 * @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
1533 * @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
1534 * @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
1535 * @arg @ref LL_DMAMUX_REQ_DAC3_CH1
1536 * @arg @ref LL_DMAMUX_REQ_DAC3_CH2
1537 * @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
1538 * @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
1539 * @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
1540 * @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
1541 * @arg @ref LL_DMAMUX_REQ_SAI1_A
1542 * @arg @ref LL_DMAMUX_REQ_SAI1_B
1543 * @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
1544 * @arg @ref LL_DMAMUX_REQ_FMAC_READ
1545 * @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
1546 * @arg @ref LL_DMAMUX_REQ_CORDIC_READ
1547 * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
1548 * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
1549 * (*) Not on all G4 devices
1550 */
LL_DMA_GetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel)1551 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
1552 {
1553 uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U);
1554 return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID));
1555 }
1556
1557 /**
1558 * @}
1559 */
1560
1561 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1562 * @{
1563 */
1564
1565 /**
1566 * @brief Get Channel 1 global interrupt flag.
1567 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1568 * @param DMAx DMAx Instance
1569 * @retval State of bit (1 or 0).
1570 */
LL_DMA_IsActiveFlag_GI1(DMA_TypeDef * DMAx)1571 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1572 {
1573 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
1574 }
1575
1576 /**
1577 * @brief Get Channel 2 global interrupt flag.
1578 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1579 * @param DMAx DMAx Instance
1580 * @retval State of bit (1 or 0).
1581 */
LL_DMA_IsActiveFlag_GI2(DMA_TypeDef * DMAx)1582 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1583 {
1584 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
1585 }
1586
1587 /**
1588 * @brief Get Channel 3 global interrupt flag.
1589 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1590 * @param DMAx DMAx Instance
1591 * @retval State of bit (1 or 0).
1592 */
LL_DMA_IsActiveFlag_GI3(DMA_TypeDef * DMAx)1593 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1594 {
1595 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
1596 }
1597
1598 /**
1599 * @brief Get Channel 4 global interrupt flag.
1600 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1601 * @param DMAx DMAx Instance
1602 * @retval State of bit (1 or 0).
1603 */
LL_DMA_IsActiveFlag_GI4(DMA_TypeDef * DMAx)1604 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1605 {
1606 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
1607 }
1608
1609 /**
1610 * @brief Get Channel 5 global interrupt flag.
1611 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1612 * @param DMAx DMAx Instance
1613 * @retval State of bit (1 or 0).
1614 */
LL_DMA_IsActiveFlag_GI5(DMA_TypeDef * DMAx)1615 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1616 {
1617 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
1618 }
1619
1620 /**
1621 * @brief Get Channel 6 global interrupt flag.
1622 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
1623 * @param DMAx DMAx Instance
1624 * @retval State of bit (1 or 0).
1625 */
LL_DMA_IsActiveFlag_GI6(DMA_TypeDef * DMAx)1626 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
1627 {
1628 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
1629 }
1630
1631 #if defined (DMA1_Channel7)
1632 /**
1633 * @brief Get Channel 7 global interrupt flag.
1634 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
1635 * @param DMAx DMAx Instance
1636 * @retval State of bit (1 or 0).
1637 */
LL_DMA_IsActiveFlag_GI7(DMA_TypeDef * DMAx)1638 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
1639 {
1640 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
1641 }
1642 #endif /* DMA1_Channel7 */
1643
1644 #if defined (DMA1_Channel8)
1645 /**
1646 * @brief Get Channel 8 global interrupt flag.
1647 * @rmtoll ISR GIF8 LL_DMA_IsActiveFlag_GI8
1648 * @param DMAx DMAx Instance
1649 * @retval State of bit (1 or 0).
1650 */
LL_DMA_IsActiveFlag_GI8(DMA_TypeDef * DMAx)1651 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx)
1652 {
1653 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF8) == (DMA_ISR_GIF8)) ? 1UL : 0UL);
1654 }
1655 #endif /* DMA1_Channel8 */
1656
1657 /**
1658 * @brief Get Channel 1 transfer complete flag.
1659 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1660 * @param DMAx DMAx Instance
1661 * @retval State of bit (1 or 0).
1662 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1663 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1664 {
1665 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
1666 }
1667
1668 /**
1669 * @brief Get Channel 2 transfer complete flag.
1670 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1671 * @param DMAx DMAx Instance
1672 * @retval State of bit (1 or 0).
1673 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1674 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1675 {
1676 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
1677 }
1678
1679 /**
1680 * @brief Get Channel 3 transfer complete flag.
1681 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1682 * @param DMAx DMAx Instance
1683 * @retval State of bit (1 or 0).
1684 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1685 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1686 {
1687 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
1688 }
1689
1690 /**
1691 * @brief Get Channel 4 transfer complete flag.
1692 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1693 * @param DMAx DMAx Instance
1694 * @retval State of bit (1 or 0).
1695 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1696 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1697 {
1698 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
1699 }
1700
1701 /**
1702 * @brief Get Channel 5 transfer complete flag.
1703 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1704 * @param DMAx DMAx Instance
1705 * @retval State of bit (1 or 0).
1706 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1707 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1708 {
1709 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
1710 }
1711
1712 /**
1713 * @brief Get Channel 6 transfer complete flag.
1714 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
1715 * @param DMAx DMAx Instance
1716 * @retval State of bit (1 or 0).
1717 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)1718 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1719 {
1720 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
1721 }
1722
1723 #if defined (DMA1_Channel7)
1724 /**
1725 * @brief Get Channel 7 transfer complete flag.
1726 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
1727 * @param DMAx DMAx Instance
1728 * @retval State of bit (1 or 0).
1729 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)1730 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1731 {
1732 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
1733 }
1734 #endif /* DMA1_Channel7 */
1735
1736 #if defined (DMA1_Channel8)
1737 /**
1738 * @brief Get Channel 8 transfer complete flag.
1739 * @rmtoll ISR TCIF8 LL_DMA_IsActiveFlag_TC8
1740 * @param DMAx DMAx Instance
1741 * @retval State of bit (1 or 0).
1742 */
LL_DMA_IsActiveFlag_TC8(DMA_TypeDef * DMAx)1743 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx)
1744 {
1745 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF8) == (DMA_ISR_TCIF8)) ? 1UL : 0UL);
1746 }
1747 #endif /* DMA1_Channel8 */
1748
1749 /**
1750 * @brief Get Channel 1 half transfer flag.
1751 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1752 * @param DMAx DMAx Instance
1753 * @retval State of bit (1 or 0).
1754 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1755 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1756 {
1757 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
1758 }
1759
1760 /**
1761 * @brief Get Channel 2 half transfer flag.
1762 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1763 * @param DMAx DMAx Instance
1764 * @retval State of bit (1 or 0).
1765 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1766 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1767 {
1768 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
1769 }
1770
1771 /**
1772 * @brief Get Channel 3 half transfer flag.
1773 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1774 * @param DMAx DMAx Instance
1775 * @retval State of bit (1 or 0).
1776 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1777 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1778 {
1779 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
1780 }
1781
1782 /**
1783 * @brief Get Channel 4 half transfer flag.
1784 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1785 * @param DMAx DMAx Instance
1786 * @retval State of bit (1 or 0).
1787 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1788 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1789 {
1790 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
1791 }
1792
1793 /**
1794 * @brief Get Channel 5 half transfer flag.
1795 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1796 * @param DMAx DMAx Instance
1797 * @retval State of bit (1 or 0).
1798 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1799 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1800 {
1801 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
1802 }
1803
1804 /**
1805 * @brief Get Channel 6 half transfer flag.
1806 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
1807 * @param DMAx DMAx Instance
1808 * @retval State of bit (1 or 0).
1809 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1810 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1811 {
1812 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
1813 }
1814
1815 #if defined (DMA1_Channel8)
1816 /**
1817 * @brief Get Channel 7 half transfer flag.
1818 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
1819 * @param DMAx DMAx Instance
1820 * @retval State of bit (1 or 0).
1821 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)1822 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1823 {
1824 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
1825 }
1826 #endif /* DMA1_Channel7 */
1827
1828 #if defined (DMA1_Channel8)
1829 /**
1830 * @brief Get Channel 8 half transfer flag.
1831 * @rmtoll ISR HTIF8 LL_DMA_IsActiveFlag_HT8
1832 * @param DMAx DMAx Instance
1833 * @retval State of bit (1 or 0).
1834 */
LL_DMA_IsActiveFlag_HT8(DMA_TypeDef * DMAx)1835 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx)
1836 {
1837 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF8) == (DMA_ISR_HTIF8)) ? 1UL : 0UL);
1838 }
1839 #endif /* DMA1_Channel8 */
1840
1841 /**
1842 * @brief Get Channel 1 transfer error flag.
1843 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1844 * @param DMAx DMAx Instance
1845 * @retval State of bit (1 or 0).
1846 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1847 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1848 {
1849 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
1850 }
1851
1852 /**
1853 * @brief Get Channel 2 transfer error flag.
1854 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1855 * @param DMAx DMAx Instance
1856 * @retval State of bit (1 or 0).
1857 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1858 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1859 {
1860 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
1861 }
1862
1863 /**
1864 * @brief Get Channel 3 transfer error flag.
1865 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1866 * @param DMAx DMAx Instance
1867 * @retval State of bit (1 or 0).
1868 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1869 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1870 {
1871 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
1872 }
1873
1874 /**
1875 * @brief Get Channel 4 transfer error flag.
1876 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1877 * @param DMAx DMAx Instance
1878 * @retval State of bit (1 or 0).
1879 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1880 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1881 {
1882 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
1883 }
1884
1885 /**
1886 * @brief Get Channel 5 transfer error flag.
1887 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1888 * @param DMAx DMAx Instance
1889 * @retval State of bit (1 or 0).
1890 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1891 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1892 {
1893 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
1894 }
1895
1896 /**
1897 * @brief Get Channel 6 transfer error flag.
1898 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
1899 * @param DMAx DMAx Instance
1900 * @retval State of bit (1 or 0).
1901 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)1902 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1903 {
1904 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
1905 }
1906
1907 #if defined (DMA1_Channel7)
1908 /**
1909 * @brief Get Channel 7 transfer error flag.
1910 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
1911 * @param DMAx DMAx Instance
1912 * @retval State of bit (1 or 0).
1913 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)1914 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1915 {
1916 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
1917 }
1918 #endif /* DMA1_Channel7 */
1919
1920 #if defined (DMA1_Channel8)
1921 /**
1922 * @brief Get Channel 8 transfer error flag.
1923 * @rmtoll ISR TEIF8 LL_DMA_IsActiveFlag_TE8
1924 * @param DMAx DMAx Instance
1925 * @retval State of bit (1 or 0).
1926 */
LL_DMA_IsActiveFlag_TE8(DMA_TypeDef * DMAx)1927 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx)
1928 {
1929 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF8) == (DMA_ISR_TEIF8)) ? 1UL : 0UL);
1930 }
1931 #endif /* DMA1_Channel8 */
1932
1933 /**
1934 * @brief Clear Channel 1 global interrupt flag.
1935 * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
1936 Instead clear specific flags transfer complete, half transfer & transfer
1937 error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
1938 LL_DMA_ClearFlag_TE1. bug id 2.3.1 in Product Errata Sheet.
1939 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1940 * @param DMAx DMAx Instance
1941 * @retval None
1942 */
LL_DMA_ClearFlag_GI1(DMA_TypeDef * DMAx)1943 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1944 {
1945 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1946 }
1947
1948 /**
1949 * @brief Clear Channel 2 global interrupt flag.
1950 * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
1951 Instead clear specific flags transfer complete, half transfer & transfer
1952 error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
1953 LL_DMA_ClearFlag_TE2. bug id 2.3.1 in Product Errata Sheet.
1954 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1955 * @param DMAx DMAx Instance
1956 * @retval None
1957 */
LL_DMA_ClearFlag_GI2(DMA_TypeDef * DMAx)1958 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1959 {
1960 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1961 }
1962
1963 /**
1964 * @brief Clear Channel 3 global interrupt flag.
1965 * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
1966 Instead clear specific flags transfer complete, half transfer & transfer
1967 error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
1968 LL_DMA_ClearFlag_TE3. bug id 2.3.1 in Product Errata Sheet.
1969 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1970 * @param DMAx DMAx Instance
1971 * @retval None
1972 */
LL_DMA_ClearFlag_GI3(DMA_TypeDef * DMAx)1973 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1974 {
1975 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1976 }
1977
1978 /**
1979 * @brief Clear Channel 4 global interrupt flag.
1980 * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
1981 Instead clear specific flags transfer complete, half transfer & transfer
1982 error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
1983 LL_DMA_ClearFlag_TE4. bug id 2.3.1 in Product Errata Sheet.
1984 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1985 * @param DMAx DMAx Instance
1986 * @retval None
1987 */
LL_DMA_ClearFlag_GI4(DMA_TypeDef * DMAx)1988 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1989 {
1990 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
1991 }
1992
1993 /**
1994 * @brief Clear Channel 5 global interrupt flag.
1995 * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
1996 Instead clear specific flags transfer complete, half transfer & transfer
1997 error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
1998 LL_DMA_ClearFlag_TE5. bug id 2.3.1 in Product Errata Sheet.
1999 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
2000 * @param DMAx DMAx Instance
2001 * @retval None
2002 */
LL_DMA_ClearFlag_GI5(DMA_TypeDef * DMAx)2003 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
2004 {
2005 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
2006 }
2007
2008 /**
2009 * @brief Clear Channel 6 global interrupt flag.
2010 * @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
2011 Instead clear specific flags transfer complete, half transfer & transfer
2012 error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
2013 LL_DMA_ClearFlag_TE6. bug id 2.3.1 in Product Errata Sheet.
2014 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
2015 * @param DMAx DMAx Instance
2016 * @retval None
2017 */
LL_DMA_ClearFlag_GI6(DMA_TypeDef * DMAx)2018 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
2019 {
2020 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
2021 }
2022
2023 #if defined (DMA1_Channel7)
2024 /**
2025 * @brief Clear Channel 7 global interrupt flag.
2026 * @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
2027 Instead clear specific flags transfer complete, half transfer & transfer
2028 error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
2029 LL_DMA_ClearFlag_TE7. bug id 2.3.1 in Product Errata Sheet.
2030 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
2031 * @param DMAx DMAx Instance
2032 * @retval None
2033 */
LL_DMA_ClearFlag_GI7(DMA_TypeDef * DMAx)2034 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
2035 {
2036 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
2037 }
2038 #endif /* DMA1_Channel7 */
2039
2040 #if defined (DMA1_Channel8)
2041 /**
2042 * @brief Clear Channel 8 global interrupt flag.
2043 * @note Do not Clear Channel 8 global interrupt flag when the channel in ON.
2044 Instead clear specific flags transfer complete, half transfer & transfer
2045 error flag with LL_DMA_ClearFlag_TC8, LL_DMA_ClearFlag_HT8,
2046 LL_DMA_ClearFlag_TE8. bug id 2.3.1 in Product Errata Sheet.
2047 * @rmtoll IFCR CGIF8 LL_DMA_ClearFlag_GI8
2048 * @param DMAx DMAx Instance
2049 * @retval None
2050 */
LL_DMA_ClearFlag_GI8(DMA_TypeDef * DMAx)2051 __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx)
2052 {
2053 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF8);
2054 }
2055 #endif /* DMA1_Channel8 */
2056
2057 /**
2058 * @brief Clear Channel 1 transfer complete flag.
2059 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
2060 * @param DMAx DMAx Instance
2061 * @retval None
2062 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)2063 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
2064 {
2065 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
2066 }
2067
2068 /**
2069 * @brief Clear Channel 2 transfer complete flag.
2070 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
2071 * @param DMAx DMAx Instance
2072 * @retval None
2073 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)2074 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
2075 {
2076 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
2077 }
2078
2079 /**
2080 * @brief Clear Channel 3 transfer complete flag.
2081 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
2082 * @param DMAx DMAx Instance
2083 * @retval None
2084 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)2085 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
2086 {
2087 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
2088 }
2089
2090 /**
2091 * @brief Clear Channel 4 transfer complete flag.
2092 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
2093 * @param DMAx DMAx Instance
2094 * @retval None
2095 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)2096 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
2097 {
2098 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
2099 }
2100
2101 /**
2102 * @brief Clear Channel 5 transfer complete flag.
2103 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
2104 * @param DMAx DMAx Instance
2105 * @retval None
2106 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)2107 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
2108 {
2109 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
2110 }
2111
2112 /**
2113 * @brief Clear Channel 6 transfer complete flag.
2114 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
2115 * @param DMAx DMAx Instance
2116 * @retval None
2117 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)2118 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
2119 {
2120 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
2121 }
2122
2123 #if defined (DMA1_Channel7)
2124 /**
2125 * @brief Clear Channel 7 transfer complete flag.
2126 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
2127 * @param DMAx DMAx Instance
2128 * @retval None
2129 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)2130 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
2131 {
2132 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
2133 }
2134 #endif /* DMA1_Channel7 */
2135
2136 #if defined (DMA1_Channel8)
2137 /**
2138 * @brief Clear Channel 8 transfer complete flag.
2139 * @rmtoll IFCR CTCIF8 LL_DMA_ClearFlag_TC8
2140 * @param DMAx DMAx Instance
2141 * @retval None
2142 */
LL_DMA_ClearFlag_TC8(DMA_TypeDef * DMAx)2143 __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx)
2144 {
2145 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF8);
2146 }
2147 #endif /* DMA1_Channel8 */
2148
2149 /**
2150 * @brief Clear Channel 1 half transfer flag.
2151 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
2152 * @param DMAx DMAx Instance
2153 * @retval None
2154 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)2155 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
2156 {
2157 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
2158 }
2159
2160 /**
2161 * @brief Clear Channel 2 half transfer flag.
2162 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
2163 * @param DMAx DMAx Instance
2164 * @retval None
2165 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)2166 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
2167 {
2168 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
2169 }
2170
2171 /**
2172 * @brief Clear Channel 3 half transfer flag.
2173 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
2174 * @param DMAx DMAx Instance
2175 * @retval None
2176 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)2177 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
2178 {
2179 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
2180 }
2181
2182 /**
2183 * @brief Clear Channel 4 half transfer flag.
2184 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
2185 * @param DMAx DMAx Instance
2186 * @retval None
2187 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)2188 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
2189 {
2190 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
2191 }
2192
2193 /**
2194 * @brief Clear Channel 5 half transfer flag.
2195 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
2196 * @param DMAx DMAx Instance
2197 * @retval None
2198 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)2199 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
2200 {
2201 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
2202 }
2203
2204 /**
2205 * @brief Clear Channel 6 half transfer flag.
2206 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
2207 * @param DMAx DMAx Instance
2208 * @retval None
2209 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)2210 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
2211 {
2212 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
2213 }
2214
2215 #if defined (DMA1_Channel7)
2216 /**
2217 * @brief Clear Channel 7 half transfer flag.
2218 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
2219 * @param DMAx DMAx Instance
2220 * @retval None
2221 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)2222 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
2223 {
2224 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
2225 }
2226 #endif /* DMA1_Channel7 */
2227
2228 #if defined (DMA1_Channel8)
2229 /**
2230 * @brief Clear Channel 8 half transfer flag.
2231 * @rmtoll IFCR CHTIF8 LL_DMA_ClearFlag_HT8
2232 * @param DMAx DMAx Instance
2233 * @retval None
2234 */
LL_DMA_ClearFlag_HT8(DMA_TypeDef * DMAx)2235 __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx)
2236 {
2237 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF8);
2238 }
2239 #endif /* DMA1_Channel8 */
2240
2241 /**
2242 * @brief Clear Channel 1 transfer error flag.
2243 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
2244 * @param DMAx DMAx Instance
2245 * @retval None
2246 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)2247 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
2248 {
2249 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
2250 }
2251
2252 /**
2253 * @brief Clear Channel 2 transfer error flag.
2254 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
2255 * @param DMAx DMAx Instance
2256 * @retval None
2257 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)2258 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
2259 {
2260 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
2261 }
2262
2263 /**
2264 * @brief Clear Channel 3 transfer error flag.
2265 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
2266 * @param DMAx DMAx Instance
2267 * @retval None
2268 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)2269 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
2270 {
2271 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
2272 }
2273
2274 /**
2275 * @brief Clear Channel 4 transfer error flag.
2276 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
2277 * @param DMAx DMAx Instance
2278 * @retval None
2279 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)2280 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2281 {
2282 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
2283 }
2284
2285 /**
2286 * @brief Clear Channel 5 transfer error flag.
2287 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
2288 * @param DMAx DMAx Instance
2289 * @retval None
2290 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)2291 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2292 {
2293 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
2294 }
2295
2296 /**
2297 * @brief Clear Channel 6 transfer error flag.
2298 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
2299 * @param DMAx DMAx Instance
2300 * @retval None
2301 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)2302 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2303 {
2304 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
2305 }
2306
2307 #if defined (DMA1_Channel7)
2308 /**
2309 * @brief Clear Channel 7 transfer error flag.
2310 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
2311 * @param DMAx DMAx Instance
2312 * @retval None
2313 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)2314 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2315 {
2316 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
2317 }
2318 #endif /* DMA1_Channel7 */
2319
2320 #if defined (DMA1_Channel8)
2321 /**
2322 * @brief Clear Channel 8 transfer error flag.
2323 * @rmtoll IFCR CTEIF8 LL_DMA_ClearFlag_TE8
2324 * @param DMAx DMAx Instance
2325 * @retval None
2326 */
LL_DMA_ClearFlag_TE8(DMA_TypeDef * DMAx)2327 __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx)
2328 {
2329 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF8);
2330 }
2331 #endif /* DMA1_Channel8 */
2332
2333 /**
2334 * @}
2335 */
2336
2337 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2338 * @{
2339 */
2340 /**
2341 * @brief Enable Transfer complete interrupt.
2342 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
2343 * @param DMAx DMAx Instance
2344 * @param Channel This parameter can be one of the following values:
2345 * @arg @ref LL_DMA_CHANNEL_1
2346 * @arg @ref LL_DMA_CHANNEL_2
2347 * @arg @ref LL_DMA_CHANNEL_3
2348 * @arg @ref LL_DMA_CHANNEL_4
2349 * @arg @ref LL_DMA_CHANNEL_5
2350 * @arg @ref LL_DMA_CHANNEL_6
2351 * @arg @ref LL_DMA_CHANNEL_7 (*)
2352 * @arg @ref LL_DMA_CHANNEL_8 (*)
2353 * (*) Not on all G4 devices
2354 * @retval None
2355 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2356 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2357 {
2358 uint32_t dma_base_addr = (uint32_t)DMAx;
2359 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TCIE);
2360 }
2361
2362 /**
2363 * @brief Enable Half transfer interrupt.
2364 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
2365 * @param DMAx DMAx Instance
2366 * @param Channel This parameter can be one of the following values:
2367 * @arg @ref LL_DMA_CHANNEL_1
2368 * @arg @ref LL_DMA_CHANNEL_2
2369 * @arg @ref LL_DMA_CHANNEL_3
2370 * @arg @ref LL_DMA_CHANNEL_4
2371 * @arg @ref LL_DMA_CHANNEL_5
2372 * @arg @ref LL_DMA_CHANNEL_6
2373 * @arg @ref LL_DMA_CHANNEL_7 (*)
2374 * @arg @ref LL_DMA_CHANNEL_8 (*)
2375 * (*) Not on all G4 devices
2376 * @retval None
2377 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2378 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2379 {
2380 uint32_t dma_base_addr = (uint32_t)DMAx;
2381 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_HTIE);
2382 }
2383
2384 /**
2385 * @brief Enable Transfer error interrupt.
2386 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
2387 * @param DMAx DMAx Instance
2388 * @param Channel This parameter can be one of the following values:
2389 * @arg @ref LL_DMA_CHANNEL_1
2390 * @arg @ref LL_DMA_CHANNEL_2
2391 * @arg @ref LL_DMA_CHANNEL_3
2392 * @arg @ref LL_DMA_CHANNEL_4
2393 * @arg @ref LL_DMA_CHANNEL_5
2394 * @arg @ref LL_DMA_CHANNEL_6
2395 * @arg @ref LL_DMA_CHANNEL_7 (*)
2396 * @arg @ref LL_DMA_CHANNEL_8 (*)
2397 * (*) Not on all G4 devices
2398 * @retval None
2399 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2400 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2401 {
2402 uint32_t dma_base_addr = (uint32_t)DMAx;
2403 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TEIE);
2404 }
2405
2406 /**
2407 * @brief Disable Transfer complete interrupt.
2408 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
2409 * @param DMAx DMAx Instance
2410 * @param Channel This parameter can be one of the following values:
2411 * @arg @ref LL_DMA_CHANNEL_1
2412 * @arg @ref LL_DMA_CHANNEL_2
2413 * @arg @ref LL_DMA_CHANNEL_3
2414 * @arg @ref LL_DMA_CHANNEL_4
2415 * @arg @ref LL_DMA_CHANNEL_5
2416 * @arg @ref LL_DMA_CHANNEL_6
2417 * @arg @ref LL_DMA_CHANNEL_7 (*)
2418 * @arg @ref LL_DMA_CHANNEL_8 (*)
2419 * (*) Not on all G4 devices
2420 * @retval None
2421 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2422 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2423 {
2424 uint32_t dma_base_addr = (uint32_t)DMAx;
2425 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TCIE);
2426 }
2427
2428 /**
2429 * @brief Disable Half transfer interrupt.
2430 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
2431 * @param DMAx DMAx Instance
2432 * @param Channel This parameter can be one of the following values:
2433 * @arg @ref LL_DMA_CHANNEL_1
2434 * @arg @ref LL_DMA_CHANNEL_2
2435 * @arg @ref LL_DMA_CHANNEL_3
2436 * @arg @ref LL_DMA_CHANNEL_4
2437 * @arg @ref LL_DMA_CHANNEL_5
2438 * @arg @ref LL_DMA_CHANNEL_6
2439 * @arg @ref LL_DMA_CHANNEL_7 (*)
2440 * @arg @ref LL_DMA_CHANNEL_8 (*)
2441 * (*) Not on all G4 devices
2442 * @retval None
2443 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2444 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2445 {
2446 uint32_t dma_base_addr = (uint32_t)DMAx;
2447 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_HTIE);
2448 }
2449
2450 /**
2451 * @brief Disable Transfer error interrupt.
2452 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
2453 * @param DMAx DMAx Instance
2454 * @param Channel This parameter can be one of the following values:
2455 * @arg @ref LL_DMA_CHANNEL_1
2456 * @arg @ref LL_DMA_CHANNEL_2
2457 * @arg @ref LL_DMA_CHANNEL_3
2458 * @arg @ref LL_DMA_CHANNEL_4
2459 * @arg @ref LL_DMA_CHANNEL_5
2460 * @arg @ref LL_DMA_CHANNEL_6
2461 * @arg @ref LL_DMA_CHANNEL_7 (*)
2462 * @arg @ref LL_DMA_CHANNEL_8 (*)
2463 * (*) Not on all G4 devices
2464 * @retval None
2465 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2466 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2467 {
2468 uint32_t dma_base_addr = (uint32_t)DMAx;
2469 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TEIE);
2470 }
2471
2472 /**
2473 * @brief Check if Transfer complete Interrupt is enabled.
2474 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
2475 * @param DMAx DMAx Instance
2476 * @param Channel This parameter can be one of the following values:
2477 * @arg @ref LL_DMA_CHANNEL_1
2478 * @arg @ref LL_DMA_CHANNEL_2
2479 * @arg @ref LL_DMA_CHANNEL_3
2480 * @arg @ref LL_DMA_CHANNEL_4
2481 * @arg @ref LL_DMA_CHANNEL_5
2482 * @arg @ref LL_DMA_CHANNEL_6
2483 * @arg @ref LL_DMA_CHANNEL_7 (*)
2484 * @arg @ref LL_DMA_CHANNEL_8 (*)
2485 * (*) Not on all G4 devices
2486 * @retval State of bit (1 or 0).
2487 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2488 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2489 {
2490 uint32_t dma_base_addr = (uint32_t)DMAx;
2491 return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
2492 DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
2493 }
2494
2495 /**
2496 * @brief Check if Half transfer Interrupt is enabled.
2497 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
2498 * @param DMAx DMAx Instance
2499 * @param Channel This parameter can be one of the following values:
2500 * @arg @ref LL_DMA_CHANNEL_1
2501 * @arg @ref LL_DMA_CHANNEL_2
2502 * @arg @ref LL_DMA_CHANNEL_3
2503 * @arg @ref LL_DMA_CHANNEL_4
2504 * @arg @ref LL_DMA_CHANNEL_5
2505 * @arg @ref LL_DMA_CHANNEL_6
2506 * @arg @ref LL_DMA_CHANNEL_7 (*)
2507 * @arg @ref LL_DMA_CHANNEL_8 (*)
2508 * (*) Not on all G4 devices
2509 * @retval State of bit (1 or 0).
2510 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2511 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2512 {
2513 uint32_t dma_base_addr = (uint32_t)DMAx;
2514 return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
2515 DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
2516 }
2517
2518 /**
2519 * @brief Check if Transfer error Interrupt is enabled.
2520 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
2521 * @param DMAx DMAx Instance
2522 * @param Channel This parameter can be one of the following values:
2523 * @arg @ref LL_DMA_CHANNEL_1
2524 * @arg @ref LL_DMA_CHANNEL_2
2525 * @arg @ref LL_DMA_CHANNEL_3
2526 * @arg @ref LL_DMA_CHANNEL_4
2527 * @arg @ref LL_DMA_CHANNEL_5
2528 * @arg @ref LL_DMA_CHANNEL_6
2529 * @arg @ref LL_DMA_CHANNEL_7 (*)
2530 * @arg @ref LL_DMA_CHANNEL_8 (*)
2531 * (*) Not on all G4 devices
2532 * @retval State of bit (1 or 0).
2533 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2534 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2535 {
2536 uint32_t dma_base_addr = (uint32_t)DMAx;
2537 return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
2538 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
2539 }
2540
2541 /**
2542 * @}
2543 */
2544
2545 #if defined(USE_FULL_LL_DRIVER)
2546 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2547 * @{
2548 */
2549
2550 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
2551 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
2552 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2553
2554 /**
2555 * @}
2556 */
2557 #endif /* USE_FULL_LL_DRIVER */
2558
2559 /**
2560 * @}
2561 */
2562
2563 /**
2564 * @}
2565 */
2566
2567 #endif /* DMA1 || DMA2 */
2568
2569 /**
2570 * @}
2571 */
2572
2573 #ifdef __cplusplus
2574 }
2575 #endif
2576
2577 #endif /* __STM32G4xx_LL_DMA_H */
2578
2579
