1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32G4xx_LL_DAC_H
21 #define STM32G4xx_LL_DAC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g4xx.h"
29
30 /** @addtogroup STM32G4xx_LL_Driver
31 * @{
32 */
33
34 #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
35
36 /** @defgroup DAC_LL DAC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45 * @{
46 */
47
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR, STMODR */
51 /* - channel bits position into register SWTRIG */
52 /* - channel bits position into register SWTRIGB */
53 /* - channel register offset of data holding register DHRx */
54 /* - channel register offset of data output register DORx */
55 /* - channel register offset of sample-and-hold sample time register SHSRx */
56 /* - channel register offset of sawtooth register STRx */
57 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
58 CR, MCR, CCR, SHHR, SHRR, STMODR of channel 1 */
59 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
60 CR, MCR, CCR, SHHR, SHRR, STMODR of channel 2 */
61 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
62
63 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
64 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
65 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
66
67 #define DAC_SWTRB_CH1 (DAC_SWTRIGR_SWTRIGB1) /* Channel bit into register SWTRIGRB of channel 1.*/
68 #define DAC_SWTRB_CH2 (DAC_SWTRIGR_SWTRIGB2) /* Channel bit into register SWTRIGR of channel 2.*/
69 #define DAC_SWTRB_CHX_MASK (DAC_SWTRB_CH1 | DAC_SWTRB_CH2)
70
71 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
72 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
73 DHR12Rx channel 1 (shifted left of 20 bits) */
74 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
75 DHR12Rx channel 1 (shifted left of 24 bits) */
76
77 #define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus
78 DHR12Rx channel 1 (shifted left of 28 bits) */
79 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
80 DHR12Rx channel 1 (shifted left of 20 bits) */
81 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
82 DHR12Rx channel 1 (shifted left of 24 bits) */
83
84 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
85 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
86 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
87 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
88 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
89
90 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
91
92 #define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus
93 DORx channel 2 (shifted left of 5 bits) */
94 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
95
96 #define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
97 #define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus
98 SHSRx channel 2 (shifted left of 6 bits) */
99 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
100
101 #define DAC_REG_STR1_REGOFFSET 0x00000000UL /* Register STRx channel 1 taken as reference */
102 #define DAC_REG_STR2_REGOFFSET 0x00000080UL /* Register offset of STRx channel 1 versus
103 STRx channel 2 (shifted left of 7 bits) */
104 #define DAC_REG_STRX_REGOFFSET_MASK (DAC_REG_STR1_REGOFFSET | DAC_REG_STR2_REGOFFSET)
105
106 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
107 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
108 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
109 to position 0 */
110 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
111 to position 0 */
112 #define DAC_REG_STRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of STRx registers offset when shifted
113 to position 0 */
114
115 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx
116 channel 1 or 2 versus DHR12Rx channel 1
117 (shifted left of 28 bits) */
118 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
119 channel 1 or 2 versus DHR12Rx channel 1
120 (shifted left of 20 bits) */
121 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
122 channel 1 or 2 versus DHR12Rx channel 1
123 (shifted left of 24 bits) */
124 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx
125 channel 1 or 2 versus DORx channel 1
126 (shifted left of 5 bits) */
127 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx
128 channel 1 or 2 versus SHSRx channel 1
129 (shifted left of 6 bits) */
130 #define DAC_REG_STRX_REGOFFSET_BITOFFSET_POS 7UL /* Position of bits register offset of STRx
131 channel 1 or 2 versus STRx channel 1
132 (shifted left of 7 bits) */
133
134 /* DAC registers bits positions */
135 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
136 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
137 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
138
139 /* Miscellaneous data */
140 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
141 bits (voltage range determined by analog voltage
142 references Vref+ and Vref-, refer to reference manual) */
143
144 /**
145 * @}
146 */
147
148
149 /* Private macros ------------------------------------------------------------*/
150 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
151 * @{
152 */
153
154 /**
155 * @brief Driver macro reserved for internal use: set a pointer to
156 * a register from a register basis from which an offset
157 * is applied.
158 * @param __REG__ Register basis from which the offset is applied.
159 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
160 * @retval Pointer to register address
161 */
162 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
163 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
164
165 /**
166 * @}
167 */
168
169
170 /* Exported types ------------------------------------------------------------*/
171 #if defined(USE_FULL_LL_DRIVER)
172 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
173 * @{
174 */
175
176 /**
177 * @brief Structure definition of some features of DAC instance.
178 */
179 typedef struct
180 {
181 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
182 internal (SW start) or from external peripheral
183 (timer event, external interrupt line).
184 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
185
186 This feature can be modified afterwards using unitary
187 function @ref LL_DAC_SetTriggerSource().
188 @note If waveform automatic generation mode is set to sawtooth,
189 this parameter is used as sawtooth RESET trigger */
190
191 uint32_t TriggerSource2; /*!< Set the conversion secondary trigger source for the selected DAC channel:
192 internal (SW start) or from external peripheral
193 (timer event, external interrupt line).
194 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
195
196 This feature can be modified afterwards using unitary
197 function @ref LL_DAC_SetTriggerSource2().
198 @note If waveform automatic generation mode is set to sawtooth,
199 this parameter is used as sawtooth step trigger */
200
201 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
202 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
203
204 This feature can be modified afterwards using unitary
205 function @ref LL_DAC_SetWaveAutoGeneration(). */
206
207 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
208 If waveform automatic generation mode is set to noise, this parameter
209 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
210 If waveform automatic generation mode is set to triangle,
211 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
212 If waveform automatic generation mode is set to sawtooth, this parameter
213 host the sawtooth configuration: polarity, reset data, increment data.
214 Use __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG macro to set this parameter value.
215 @note If waveform automatic generation mode is disabled,
216 this parameter is discarded.
217
218 This feature can be modified afterwards using unitary
219 function @ref LL_DAC_SetWaveNoiseLFSR(),
220 @ref LL_DAC_SetWaveTriangleAmplitude(),
221 @ref LL_DAC_SetWaveSawtoothPolarity(),
222 @ref LL_DAC_SetWaveSawtoothResetData()
223 or @ref LL_DAC_SetWaveSawtoothStepData(),
224 depending on the wave automatic generation selected. */
225
226 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
227 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
228
229 This feature can be modified afterwards using unitary
230 function @ref LL_DAC_SetOutputBuffer(). */
231
232 uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
233 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
234
235 This feature can be modified afterwards using unitary
236 function @ref LL_DAC_SetOutputConnection(). */
237
238 uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC
239 channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
240
241 This feature can be modified afterwards using unitary
242 function @ref LL_DAC_SetOutputMode(). */
243 } LL_DAC_InitTypeDef;
244
245 /**
246 * @}
247 */
248 #endif /* USE_FULL_LL_DRIVER */
249
250 /* Exported constants --------------------------------------------------------*/
251 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
252 * @{
253 */
254
255 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
256 * @brief Flags defines which can be used with LL_DAC_ReadReg function
257 * @{
258 */
259 /* DAC channel 1 flags */
260 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
261 #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
262 #define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */
263 #define LL_DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY) /*!< DAC channel 1 flag ready */
264 #define LL_DAC_FLAG_DORSTAT1 (DAC_SR_DORSTAT1) /*!< DAC channel 1 flag output register */
265
266 /* DAC channel 2 flags */
267 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
268 #define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
269 #define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */
270 #define LL_DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY) /*!< DAC channel 2 flag ready */
271 #define LL_DAC_FLAG_DORSTAT2 (DAC_SR_DORSTAT2) /*!< DAC channel 2 flag output register */
272
273 /**
274 * @}
275 */
276
277 /** @defgroup DAC_LL_EC_IT DAC interruptions
278 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
279 * @{
280 */
281 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
282
283 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
284
285 /**
286 * @}
287 */
288
289 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
290 * @{
291 */
292 #define LL_DAC_CHANNEL_1 (DAC_REG_STR1_REGOFFSET | DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1 | DAC_SWTRB_CH1) /*!< DAC channel 1 */
293 #define LL_DAC_CHANNEL_2 (DAC_REG_STR2_REGOFFSET | DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2 | DAC_SWTRB_CH2) /*!< DAC channel 2 */
294 /**
295 * @}
296 */
297
298 /** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode
299 * @brief High frequency interface mode defines that can be used
300 * with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode
301 * @{
302 */
303 #define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */
304 #define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
305 #define LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */
306 /**
307 * @}
308 */
309
310 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
311 * @{
312 */
313 #define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */
314 #define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */
315 /**
316 * @}
317 */
318
319 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
320 * @{
321 */
322 #define LL_DAC_TRIG_SOFTWARE 0x00000000UL /*!< DAC (all) channel conversion trigger internal (SW start) */
323 #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external peripheral: TIM1 TRGO. */
324 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC1/2/4 channel conversion trigger from external peripheral: TIM8 TRGO. Refer to device datasheet for DACx instance availability. */
325 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM7 TRGO. */
326 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM15 TRGO. */
327 #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM2 TRGO. */
328 #define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM4 TRGO. */
329 #define LL_DAC_TRIG_EXT_EXTI_LINE9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: external interrupt line 9. Note: only to be used as update or reset (sawtooth generation) trigger */
330 #define LL_DAC_TRIG_EXT_EXTI_LINE10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: external interrupt line 10. Note: only to be used as increment (sawtooth generation) trigger */
331 #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM6 TRGO. */
332 #define LL_DAC_TRIG_EXT_TIM3_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM3 TRGO. */
333 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG1 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
334 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG1 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
335 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG2 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
336 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG2 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
337 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG3 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
338 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG3 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
339 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG4 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
340 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG4 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
341 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG5 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
342 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG5 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
343 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG6 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
344 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG6 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
345 #define LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC1&4 channel conversion trigger from external peripheral: HRTIM1 DACTRG1. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
346 #define LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC2 channel conversion trigger from external peripheral: HRTIM1 DACTRG2. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */
347 #define LL_DAC_TRIG_EXT_HRTIM_TRGO3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external peripheral: HRTIM1 DACTRG3. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
348 /**
349 * @}
350 */
351
352 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
353 * @{
354 */
355 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
356 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
357 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
358 #define LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH (DAC_CR_WAVE1_1|DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated sawtooth waveform. */
359 /**
360 * @}
361 */
362
363 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
364 * @{
365 */
366 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
367 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
368 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
369 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
370 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
371 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
372 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
373 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
374 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
375 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
376 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
377 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
378 /**
379 * @}
380 */
381
382 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
383 * @{
384 */
385 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
386 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
387 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
388 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
389 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
390 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
391 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
392 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
393 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
394 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
395 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
396 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
397 /**
398 * @}
399 */
400
401 /** @defgroup DAC_LL_EC_SAWTOOTH_POLARITY_MODE DAC wave generation - Sawtooth polarity mode
402 * @{
403 */
404 #define LL_DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000UL /*!< Sawtooth wave generation, polarity is decrement */
405 #define LL_DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1) /*!< Sawtooth wave generation, polarity is increment */
406 /**
407 * @}
408 */
409
410 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
411 * @{
412 */
413 #define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL /*!< The selected DAC channel output is on mode normal. */
414 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
415 /**
416 * @}
417 */
418
419 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
420 * @{
421 */
422 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
423 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
424 /**
425 * @}
426 */
427
428 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
429 * @{
430 */
431 #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */
432 #define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
433 /**
434 * @}
435 */
436
437 /** @defgroup DAC_LL_EC_SIGNED_FORMAT DAC channel signed format
438 * @{
439 */
440 #define LL_DAC_SIGNED_FORMAT_DISABLE 0x00000000UL /*!< The selected DAC channel data format is not signed */
441 #define LL_DAC_SIGNED_FORMAT_ENABLE (DAC_MCR_SINFORMAT1) /*!< The selected DAC channel data format is signed */
442 /**
443 * @}
444 */
445
446 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
447 * @{
448 */
449 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
450 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
451 /**
452 * @}
453 */
454
455 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
456 * @{
457 */
458 /* List of DAC registers intended to be used (most commonly) with */
459 /* DMA transfer. */
460 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
461 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
462 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
463 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
464 /**
465 * @}
466 */
467
468 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
469 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
470 * not timeout values.
471 * For details on delays values, refer to descriptions in source code
472 * above each literal definition.
473 * @{
474 */
475
476 /* Delay for DAC channel voltage settling time from DAC channel startup */
477 /* (transition from disable to enable). */
478 /* Note: DAC channel startup time depends on board application environment: */
479 /* impedance connected to DAC channel output. */
480 /* The delay below is specified under conditions: */
481 /* - voltage maximum transition (lowest to highest value) */
482 /* - until voltage reaches final value +-1LSB */
483 /* - DAC channel output buffer enabled */
484 /* - load impedance of 5kOhm (min), 50pF (max) */
485 /* Literal set to maximum value (refer to device datasheet, */
486 /* parameter "tWAKEUP"). */
487 /* Unit: us */
488 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
489
490 /* Delay for DAC channel voltage settling time. */
491 /* Note: DAC channel startup time depends on board application environment: */
492 /* impedance connected to DAC channel output. */
493 /* The delay below is specified under conditions: */
494 /* - voltage maximum transition (lowest to highest value) */
495 /* - until voltage reaches final value +-1LSB */
496 /* - DAC channel output buffer enabled */
497 /* - load impedance of 5kOhm min, 50pF max */
498 /* Literal set to maximum value (refer to device datasheet, */
499 /* parameter "tSETTLING"). */
500 /* Unit: us */
501 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */
502
503 /**
504 * @}
505 */
506
507 /**
508 * @}
509 */
510
511 /* Exported macro ------------------------------------------------------------*/
512 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
513 * @{
514 */
515
516 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
517 * @{
518 */
519
520 /**
521 * @brief Write a value in DAC register
522 * @param __INSTANCE__ DAC Instance
523 * @param __REG__ Register to be written
524 * @param __VALUE__ Value to be written in the register
525 * @retval None
526 */
527 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
528
529 /**
530 * @brief Read a value in DAC register
531 * @param __INSTANCE__ DAC Instance
532 * @param __REG__ Register to be read
533 * @retval Register value
534 */
535 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
536
537 /**
538 * @}
539 */
540
541 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
542 * @{
543 */
544
545 /**
546 * @brief Helper macro to get DAC channel number in decimal format
547 * from literals LL_DAC_CHANNEL_x.
548 * Example:
549 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
550 * will return decimal number "1".
551 * @note The input can be a value from functions where a channel
552 * number is returned.
553 * @param __CHANNEL__ This parameter can be one of the following values:
554 * @arg @ref LL_DAC_CHANNEL_1
555 * @arg @ref LL_DAC_CHANNEL_2 (1)
556 *
557 * (1) On this STM32 series, parameter not available on all instances.
558 * Refer to device datasheet for channels availability.
559 * @retval 1...2
560 */
561 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
562 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
563
564 /**
565 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
566 * from number in decimal format.
567 * Example:
568 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
569 * will return a data equivalent to "LL_DAC_CHANNEL_1".
570 * @note If the input parameter does not correspond to a DAC channel,
571 * this macro returns value '0'.
572 * @param __DECIMAL_NB__ 1...2
573 * @retval Returned value can be one of the following values:
574 * @arg @ref LL_DAC_CHANNEL_1
575 * @arg @ref LL_DAC_CHANNEL_2 (1)
576 *
577 * (1) On this STM32 series, parameter not available on all instances.
578 * Refer to device datasheet for channels availability.
579 */
580 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
581 (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
582
583 /**
584 * @brief Helper macro to define the DAC conversion data full-scale digital
585 * value corresponding to the selected DAC resolution.
586 * @note DAC conversion data full-scale corresponds to voltage range
587 * determined by analog voltage references Vref+ and Vref-
588 * (refer to reference manual).
589 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
590 * @arg @ref LL_DAC_RESOLUTION_12B
591 * @arg @ref LL_DAC_RESOLUTION_8B
592 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
593 */
594 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
595 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
596
597 /**
598 * @brief Helper macro to calculate the DAC conversion data (unit: digital
599 * value) corresponding to a voltage (unit: mVolt).
600 * @note This helper macro is intended to provide input data in voltage
601 * rather than digital value,
602 * to be used with LL DAC functions such as
603 * @ref LL_DAC_ConvertData12RightAligned().
604 * @note Analog reference voltage (Vref+) must be either known from
605 * user board environment or can be calculated using ADC measurement
606 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
607 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
608 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
609 * (unit: mVolt).
610 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
611 * @arg @ref LL_DAC_RESOLUTION_12B
612 * @arg @ref LL_DAC_RESOLUTION_8B
613 * @retval DAC conversion data (unit: digital value)
614 */
615 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
616 __DAC_VOLTAGE__,\
617 __DAC_RESOLUTION__) \
618 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
619 / (__VREFANALOG_VOLTAGE__) \
620 )
621
622 /**
623 * @brief Helper macro to format sawtooth wave generation configuration
624 * value to be filled into WaveAutoGenerationConfig parameter of @ref LL_DAC_InitTypeDef.
625 * @note This helper will format information to fit in DAC_STRx register.
626 * @param __POLARITY__ sawtooth wave polarity (must be value of @ref DAC_LL_EC_SAWTOOTH_POLARITY_MODE)
627 * @param __RESET_DATA__ sawtooth reset data.
628 * @param __STEP_DATA__ sawtooth step data
629 * @retval Sawtooth configuration organized in DAC_STRx compatible format.
630 */
631 #define __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG(__POLARITY__,\
632 __RESET_DATA__,\
633 __STEP_DATA__) \
634 ( (((__STEP_DATA__) << DAC_STR1_STINCDATA1_Pos) & DAC_STR1_STINCDATA1_Msk) \
635 | ((__POLARITY__) & DAC_STR1_STDIR1_Msk) \
636 | (((__RESET_DATA__) << DAC_STR1_STRSTDATA1_Pos) & DAC_STR1_STRSTDATA1_Msk) \
637 )
638
639 /**
640 * @}
641 */
642
643 /**
644 * @}
645 */
646
647
648 /* Exported functions --------------------------------------------------------*/
649 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
650 * @{
651 */
652 /** @defgroup DAC_LL_EF_Channel_Configuration Configuration of DAC instance
653 * @{
654 */
655 /**
656 * @brief Set the high frequency interface mode for the selected DAC instance
657 * @rmtoll MCR HFSEL LL_DAC_SetHighFrequencyMode
658 * @param DACx DAC instance
659 * @param HighFreqMode This parameter can be one of the following values:
660 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
661 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
662 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
663 * @retval None
664 */
LL_DAC_SetHighFrequencyMode(DAC_TypeDef * DACx,uint32_t HighFreqMode)665 __STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t HighFreqMode)
666 {
667 MODIFY_REG(DACx->MCR, DAC_MCR_HFSEL, HighFreqMode);
668 }
669
670 /**
671 * @brief Get the high frequency interface mode for the selected DAC instance
672 * @rmtoll MCR HFSEL LL_DAC_GetHighFrequencyMode
673 * @param DACx DAC instance
674 * @retval Returned value can be one of the following values:
675 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
676 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
677 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
678 */
LL_DAC_GetHighFrequencyMode(DAC_TypeDef * DACx)679 __STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(DAC_TypeDef *DACx)
680 {
681 return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_HFSEL));
682 }
683 /**
684 * @}
685 */
686
687 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
688 * @{
689 */
690
691 /**
692 * @brief Set the operating mode for the selected DAC channel:
693 * calibration or normal operating mode.
694 * @rmtoll CR CEN1 LL_DAC_SetMode\n
695 * CR CEN2 LL_DAC_SetMode
696 * @param DACx DAC instance
697 * @param DAC_Channel This parameter can be one of the following values:
698 * @arg @ref LL_DAC_CHANNEL_1
699 * @arg @ref LL_DAC_CHANNEL_2 (1)
700 *
701 * (1) On this STM32 series, parameter not available on all instances.
702 * Refer to device datasheet for channels availability.
703 * @param ChannelMode This parameter can be one of the following values:
704 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
705 * @arg @ref LL_DAC_MODE_CALIBRATION
706 * @retval None
707 */
LL_DAC_SetMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t ChannelMode)708 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
709 {
710 MODIFY_REG(DACx->CR,
711 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
712 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
713 }
714
715 /**
716 * @brief Get the operating mode for the selected DAC channel:
717 * calibration or normal operating mode.
718 * @rmtoll CR CEN1 LL_DAC_GetMode\n
719 * CR CEN2 LL_DAC_GetMode
720 * @param DACx DAC instance
721 * @param DAC_Channel This parameter can be one of the following values:
722 * @arg @ref LL_DAC_CHANNEL_1
723 * @arg @ref LL_DAC_CHANNEL_2 (1)
724 *
725 * (1) On this STM32 series, parameter not available on all instances.
726 * Refer to device datasheet for channels availability.
727 * @retval Returned value can be one of the following values:
728 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
729 * @arg @ref LL_DAC_MODE_CALIBRATION
730 */
LL_DAC_GetMode(DAC_TypeDef * DACx,uint32_t DAC_Channel)731 __STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
732 {
733 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
734 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
735 );
736 }
737
738 /**
739 * @brief Set the offset trimming value for the selected DAC channel.
740 * Trimming has an impact when output buffer is enabled
741 * and is intended to replace factory calibration default values.
742 * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
743 * CCR OTRIM2 LL_DAC_SetTrimmingValue
744 * @param DACx DAC instance
745 * @param DAC_Channel This parameter can be one of the following values:
746 * @arg @ref LL_DAC_CHANNEL_1
747 * @arg @ref LL_DAC_CHANNEL_2 (1)
748 *
749 * (1) On this STM32 series, parameter not available on all instances.
750 * Refer to device datasheet for channels availability.
751 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
752 * @retval None
753 */
LL_DAC_SetTrimmingValue(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TrimmingValue)754 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
755 {
756 MODIFY_REG(DACx->CCR,
757 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
758 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
759 }
760
761 /**
762 * @brief Get the offset trimming value for the selected DAC channel.
763 * Trimming has an impact when output buffer is enabled
764 * and is intended to replace factory calibration default values.
765 * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
766 * CCR OTRIM2 LL_DAC_GetTrimmingValue
767 * @param DACx DAC instance
768 * @param DAC_Channel This parameter can be one of the following values:
769 * @arg @ref LL_DAC_CHANNEL_1
770 * @arg @ref LL_DAC_CHANNEL_2 (1)
771 *
772 * (1) On this STM32 series, parameter not available on all instances.
773 * Refer to device datasheet for channels availability.
774 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
775 */
LL_DAC_GetTrimmingValue(DAC_TypeDef * DACx,uint32_t DAC_Channel)776 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
777 {
778 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
779 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
780 );
781 }
782
783 /**
784 * @brief Set the conversion trigger source for the selected DAC channel.
785 * @note For conversion trigger source to be effective, DAC trigger
786 * must be enabled using function @ref LL_DAC_EnableTrigger().
787 * @note To set conversion trigger source, DAC channel must be disabled.
788 * Otherwise, the setting is discarded.
789 * @note Availability of parameters of trigger sources from timer
790 * depends on timers availability on the selected device.
791 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
792 * CR TSEL2 LL_DAC_SetTriggerSource
793 * @param DACx DAC instance
794 * @param DAC_Channel This parameter can be one of the following values:
795 * @arg @ref LL_DAC_CHANNEL_1
796 * @arg @ref LL_DAC_CHANNEL_2 (1)
797 *
798 * (1) On this STM32 series, parameter not available on all instances.
799 * Refer to device datasheet for channels availability.
800 * @param TriggerSource This parameter can be one of the following values:
801 * @arg @ref LL_DAC_TRIG_SOFTWARE
802 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
803 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
804 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
805 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
806 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
807 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
808 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
809 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
810 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
811 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
812 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
813 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
814 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
815 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
816 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
817 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
818 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
819 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
820 *
821 * (1) On this STM32 series, parameter only available on DAC3.
822 * (2) On this STM32 series, parameter only available on DAC1/2/4.
823 * (3) On this STM32 series, parameter only available on DAC1&4.
824 * (4) On this STM32 series, parameter only available on DAC2.
825 * Refer to device datasheet for DACx instances availability.
826 * (5) On this STM32 series, parameter not available on all devices.
827 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
828 * @retval None
829 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)830 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
831 {
832 MODIFY_REG(DACx->CR,
833 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
834 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
835 }
836
837 /**
838 * @brief Get the conversion trigger source for the selected DAC channel.
839 * @note For conversion trigger source to be effective, DAC trigger
840 * must be enabled using function @ref LL_DAC_EnableTrigger().
841 * @note Availability of parameters of trigger sources from timer
842 * depends on timers availability on the selected device.
843 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
844 * CR TSEL2 LL_DAC_GetTriggerSource
845 * @param DACx DAC instance
846 * @param DAC_Channel This parameter can be one of the following values:
847 * @arg @ref LL_DAC_CHANNEL_1
848 * @arg @ref LL_DAC_CHANNEL_2 (1)
849 *
850 * (1) On this STM32 series, parameter not available on all instances.
851 * Refer to device datasheet for channels availability.
852 * @retval Returned value can be one of the following values:
853 * @arg @ref LL_DAC_TRIG_SOFTWARE
854 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
855 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
856 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
857 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
858 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
859 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
860 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
861 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
862 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
863 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
864 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
865 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
866 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
867 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
868 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
869 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
870 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
871 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
872 *
873 * (1) On this STM32 series, parameter only available on DAC3.
874 * (2) On this STM32 series, parameter only available on DAC1/2/4.
875 * (3) On this STM32 series, parameter only available on DAC1&4.
876 * (4) On this STM32 series, parameter only available on DAC2.
877 * Refer to device datasheet for DACx instances availability.
878 * (5) On this STM32 series, parameter not available on all devices.
879 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
880 */
LL_DAC_GetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel)881 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
882 {
883 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
884 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
885 );
886 }
887
888 /**
889 * @brief Set the waveform automatic generation mode
890 * for the selected DAC channel.
891 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
892 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
893 * @param DACx DAC instance
894 * @param DAC_Channel This parameter can be one of the following values:
895 * @arg @ref LL_DAC_CHANNEL_1
896 * @arg @ref LL_DAC_CHANNEL_2 (1)
897 *
898 * (1) On this STM32 series, parameter not available on all instances.
899 * Refer to device datasheet for channels availability.
900 * @param WaveAutoGeneration This parameter can be one of the following values:
901 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
902 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
903 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
904 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH
905 * @retval None
906 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)907 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
908 {
909 MODIFY_REG(DACx->CR,
910 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
911 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
912 }
913
914 /**
915 * @brief Get the waveform automatic generation mode
916 * for the selected DAC channel.
917 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
918 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
919 * @param DACx DAC instance
920 * @param DAC_Channel This parameter can be one of the following values:
921 * @arg @ref LL_DAC_CHANNEL_1
922 * @arg @ref LL_DAC_CHANNEL_2 (1)
923 *
924 * (1) On this STM32 series, parameter not available on all instances.
925 * Refer to device datasheet for channels availability.
926 * @retval Returned value can be one of the following values:
927 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
928 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
929 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
930 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH
931 */
LL_DAC_GetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel)932 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
933 {
934 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
935 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
936 );
937 }
938
939 /**
940 * @brief Set the noise waveform generation for the selected DAC channel:
941 * Noise mode and parameters LFSR (linear feedback shift register).
942 * @note For wave generation to be effective, DAC channel
943 * wave generation mode must be enabled using
944 * function @ref LL_DAC_SetWaveAutoGeneration().
945 * @note This setting can be set when the selected DAC channel is disabled
946 * (otherwise, the setting operation is ignored).
947 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
948 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
949 * @param DACx DAC instance
950 * @param DAC_Channel This parameter can be one of the following values:
951 * @arg @ref LL_DAC_CHANNEL_1
952 * @arg @ref LL_DAC_CHANNEL_2 (1)
953 *
954 * (1) On this STM32 series, parameter not available on all instances.
955 * Refer to device datasheet for channels availability.
956 * @param NoiseLFSRMask This parameter can be one of the following values:
957 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
958 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
959 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
960 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
961 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
962 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
963 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
964 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
965 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
966 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
967 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
968 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
969 * @retval None
970 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)971 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
972 {
973 MODIFY_REG(DACx->CR,
974 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
975 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
976 }
977
978 /**
979 * @brief Get the noise waveform generation for the selected DAC channel:
980 * Noise mode and parameters LFSR (linear feedback shift register).
981 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
982 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
983 * @param DACx DAC instance
984 * @param DAC_Channel This parameter can be one of the following values:
985 * @arg @ref LL_DAC_CHANNEL_1
986 * @arg @ref LL_DAC_CHANNEL_2 (1)
987 *
988 * (1) On this STM32 series, parameter not available on all instances.
989 * Refer to device datasheet for channels availability.
990 * @retval Returned value can be one of the following values:
991 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
992 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
993 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
994 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
995 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
996 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
997 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
998 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
999 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
1000 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
1001 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
1002 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
1003 */
LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel)1004 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1005 {
1006 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1007 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1008 );
1009 }
1010
1011 /**
1012 * @brief Set the triangle waveform generation for the selected DAC channel:
1013 * triangle mode and amplitude.
1014 * @note For wave generation to be effective, DAC channel
1015 * wave generation mode must be enabled using
1016 * function @ref LL_DAC_SetWaveAutoGeneration().
1017 * @note This setting can be set when the selected DAC channel is disabled
1018 * (otherwise, the setting operation is ignored).
1019 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
1020 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
1021 * @param DACx DAC instance
1022 * @param DAC_Channel This parameter can be one of the following values:
1023 * @arg @ref LL_DAC_CHANNEL_1
1024 * @arg @ref LL_DAC_CHANNEL_2 (1)
1025 *
1026 * (1) On this STM32 series, parameter not available on all instances.
1027 * Refer to device datasheet for channels availability.
1028 * @param TriangleAmplitude This parameter can be one of the following values:
1029 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
1030 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
1031 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
1032 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
1033 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
1034 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
1035 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
1036 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
1037 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
1038 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
1039 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
1040 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
1041 * @retval None
1042 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)1043 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
1044 uint32_t TriangleAmplitude)
1045 {
1046 MODIFY_REG(DACx->CR,
1047 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1048 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1049 }
1050
1051 /**
1052 * @brief Get the triangle waveform generation for the selected DAC channel:
1053 * triangle mode and amplitude.
1054 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
1055 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
1056 * @param DACx DAC instance
1057 * @param DAC_Channel This parameter can be one of the following values:
1058 * @arg @ref LL_DAC_CHANNEL_1
1059 * @arg @ref LL_DAC_CHANNEL_2 (1)
1060 *
1061 * (1) On this STM32 series, parameter not available on all instances.
1062 * Refer to device datasheet for channels availability.
1063 * @retval Returned value can be one of the following values:
1064 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
1065 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
1066 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
1067 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
1068 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
1069 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
1070 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
1071 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
1072 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
1073 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
1074 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
1075 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
1076 */
LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel)1077 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1078 {
1079 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1080 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1081 );
1082 }
1083
1084 /**
1085 * @brief Set the swatooth waveform generation polarity.
1086 * @note For wave generation to be effective, DAC channel
1087 * wave generation mode must be enabled using
1088 * function @ref LL_DAC_SetWaveAutoGeneration().
1089 * @note This setting can be set when the selected DAC channel is disabled
1090 * (otherwise, the setting operation is ignored).
1091 * @rmtoll STR1 STDIR1 LL_DAC_SetWaveSawtoothPolarity\n
1092 * STR2 STDIR2 LL_DAC_SetWaveSawtoothPolarity
1093 * @param DACx DAC instance
1094 * @param DAC_Channel This parameter can be one of the following values:
1095 * @arg @ref LL_DAC_CHANNEL_1
1096 * @arg @ref LL_DAC_CHANNEL_2 (1)
1097 *
1098 * (1) On this STM32 series, parameter not available on all instances.
1099 * Refer to device datasheet for channels availability.
1100 * @param Polarity This parameter can be one of the following values:
1101 * @arg @ref LL_DAC_SAWTOOTH_POLARITY_DECREMENT
1102 * @arg @ref LL_DAC_SAWTOOTH_POLARITY_INCREMENT
1103 * @retval None
1104 */
LL_DAC_SetWaveSawtoothPolarity(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Polarity)1105 __STATIC_INLINE void LL_DAC_SetWaveSawtoothPolarity(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Polarity)
1106 {
1107 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
1108
1109 MODIFY_REG(*preg,
1110 DAC_STR1_STDIR1,
1111 Polarity);
1112 }
1113
1114 /**
1115 * @brief Get the sawtooth waveform generation polarity.
1116 * @rmtoll STR1 STDIR1 LL_DAC_GetWaveSawtoothPolarity\n
1117 * STR2 STDIR2 LL_DAC_GetWaveSawtoothPolarity
1118 * @param DACx DAC instance
1119 * @param DAC_Channel This parameter can be one of the following values:
1120 * @arg @ref LL_DAC_CHANNEL_1
1121 * @arg @ref LL_DAC_CHANNEL_2 (1)
1122 *
1123 * (1) On this STM32 series, parameter not available on all instances.
1124 * Refer to device datasheet for channels availability.
1125 * @retval Returned value can be one of the following values:
1126 * @arg @ref LL_DAC_SAWTOOTH_POLARITY_DECREMENT
1127 * @arg @ref LL_DAC_SAWTOOTH_POLARITY_INCREMENT
1128 */
LL_DAC_GetWaveSawtoothPolarity(DAC_TypeDef * DACx,uint32_t DAC_Channel)1129 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothPolarity(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1130 {
1131 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
1132
1133 return (uint32_t) READ_BIT(*preg, DAC_STR1_STDIR1);
1134 }
1135
1136 /**
1137 * @brief Set the swatooth waveform generation reset data.
1138 * @note For wave generation to be effective, DAC channel
1139 * wave generation mode must be enabled using
1140 * function @ref LL_DAC_SetWaveAutoGeneration().
1141 * @note This setting can be set when the selected DAC channel is disabled
1142 * (otherwise, the setting operation is ignored).
1143 * @rmtoll STR1 STRSTDATA1 LL_DAC_SetWaveSawtoothResetData\n
1144 * STR2 STRSTDATA2 LL_DAC_SetWaveSawtoothResetData
1145 * @param DACx DAC instance
1146 * @param DAC_Channel This parameter can be one of the following values:
1147 * @arg @ref LL_DAC_CHANNEL_1
1148 * @arg @ref LL_DAC_CHANNEL_2 (1)
1149 *
1150 * (1) On this STM32 series, parameter not available on all instances.
1151 * Refer to device datasheet for channels availability.
1152 * @param ResetData This parameter is the sawtooth reset value.
1153 * Range is from 0 to DAC full range 4095 (0xFFF)
1154 * @retval None
1155 */
LL_DAC_SetWaveSawtoothResetData(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t ResetData)1156 __STATIC_INLINE void LL_DAC_SetWaveSawtoothResetData(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ResetData)
1157 {
1158 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
1159
1160 MODIFY_REG(*preg,
1161 DAC_STR1_STRSTDATA1,
1162 ResetData << DAC_STR1_STRSTDATA1_Pos);
1163 }
1164
1165 /**
1166 * @brief Get the sawtooth waveform generation reset data.
1167 * @rmtoll STR1 STRSTDATA1 LL_DAC_GetWaveSawtoothResetData\n
1168 * STR2 STRSTDATA2 LL_DAC_GetWaveSawtoothResetData
1169 * @param DACx DAC instance
1170 * @param DAC_Channel This parameter can be one of the following values:
1171 * @arg @ref LL_DAC_CHANNEL_1
1172 * @arg @ref LL_DAC_CHANNEL_2 (1)
1173 *
1174 * (1) On this STM32 series, parameter not available on all instances.
1175 * Refer to device datasheet for channels availability.
1176 * @retval Returned value is the sawtooth reset value.
1177 * Range is from 0 to DAC full range 4095 (0xFFF)
1178 */
LL_DAC_GetWaveSawtoothResetData(DAC_TypeDef * DACx,uint32_t DAC_Channel)1179 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1180 {
1181 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
1182
1183 return (uint32_t)(READ_BIT(*preg, DAC_STR1_STRSTDATA1) >> DAC_STR1_STRSTDATA1_Pos);
1184 }
1185
1186 /**
1187 * @brief Set the swatooth waveform generation step data.
1188 * @note For wave generation to be effective, DAC channel
1189 * wave generation mode must be enabled using
1190 * function @ref LL_DAC_SetWaveAutoGeneration().
1191 * @note This setting can be set when the selected DAC channel is disabled
1192 * (otherwise, the setting operation is ignored).
1193 * @rmtoll STR1 STINCDATA1 LL_DAC_SetWaveSawtoothStepData\n
1194 * STR2 STINCDATA2 LL_DAC_SetWaveSawtoothStepData
1195 * @param DACx DAC instance
1196 * @param DAC_Channel This parameter can be one of the following values:
1197 * @arg @ref LL_DAC_CHANNEL_1
1198 * @arg @ref LL_DAC_CHANNEL_2 (1)
1199 *
1200 * (1) On this STM32 series, parameter not available on all instances.
1201 * Refer to device datasheet for channels availability.
1202 * @param StepData This parameter is the sawtooth step value.
1203 * 12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa
1204 * Step value step is 1/16 = 0.0625
1205 * Step value range is 0.0000 to 4095.9375 (0xFFF.F)
1206 * @retval None
1207 */
LL_DAC_SetWaveSawtoothStepData(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t StepData)1208 __STATIC_INLINE void LL_DAC_SetWaveSawtoothStepData(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t StepData)
1209 {
1210 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
1211
1212 MODIFY_REG(*preg,
1213 DAC_STR1_STINCDATA1,
1214 StepData << DAC_STR1_STINCDATA1_Pos);
1215 }
1216
1217 /**
1218 * @brief Get the sawtooth waveform generation step data.
1219 * @rmtoll STR1 STINCDATA1 LL_DAC_GetWaveSawtoothStepData\n
1220 * STR2 STINCDATA2 LL_DAC_GetWaveSawtoothStepData
1221 * @param DACx DAC instance
1222 * @param DAC_Channel This parameter can be one of the following values:
1223 * @arg @ref LL_DAC_CHANNEL_1
1224 * @arg @ref LL_DAC_CHANNEL_2 (1)
1225 *
1226 * (1) On this STM32 series, parameter not available on all instances.
1227 * Refer to device datasheet for channels availability.
1228 * @retval Returned value is the sawtooth step value.
1229 * 12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa
1230 * Step value step is 1/16 = 0.0625
1231 * Step value range is 0.0000 to 4095.9375 (0xFFF.F)
1232 */
LL_DAC_GetWaveSawtoothStepData(DAC_TypeDef * DACx,uint32_t DAC_Channel)1233 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1234 {
1235 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
1236
1237 return (uint32_t)(READ_BIT(*preg, DAC_STR1_STINCDATA1) >> DAC_STR1_STINCDATA1_Pos);
1238 }
1239
1240 /**
1241 * @brief Set the swatooth waveform generation reset trigger source.
1242 * @note For wave generation to be effective, DAC channel
1243 * wave generation mode must be enabled using
1244 * function @ref LL_DAC_SetWaveAutoGeneration().
1245 * @note This setting can be set when the selected DAC channel is disabled
1246 * (otherwise, the setting operation is ignored).
1247 * @rmtoll STMODR STRSTTRIGSEL1 LL_DAC_SetWaveSawtoothResetTriggerSource\n
1248 * STMODR STRSTTRIGSEL2 LL_DAC_SetWaveSawtoothResetTriggerSource
1249 * @param DACx DAC instance
1250 * @param DAC_Channel This parameter can be one of the following values:
1251 * @arg @ref LL_DAC_CHANNEL_1
1252 * @arg @ref LL_DAC_CHANNEL_2 (1)
1253 *
1254 * (1) On this STM32 series, parameter not available on all instances.
1255 * Refer to device datasheet for channels availability.
1256 * @param TriggerSource This parameter can be one of the following values:
1257 * @arg @ref LL_DAC_TRIG_SOFTWARE
1258 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
1259 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
1260 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
1261 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
1262 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
1263 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
1264 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
1265 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
1266 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
1267 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
1268 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
1269 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
1270 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
1271 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
1272 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
1273 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
1274 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
1275 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
1276 *
1277 * (1) On this STM32 series, parameter only available on DAC3.
1278 * (2) On this STM32 series, parameter only available on DAC1/2/4.
1279 * (3) On this STM32 series, parameter only available on DAC1&4.
1280 * (4) On this STM32 series, parameter only available on DAC2.
1281 * Refer to device datasheet for DACx instances availability.
1282 * (5) On this STM32 series, parameter not available on all devices.
1283 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
1284 * @retval None
1285 */
LL_DAC_SetWaveSawtoothResetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)1286 __STATIC_INLINE void LL_DAC_SetWaveSawtoothResetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel,
1287 uint32_t TriggerSource)
1288 {
1289 MODIFY_REG(DACx->STMODR,
1290 DAC_STMODR_STRSTTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1291 ((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1292 }
1293
1294 /**
1295 * @brief Get the sawtooth waveform generation reset trigger source.
1296 * @rmtoll STMODR STRSTTRIGSEL1 LL_DAC_GetWaveSawtoothResetTriggerSource\n
1297 * STMODR STRSTTRIGSEL2 LL_DAC_GetWaveSawtoothResetTriggerSource
1298 * @param DACx DAC instance
1299 * @param DAC_Channel This parameter can be one of the following values:
1300 * @arg @ref LL_DAC_CHANNEL_1
1301 * @arg @ref LL_DAC_CHANNEL_2 (1)
1302 *
1303 * (1) On this STM32 series, parameter not available on all instances.
1304 * Refer to device datasheet for channels availability.
1305 * @retval Returned value can be one of the following values:
1306 * @arg @ref LL_DAC_TRIG_SOFTWARE
1307 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
1308 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
1309 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
1310 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
1311 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
1312 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
1313 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
1314 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
1315 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
1316 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
1317 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
1318 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
1319 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
1320 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
1321 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
1322 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
1323 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
1324 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
1325 *
1326 * (1) On this STM32 series, parameter only available on DAC3.
1327 * (2) On this STM32 series, parameter only available on DAC1/2/4.
1328 * (3) On this STM32 series, parameter only available on DAC1&4.
1329 * (4) On this STM32 series, parameter only available on DAC2.
1330 * Refer to device datasheet for DACx instances availability.
1331 * (5) On this STM32 series, parameter not available on all devices.
1332 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
1333 */
LL_DAC_GetWaveSawtoothResetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel)1334 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1335 {
1336 return (uint32_t)((READ_BIT(DACx->STMODR,
1337 DAC_STMODR_STRSTTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1338 )
1339 >> (DAC_STMODR_STRSTTRIGSEL1_Pos + (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1340 ) << DAC_CR_TSEL1_Pos);
1341 }
1342
1343 /**
1344 * @brief Set the swatooth waveform generation step trigger source.
1345 * @note For wave generation to be effective, DAC channel
1346 * wave generation mode must be enabled using
1347 * function @ref LL_DAC_SetWaveAutoGeneration().
1348 * @note This setting can be set when the selected DAC channel is disabled
1349 * (otherwise, the setting operation is ignored).
1350 * @rmtoll STMODR STINCTRIGSEL1 LL_DAC_SetWaveSawtoothStepTriggerSource\n
1351 * STMODR STINCTRIGSEL2 LL_DAC_SetWaveSawtoothStepTriggerSource
1352 * @param DACx DAC instance
1353 * @param DAC_Channel This parameter can be one of the following values:
1354 * @arg @ref LL_DAC_CHANNEL_1
1355 * @arg @ref LL_DAC_CHANNEL_2 (1)
1356 *
1357 * (1) On this STM32 series, parameter not available on all instances.
1358 * Refer to device datasheet for channels availability.
1359 * @param TriggerSource This parameter can be one of the following values:
1360 * @arg @ref LL_DAC_TRIG_SOFTWARE
1361 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
1362 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
1363 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
1364 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
1365 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
1366 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
1367 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE10
1368 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
1369 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
1370 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (3)
1371 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (3)
1372 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (3)
1373 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (3)
1374 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (3)
1375 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (3)
1376 *
1377 * (1) On this STM32 series, parameter only available on DAC3.
1378 * (2) On this STM32 series, parameter only available on DAC1/2/4.
1379 * Refer to device datasheet for DACx instances availability.
1380 * (3) On this STM32 series, parameter not available on all devices.
1381 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
1382 * @retval None
1383 */
LL_DAC_SetWaveSawtoothStepTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)1384 __STATIC_INLINE void LL_DAC_SetWaveSawtoothStepTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel,
1385 uint32_t TriggerSource)
1386 {
1387 MODIFY_REG(DACx->STMODR,
1388 DAC_STMODR_STINCTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1389 ((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1390 }
1391
1392 /**
1393 * @brief Get the sawtooth waveform generation step trigger source.
1394 * @rmtoll STMODR STINCTRIGSEL1 LL_DAC_GetWaveSawtoothStepTriggerSource\n
1395 * STMODR STINCTRIGSEL2 LL_DAC_GetWaveSawtoothStepTriggerSource
1396 * @param DACx DAC instance
1397 * @param DAC_Channel This parameter can be one of the following values:
1398 * @arg @ref LL_DAC_CHANNEL_1
1399 * @arg @ref LL_DAC_CHANNEL_2 (1)
1400 *
1401 * (1) On this STM32 series, parameter not available on all instances.
1402 * Refer to device datasheet for channels availability.
1403 * @retval Returned value can be one of the following values:
1404 * @arg @ref LL_DAC_TRIG_SOFTWARE
1405 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
1406 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
1407 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
1408 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
1409 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
1410 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
1411 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE10
1412 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
1413 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
1414 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (3)
1415 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (3)
1416 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (3)
1417 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (3)
1418 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (3)
1419 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (3)
1420 *
1421 * (1) On this STM32 series, parameter only available on DAC3.
1422 * (2) On this STM32 series, parameter only available on DAC1/2/4.
1423 * Refer to device datasheet for DACx instances availability.
1424 * (3) On this STM32 series, parameter not available on all devices.
1425 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
1426 */
LL_DAC_GetWaveSawtoothStepTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel)1427 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1428 {
1429 return (uint32_t)((READ_BIT(DACx->STMODR,
1430 DAC_STMODR_STINCTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1431 )
1432 >> (DAC_STMODR_STINCTRIGSEL1_Pos + (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1433 ) << DAC_CR_TSEL1_Pos);
1434 }
1435
1436 /**
1437 * @brief Set the output for the selected DAC channel.
1438 * @note This function set several features:
1439 * - mode normal or sample-and-hold
1440 * - buffer
1441 * - connection to GPIO or internal path.
1442 * These features can also be set individually using
1443 * dedicated functions:
1444 * - @ref LL_DAC_SetOutputBuffer()
1445 * - @ref LL_DAC_SetOutputMode()
1446 * - @ref LL_DAC_SetOutputConnection()
1447 * @note On this STM32 series, output connection depends on output mode
1448 * (normal or sample and hold) and output buffer state.
1449 * - if output connection is set to internal path and output buffer
1450 * is enabled (whatever output mode):
1451 * output connection is also connected to GPIO pin
1452 * (both connections to GPIO pin and internal path).
1453 * - if output connection is set to GPIO pin, output buffer
1454 * is disabled, output mode set to sample and hold:
1455 * output connection is also connected to internal path
1456 * (both connections to GPIO pin and internal path).
1457 * @note Mode sample-and-hold requires an external capacitor
1458 * to be connected between DAC channel output and ground.
1459 * Capacitor value depends on load on DAC channel output and
1460 * sample-and-hold timings configured.
1461 * As indication, capacitor typical value is 100nF
1462 * (refer to device datasheet, parameter "CSH").
1463 * @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
1464 * CR MODE2 LL_DAC_ConfigOutput
1465 * @param DACx DAC instance
1466 * @param DAC_Channel This parameter can be one of the following values:
1467 * @arg @ref LL_DAC_CHANNEL_1
1468 * @arg @ref LL_DAC_CHANNEL_2 (1)
1469 *
1470 * (1) On this STM32 series, parameter not available on all instances.
1471 * Refer to device datasheet for channels availability.
1472 * @param OutputMode This parameter can be one of the following values:
1473 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1474 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1475 * @param OutputBuffer This parameter can be one of the following values:
1476 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1477 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1478 * @param OutputConnection This parameter can be one of the following values:
1479 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1480 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1481 * @retval None
1482 */
LL_DAC_ConfigOutput(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode,uint32_t OutputBuffer,uint32_t OutputConnection)1483 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
1484 uint32_t OutputBuffer, uint32_t OutputConnection)
1485 {
1486 MODIFY_REG(DACx->MCR,
1487 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1488 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1489 }
1490
1491 /**
1492 * @brief Set the output mode normal or sample-and-hold
1493 * for the selected DAC channel.
1494 * @note Mode sample-and-hold requires an external capacitor
1495 * to be connected between DAC channel output and ground.
1496 * Capacitor value depends on load on DAC channel output and
1497 * sample-and-hold timings configured.
1498 * As indication, capacitor typical value is 100nF
1499 * (refer to device datasheet, parameter "CSH").
1500 * @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
1501 * CR MODE2 LL_DAC_SetOutputMode
1502 * @param DACx DAC instance
1503 * @param DAC_Channel This parameter can be one of the following values:
1504 * @arg @ref LL_DAC_CHANNEL_1
1505 * @arg @ref LL_DAC_CHANNEL_2 (1)
1506 *
1507 * (1) On this STM32 series, parameter not available on all instances.
1508 * Refer to device datasheet for channels availability.
1509 * @param OutputMode This parameter can be one of the following values:
1510 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1511 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1512 * @retval None
1513 */
LL_DAC_SetOutputMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode)1514 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
1515 {
1516 MODIFY_REG(DACx->MCR,
1517 (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1518 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1519 }
1520
1521 /**
1522 * @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
1523 * @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
1524 * CR MODE2 LL_DAC_GetOutputMode
1525 * @param DACx DAC instance
1526 * @param DAC_Channel This parameter can be one of the following values:
1527 * @arg @ref LL_DAC_CHANNEL_1
1528 * @arg @ref LL_DAC_CHANNEL_2 (1)
1529 *
1530 * (1) On this STM32 series, parameter not available on all instances.
1531 * Refer to device datasheet for channels availability.
1532 * @retval Returned value can be one of the following values:
1533 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1534 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1535 */
LL_DAC_GetOutputMode(DAC_TypeDef * DACx,uint32_t DAC_Channel)1536 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1537 {
1538 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1539 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1540 );
1541 }
1542
1543 /**
1544 * @brief Set the output buffer for the selected DAC channel.
1545 * @note On this STM32 series, when buffer is enabled, its offset can be
1546 * trimmed: factory calibration default values can be
1547 * replaced by user trimming values, using function
1548 * @ref LL_DAC_SetTrimmingValue().
1549 * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
1550 * CR MODE2 LL_DAC_SetOutputBuffer
1551 * @param DACx DAC instance
1552 * @param DAC_Channel This parameter can be one of the following values:
1553 * @arg @ref LL_DAC_CHANNEL_1
1554 * @arg @ref LL_DAC_CHANNEL_2 (1)
1555 *
1556 * (1) On this STM32 series, parameter not available on all instances.
1557 * Refer to device datasheet for channels availability.
1558 * @param OutputBuffer This parameter can be one of the following values:
1559 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1560 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1561 * @retval None
1562 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)1563 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
1564 {
1565 MODIFY_REG(DACx->MCR,
1566 (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1567 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1568 }
1569
1570 /**
1571 * @brief Get the output buffer state for the selected DAC channel.
1572 * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
1573 * CR MODE2 LL_DAC_GetOutputBuffer
1574 * @param DACx DAC instance
1575 * @param DAC_Channel This parameter can be one of the following values:
1576 * @arg @ref LL_DAC_CHANNEL_1
1577 * @arg @ref LL_DAC_CHANNEL_2 (1)
1578 *
1579 * (1) On this STM32 series, parameter not available on all instances.
1580 * Refer to device datasheet for channels availability.
1581 * @retval Returned value can be one of the following values:
1582 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1583 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1584 */
LL_DAC_GetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel)1585 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1586 {
1587 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1588 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1589 );
1590 }
1591
1592 /**
1593 * @brief Set the output connection for the selected DAC channel.
1594 * @note On this STM32 series, output connection depends on output mode (normal or
1595 * sample and hold) and output buffer state.
1596 * - if output connection is set to internal path and output buffer
1597 * is enabled (whatever output mode):
1598 * output connection is also connected to GPIO pin
1599 * (both connections to GPIO pin and internal path).
1600 * - if output connection is set to GPIO pin, output buffer
1601 * is disabled, output mode set to sample and hold:
1602 * output connection is also connected to internal path
1603 * (both connections to GPIO pin and internal path).
1604 * @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
1605 * CR MODE2 LL_DAC_SetOutputConnection
1606 * @param DACx DAC instance
1607 * @param DAC_Channel This parameter can be one of the following values:
1608 * @arg @ref LL_DAC_CHANNEL_1
1609 * @arg @ref LL_DAC_CHANNEL_2 (1)
1610 *
1611 * (1) On this STM32 series, parameter not available on all instances.
1612 * Refer to device datasheet for channels availability.
1613 * @param OutputConnection This parameter can be one of the following values:
1614 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1615 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1616 * @retval None
1617 */
LL_DAC_SetOutputConnection(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputConnection)1618 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
1619 {
1620 MODIFY_REG(DACx->MCR,
1621 (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1622 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1623 }
1624
1625 /**
1626 * @brief Get the output connection for the selected DAC channel.
1627 * @note On this STM32 series, output connection depends on output mode (normal or
1628 * sample and hold) and output buffer state.
1629 * - if output connection is set to internal path and output buffer
1630 * is enabled (whatever output mode):
1631 * output connection is also connected to GPIO pin
1632 * (both connections to GPIO pin and internal path).
1633 * - if output connection is set to GPIO pin, output buffer
1634 * is disabled, output mode set to sample and hold:
1635 * output connection is also connected to internal path
1636 * (both connections to GPIO pin and internal path).
1637 * @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
1638 * CR MODE2 LL_DAC_GetOutputConnection
1639 * @param DACx DAC instance
1640 * @param DAC_Channel This parameter can be one of the following values:
1641 * @arg @ref LL_DAC_CHANNEL_1
1642 * @arg @ref LL_DAC_CHANNEL_2 (1)
1643 *
1644 * (1) On this STM32 series, parameter not available on all instances.
1645 * Refer to device datasheet for channels availability.
1646 * @retval Returned value can be one of the following values:
1647 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1648 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1649 */
LL_DAC_GetOutputConnection(DAC_TypeDef * DACx,uint32_t DAC_Channel)1650 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1651 {
1652 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1653 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1654 );
1655 }
1656
1657 /**
1658 * @brief Set the sample-and-hold timing for the selected DAC channel:
1659 * sample time
1660 * @note Sample time must be set when DAC channel is disabled
1661 * or during DAC operation when DAC channel flag BWSTx is reset,
1662 * otherwise the setting is ignored.
1663 * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
1664 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
1665 * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
1666 * @param DACx DAC instance
1667 * @param DAC_Channel This parameter can be one of the following values:
1668 * @arg @ref LL_DAC_CHANNEL_1
1669 * @arg @ref LL_DAC_CHANNEL_2 (1)
1670 *
1671 * (1) On this STM32 series, parameter not available on all instances.
1672 * Refer to device datasheet for channels availability.
1673 * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
1674 * @retval None
1675 */
LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t SampleTime)1676 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
1677 {
1678 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1679 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1680
1681 MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
1682 }
1683
1684 /**
1685 * @brief Get the sample-and-hold timing for the selected DAC channel:
1686 * sample time
1687 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
1688 * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
1689 * @param DACx DAC instance
1690 * @param DAC_Channel This parameter can be one of the following values:
1691 * @arg @ref LL_DAC_CHANNEL_1
1692 * @arg @ref LL_DAC_CHANNEL_2 (1)
1693 *
1694 * (1) On this STM32 series, parameter not available on all instances.
1695 * Refer to device datasheet for channels availability.
1696 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1697 */
LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef * DACx,uint32_t DAC_Channel)1698 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1699 {
1700 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1701 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1702
1703 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
1704 }
1705
1706 /**
1707 * @brief Set the sample-and-hold timing for the selected DAC channel:
1708 * hold time
1709 * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
1710 * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
1711 * @param DACx DAC instance
1712 * @param DAC_Channel This parameter can be one of the following values:
1713 * @arg @ref LL_DAC_CHANNEL_1
1714 * @arg @ref LL_DAC_CHANNEL_2 (1)
1715 *
1716 * (1) On this STM32 series, parameter not available on all instances.
1717 * Refer to device datasheet for channels availability.
1718 * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
1719 * @retval None
1720 */
LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t HoldTime)1721 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
1722 {
1723 MODIFY_REG(DACx->SHHR,
1724 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1725 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1726 }
1727
1728 /**
1729 * @brief Get the sample-and-hold timing for the selected DAC channel:
1730 * hold time
1731 * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
1732 * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
1733 * @param DACx DAC instance
1734 * @param DAC_Channel This parameter can be one of the following values:
1735 * @arg @ref LL_DAC_CHANNEL_1
1736 * @arg @ref LL_DAC_CHANNEL_2 (1)
1737 *
1738 * (1) On this STM32 series, parameter not available on all instances.
1739 * Refer to device datasheet for channels availability.
1740 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1741 */
LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef * DACx,uint32_t DAC_Channel)1742 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1743 {
1744 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1745 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1746 );
1747 }
1748
1749 /**
1750 * @brief Set the sample-and-hold timing for the selected DAC channel:
1751 * refresh time
1752 * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
1753 * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
1754 * @param DACx DAC instance
1755 * @param DAC_Channel This parameter can be one of the following values:
1756 * @arg @ref LL_DAC_CHANNEL_1
1757 * @arg @ref LL_DAC_CHANNEL_2 (1)
1758 *
1759 * (1) On this STM32 series, parameter not available on all instances.
1760 * Refer to device datasheet for channels availability.
1761 * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
1762 * @retval None
1763 */
LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t RefreshTime)1764 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
1765 {
1766 MODIFY_REG(DACx->SHRR,
1767 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1768 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1769 }
1770
1771 /**
1772 * @brief Get the sample-and-hold timing for the selected DAC channel:
1773 * refresh time
1774 * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
1775 * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
1776 * @param DACx DAC instance
1777 * @param DAC_Channel This parameter can be one of the following values:
1778 * @arg @ref LL_DAC_CHANNEL_1
1779 * @arg @ref LL_DAC_CHANNEL_2 (1)
1780 *
1781 * (1) On this STM32 series, parameter not available on all instances.
1782 * Refer to device datasheet for channels availability.
1783 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1784 */
LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef * DACx,uint32_t DAC_Channel)1785 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1786 {
1787 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1788 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1789 );
1790 }
1791
1792 /**
1793 * @brief Set the signed format for the selected DAC channel.
1794 * @note On this STM32 series, signed format can be used to inject
1795 * Q1.15, Q1.11, Q1.7 signed format data to DAC.
1796 * Ex when using 12bits data format (Q1.11 is used):
1797 * 0x800 will output 0v level
1798 * 0xFFF will output mid-scale level
1799 * 0x000 will output mid-scale level
1800 * 0x7FF will output full-scale level
1801 * @rmtoll MCR SINFORMAT1 LL_DAC_SetSignedFormat\n
1802 * MCR SINFORMAT2 LL_DAC_SetSignedFormat
1803 * @param DACx DAC instance
1804 * @param DAC_Channel This parameter can be one of the following values:
1805 * @arg @ref LL_DAC_CHANNEL_1
1806 * @arg @ref LL_DAC_CHANNEL_2 (1)
1807 *
1808 * (1) On this STM32 series, parameter not available on all instances.
1809 * Refer to device datasheet for channels availability.
1810 * @param SignedFormat This parameter can be one of the following values:
1811 * @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
1812 * @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
1813 * @retval None
1814 */
LL_DAC_SetSignedFormat(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t SignedFormat)1815 __STATIC_INLINE void LL_DAC_SetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SignedFormat)
1816 {
1817 MODIFY_REG(DACx->MCR,
1818 DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1819 SignedFormat << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1820 }
1821
1822 /**
1823 * @brief Get the signed format state for the selected DAC channel.
1824 * @rmtoll MCR SINFORMAT1 LL_DAC_GetSignedFormat\n
1825 * MCR SINFORMAT2 LL_DAC_GetSignedFormat
1826 * @param DACx DAC instance
1827 * @param DAC_Channel This parameter can be one of the following values:
1828 * @arg @ref LL_DAC_CHANNEL_1
1829 * @arg @ref LL_DAC_CHANNEL_2 (1)
1830 *
1831 * (1) On this STM32 series, parameter not available on all instances.
1832 * Refer to device datasheet for channels availability.
1833 * @retval Returned value can be one of the following values:
1834 * @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
1835 * @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
1836 */
LL_DAC_GetSignedFormat(DAC_TypeDef * DACx,uint32_t DAC_Channel)1837 __STATIC_INLINE uint32_t LL_DAC_GetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1838 {
1839 return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1840 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1841 );
1842 }
1843
1844 /**
1845 * @}
1846 */
1847
1848 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
1849 * @{
1850 */
1851
1852 /**
1853 * @brief Enable DAC DMA transfer request of the selected channel.
1854 * @note To configure DMA source address (peripheral address),
1855 * use function @ref LL_DAC_DMA_GetRegAddr().
1856 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
1857 * CR DMAEN2 LL_DAC_EnableDMAReq
1858 * @param DACx DAC instance
1859 * @param DAC_Channel This parameter can be one of the following values:
1860 * @arg @ref LL_DAC_CHANNEL_1
1861 * @arg @ref LL_DAC_CHANNEL_2 (1)
1862 *
1863 * (1) On this STM32 series, parameter not available on all instances.
1864 * Refer to device datasheet for channels availability.
1865 * @retval None
1866 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1867 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1868 {
1869 SET_BIT(DACx->CR,
1870 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1871 }
1872
1873 /**
1874 * @brief Disable DAC DMA transfer request of the selected channel.
1875 * @note To configure DMA source address (peripheral address),
1876 * use function @ref LL_DAC_DMA_GetRegAddr().
1877 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
1878 * CR DMAEN2 LL_DAC_DisableDMAReq
1879 * @param DACx DAC instance
1880 * @param DAC_Channel This parameter can be one of the following values:
1881 * @arg @ref LL_DAC_CHANNEL_1
1882 * @arg @ref LL_DAC_CHANNEL_2 (1)
1883 *
1884 * (1) On this STM32 series, parameter not available on all instances.
1885 * Refer to device datasheet for channels availability.
1886 * @retval None
1887 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1888 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1889 {
1890 CLEAR_BIT(DACx->CR,
1891 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1892 }
1893
1894 /**
1895 * @brief Get DAC DMA transfer request state of the selected channel.
1896 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
1897 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
1898 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
1899 * @param DACx DAC instance
1900 * @param DAC_Channel This parameter can be one of the following values:
1901 * @arg @ref LL_DAC_CHANNEL_1
1902 * @arg @ref LL_DAC_CHANNEL_2 (1)
1903 *
1904 * (1) On this STM32 series, parameter not available on all instances.
1905 * Refer to device datasheet for channels availability.
1906 * @retval State of bit (1 or 0).
1907 */
LL_DAC_IsDMAReqEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1908 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1909 {
1910 return ((READ_BIT(DACx->CR,
1911 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1912 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1913 }
1914
1915 /**
1916 * @brief Enable DAC DMA Double data mode of the selected channel.
1917 * @rmtoll MCR DMADOUBLE1 LL_DAC_EnableDMADoubleDataMode\n
1918 * MCR DMADOUBLE2 LL_DAC_EnableDMADoubleDataMode
1919 * @param DACx DAC instance
1920 * @param DAC_Channel This parameter can be one of the following values:
1921 * @arg @ref LL_DAC_CHANNEL_1
1922 * @arg @ref LL_DAC_CHANNEL_2 (1)
1923 *
1924 * (1) On this STM32 series, parameter not available on all instances.
1925 * Refer to device datasheet for channels availability.
1926 * @retval None
1927 */
LL_DAC_EnableDMADoubleDataMode(DAC_TypeDef * DACx,uint32_t DAC_Channel)1928 __STATIC_INLINE void LL_DAC_EnableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1929 {
1930 SET_BIT(DACx->MCR,
1931 DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1932 }
1933
1934 /**
1935 * @brief Disable DAC DMA Double data mode of the selected channel.
1936 * @rmtoll MCR DMADOUBLE1 LL_DAC_DisableDMADoubleDataMode\n
1937 * MCR DMADOUBLE2 LL_DAC_DisableDMADoubleDataMode
1938 * @param DACx DAC instance
1939 * @param DAC_Channel This parameter can be one of the following values:
1940 * @arg @ref LL_DAC_CHANNEL_1
1941 * @arg @ref LL_DAC_CHANNEL_2 (1)
1942 *
1943 * (1) On this STM32 series, parameter not available on all instances.
1944 * Refer to device datasheet for channels availability.
1945 * @retval None
1946 */
LL_DAC_DisableDMADoubleDataMode(DAC_TypeDef * DACx,uint32_t DAC_Channel)1947 __STATIC_INLINE void LL_DAC_DisableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1948 {
1949 CLEAR_BIT(DACx->MCR,
1950 DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1951 }
1952
1953 /**
1954 * @brief Get DAC DMA double data mode state of the selected channel.
1955 * (0: DAC DMA double data mode is disabled, 1: DAC DMA double data mode is enabled)
1956 * @rmtoll MCR DMADOUBLE1 LL_DAC_IsDMADoubleDataModeEnabled\n
1957 * MCR DMADOUBLE2 LL_DAC_IsDMADoubleDataModeEnabled
1958 * @param DACx DAC instance
1959 * @param DAC_Channel This parameter can be one of the following values:
1960 * @arg @ref LL_DAC_CHANNEL_1
1961 * @arg @ref LL_DAC_CHANNEL_2 (1)
1962 *
1963 * (1) On this STM32 series, parameter not available on all instances.
1964 * Refer to device datasheet for channels availability.
1965 * @retval State of bit (1 or 0).
1966 */
LL_DAC_IsDMADoubleDataModeEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1967 __STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1968 {
1969 return ((READ_BIT(DACx->MCR,
1970 DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1971 == (DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1972 }
1973
1974 /**
1975 * @brief Function to help to configure DMA transfer to DAC: retrieve the
1976 * DAC register address from DAC instance and a list of DAC registers
1977 * intended to be used (most commonly) with DMA transfer.
1978 * @note These DAC registers are data holding registers:
1979 * when DAC conversion is requested, DAC generates a DMA transfer
1980 * request to have data available in DAC data holding registers.
1981 * @note This macro is intended to be used with LL DMA driver, refer to
1982 * function "LL_DMA_ConfigAddresses()".
1983 * Example:
1984 * LL_DMA_ConfigAddresses(DMA1,
1985 * LL_DMA_CHANNEL_1,
1986 * (uint32_t)&< array or variable >,
1987 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
1988 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
1989 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
1990 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1991 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1992 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1993 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1994 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1995 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
1996 * @param DACx DAC instance
1997 * @param DAC_Channel This parameter can be one of the following values:
1998 * @arg @ref LL_DAC_CHANNEL_1
1999 * @arg @ref LL_DAC_CHANNEL_2 (1)
2000 *
2001 * (1) On this STM32 series, parameter not available on all instances.
2002 * Refer to device datasheet for channels availability.
2003 * @param Register This parameter can be one of the following values:
2004 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
2005 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
2006 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
2007 * @retval DAC register address
2008 */
LL_DAC_DMA_GetRegAddr(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)2009 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
2010 {
2011 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
2012 /* DAC channel selected. */
2013 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
2014 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
2015 }
2016 /**
2017 * @}
2018 */
2019
2020 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
2021 * @{
2022 */
2023
2024 /**
2025 * @brief Enable DAC selected channel.
2026 * @rmtoll CR EN1 LL_DAC_Enable\n
2027 * CR EN2 LL_DAC_Enable
2028 * @note After enable from off state, DAC channel requires a delay
2029 * for output voltage to reach accuracy +/- 1 LSB.
2030 * Refer to device datasheet, parameter "tWAKEUP".
2031 * @param DACx DAC instance
2032 * @param DAC_Channel This parameter can be one of the following values:
2033 * @arg @ref LL_DAC_CHANNEL_1
2034 * @arg @ref LL_DAC_CHANNEL_2 (1)
2035 *
2036 * (1) On this STM32 series, parameter not available on all instances.
2037 * Refer to device datasheet for channels availability.
2038 * @retval None
2039 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)2040 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
2041 {
2042 SET_BIT(DACx->CR,
2043 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
2044 }
2045
2046 /**
2047 * @brief Disable DAC selected channel.
2048 * @rmtoll CR EN1 LL_DAC_Disable\n
2049 * CR EN2 LL_DAC_Disable
2050 * @param DACx DAC instance
2051 * @param DAC_Channel This parameter can be one of the following values:
2052 * @arg @ref LL_DAC_CHANNEL_1
2053 * @arg @ref LL_DAC_CHANNEL_2 (1)
2054 *
2055 * (1) On this STM32 series, parameter not available on all instances.
2056 * Refer to device datasheet for channels availability.
2057 * @retval None
2058 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)2059 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
2060 {
2061 CLEAR_BIT(DACx->CR,
2062 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
2063 }
2064
2065 /**
2066 * @brief Get DAC enable state of the selected channel.
2067 * (0: DAC channel is disabled, 1: DAC channel is enabled)
2068 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
2069 * CR EN2 LL_DAC_IsEnabled
2070 * @param DACx DAC instance
2071 * @param DAC_Channel This parameter can be one of the following values:
2072 * @arg @ref LL_DAC_CHANNEL_1
2073 * @arg @ref LL_DAC_CHANNEL_2 (1)
2074 *
2075 * (1) On this STM32 series, parameter not available on all instances.
2076 * Refer to device datasheet for channels availability.
2077 * @retval State of bit (1 or 0).
2078 */
LL_DAC_IsEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)2079 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
2080 {
2081 return ((READ_BIT(DACx->CR,
2082 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
2083 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
2084 }
2085
2086 /**
2087 * @brief Get DAC ready for conversion state of the selected channel.
2088 * (0: DAC channel is not ready, 1: DAC channel is ready)
2089 * @rmtoll SR DAC1RDY LL_DAC_IsReady\n
2090 * SR DAC2RDY LL_DAC_IsReady
2091 * @param DACx DAC instance
2092 * @param DAC_Channel This parameter can be one of the following values:
2093 * @arg @ref LL_DAC_CHANNEL_1
2094 * @arg @ref LL_DAC_CHANNEL_2 (1)
2095 *
2096 * (1) On this STM32 series, parameter not available on all instances.
2097 * Refer to device datasheet for channels availability.
2098 * @retval State of bit (1 or 0).
2099 */
LL_DAC_IsReady(DAC_TypeDef * DACx,uint32_t DAC_Channel)2100 __STATIC_INLINE uint32_t LL_DAC_IsReady(DAC_TypeDef *DACx, uint32_t DAC_Channel)
2101 {
2102 return ((READ_BIT(DACx->SR,
2103 DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
2104 == (DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
2105 }
2106
2107 /**
2108 * @brief Enable DAC trigger of the selected channel.
2109 * @note - If DAC trigger is disabled, DAC conversion is performed
2110 * automatically once the data holding register is updated,
2111 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
2112 * @ref LL_DAC_ConvertData12RightAligned(), ...
2113 * - If DAC trigger is enabled, DAC conversion is performed
2114 * only when a hardware of software trigger event is occurring.
2115 * Select trigger source using
2116 * function @ref LL_DAC_SetTriggerSource().
2117 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
2118 * CR TEN2 LL_DAC_EnableTrigger
2119 * @param DACx DAC instance
2120 * @param DAC_Channel This parameter can be one of the following values:
2121 * @arg @ref LL_DAC_CHANNEL_1
2122 * @arg @ref LL_DAC_CHANNEL_2 (1)
2123 *
2124 * (1) On this STM32 series, parameter not available on all instances.
2125 * Refer to device datasheet for channels availability.
2126 * @retval None
2127 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)2128 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
2129 {
2130 SET_BIT(DACx->CR,
2131 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
2132 }
2133
2134 /**
2135 * @brief Disable DAC trigger of the selected channel.
2136 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
2137 * CR TEN2 LL_DAC_DisableTrigger
2138 * @param DACx DAC instance
2139 * @param DAC_Channel This parameter can be one of the following values:
2140 * @arg @ref LL_DAC_CHANNEL_1
2141 * @arg @ref LL_DAC_CHANNEL_2 (1)
2142 *
2143 * (1) On this STM32 series, parameter not available on all instances.
2144 * Refer to device datasheet for channels availability.
2145 * @retval None
2146 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)2147 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
2148 {
2149 CLEAR_BIT(DACx->CR,
2150 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
2151 }
2152
2153 /**
2154 * @brief Get DAC trigger state of the selected channel.
2155 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
2156 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
2157 * CR TEN2 LL_DAC_IsTriggerEnabled
2158 * @param DACx DAC instance
2159 * @param DAC_Channel This parameter can be one of the following values:
2160 * @arg @ref LL_DAC_CHANNEL_1
2161 * @arg @ref LL_DAC_CHANNEL_2 (1)
2162 *
2163 * (1) On this STM32 series, parameter not available on all instances.
2164 * Refer to device datasheet for channels availability.
2165 * @retval State of bit (1 or 0).
2166 */
LL_DAC_IsTriggerEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)2167 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
2168 {
2169 return ((READ_BIT(DACx->CR,
2170 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
2171 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
2172 }
2173
2174 /**
2175 * @brief Trig DAC conversion by software for the selected DAC channel.
2176 * @note Preliminarily, DAC trigger must be set to software trigger
2177 * using function
2178 * @ref LL_DAC_Init()
2179 * @ref LL_DAC_SetTriggerSource()
2180 * @ref LL_DAC_SetWaveSawtoothResetTriggerSource() (1)
2181 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
2182 * and DAC trigger must be enabled using
2183 * function @ref LL_DAC_EnableTrigger().
2184 *
2185 * (1) In case, Sawtooth wave generation has been configured.
2186 * @note For devices featuring DAC with 2 channels: this function
2187 * can perform a SW start of both DAC channels simultaneously.
2188 * Two channels can be selected as parameter.
2189 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
2190 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
2191 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
2192 * @param DACx DAC instance
2193 * @param DAC_Channel This parameter can a combination of the following values:
2194 * @arg @ref LL_DAC_CHANNEL_1
2195 * @arg @ref LL_DAC_CHANNEL_2 (1)
2196 *
2197 * (1) On this STM32 series, parameter not available on all instances.
2198 * Refer to device datasheet for channels availability.
2199 * @retval None
2200 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)2201 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
2202 {
2203 SET_BIT(DACx->SWTRIGR,
2204 (DAC_Channel & DAC_SWTR_CHX_MASK));
2205 }
2206
2207 /**
2208 * @brief Trig DAC conversion by secondary software trigger for the selected DAC channel.
2209 * @note Preliminarily, DAC secondary trigger must be set to software trigger
2210 * using function
2211 * @ref LL_DAC_Init()
2212 * @ref LL_DAC_SetWaveSawtoothStepTriggerSource() (1)
2213 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
2214 * and DAC trigger must be enabled using
2215 * function @ref LL_DAC_EnableTrigger().
2216 *
2217 * (1) In case, Sawtooth wave generation has been configured.
2218 * @note For devices featuring DAC with 2 channels: this function
2219 * can perform a SW start of both DAC channels simultaneously.
2220 * Two channels can be selected as parameter.
2221 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
2222 * @rmtoll SWTRIGR SWTRIGB1 LL_DAC_TrigSWConversion2\n
2223 * SWTRIGR SWTRIGB2 LL_DAC_TrigSWConversion2
2224 * @param DACx DAC instance
2225 * @param DAC_Channel This parameter can a combination of the following values:
2226 * @arg @ref LL_DAC_CHANNEL_1
2227 * @arg @ref LL_DAC_CHANNEL_2 (1)
2228 *
2229 * (1) On this STM32 series, parameter not available on all instances.
2230 * Refer to device datasheet for channels availability.
2231 * @retval None
2232 */
LL_DAC_TrigSWConversion2(DAC_TypeDef * DACx,uint32_t DAC_Channel)2233 __STATIC_INLINE void LL_DAC_TrigSWConversion2(DAC_TypeDef *DACx, uint32_t DAC_Channel)
2234 {
2235 SET_BIT(DACx->SWTRIGR,
2236 (DAC_Channel & DAC_SWTRB_CHX_MASK));
2237 }
2238
2239 /**
2240 * @brief Set the data to be loaded in the data holding register
2241 * in format 12 bits left alignment (LSB aligned on bit 0),
2242 * for the selected DAC channel.
2243 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
2244 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
2245 * @param DACx DAC instance
2246 * @param DAC_Channel This parameter can be one of the following values:
2247 * @arg @ref LL_DAC_CHANNEL_1
2248 * @arg @ref LL_DAC_CHANNEL_2 (1)
2249 *
2250 * (1) On this STM32 series, parameter not available on all instances.
2251 * Refer to device datasheet for channels availability.
2252 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
2253 * @retval None
2254 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)2255 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
2256 {
2257 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
2258 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
2259
2260 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
2261 }
2262
2263 /**
2264 * @brief Set the data to be loaded in the data holding register
2265 * in format 12 bits left alignment (MSB aligned on bit 15),
2266 * for the selected DAC channel.
2267 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
2268 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
2269 * @param DACx DAC instance
2270 * @param DAC_Channel This parameter can be one of the following values:
2271 * @arg @ref LL_DAC_CHANNEL_1
2272 * @arg @ref LL_DAC_CHANNEL_2 (1)
2273 *
2274 * (1) On this STM32 series, parameter not available on all instances.
2275 * Refer to device datasheet for channels availability.
2276 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
2277 * @retval None
2278 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)2279 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
2280 {
2281 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
2282 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
2283
2284 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
2285 }
2286
2287 /**
2288 * @brief Set the data to be loaded in the data holding register
2289 * in format 8 bits left alignment (LSB aligned on bit 0),
2290 * for the selected DAC channel.
2291 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
2292 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
2293 * @param DACx DAC instance
2294 * @param DAC_Channel This parameter can be one of the following values:
2295 * @arg @ref LL_DAC_CHANNEL_1
2296 * @arg @ref LL_DAC_CHANNEL_2 (1)
2297 *
2298 * (1) On this STM32 series, parameter not available on all instances.
2299 * Refer to device datasheet for channels availability.
2300 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
2301 * @retval None
2302 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)2303 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
2304 {
2305 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
2306 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
2307
2308 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
2309 }
2310
2311
2312 /**
2313 * @brief Set the data to be loaded in the data holding register
2314 * in format 12 bits left alignment (LSB aligned on bit 0),
2315 * for both DAC channels.
2316 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
2317 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
2318 * @param DACx DAC instance
2319 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
2320 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
2321 * @retval None
2322 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)2323 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
2324 uint32_t DataChannel2)
2325 {
2326 MODIFY_REG(DACx->DHR12RD,
2327 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
2328 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
2329 }
2330
2331 /**
2332 * @brief Set the data to be loaded in the data holding register
2333 * in format 12 bits left alignment (MSB aligned on bit 15),
2334 * for both DAC channels.
2335 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
2336 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
2337 * @param DACx DAC instance
2338 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
2339 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
2340 * @retval None
2341 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)2342 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
2343 uint32_t DataChannel2)
2344 {
2345 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
2346 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
2347 /* the 4 LSB must be taken into account for the shift value. */
2348 MODIFY_REG(DACx->DHR12LD,
2349 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
2350 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
2351 }
2352
2353 /**
2354 * @brief Set the data to be loaded in the data holding register
2355 * in format 8 bits left alignment (LSB aligned on bit 0),
2356 * for both DAC channels.
2357 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
2358 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
2359 * @param DACx DAC instance
2360 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
2361 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
2362 * @retval None
2363 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)2364 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
2365 uint32_t DataChannel2)
2366 {
2367 MODIFY_REG(DACx->DHR8RD,
2368 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
2369 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
2370 }
2371
2372
2373 /**
2374 * @brief Retrieve output data currently generated for the selected DAC channel.
2375 * @note Whatever alignment and resolution settings
2376 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
2377 * @ref LL_DAC_ConvertData12RightAligned(), ...),
2378 * output data format is 12 bits right aligned (LSB aligned on bit 0).
2379 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
2380 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
2381 * @param DACx DAC instance
2382 * @param DAC_Channel This parameter can be one of the following values:
2383 * @arg @ref LL_DAC_CHANNEL_1
2384 * @arg @ref LL_DAC_CHANNEL_2 (1)
2385 *
2386 * (1) On this STM32 series, parameter not available on all instances.
2387 * Refer to device datasheet for channels availability.
2388 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2389 */
LL_DAC_RetrieveOutputData(DAC_TypeDef * DACx,uint32_t DAC_Channel)2390 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
2391 {
2392 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
2393 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
2394
2395 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
2396 }
2397
2398 /**
2399 * @}
2400 */
2401
2402 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
2403 * @{
2404 */
2405
2406 /**
2407 * @brief Get DAC calibration offset flag for DAC channel 1
2408 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
2409 * @param DACx DAC instance
2410 * @retval State of bit (1 or 0).
2411 */
LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef * DACx)2412 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
2413 {
2414 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
2415 }
2416
2417
2418 /**
2419 * @brief Get DAC calibration offset flag for DAC channel 2
2420 * @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
2421 * @param DACx DAC instance
2422 * @retval State of bit (1 or 0).
2423 */
LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef * DACx)2424 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
2425 {
2426 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
2427 }
2428
2429
2430 /**
2431 * @brief Get DAC busy writing sample time flag for DAC channel 1
2432 * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
2433 * @param DACx DAC instance
2434 * @retval State of bit (1 or 0).
2435 */
LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef * DACx)2436 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
2437 {
2438 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
2439 }
2440
2441 /**
2442 * @brief Get DAC busy writing sample time flag for DAC channel 2
2443 * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
2444 * @param DACx DAC instance
2445 * @retval State of bit (1 or 0).
2446 */
LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef * DACx)2447 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
2448 {
2449 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
2450 }
2451
2452
2453 /**
2454 * @brief Get DAC ready status flag for DAC channel 1
2455 * @rmtoll SR DAC1RDY LL_DAC_IsActiveFlag_DAC1RDY
2456 * @param DACx DAC instance
2457 * @retval State of bit (1 or 0).
2458 */
LL_DAC_IsActiveFlag_DAC1RDY(DAC_TypeDef * DACx)2459 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC1RDY(DAC_TypeDef *DACx)
2460 {
2461 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC1RDY) == (LL_DAC_FLAG_DAC1RDY)) ? 1UL : 0UL);
2462 }
2463
2464
2465 /**
2466 * @brief Get DAC ready status flag for DAC channel 2
2467 * @rmtoll SR DAC2RDY LL_DAC_IsActiveFlag_DAC2RDY
2468 * @param DACx DAC instance
2469 * @retval State of bit (1 or 0).
2470 */
LL_DAC_IsActiveFlag_DAC2RDY(DAC_TypeDef * DACx)2471 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC2RDY(DAC_TypeDef *DACx)
2472 {
2473 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC2RDY) == (LL_DAC_FLAG_DAC2RDY)) ? 1UL : 0UL);
2474 }
2475
2476
2477 /**
2478 * @brief Get DAC output register status flag for DAC channel 1
2479 * @rmtoll SR DORSTAT1 LL_DAC_IsActiveFlag_DORSTAT1
2480 * @param DACx DAC instance
2481 * @retval State of bit (1 or 0).
2482 */
LL_DAC_IsActiveFlag_DORSTAT1(DAC_TypeDef * DACx)2483 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT1(DAC_TypeDef *DACx)
2484 {
2485 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT1) == (LL_DAC_FLAG_DORSTAT1)) ? 1UL : 0UL);
2486 }
2487
2488
2489 /**
2490 * @brief Get DAC output register status flag for DAC channel 2
2491 * @rmtoll SR DORSTAT2 LL_DAC_IsActiveFlag_DORSTAT2
2492 * @param DACx DAC instance
2493 * @retval State of bit (1 or 0).
2494 */
LL_DAC_IsActiveFlag_DORSTAT2(DAC_TypeDef * DACx)2495 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT2(DAC_TypeDef *DACx)
2496 {
2497 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT2) == (LL_DAC_FLAG_DORSTAT2)) ? 1UL : 0UL);
2498 }
2499
2500 /**
2501 * @brief Get DAC underrun flag for DAC channel 1
2502 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
2503 * @param DACx DAC instance
2504 * @retval State of bit (1 or 0).
2505 */
LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef * DACx)2506 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
2507 {
2508 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
2509 }
2510
2511
2512 /**
2513 * @brief Get DAC underrun flag for DAC channel 2
2514 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
2515 * @param DACx DAC instance
2516 * @retval State of bit (1 or 0).
2517 */
LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef * DACx)2518 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
2519 {
2520 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
2521 }
2522
2523
2524 /**
2525 * @brief Clear DAC underrun flag for DAC channel 1
2526 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
2527 * @param DACx DAC instance
2528 * @retval None
2529 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)2530 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
2531 {
2532 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
2533 }
2534
2535
2536 /**
2537 * @brief Clear DAC underrun flag for DAC channel 2
2538 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
2539 * @param DACx DAC instance
2540 * @retval None
2541 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)2542 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
2543 {
2544 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
2545 }
2546
2547
2548 /**
2549 * @}
2550 */
2551
2552 /** @defgroup DAC_LL_EF_IT_Management IT management
2553 * @{
2554 */
2555
2556 /**
2557 * @brief Enable DMA underrun interrupt for DAC channel 1
2558 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
2559 * @param DACx DAC instance
2560 * @retval None
2561 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)2562 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
2563 {
2564 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
2565 }
2566
2567
2568 /**
2569 * @brief Enable DMA underrun interrupt for DAC channel 2
2570 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
2571 * @param DACx DAC instance
2572 * @retval None
2573 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)2574 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
2575 {
2576 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
2577 }
2578
2579
2580 /**
2581 * @brief Disable DMA underrun interrupt for DAC channel 1
2582 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
2583 * @param DACx DAC instance
2584 * @retval None
2585 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)2586 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
2587 {
2588 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
2589 }
2590
2591
2592 /**
2593 * @brief Disable DMA underrun interrupt for DAC channel 2
2594 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
2595 * @param DACx DAC instance
2596 * @retval None
2597 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)2598 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
2599 {
2600 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
2601 }
2602
2603
2604 /**
2605 * @brief Get DMA underrun interrupt for DAC channel 1
2606 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
2607 * @param DACx DAC instance
2608 * @retval State of bit (1 or 0).
2609 */
LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef * DACx)2610 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
2611 {
2612 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
2613 }
2614
2615
2616 /**
2617 * @brief Get DMA underrun interrupt for DAC channel 2
2618 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
2619 * @param DACx DAC instance
2620 * @retval State of bit (1 or 0).
2621 */
LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef * DACx)2622 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
2623 {
2624 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
2625 }
2626
2627
2628 /**
2629 * @}
2630 */
2631
2632 #if defined(USE_FULL_LL_DRIVER)
2633 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
2634 * @{
2635 */
2636
2637 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
2638 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
2639 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
2640
2641 /**
2642 * @}
2643 */
2644 #endif /* USE_FULL_LL_DRIVER */
2645
2646 /**
2647 * @}
2648 */
2649
2650 /**
2651 * @}
2652 */
2653
2654 #endif /* DAC1 || DAC2 || DAC3 || DAC4 */
2655
2656 /**
2657 * @}
2658 */
2659
2660 #ifdef __cplusplus
2661 }
2662 #endif
2663
2664 #endif /* STM32G4xx_LL_DAC_H */
2665
2666
