1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32G4xx_LL_ADC_H
21 #define STM32G4xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g4xx.h"
29
30 /** @addtogroup STM32G4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer register offset */
51 /* - sequencer rank bits position into the selected register */
52
53 /* Internal register offset for ADC group regular sequencer configuration */
54 /* (offset placed into a spare area of literal definition) */
55 #define ADC_SQR1_REGOFFSET (0x00000000UL)
56 #define ADC_SQR2_REGOFFSET (0x00000100UL)
57 #define ADC_SQR3_REGOFFSET (0x00000200UL)
58 #define ADC_SQR4_REGOFFSET (0x00000300UL)
59
60 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
61 | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
62 #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
63 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
64
65 /* Definition of ADC group regular sequencer bits information to be inserted */
66 /* into ADC group regular sequencer ranks literals definition. */
67 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos)
68 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos)
69 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos)
70 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos)
71 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR2_SQ5_Pos)
72 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR2_SQ6_Pos)
73 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR2_SQ7_Pos)
74 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos)
75 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos)
76 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos)
77 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos)
78 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos)
79 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos)
80 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos)
81 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos)
82 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)
83
84
85
86 /* Internal mask for ADC group injected sequencer: */
87 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
88 /* - data register offset */
89 /* - sequencer rank bits position into the selected register */
90
91 /* Internal register offset for ADC group injected data register */
92 /* (offset placed into a spare area of literal definition) */
93 #define ADC_JDR1_REGOFFSET (0x00000000UL)
94 #define ADC_JDR2_REGOFFSET (0x00000100UL)
95 #define ADC_JDR3_REGOFFSET (0x00000200UL)
96 #define ADC_JDR4_REGOFFSET (0x00000300UL)
97
98 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
99 | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
100 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
101 #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
102
103 /* Definition of ADC group injected sequencer bits information to be inserted */
104 /* into ADC group injected sequencer ranks literals definition. */
105 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
106 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
107 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
108 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
109
110
111
112 /* Internal mask for ADC group regular trigger: */
113 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
114 /* - regular trigger source */
115 /* - regular trigger edge */
116 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
117
118 /* Mask containing trigger source masks for each of possible */
119 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
120 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
121 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
122 ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
123 ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
124 ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
125
126 /* Mask containing trigger edge masks for each of possible */
127 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
128 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
129 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
130 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
131 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
132 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
133
134 /* Definition of ADC group regular trigger bits information. */
135 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos)
136 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos)
137
138
139
140 /* Internal mask for ADC group injected trigger: */
141 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
142 /* - injected trigger source */
143 /* - injected trigger edge */
144 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
145
146 /* Mask containing trigger source masks for each of possible */
147 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
148 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
149 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
150 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
151 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
152 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
153
154 /* Mask containing trigger edge masks for each of possible */
155 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
156 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
157 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
158 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
159 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
160 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
161
162 /* Definition of ADC group injected trigger bits information. */
163 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos)
164 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos)
165
166
167
168
169
170
171 /* Internal mask for ADC channel: */
172 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
173 /* - channel identifier defined by number */
174 /* - channel identifier defined by bitfield */
175 /* - channel differentiation between external channels (connected to */
176 /* GPIO pins) and internal channels (connected to internal paths) */
177 /* - channel sampling time defined by SMPRx register offset */
178 /* and SMPx bits positions into SMPRx register */
179 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
180 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
181 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)
182 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
183 | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
184 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
185 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
186
187 /* Channel differentiation between external and internal channels */
188 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
189 #define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
190 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
191
192 /* Internal register offset for ADC channel sampling time configuration */
193 /* (offset placed into a spare area of literal definition) */
194 #define ADC_SMPR1_REGOFFSET (0x00000000UL)
195 #define ADC_SMPR2_REGOFFSET (0x02000000UL)
196 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
197 #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
198
199 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
200 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
201
202 /* Definition of channels ID number information to be inserted into */
203 /* channels literals definition. */
204 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
205 #define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)
206 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)
207 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
208 #define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)
209 #define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
210 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
211 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
212 #define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3)
213 #define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
214 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
215 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
216 #define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
217 #define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
218 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
219 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \
220 ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
221 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4)
222 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
223 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
224
225 /* Definition of channels ID bitfield information to be inserted into */
226 /* channels literals definition. */
227 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
228 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
229 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
230 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
231 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
232 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
233 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
234 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
235 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
236 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
237 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
238 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
239 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
240 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
241 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
242 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
243 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
244 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
245 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
246
247 /* Definition of channels sampling time information to be inserted into */
248 /* channels literals definition. */
249 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
250 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
251 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
252 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
253 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
254 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
255 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
256 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
257 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
258 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
259 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
260 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
261 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
262 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
263 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
264 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
265 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
266 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
267 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
268
269
270 /* Internal mask for ADC mode single or differential ended: */
271 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
272 /* the relevant bits for: */
273 /* (concatenation of multiple bits used in different registers) */
274 /* - ADC calibration: calibration start, calibration factor get or set */
275 /* - ADC channels: set each ADC channel ending mode */
276 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
277 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
278 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
279 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
280 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */
281 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */
282 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
283
284 /* Internal mask for ADC analog watchdog: */
285 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
286 /* (concatenation of multiple bits used in different analog watchdogs, */
287 /* (feature of several watchdogs not available on all STM32 families)). */
288 /* - analog watchdog 1: monitored channel defined by number, */
289 /* selection of ADC group (ADC groups regular and-or injected). */
290 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
291 /* selection on groups. */
292
293 /* Internal register offset for ADC analog watchdog channel configuration */
294 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
295 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
296 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
297
298 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
299 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
300 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
301 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
302
303 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
304
305 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
306 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
307 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
308
309 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
310
311 /* Internal register offset for ADC analog watchdog threshold configuration */
312 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
313 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
314 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
315 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
316 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
317 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
318 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
319 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
320
321 /* Internal mask for ADC offset: */
322 /* Internal register offset for ADC offset number configuration */
323 #define ADC_OFR1_REGOFFSET (0x00000000UL)
324 #define ADC_OFR2_REGOFFSET (0x00000001UL)
325 #define ADC_OFR3_REGOFFSET (0x00000002UL)
326 #define ADC_OFR4_REGOFFSET (0x00000003UL)
327 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
328 | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
329
330
331 /* ADC registers bits positions */
332 #define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)
333 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
334 #define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
335 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
336 #define ADC_TR1_HT1_BITOFFSET_POS (ADC_TR1_HT1_Pos)
337
338
339 /* ADC registers bits groups */
340 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
341
342
343 /* ADC internal channels related definitions */
344 /* Internal voltage reference VrefInt */
345 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
346 #define VREFINT_CAL_VREF (3000UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
347 /* Temperature sensor */
348 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32G4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
349 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32G4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
350 #define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
351 #define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
352 #define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
353
354 /**
355 * @}
356 */
357
358
359 /* Private macros ------------------------------------------------------------*/
360 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
361 * @{
362 */
363
364 /**
365 * @brief Driver macro reserved for internal use: set a pointer to
366 * a register from a register basis from which an offset
367 * is applied.
368 * @param __REG__ Register basis from which the offset is applied.
369 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
370 * @retval Pointer to register address
371 */
372 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
373 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
374
375 /**
376 * @}
377 */
378
379
380 /* Exported types ------------------------------------------------------------*/
381 #if defined(USE_FULL_LL_DRIVER)
382 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
383 * @{
384 */
385
386 /**
387 * @brief Structure definition of some features of ADC common parameters
388 * and multimode
389 * (all ADC instances belonging to the same ADC common instance).
390 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
391 * is conditioned to ADC instances state (all ADC instances
392 * sharing the same ADC common instance):
393 * All ADC instances sharing the same ADC common instance must be
394 * disabled.
395 */
396 typedef struct
397 {
398 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
399 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
400 @note On this STM32 series, if ADC group injected is used, some
401 clock ratio constraints between ADC clock and AHB clock
402 must be respected. Refer to reference manual.
403
404 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
405
406 #if defined(ADC_MULTIMODE_SUPPORT)
407 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
408 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
409
410 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
411
412 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
413 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
414
415 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
416
417 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
418 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
419
420 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
421 #endif /* ADC_MULTIMODE_SUPPORT */
422
423 } LL_ADC_CommonInitTypeDef;
424
425 /**
426 * @brief Structure definition of some features of ADC instance.
427 * @note These parameters have an impact on ADC scope: ADC instance.
428 * Affects both group regular and group injected (availability
429 * of ADC group injected depends on STM32 families).
430 * Refer to corresponding unitary functions into
431 * @ref ADC_LL_EF_Configuration_ADC_Instance .
432 * @note The setting of these parameters by function @ref LL_ADC_Init()
433 * is conditioned to ADC state:
434 * ADC instance must be disabled.
435 * This condition is applied to all ADC features, for efficiency
436 * and compatibility over all STM32 families. However, the different
437 * features can be set under different ADC state conditions
438 * (setting possible with ADC enabled without conversion on going,
439 * ADC enabled with conversion on going, ...)
440 * Each feature can be updated afterwards with a unitary function
441 * and potentially with ADC in a different state than disabled,
442 * refer to description of each function for setting
443 * conditioned to ADC state.
444 */
445 typedef struct
446 {
447 uint32_t Resolution; /*!< Set ADC resolution.
448 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
449
450 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
451
452 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
453 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
454
455 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
456
457 uint32_t LowPowerMode; /*!< Set ADC low power mode.
458 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
459
460 This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
461
462 } LL_ADC_InitTypeDef;
463
464 /**
465 * @brief Structure definition of some features of ADC group regular.
466 * @note These parameters have an impact on ADC scope: ADC group regular.
467 * Refer to corresponding unitary functions into
468 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
469 * (functions with prefix "REG").
470 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
471 * is conditioned to ADC state:
472 * ADC instance must be disabled.
473 * This condition is applied to all ADC features, for efficiency
474 * and compatibility over all STM32 families. However, the different
475 * features can be set under different ADC state conditions
476 * (setting possible with ADC enabled without conversion on going,
477 * ADC enabled with conversion on going, ...)
478 * Each feature can be updated afterwards with a unitary function
479 * and potentially with ADC in a different state than disabled,
480 * refer to description of each function for setting
481 * conditioned to ADC state.
482 */
483 typedef struct
484 {
485 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
486 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
487 @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
488 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
489 In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
490
491 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
492
493 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
494 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
495
496 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
497
498 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
499 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
500 @note This parameter has an effect only if group regular sequencer is enabled
501 (scan length of 2 ranks or more).
502
503 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
504
505 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
506 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
507 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
508
509 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
510
511 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
512 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
513
514 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
515
516 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
517 data preserved or overwritten.
518 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
519
520 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
521
522 } LL_ADC_REG_InitTypeDef;
523
524 /**
525 * @brief Structure definition of some features of ADC group injected.
526 * @note These parameters have an impact on ADC scope: ADC group injected.
527 * Refer to corresponding unitary functions into
528 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
529 * (functions with prefix "INJ").
530 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
531 * is conditioned to ADC state:
532 * ADC instance must be disabled.
533 * This condition is applied to all ADC features, for efficiency
534 * and compatibility over all STM32 families. However, the different
535 * features can be set under different ADC state conditions
536 * (setting possible with ADC enabled without conversion on going,
537 * ADC enabled with conversion on going, ...)
538 * Each feature can be updated afterwards with a unitary function
539 * and potentially with ADC in a different state than disabled,
540 * refer to description of each function for setting
541 * conditioned to ADC state.
542 */
543 typedef struct
544 {
545 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
546 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
547 @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
548 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
549 In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
550
551 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
552
553 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
554 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
555
556 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
557
558 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
559 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
560 @note This parameter has an effect only if group injected sequencer is enabled
561 (scan length of 2 ranks or more).
562
563 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
564
565 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
566 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
567 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
568
569 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
570
571 } LL_ADC_INJ_InitTypeDef;
572
573 /**
574 * @}
575 */
576 #endif /* USE_FULL_LL_DRIVER */
577
578 /* Exported constants --------------------------------------------------------*/
579 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
580 * @{
581 */
582
583 /** @defgroup ADC_LL_EC_FLAG ADC flags
584 * @brief Flags defines which can be used with LL_ADC_ReadReg function
585 * @{
586 */
587 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
588 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
589 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
590 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
591 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
592 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
593 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
594 #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */
595 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
596 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
597 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
598 #if defined(ADC_MULTIMODE_SUPPORT)
599 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
600 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
601 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */
602 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
603 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */
604 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
605 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
606 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
607 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */
608 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */
609 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */
610 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
611 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */
612 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
613 #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */
614 #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
615 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
616 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
617 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
618 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
619 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
620 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
621 #endif /* ADC_MULTIMODE_SUPPORT */
622 /**
623 * @}
624 */
625
626 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
627 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
628 * @{
629 */
630 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
631 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
632 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
633 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
634 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
635 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */
636 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */
637 #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */
638 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
639 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
640 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
641 /**
642 * @}
643 */
644
645 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
646 * @{
647 */
648 /* List of ADC registers intended to be used (most commonly) with */
649 /* DMA transfer. */
650 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
651 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
652 #if defined(ADC_MULTIMODE_SUPPORT)
653 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
654 #endif /* ADC_MULTIMODE_SUPPORT */
655 /**
656 * @}
657 */
658
659 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
660 * @{
661 */
662 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
663 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
664 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
665 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */
666 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */
667 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */
668 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */
669 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8 */
670 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10 */
671 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12 */
672 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 */
673 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */
674 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64 */
675 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128 */
676 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */
677 /**
678 * @}
679 */
680
681 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
682 * @{
683 */
684 /* Note: Other measurement paths to internal channels may be available */
685 /* (connections to other peripherals). */
686 /* If they are not listed below, they do not require any specific */
687 /* path enable. In this case, Access to measurement path is done */
688 /* only by selecting the corresponding ADC internal channel. */
689 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
690 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
691 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSESEL) /*!< ADC measurement path to internal channel temperature sensor */
692 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATSEL) /*!< ADC measurement path to internal channel Vbat */
693 /**
694 * @}
695 */
696
697 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
698 * @{
699 */
700 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
701 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
702 #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */
703 #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */
704 /**
705 * @}
706 */
707
708 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
709 * @{
710 */
711 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
712 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
713 /**
714 * @}
715 */
716
717 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
718 * @{
719 */
720 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
721 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
722 /**
723 * @}
724 */
725
726 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
727 * @{
728 */
729 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
730 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
731 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
732 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
733 /**
734 * @}
735 */
736
737 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
738 * @{
739 */
740 #define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
741 #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
742 /**
743 * @}
744 */
745
746 /** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
747 * @{
748 */
749 #define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative (among ADC selected offset number 1, 2, 3 or 4) */
750 #define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive (among ADC selected offset number 1, 2, 3 or 4) */
751 /**
752 * @}
753 */
754
755 /** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode
756 * @{
757 */
758 #define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */
759 #define LL_ADC_OFFSET_SATURATION_ENABLE (ADC_OFR1_SATEN) /*!< ADC offset saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */
760 /**
761 * @}
762 */
763 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
764 * @{
765 */
766 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
767 #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
768 #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
769 /**
770 * @}
771 */
772
773 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
774 * @{
775 */
776 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
777 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
778 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
779 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
780 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
781 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
782 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
783 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
784 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
785 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
786 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
787 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
788 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
789 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
790 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
791 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
792 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
793 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
794 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
795 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2. */
796 #define LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance. */
797 #define LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_4 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */
798 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 series, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */
799 #define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance. */
800 #define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance. */
801 #define LL_ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance. */
802 #define LL_ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */
803 #define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_5 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP4 availability */
804 #define LL_ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP5 availability */
805 #define LL_ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 & OPAMP6 availability */
806 /**
807 * @}
808 */
809
810 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
811 * @{
812 */
813 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!<
814 ADC group regular conversion trigger internal: SW start. */
815 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
816 ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
817 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
818 ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
819 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
820 ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
821 Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
822 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
823 ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
824 Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
825 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
826 ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
827 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
828 ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
829 #define LL_ADC_REG_TRIG_EXT_TIM2_CH1 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
830 ADC group regular conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
831 Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
832 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
833 ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
834 Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
835 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
836 ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
837 Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
838 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
839 ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
840 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
841 ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
842 Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
843 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
844 ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
845 Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
846 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
847 ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
848 #define LL_ADC_REG_TRIG_EXT_TIM4_CH1 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
849 ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
850 Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
851 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
852 ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
853 Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
854 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
855 ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
856 #define LL_ADC_REG_TRIG_EXT_TIM7_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
857 ADC group regular conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
858 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
859 ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
860 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
861 ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
862 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
863 ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
864 Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
865 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
866 ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
867 #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
868 ADC group regular conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting).
869 Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
870 #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
871 ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting).
872 Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
873 #define LL_ADC_REG_TRIG_EXT_TIM20_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
874 ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
875 Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
876 #define LL_ADC_REG_TRIG_EXT_TIM20_CH2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
877 ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
878 Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */
879 #define LL_ADC_REG_TRIG_EXT_TIM20_CH3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
880 ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
881 Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */
882 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
883 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting).
884 Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
885 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
886 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting).
887 Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */
888 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
889 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting).
890 Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
891 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
892 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting).
893 Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */
894 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
895 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting).
896 Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
897 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
898 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting).
899 Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
900 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
901 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting).
902 Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
903 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
904 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting).
905 Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
906 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
907 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting).
908 Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
909 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
910 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting).
911 Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
912 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
913 ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting).
914 Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
915 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
916 ADC group regular conversion trigger from external peripheral: external interrupt line 2. Trigger edge set to rising edge (default setting).
917 Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
918 #define LL_ADC_REG_TRIG_EXT_LPTIM_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
919 ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */
920 /**
921 * @}
922 */
923
924 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
925 * @{
926 */
927 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
928 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
929 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
930 /**
931 * @}
932 */
933
934 /** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode
935 * @{
936 */
937 #define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME */
938 #define LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event.
939 Note: First conversion is using minimal sampling time (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME) */
940 #define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events:
941 Trigger rising edge = start sampling
942 Trigger falling edge = stop sampling and start conversion */
943 /**
944 * @}
945 */
946
947 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
948 * @{
949 */
950 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
951 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
952 /**
953 * @}
954 */
955
956 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
957 * @{
958 */
959 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
960 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
961 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
962 /**
963 * @}
964 */
965
966 #if defined(ADC_SMPR1_SMPPLUS)
967 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration
968 * @{
969 */
970 #define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL) /*!< ADC sampling time let to default settings. */
971 #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped with selection sampling time 2.5 ADC clock cycles, whatever channels mapped on ADC groups regular or injected). */
972 /**
973 * @}
974 */
975 #endif
976
977 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
978 * @{
979 */
980 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
981 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
982 /**
983 * @}
984 */
985
986 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
987 * @{
988 */
989 #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
990 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
991 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
992 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
993 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
994 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
995 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
996 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
997 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
998 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
999 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
1000 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
1001 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
1002 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
1003 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
1004 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
1005 /**
1006 * @}
1007 */
1008
1009 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
1010 * @{
1011 */
1012 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
1013 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
1014 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
1015 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
1016 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
1017 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
1018 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
1019 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
1020 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
1021 /**
1022 * @}
1023 */
1024
1025 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
1026 * @{
1027 */
1028 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
1029 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
1030 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
1031 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
1032 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
1033 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
1034 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
1035 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
1036 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
1037 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
1038 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
1039 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
1040 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
1041 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
1042 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
1043 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
1044 /**
1045 * @}
1046 */
1047
1048 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
1049 * @{
1050 */
1051 #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!<
1052 ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */
1053 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1054 ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
1055 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1056 ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
1057 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1058 ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1059 Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
1060 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1061 ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1062 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1063 ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
1064 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1065 ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1066 Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
1067 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1068 ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
1069 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1070 ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1071 Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
1072 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1073 ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1074 Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
1075 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1076 ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1077 Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
1078 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1079 ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
1080 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1081 ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1082 Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
1083 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1084 ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1085 Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
1086 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1087 ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
1088 #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1089 ADC group injected conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
1090 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1091 ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
1092 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1093 ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
1094 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1095 ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1096 Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
1097 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1098 ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1099 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1100 ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
1101 #define LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1102 ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1103 Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
1104 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1105 ADC group injected conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting).
1106 Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
1107 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1108 ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting).
1109 Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
1110 #define LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1111 ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1112 Trigger available only on ADC3/4/5 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
1113 #define LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1114 ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1115 Trigger available only on ADC1/2 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
1116 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1117 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting).
1118 Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */
1119 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1120 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting).
1121 Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
1122 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1123 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting).
1124 Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */
1125 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1126 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting).
1127 Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
1128 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1129 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting).
1130 Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
1131 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1132 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting).
1133 Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
1134 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1135 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting).
1136 Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
1137 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1138 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting).
1139 Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
1140 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1141 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting).
1142 Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
1143 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1144 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting).
1145 Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
1146 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1147 ADC group injected conversion trigger from external peripheral: external interrupt line 3. Trigger edge set to rising edge (default setting).
1148 Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
1149 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1150 ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting).
1151 Note: On this STM32 series, this trigger is available only on ADC1/2 instances. */
1152 #define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1153 ADC group injected conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */
1154 /**
1155 * @}
1156 */
1157
1158 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
1159 * @{
1160 */
1161 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
1162 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
1163 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
1164 /**
1165 * @}
1166 */
1167
1168 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
1169 * @{
1170 */
1171 #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
1172 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
1173 /**
1174 * @}
1175 */
1176
1177 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
1178 * @{
1179 */
1180 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
1181 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
1182 #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
1183 /**
1184 * @}
1185 */
1186
1187 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
1188 * @{
1189 */
1190 #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1191 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
1192 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
1193 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
1194 /**
1195 * @}
1196 */
1197
1198 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1199 * @{
1200 */
1201 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */
1202 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
1203 /**
1204 * @}
1205 */
1206
1207 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1208 * @{
1209 */
1210 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
1211 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
1212 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
1213 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
1214 /**
1215 * @}
1216 */
1217
1218 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1219 * @{
1220 */
1221 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */
1222 #define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
1223 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles */
1224 #define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
1225 #define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 47.5 ADC clock cycles */
1226 #define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
1227 #define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 247.5 ADC clock cycles */
1228 #define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
1229 /**
1230 * @}
1231 */
1232
1233 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1234 * @{
1235 */
1236 #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
1237 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
1238 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
1239 /**
1240 * @}
1241 */
1242
1243 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1244 * @{
1245 */
1246 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1247 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1248 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1249 /**
1250 * @}
1251 */
1252
1253 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1254 * @{
1255 */
1256 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
1257 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
1258 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
1259 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
1260 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
1261 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
1262 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
1263 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
1264 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
1265 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
1266 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
1267 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
1268 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
1269 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
1270 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
1271 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
1272 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
1273 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
1274 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
1275 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
1276 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
1277 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
1278 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
1279 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
1280 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
1281 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
1282 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
1283 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
1284 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
1285 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
1286 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
1287 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
1288 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
1289 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
1290 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
1291 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
1292 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
1293 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
1294 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
1295 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
1296 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
1297 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
1298 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
1299 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
1300 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
1301 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
1302 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
1303 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
1304 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
1305 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
1306 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
1307 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
1308 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
1309 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
1310 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
1311 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
1312 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
1313 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
1314 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
1315 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
1316 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
1317 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
1318 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
1319 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
1320 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by group regular only */
1321 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by group injected only */
1322 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by either group regular or injected */
1323 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by group regular only */
1324 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by group injected only */
1325 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by either group regular or injected */
1326 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
1327 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
1328 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
1329 #define LL_ADC_AWD_CH_VOPAMP1_REG ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by group regular only */
1330 #define LL_ADC_AWD_CH_VOPAMP1_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by group injected only */
1331 #define LL_ADC_AWD_CH_VOPAMP1_REG_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by either group regular or injected */
1332 #define LL_ADC_AWD_CH_VOPAMP2_REG ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by group regular only */
1333 #define LL_ADC_AWD_CH_VOPAMP2_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by group injected only */
1334 #define LL_ADC_AWD_CH_VOPAMP2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by either group regular or injected */
1335 #define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by group regular only */
1336 #define LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by group injected only */
1337 #define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by either group regular or injected */
1338 #define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by group regular only */
1339 #define LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by group injected only */
1340 #define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by either group regular or injected */
1341 #define LL_ADC_AWD_CH_VOPAMP4_REG ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by group regular only */
1342 #define LL_ADC_AWD_CH_VOPAMP4_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by group injected only */
1343 #define LL_ADC_AWD_CH_VOPAMP4_REG_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by either group regular or injected */
1344 #define LL_ADC_AWD_CH_VOPAMP5_REG ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by group regular only */
1345 #define LL_ADC_AWD_CH_VOPAMP5_INJ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by group injected only */
1346 #define LL_ADC_AWD_CH_VOPAMP5_REG_INJ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by either group regular or injected */
1347 #define LL_ADC_AWD_CH_VOPAMP6_REG ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by group regular only */
1348 #define LL_ADC_AWD_CH_VOPAMP6_INJ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by group injected only */
1349 #define LL_ADC_AWD_CH_VOPAMP6_REG_INJ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by either group regular or injected */
1350 /**
1351 * @}
1352 */
1353
1354 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1355 * @{
1356 */
1357 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */
1358 #define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
1359 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
1360 /**
1361 * @}
1362 */
1363
1364 /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config
1365 * @{
1366 */
1367 #define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */
1368 #define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */
1369 #define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC_TR1_AWDFILT_1 ) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */
1370 #define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */
1371 #define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_TR1_AWDFILT_2 ) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */
1372 #define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */
1373 #define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 ) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */
1374 #define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */
1375 /**
1376 * @}
1377 */
1378
1379 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1380 * @{
1381 */
1382 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1383 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
1384 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1385 #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */
1386 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1387 /**
1388 * @}
1389 */
1390
1391 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1392 * @{
1393 */
1394 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
1395 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
1396 /**
1397 * @}
1398 */
1399
1400 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1401 * @{
1402 */
1403 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1404 #define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1405 #define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1406 #define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1407 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1408 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1409 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1410 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1411 /**
1412 * @}
1413 */
1414
1415 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
1416 * @{
1417 */
1418 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
1419 #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
1420 #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
1421 #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
1422 #define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
1423 #define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
1424 #define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
1425 #define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
1426 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
1427 /**
1428 * @}
1429 */
1430
1431 #if defined(ADC_MULTIMODE_SUPPORT)
1432 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
1433 * @{
1434 */
1435 #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */
1436 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
1437 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
1438 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
1439 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
1440 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
1441 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
1442 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
1443 /**
1444 * @}
1445 */
1446
1447 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
1448 * @{
1449 */
1450 #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
1451 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */
1452 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */
1453 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */
1454 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */
1455 /**
1456 * @}
1457 */
1458
1459 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1460 * @{
1461 */
1462 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
1463 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
1464 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
1465 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
1466 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
1467 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
1468 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
1469 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
1470 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
1471 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
1472 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
1473 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
1474 /**
1475 * @}
1476 */
1477
1478 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1479 * @{
1480 */
1481 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1482 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1483 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1484 /**
1485 * @}
1486 */
1487
1488 #endif /* ADC_MULTIMODE_SUPPORT */
1489
1490
1491 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1492 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
1493 * not timeout values.
1494 * For details on delays values, refer to descriptions in source code
1495 * above each literal definition.
1496 * @{
1497 */
1498
1499 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1500 /* not timeout values. */
1501 /* Timeout values for ADC operations are dependent to device clock */
1502 /* configuration (system clock versus ADC clock), */
1503 /* and therefore must be defined in user application. */
1504 /* Indications for estimation of ADC timeout delays, for this */
1505 /* STM32 series: */
1506 /* - ADC calibration time: maximum delay is 112/fADC. */
1507 /* (refer to device datasheet, parameter "tCAL") */
1508 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1509 /* (refer to device datasheet, parameter "tSTAB") */
1510 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1511 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1512 /* cycles */
1513 /* - ADC conversion time: duration depending on ADC clock and ADC */
1514 /* configuration. */
1515 /* (refer to device reference manual, section "Timing") */
1516
1517 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1518 /* Delay set to maximum value (refer to device datasheet, */
1519 /* parameter "tADCVREG_STUP"). */
1520 /* Unit: us */
1521 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1522
1523 /* Delay for internal voltage reference stabilization time. */
1524 /* Delay set to maximum value (refer to device datasheet, */
1525 /* parameter "tstart_vrefint"). */
1526 /* Unit: us */
1527 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */
1528
1529 /* Delay for temperature sensor stabilization time. */
1530 /* Literal set to maximum value (refer to device datasheet, */
1531 /* parameter "tSTART"). */
1532 /* Unit: us */
1533 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */
1534
1535 /* Delay required between ADC end of calibration and ADC enable. */
1536 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
1537 /* are required between ADC end of calibration and ADC enable. */
1538 /* Wait time can be computed in user application by waiting for the */
1539 /* equivalent number of CPU cycles, by taking into account */
1540 /* ratio of CPU clock versus ADC clock prescalers. */
1541 /* Unit: ADC clock cycles. */
1542 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
1543
1544 /**
1545 * @}
1546 */
1547
1548 /**
1549 * @}
1550 */
1551
1552
1553 /* Exported macro ------------------------------------------------------------*/
1554 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1555 * @{
1556 */
1557
1558 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1559 * @{
1560 */
1561
1562 /**
1563 * @brief Write a value in ADC register
1564 * @param __INSTANCE__ ADC Instance
1565 * @param __REG__ Register to be written
1566 * @param __VALUE__ Value to be written in the register
1567 * @retval None
1568 */
1569 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1570
1571 /**
1572 * @brief Read a value in ADC register
1573 * @param __INSTANCE__ ADC Instance
1574 * @param __REG__ Register to be read
1575 * @retval Register value
1576 */
1577 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1578 /**
1579 * @}
1580 */
1581
1582 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1583 * @{
1584 */
1585
1586 /**
1587 * @brief Helper macro to get ADC channel number in decimal format
1588 * from literals LL_ADC_CHANNEL_x.
1589 * @note Example:
1590 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1591 * will return decimal number "4".
1592 * @note The input can be a value from functions where a channel
1593 * number is returned, either defined with number
1594 * or with bitfield (only one bit must be set).
1595 * @param __CHANNEL__ This parameter can be one of the following values:
1596 * @arg @ref LL_ADC_CHANNEL_0
1597 * @arg @ref LL_ADC_CHANNEL_1 (8)
1598 * @arg @ref LL_ADC_CHANNEL_2 (8)
1599 * @arg @ref LL_ADC_CHANNEL_3 (8)
1600 * @arg @ref LL_ADC_CHANNEL_4 (8)
1601 * @arg @ref LL_ADC_CHANNEL_5 (8)
1602 * @arg @ref LL_ADC_CHANNEL_6
1603 * @arg @ref LL_ADC_CHANNEL_7
1604 * @arg @ref LL_ADC_CHANNEL_8
1605 * @arg @ref LL_ADC_CHANNEL_9
1606 * @arg @ref LL_ADC_CHANNEL_10
1607 * @arg @ref LL_ADC_CHANNEL_11
1608 * @arg @ref LL_ADC_CHANNEL_12
1609 * @arg @ref LL_ADC_CHANNEL_13
1610 * @arg @ref LL_ADC_CHANNEL_14
1611 * @arg @ref LL_ADC_CHANNEL_15
1612 * @arg @ref LL_ADC_CHANNEL_16
1613 * @arg @ref LL_ADC_CHANNEL_17
1614 * @arg @ref LL_ADC_CHANNEL_18
1615 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
1616 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
1617 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
1618 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
1619 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1620 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1621 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
1622 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
1623 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
1624 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
1625 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
1626 *
1627 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
1628 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
1629 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
1630 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
1631 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
1632 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
1633 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
1634 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
1635 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
1636 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
1637 * @retval Value between Min_Data=0 and Max_Data=18
1638 */
1639 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1640 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
1641 ( \
1642 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1643 ) \
1644 : \
1645 ( \
1646 (uint32_t)POSITION_VAL((__CHANNEL__)) \
1647 ) \
1648 )
1649
1650 /**
1651 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1652 * from number in decimal format.
1653 * @note Example:
1654 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1655 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1656 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1657 * @retval Returned value can be one of the following values:
1658 * @arg @ref LL_ADC_CHANNEL_0
1659 * @arg @ref LL_ADC_CHANNEL_1 (8)
1660 * @arg @ref LL_ADC_CHANNEL_2 (8)
1661 * @arg @ref LL_ADC_CHANNEL_3 (8)
1662 * @arg @ref LL_ADC_CHANNEL_4 (8)
1663 * @arg @ref LL_ADC_CHANNEL_5 (8)
1664 * @arg @ref LL_ADC_CHANNEL_6
1665 * @arg @ref LL_ADC_CHANNEL_7
1666 * @arg @ref LL_ADC_CHANNEL_8
1667 * @arg @ref LL_ADC_CHANNEL_9
1668 * @arg @ref LL_ADC_CHANNEL_10
1669 * @arg @ref LL_ADC_CHANNEL_11
1670 * @arg @ref LL_ADC_CHANNEL_12
1671 * @arg @ref LL_ADC_CHANNEL_13
1672 * @arg @ref LL_ADC_CHANNEL_14
1673 * @arg @ref LL_ADC_CHANNEL_15
1674 * @arg @ref LL_ADC_CHANNEL_16
1675 * @arg @ref LL_ADC_CHANNEL_17
1676 * @arg @ref LL_ADC_CHANNEL_18
1677 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
1678 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
1679 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
1680 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
1681 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1682 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1683 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
1684 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
1685 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
1686 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
1687 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
1688 *
1689 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
1690 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
1691 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
1692 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
1693 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
1694 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
1695 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
1696 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
1697 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
1698 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
1699 * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
1700 * comparison with internal channel parameter to be done
1701 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1702 */
1703 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1704 (((__DECIMAL_NB__) <= 9UL) ? \
1705 ( \
1706 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1707 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1708 (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1709 ) \
1710 : \
1711 ( \
1712 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1713 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1714 (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1715 ) \
1716 )
1717
1718 /**
1719 * @brief Helper macro to determine whether the selected channel
1720 * corresponds to literal definitions of driver.
1721 * @note The different literal definitions of ADC channels are:
1722 * - ADC internal channel:
1723 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1724 * - ADC external channel (channel connected to a GPIO pin):
1725 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1726 * @note The channel parameter must be a value defined from literal
1727 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1728 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1729 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1730 * must not be a value from functions where a channel number is
1731 * returned from ADC registers,
1732 * because internal and external channels share the same channel
1733 * number in ADC registers. The differentiation is made only with
1734 * parameters definitions of driver.
1735 * @param __CHANNEL__ This parameter can be one of the following values:
1736 * @arg @ref LL_ADC_CHANNEL_0
1737 * @arg @ref LL_ADC_CHANNEL_1 (8)
1738 * @arg @ref LL_ADC_CHANNEL_2 (8)
1739 * @arg @ref LL_ADC_CHANNEL_3 (8)
1740 * @arg @ref LL_ADC_CHANNEL_4 (8)
1741 * @arg @ref LL_ADC_CHANNEL_5 (8)
1742 * @arg @ref LL_ADC_CHANNEL_6
1743 * @arg @ref LL_ADC_CHANNEL_7
1744 * @arg @ref LL_ADC_CHANNEL_8
1745 * @arg @ref LL_ADC_CHANNEL_9
1746 * @arg @ref LL_ADC_CHANNEL_10
1747 * @arg @ref LL_ADC_CHANNEL_11
1748 * @arg @ref LL_ADC_CHANNEL_12
1749 * @arg @ref LL_ADC_CHANNEL_13
1750 * @arg @ref LL_ADC_CHANNEL_14
1751 * @arg @ref LL_ADC_CHANNEL_15
1752 * @arg @ref LL_ADC_CHANNEL_16
1753 * @arg @ref LL_ADC_CHANNEL_17
1754 * @arg @ref LL_ADC_CHANNEL_18
1755 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
1756 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
1757 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
1758 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
1759 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1760 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1761 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
1762 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
1763 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
1764 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
1765 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
1766 *
1767 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
1768 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
1769 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
1770 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
1771 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
1772 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
1773 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
1774 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
1775 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
1776 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
1777 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1778 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1779 */
1780 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1781 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1782
1783 /**
1784 * @brief Helper macro to convert a channel defined from parameter
1785 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1786 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1787 * to its equivalent parameter definition of a ADC external channel
1788 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1789 * @note The channel parameter can be, additionally to a value
1790 * defined from parameter definition of a ADC internal channel
1791 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1792 * a value defined from parameter definition of
1793 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1794 * or a value from functions where a channel number is returned
1795 * from ADC registers.
1796 * @param __CHANNEL__ This parameter can be one of the following values:
1797 * @arg @ref LL_ADC_CHANNEL_0
1798 * @arg @ref LL_ADC_CHANNEL_1 (8)
1799 * @arg @ref LL_ADC_CHANNEL_2 (8)
1800 * @arg @ref LL_ADC_CHANNEL_3 (8)
1801 * @arg @ref LL_ADC_CHANNEL_4 (8)
1802 * @arg @ref LL_ADC_CHANNEL_5 (8)
1803 * @arg @ref LL_ADC_CHANNEL_6
1804 * @arg @ref LL_ADC_CHANNEL_7
1805 * @arg @ref LL_ADC_CHANNEL_8
1806 * @arg @ref LL_ADC_CHANNEL_9
1807 * @arg @ref LL_ADC_CHANNEL_10
1808 * @arg @ref LL_ADC_CHANNEL_11
1809 * @arg @ref LL_ADC_CHANNEL_12
1810 * @arg @ref LL_ADC_CHANNEL_13
1811 * @arg @ref LL_ADC_CHANNEL_14
1812 * @arg @ref LL_ADC_CHANNEL_15
1813 * @arg @ref LL_ADC_CHANNEL_16
1814 * @arg @ref LL_ADC_CHANNEL_17
1815 * @arg @ref LL_ADC_CHANNEL_18
1816 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
1817 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
1818 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
1819 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
1820 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1821 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1822 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
1823 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
1824 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
1825 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
1826 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
1827 *
1828 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
1829 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
1830 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
1831 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
1832 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
1833 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
1834 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
1835 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
1836 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
1837 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
1838 * @retval Returned value can be one of the following values:
1839 * @arg @ref LL_ADC_CHANNEL_0
1840 * @arg @ref LL_ADC_CHANNEL_1
1841 * @arg @ref LL_ADC_CHANNEL_2
1842 * @arg @ref LL_ADC_CHANNEL_3
1843 * @arg @ref LL_ADC_CHANNEL_4
1844 * @arg @ref LL_ADC_CHANNEL_5
1845 * @arg @ref LL_ADC_CHANNEL_6
1846 * @arg @ref LL_ADC_CHANNEL_7
1847 * @arg @ref LL_ADC_CHANNEL_8
1848 * @arg @ref LL_ADC_CHANNEL_9
1849 * @arg @ref LL_ADC_CHANNEL_10
1850 * @arg @ref LL_ADC_CHANNEL_11
1851 * @arg @ref LL_ADC_CHANNEL_12
1852 * @arg @ref LL_ADC_CHANNEL_13
1853 * @arg @ref LL_ADC_CHANNEL_14
1854 * @arg @ref LL_ADC_CHANNEL_15
1855 * @arg @ref LL_ADC_CHANNEL_16
1856 * @arg @ref LL_ADC_CHANNEL_17
1857 * @arg @ref LL_ADC_CHANNEL_18
1858 */
1859 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1860 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1861
1862 /**
1863 * @brief Helper macro to determine whether the internal channel
1864 * selected is available on the ADC instance selected.
1865 * @note The channel parameter must be a value defined from parameter
1866 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1867 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1868 * must not be a value defined from parameter definition of
1869 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1870 * or a value from functions where a channel number is
1871 * returned from ADC registers,
1872 * because internal and external channels share the same channel
1873 * number in ADC registers. The differentiation is made only with
1874 * parameters definitions of driver.
1875 * @param __ADC_INSTANCE__ ADC instance
1876 * @param __CHANNEL__ This parameter can be one of the following values:
1877 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
1878 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
1879 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
1880 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
1881 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1882 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1883 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
1884 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
1885 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
1886 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
1887 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
1888 *
1889 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
1890 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
1891 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
1892 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
1893 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
1894 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
1895 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
1896 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
1897 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1898 * Value "1" if the internal channel selected is available on the ADC instance selected.
1899 */
1900 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
1901 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1902 ((((__ADC_INSTANCE__) == ADC1) \
1903 &&( \
1904 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
1905 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
1906 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1907 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1908 ) \
1909 ) \
1910 || \
1911 (((__ADC_INSTANCE__) == ADC2) \
1912 &&( \
1913 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
1914 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \
1915 ) \
1916 ) \
1917 || \
1918 (((__ADC_INSTANCE__) == ADC3) \
1919 &&( \
1920 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \
1921 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1922 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1923 ) \
1924 ) \
1925 || \
1926 (((__ADC_INSTANCE__) == ADC4) \
1927 &&( \
1928 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \
1929 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1930 ) \
1931 ) \
1932 || \
1933 (((__ADC_INSTANCE__) == ADC5) \
1934 &&( \
1935 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP5) || \
1936 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC5) || \
1937 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4) || \
1938 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1939 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1940 ) \
1941 ) \
1942 )
1943 #elif defined(STM32G471xx)
1944 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1945 ((((__ADC_INSTANCE__) == ADC1) \
1946 &&( \
1947 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
1948 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
1949 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1950 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1951 ) \
1952 ) \
1953 || \
1954 (((__ADC_INSTANCE__) == ADC2) \
1955 &&( \
1956 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
1957 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \
1958 ) \
1959 ) \
1960 || \
1961 (((__ADC_INSTANCE__) == ADC3) \
1962 &&( \
1963 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \
1964 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1965 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1966 ) \
1967 ) \
1968 )
1969 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
1970 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1971 ((((__ADC_INSTANCE__) == ADC1) \
1972 &&( \
1973 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
1974 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
1975 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1976 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1977 ) \
1978 ) \
1979 || \
1980 (((__ADC_INSTANCE__) == ADC2) \
1981 &&( \
1982 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
1983 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \
1984 ) \
1985 ) \
1986 )
1987 #elif defined(STM32G491xx) || defined(STM32G4A1xx)
1988 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1989 ((((__ADC_INSTANCE__) == ADC1) \
1990 &&( \
1991 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
1992 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
1993 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1994 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1995 ) \
1996 ) \
1997 || \
1998 (((__ADC_INSTANCE__) == ADC2) \
1999 &&( \
2000 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
2001 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \
2002 ) \
2003 ) \
2004 || \
2005 (((__ADC_INSTANCE__) == ADC3) \
2006 &&( \
2007 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \
2008 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \
2009 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
2010 ) \
2011 ) \
2012 )
2013 #endif
2014
2015 /**
2016 * @brief Helper macro to define ADC analog watchdog parameter:
2017 * define a single channel to monitor with analog watchdog
2018 * from sequencer channel and groups definition.
2019 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
2020 * Example:
2021 * LL_ADC_SetAnalogWDMonitChannels(
2022 * ADC1, LL_ADC_AWD1,
2023 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
2024 * @param __CHANNEL__ This parameter can be one of the following values:
2025 * @arg @ref LL_ADC_CHANNEL_0
2026 * @arg @ref LL_ADC_CHANNEL_1 (8)
2027 * @arg @ref LL_ADC_CHANNEL_2 (8)
2028 * @arg @ref LL_ADC_CHANNEL_3 (8)
2029 * @arg @ref LL_ADC_CHANNEL_4 (8)
2030 * @arg @ref LL_ADC_CHANNEL_5 (8)
2031 * @arg @ref LL_ADC_CHANNEL_6
2032 * @arg @ref LL_ADC_CHANNEL_7
2033 * @arg @ref LL_ADC_CHANNEL_8
2034 * @arg @ref LL_ADC_CHANNEL_9
2035 * @arg @ref LL_ADC_CHANNEL_10
2036 * @arg @ref LL_ADC_CHANNEL_11
2037 * @arg @ref LL_ADC_CHANNEL_12
2038 * @arg @ref LL_ADC_CHANNEL_13
2039 * @arg @ref LL_ADC_CHANNEL_14
2040 * @arg @ref LL_ADC_CHANNEL_15
2041 * @arg @ref LL_ADC_CHANNEL_16
2042 * @arg @ref LL_ADC_CHANNEL_17
2043 * @arg @ref LL_ADC_CHANNEL_18
2044 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
2045 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
2046 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
2047 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
2048 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
2049 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
2050 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
2051 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
2052 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
2053 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
2054 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
2055 *
2056 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
2057 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
2058 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
2059 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
2060 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
2061 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
2062 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
2063 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
2064 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
2065 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
2066 * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
2067 * comparison with internal channel parameter to be done
2068 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2069 * @param __GROUP__ This parameter can be one of the following values:
2070 * @arg @ref LL_ADC_GROUP_REGULAR
2071 * @arg @ref LL_ADC_GROUP_INJECTED
2072 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
2073 * @retval Returned value can be one of the following values:
2074 * @arg @ref LL_ADC_AWD_DISABLE
2075 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
2076 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
2077 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
2078 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
2079 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
2080 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
2081 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
2082 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
2083 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
2084 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
2085 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
2086 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
2087 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
2088 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
2089 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
2090 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
2091 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
2092 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
2093 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
2094 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
2095 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
2096 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
2097 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
2098 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
2099 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
2100 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
2101 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
2102 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
2103 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
2104 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
2105 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
2106 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
2107 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
2108 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
2109 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
2110 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
2111 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
2112 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
2113 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
2114 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
2115 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
2116 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
2117 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
2118 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
2119 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
2120 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
2121 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
2122 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
2123 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
2124 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
2125 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
2126 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
2127 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
2128 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
2129 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
2130 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
2131 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
2132 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
2133 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
2134 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
2135 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
2136 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)
2137 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
2138 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1)
2139 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1)
2140 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
2141 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5)
2142 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5)
2143 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
2144 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(6)
2145 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(6)
2146 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (6)
2147 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
2148 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
2149 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
2150 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
2151 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
2152 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
2153 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2)
2154 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2)
2155 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2)
2156 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3)
2157 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3)
2158 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3)
2159 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(5)
2160 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5)
2161 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5)
2162 * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG (0)(5)
2163 * @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5)
2164 * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5)
2165 * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG (0)(4)
2166 * @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4)
2167 * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4)
2168 *
2169 * (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n
2170 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
2171 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
2172 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
2173 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
2174 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
2175 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
2176 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
2177 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
2178 */
2179 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
2180 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
2181 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2182 : \
2183 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
2184 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
2185 : \
2186 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2187 )
2188
2189 /**
2190 * @brief Helper macro to set the value of ADC analog watchdog threshold high
2191 * or low in function of ADC resolution, when ADC resolution is
2192 * different of 12 bits.
2193 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
2194 * or @ref LL_ADC_SetAnalogWDThresholds().
2195 * Example, with a ADC resolution of 8 bits, to set the value of
2196 * analog watchdog threshold high (on 8 bits):
2197 * LL_ADC_SetAnalogWDThresholds
2198 * (< ADCx param >,
2199 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
2200 * );
2201 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2202 * @arg @ref LL_ADC_RESOLUTION_12B
2203 * @arg @ref LL_ADC_RESOLUTION_10B
2204 * @arg @ref LL_ADC_RESOLUTION_8B
2205 * @arg @ref LL_ADC_RESOLUTION_6B
2206 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
2207 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2208 */
2209 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
2210 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2211
2212 /**
2213 * @brief Helper macro to get the value of ADC analog watchdog threshold high
2214 * or low in function of ADC resolution, when ADC resolution is
2215 * different of 12 bits.
2216 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2217 * Example, with a ADC resolution of 8 bits, to get the value of
2218 * analog watchdog threshold high (on 8 bits):
2219 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
2220 * (LL_ADC_RESOLUTION_8B,
2221 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
2222 * );
2223 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2224 * @arg @ref LL_ADC_RESOLUTION_12B
2225 * @arg @ref LL_ADC_RESOLUTION_10B
2226 * @arg @ref LL_ADC_RESOLUTION_8B
2227 * @arg @ref LL_ADC_RESOLUTION_6B
2228 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
2229 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2230 */
2231 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
2232 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2233
2234 /**
2235 * @brief Helper macro to get the ADC analog watchdog threshold high
2236 * or low from raw value containing both thresholds concatenated.
2237 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2238 * Example, to get analog watchdog threshold high from the register raw value:
2239 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
2240 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
2241 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
2242 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
2243 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2244 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2245 */
2246 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
2247 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)
2248
2249 /**
2250 * @brief Helper macro to set the ADC calibration value with both single ended
2251 * and differential modes calibration factors concatenated.
2252 * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
2253 * Example, to set calibration factors single ended to 0x55
2254 * and differential ended to 0x2A:
2255 * LL_ADC_SetCalibrationFactor(
2256 * ADC1,
2257 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
2258 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
2259 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
2260 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2261 */
2262 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
2263 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
2264
2265 #if defined(ADC_MULTIMODE_SUPPORT)
2266 /**
2267 * @brief Helper macro to get the ADC multimode conversion data of ADC master
2268 * or ADC slave from raw value with both ADC conversion data concatenated.
2269 * @note This macro is intended to be used when multimode transfer by DMA
2270 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
2271 * In this case the transferred data need to processed with this macro
2272 * to separate the conversion data of ADC master and ADC slave.
2273 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
2274 * @arg @ref LL_ADC_MULTI_MASTER
2275 * @arg @ref LL_ADC_MULTI_SLAVE
2276 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
2277 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2278 */
2279 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2280 (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2281 #endif /* ADC_MULTIMODE_SUPPORT */
2282
2283 #if defined(ADC_MULTIMODE_SUPPORT)
2284 /**
2285 * @brief Helper macro to select, from a ADC instance, to which ADC instance
2286 * it has a dependence in multimode (ADC master of the corresponding
2287 * ADC common instance).
2288 * @note In case of device with multimode available and a mix of
2289 * ADC instances compliant and not compliant with multimode feature,
2290 * ADC instances not compliant with multimode feature are
2291 * considered as master instances (do not depend to
2292 * any other ADC instance).
2293 * @param __ADCx__ ADC instance
2294 * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
2295 */
2296 #if defined(ADC5)
2297 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2298 ( ( ((__ADCx__) == ADC2) \
2299 )? \
2300 (ADC1) \
2301 : \
2302 ( ( ((__ADCx__) == ADC4) \
2303 )? \
2304 (ADC3) \
2305 : \
2306 (__ADCx__) \
2307 ) \
2308 )
2309 #else
2310 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2311 ( ( ((__ADCx__) == ADC2) \
2312 )? \
2313 (ADC1) \
2314 : \
2315 (__ADCx__) \
2316 )
2317 #endif /* ADC5 */
2318 #endif /* ADC_MULTIMODE_SUPPORT */
2319
2320 /**
2321 * @brief Helper macro to select the ADC common instance
2322 * to which is belonging the selected ADC instance.
2323 * @note ADC common register instance can be used for:
2324 * - Set parameters common to several ADC instances
2325 * - Multimode (for devices with several ADC instances)
2326 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2327 * @param __ADCx__ ADC instance
2328 * @retval ADC common register instance
2329 */
2330 #if defined(ADC345_COMMON)
2331 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2332 ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \
2333 ? ( \
2334 (ADC12_COMMON) \
2335 ) \
2336 : \
2337 ( \
2338 (ADC345_COMMON) \
2339 ) \
2340 )
2341 #else
2342 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
2343 #endif /* ADC345_COMMON */
2344 /**
2345 * @brief Helper macro to check if all ADC instances sharing the same
2346 * ADC common instance are disabled.
2347 * @note This check is required by functions with setting conditioned to
2348 * ADC state:
2349 * All ADC instances of the ADC common group must be disabled.
2350 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2351 * @note On devices with only 1 ADC common instance, parameter of this macro
2352 * is useless and can be ignored (parameter kept for compatibility
2353 * with devices featuring several ADC common instances).
2354 * @param __ADCXY_COMMON__ ADC common instance
2355 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2356 * @retval Value "0" if all ADC instances sharing the same ADC common instance
2357 * are disabled.
2358 * Value "1" if at least one ADC instance sharing the same ADC common instance
2359 * is enabled.
2360 */
2361 #if defined(ADC345_COMMON)
2362 #if defined(ADC4) && defined(ADC5)
2363 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2364 (((__ADCXY_COMMON__) == ADC12_COMMON) \
2365 ? ( \
2366 (LL_ADC_IsEnabled(ADC1) | \
2367 LL_ADC_IsEnabled(ADC2) ) \
2368 ) \
2369 : \
2370 ( \
2371 (LL_ADC_IsEnabled(ADC3) | \
2372 LL_ADC_IsEnabled(ADC4) | \
2373 LL_ADC_IsEnabled(ADC5) ) \
2374 ) \
2375 )
2376 #else
2377 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2378 (((__ADCXY_COMMON__) == ADC12_COMMON) \
2379 ? ( \
2380 (LL_ADC_IsEnabled(ADC1) | \
2381 LL_ADC_IsEnabled(ADC2) ) \
2382 ) \
2383 : \
2384 (LL_ADC_IsEnabled(ADC3)) \
2385 )
2386 #endif /* ADC4 && ADC5 */
2387 #else
2388 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2389 (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
2390 #endif
2391
2392 /**
2393 * @brief Helper macro to define the ADC conversion data full-scale digital
2394 * value corresponding to the selected ADC resolution.
2395 * @note ADC conversion data full-scale corresponds to voltage range
2396 * determined by analog voltage references Vref+ and Vref-
2397 * (refer to reference manual).
2398 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2399 * @arg @ref LL_ADC_RESOLUTION_12B
2400 * @arg @ref LL_ADC_RESOLUTION_10B
2401 * @arg @ref LL_ADC_RESOLUTION_8B
2402 * @arg @ref LL_ADC_RESOLUTION_6B
2403 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
2404 */
2405 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2406 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
2407
2408 /**
2409 * @brief Helper macro to convert the ADC conversion data from
2410 * a resolution to another resolution.
2411 * @param __DATA__ ADC conversion data to be converted
2412 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
2413 * This parameter can be one of the following values:
2414 * @arg @ref LL_ADC_RESOLUTION_12B
2415 * @arg @ref LL_ADC_RESOLUTION_10B
2416 * @arg @ref LL_ADC_RESOLUTION_8B
2417 * @arg @ref LL_ADC_RESOLUTION_6B
2418 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2419 * This parameter can be one of the following values:
2420 * @arg @ref LL_ADC_RESOLUTION_12B
2421 * @arg @ref LL_ADC_RESOLUTION_10B
2422 * @arg @ref LL_ADC_RESOLUTION_8B
2423 * @arg @ref LL_ADC_RESOLUTION_6B
2424 * @retval ADC conversion data to the requested resolution
2425 */
2426 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2427 __ADC_RESOLUTION_CURRENT__,\
2428 __ADC_RESOLUTION_TARGET__) \
2429 (((__DATA__) \
2430 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2431 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2432 )
2433
2434 /**
2435 * @brief Helper macro to calculate the voltage (unit: mVolt)
2436 * corresponding to a ADC conversion data (unit: digital value).
2437 * @note Analog reference voltage (Vref+) must be either known from
2438 * user board environment or can be calculated using ADC measurement
2439 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2440 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2441 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
2442 * (unit: digital value).
2443 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2444 * @arg @ref LL_ADC_RESOLUTION_12B
2445 * @arg @ref LL_ADC_RESOLUTION_10B
2446 * @arg @ref LL_ADC_RESOLUTION_8B
2447 * @arg @ref LL_ADC_RESOLUTION_6B
2448 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2449 */
2450 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2451 __ADC_DATA__,\
2452 __ADC_RESOLUTION__) \
2453 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2454 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2455 )
2456
2457 /**
2458 * @brief Helper macro to calculate analog reference voltage (Vref+)
2459 * (unit: mVolt) from ADC conversion data of internal voltage
2460 * reference VrefInt.
2461 * @note Computation is using VrefInt calibration value
2462 * stored in system memory for each device during production.
2463 * @note This voltage depends on user board environment: voltage level
2464 * connected to pin Vref+.
2465 * On devices with small package, the pin Vref+ is not present
2466 * and internally bonded to pin Vdda.
2467 * @note On this STM32 series, calibration data of internal voltage reference
2468 * VrefInt corresponds to a resolution of 12 bits,
2469 * this is the recommended ADC resolution to convert voltage of
2470 * internal voltage reference VrefInt.
2471 * Otherwise, this macro performs the processing to scale
2472 * ADC conversion data to 12 bits.
2473 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
2474 * of internal voltage reference VrefInt (unit: digital value).
2475 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2476 * @arg @ref LL_ADC_RESOLUTION_12B
2477 * @arg @ref LL_ADC_RESOLUTION_10B
2478 * @arg @ref LL_ADC_RESOLUTION_8B
2479 * @arg @ref LL_ADC_RESOLUTION_6B
2480 * @retval Analog reference voltage (unit: mV)
2481 */
2482 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
2483 __ADC_RESOLUTION__) \
2484 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2485 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
2486 (__ADC_RESOLUTION__), \
2487 LL_ADC_RESOLUTION_12B) \
2488 )
2489
2490 /**
2491 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2492 * from ADC conversion data of internal temperature sensor.
2493 * @note Computation is using temperature sensor calibration values
2494 * stored in system memory for each device during production.
2495 * @note Calculation formula:
2496 * Temperature = ((TS_ADC_DATA - TS_CAL1)
2497 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
2498 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
2499 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2500 * Avg_Slope = (TS_CAL2 - TS_CAL1)
2501 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
2502 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
2503 * TEMP_DEGC_CAL1 (calibrated in factory)
2504 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
2505 * TEMP_DEGC_CAL2 (calibrated in factory)
2506 * Caution: Calculation relevancy under reserve that calibration
2507 * parameters are correct (address and data).
2508 * To calculate temperature using temperature sensor
2509 * datasheet typical values (generic values less, therefore
2510 * less accurate than calibrated values),
2511 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
2512 * @note As calculation input, the analog reference voltage (Vref+) must be
2513 * defined as it impacts the ADC LSB equivalent voltage.
2514 * @note Analog reference voltage (Vref+) must be either known from
2515 * user board environment or can be calculated using ADC measurement
2516 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2517 * @note On this STM32 series, calibration data of temperature sensor
2518 * corresponds to a resolution of 12 bits,
2519 * this is the recommended ADC resolution to convert voltage of
2520 * temperature sensor.
2521 * Otherwise, this macro performs the processing to scale
2522 * ADC conversion data to 12 bits.
2523 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2524 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
2525 * temperature sensor (unit: digital value).
2526 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
2527 * sensor voltage has been measured.
2528 * This parameter can be one of the following values:
2529 * @arg @ref LL_ADC_RESOLUTION_12B
2530 * @arg @ref LL_ADC_RESOLUTION_10B
2531 * @arg @ref LL_ADC_RESOLUTION_8B
2532 * @arg @ref LL_ADC_RESOLUTION_6B
2533 * @retval Temperature (unit: degree Celsius)
2534 */
2535 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2536 __TEMPSENSOR_ADC_DATA__,\
2537 __ADC_RESOLUTION__) \
2538 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2539 (__ADC_RESOLUTION__), \
2540 LL_ADC_RESOLUTION_12B) \
2541 * (__VREFANALOG_VOLTAGE__)) \
2542 / TEMPSENSOR_CAL_VREFANALOG) \
2543 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2544 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2545 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2546 ) + TEMPSENSOR_CAL1_TEMP \
2547 )
2548
2549 /**
2550 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2551 * from ADC conversion data of internal temperature sensor.
2552 * @note Computation is using temperature sensor typical values
2553 * (refer to device datasheet).
2554 * @note Calculation formula:
2555 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
2556 * / Avg_Slope + CALx_TEMP
2557 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2558 * (unit: digital value)
2559 * Avg_Slope = temperature sensor slope
2560 * (unit: uV/Degree Celsius)
2561 * TS_TYP_CALx_VOLT = temperature sensor digital value at
2562 * temperature CALx_TEMP (unit: mV)
2563 * Caution: Calculation relevancy under reserve the temperature sensor
2564 * of the current device has characteristics in line with
2565 * datasheet typical values.
2566 * If temperature sensor calibration values are available on
2567 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
2568 * temperature calculation will be more accurate using
2569 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
2570 * @note As calculation input, the analog reference voltage (Vref+) must be
2571 * defined as it impacts the ADC LSB equivalent voltage.
2572 * @note Analog reference voltage (Vref+) must be either known from
2573 * user board environment or can be calculated using ADC measurement
2574 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2575 * @note ADC measurement data must correspond to a resolution of 12 bits
2576 * (full scale digital value 4095). If not the case, the data must be
2577 * preliminarily rescaled to an equivalent resolution of 12 bits.
2578 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
2579 * On STM32G4, refer to device datasheet parameter "Avg_Slope".
2580 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
2581 * On STM32G4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
2582 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
2583 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
2584 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
2585 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
2586 * This parameter can be one of the following values:
2587 * @arg @ref LL_ADC_RESOLUTION_12B
2588 * @arg @ref LL_ADC_RESOLUTION_10B
2589 * @arg @ref LL_ADC_RESOLUTION_8B
2590 * @arg @ref LL_ADC_RESOLUTION_6B
2591 * @retval Temperature (unit: degree Celsius)
2592 */
2593 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
2594 __TEMPSENSOR_TYP_CALX_V__,\
2595 __TEMPSENSOR_CALX_TEMP__,\
2596 __VREFANALOG_VOLTAGE__,\
2597 __TEMPSENSOR_ADC_DATA__,\
2598 __ADC_RESOLUTION__) \
2599 (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2600 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2601 * 1000UL) \
2602 - \
2603 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2604 * 1000UL) \
2605 ) \
2606 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
2607 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
2608 )
2609
2610 /**
2611 * @}
2612 */
2613
2614 /**
2615 * @}
2616 */
2617
2618
2619 /* Exported functions --------------------------------------------------------*/
2620 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
2621 * @{
2622 */
2623
2624 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
2625 * @{
2626 */
2627 /* Note: LL ADC functions to set DMA transfer are located into sections of */
2628 /* configuration of ADC instance, groups and multimode (if available): */
2629 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
2630
2631 /**
2632 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2633 * ADC register address from ADC instance and a list of ADC registers
2634 * intended to be used (most commonly) with DMA transfer.
2635 * @note These ADC registers are data registers:
2636 * when ADC conversion data is available in ADC data registers,
2637 * ADC generates a DMA transfer request.
2638 * @note This macro is intended to be used with LL DMA driver, refer to
2639 * function "LL_DMA_ConfigAddresses()".
2640 * Example:
2641 * LL_DMA_ConfigAddresses(DMA1,
2642 * LL_DMA_CHANNEL_1,
2643 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2644 * (uint32_t)&< array or variable >,
2645 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2646 * @note For devices with several ADC: in multimode, some devices
2647 * use a different data register outside of ADC instance scope
2648 * (common data register). This macro manages this register difference,
2649 * only ADC instance has to be set as parameter.
2650 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
2651 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
2652 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
2653 * @param ADCx ADC instance
2654 * @param Register This parameter can be one of the following values:
2655 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2656 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
2657 *
2658 * (1) Available on devices with several ADC instances.
2659 * @retval ADC register address
2660 */
2661 #if defined(ADC_MULTIMODE_SUPPORT)
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)2662 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2663 {
2664 uint32_t data_reg_addr;
2665
2666 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
2667 {
2668 /* Retrieve address of register DR */
2669 data_reg_addr = (uint32_t) &(ADCx->DR);
2670 }
2671 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
2672 {
2673 /* Retrieve address of register CDR */
2674 data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
2675 }
2676
2677 return data_reg_addr;
2678 }
2679 #else
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)2680 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2681 {
2682 /* Prevent unused argument(s) compilation warning */
2683 (void)(Register);
2684
2685 /* Retrieve address of register DR */
2686 return (uint32_t) &(ADCx->DR);
2687 }
2688 #endif /* ADC_MULTIMODE_SUPPORT */
2689
2690 /**
2691 * @}
2692 */
2693
2694 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
2695 * @{
2696 */
2697
2698 /**
2699 * @brief Set parameter common to several ADC: Clock source and prescaler.
2700 * @note On this STM32 series, if ADC group injected is used, some
2701 * clock ratio constraints between ADC clock and AHB clock
2702 * must be respected.
2703 * Refer to reference manual.
2704 * @note On this STM32 series, setting of this feature is conditioned to
2705 * ADC state:
2706 * All ADC instances of the ADC common group must be disabled.
2707 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2708 * ADC instance or by using helper macro helper macro
2709 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2710 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
2711 * CCR PRESC LL_ADC_SetCommonClock
2712 * @param ADCxy_COMMON ADC common instance
2713 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2714 * @param CommonClock This parameter can be one of the following values:
2715 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2716 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2717 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2718 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2719 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2720 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2721 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2722 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2723 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2724 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2725 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2726 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2727 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2728 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2729 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2730 * @retval None
2731 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)2732 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
2733 {
2734 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
2735 }
2736
2737 /**
2738 * @brief Get parameter common to several ADC: Clock source and prescaler.
2739 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
2740 * CCR PRESC LL_ADC_GetCommonClock
2741 * @param ADCxy_COMMON ADC common instance
2742 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2743 * @retval Returned value can be one of the following values:
2744 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2745 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2746 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2747 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2748 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2749 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2750 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2751 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2752 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2753 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2754 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2755 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2756 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2757 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2758 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2759 */
LL_ADC_GetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON)2760 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
2761 {
2762 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
2763 }
2764
2765 /**
2766 * @brief Set parameter common to several ADC: measurement path to
2767 * internal channels (VrefInt, temperature sensor, ...).
2768 * Configure all paths (overwrite current configuration).
2769 * @note One or several values can be selected.
2770 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2771 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2772 * The values not selected are removed from configuration.
2773 * @note Stabilization time of measurement path to internal channel:
2774 * After enabling internal paths, before starting ADC conversion,
2775 * a delay is required for internal voltage reference and
2776 * temperature sensor stabilization time.
2777 * Refer to device datasheet.
2778 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2779 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
2780 * @note ADC internal channel sampling time constraint:
2781 * For ADC conversion of internal channels,
2782 * a sampling time minimum value is required.
2783 * Refer to device datasheet.
2784 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
2785 * CCR VSENSESEL LL_ADC_SetCommonPathInternalCh\n
2786 * CCR VBATSEL LL_ADC_SetCommonPathInternalCh
2787 * @param ADCxy_COMMON ADC common instance
2788 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2789 * @param PathInternal This parameter can be a combination of the following values:
2790 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2791 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2792 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2793 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2794 * @retval None
2795 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2796 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2797 {
2798 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal);
2799 }
2800
2801 /**
2802 * @brief Set parameter common to several ADC: measurement path to
2803 * internal channels (VrefInt, temperature sensor, ...).
2804 * Add paths to the current configuration.
2805 * @note One or several values can be selected.
2806 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2807 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2808 * @note Stabilization time of measurement path to internal channel:
2809 * After enabling internal paths, before starting ADC conversion,
2810 * a delay is required for internal voltage reference and
2811 * temperature sensor stabilization time.
2812 * Refer to device datasheet.
2813 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2814 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
2815 * @note ADC internal channel sampling time constraint:
2816 * For ADC conversion of internal channels,
2817 * a sampling time minimum value is required.
2818 * Refer to device datasheet.
2819 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
2820 * CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd\n
2821 * CCR VBATSEL LL_ADC_SetCommonPathInternalChAdd
2822 * @param ADCxy_COMMON ADC common instance
2823 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2824 * @param PathInternal This parameter can be a combination of the following values:
2825 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2826 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2827 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2828 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2829 * @retval None
2830 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2831 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2832 {
2833 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
2834 }
2835
2836 /**
2837 * @brief Set parameter common to several ADC: measurement path to
2838 * internal channels (VrefInt, temperature sensor, ...).
2839 * Remove paths to the current configuration.
2840 * @note One or several values can be selected.
2841 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2842 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2843 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
2844 * CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem\n
2845 * CCR VBATSEL LL_ADC_SetCommonPathInternalChRem
2846 * @param ADCxy_COMMON ADC common instance
2847 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2848 * @param PathInternal This parameter can be a combination of the following values:
2849 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2850 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2851 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2852 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2853 * @retval None
2854 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2855 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2856 {
2857 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
2858 }
2859
2860 /**
2861 * @brief Get parameter common to several ADC: measurement path to internal
2862 * channels (VrefInt, temperature sensor, ...).
2863 * @note One or several values can be selected.
2864 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2865 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2866 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
2867 * CCR VSENSESEL LL_ADC_GetCommonPathInternalCh\n
2868 * CCR VBATSEL LL_ADC_GetCommonPathInternalCh
2869 * @param ADCxy_COMMON ADC common instance
2870 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2871 * @retval Returned value can be a combination of the following values:
2872 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2873 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2874 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2875 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2876 */
LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON)2877 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
2878 {
2879 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL));
2880 }
2881
2882 /**
2883 * @}
2884 */
2885
2886 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
2887 * @{
2888 */
2889
2890 /**
2891 * @brief Set ADC calibration factor in the mode single-ended
2892 * or differential (for devices with differential mode available).
2893 * @note This function is intended to set calibration parameters
2894 * without having to perform a new calibration using
2895 * @ref LL_ADC_StartCalibration().
2896 * @note For devices with differential mode available:
2897 * Calibration of offset is specific to each of
2898 * single-ended and differential modes
2899 * (calibration factor must be specified for each of these
2900 * differential modes, if used afterwards and if the application
2901 * requires their calibration).
2902 * @note In case of setting calibration factors of both modes single ended
2903 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
2904 * both calibration factors must be concatenated.
2905 * To perform this processing, use helper macro
2906 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
2907 * @note On this STM32 series, setting of this feature is conditioned to
2908 * ADC state:
2909 * ADC must be enabled, without calibration on going, without conversion
2910 * on going on group regular.
2911 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
2912 * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
2913 * @param ADCx ADC instance
2914 * @param SingleDiff This parameter can be one of the following values:
2915 * @arg @ref LL_ADC_SINGLE_ENDED
2916 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2917 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
2918 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
2919 * @retval None
2920 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff,uint32_t CalibrationFactor)2921 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
2922 {
2923 MODIFY_REG(ADCx->CALFACT,
2924 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
2925 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
2926 }
2927
2928 /**
2929 * @brief Get ADC calibration factor in the mode single-ended
2930 * or differential (for devices with differential mode available).
2931 * @note Calibration factors are set by hardware after performing
2932 * a calibration run using function @ref LL_ADC_StartCalibration().
2933 * @note For devices with differential mode available:
2934 * Calibration of offset is specific to each of
2935 * single-ended and differential modes
2936 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
2937 * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
2938 * @param ADCx ADC instance
2939 * @param SingleDiff This parameter can be one of the following values:
2940 * @arg @ref LL_ADC_SINGLE_ENDED
2941 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2942 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
2943 */
LL_ADC_GetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff)2944 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
2945 {
2946 /* Retrieve bits with position in register depending on parameter */
2947 /* "SingleDiff". */
2948 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
2949 /* containing other bits reserved for other purpose. */
2950 return (uint32_t)(READ_BIT(ADCx->CALFACT,
2951 (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
2952 ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
2953 }
2954
2955 /**
2956 * @brief Set ADC resolution.
2957 * Refer to reference manual for alignments formats
2958 * dependencies to ADC resolutions.
2959 * @note On this STM32 series, setting of this feature is conditioned to
2960 * ADC state:
2961 * ADC must be disabled or enabled without conversion on going
2962 * on either groups regular or injected.
2963 * @rmtoll CFGR RES LL_ADC_SetResolution
2964 * @param ADCx ADC instance
2965 * @param Resolution This parameter can be one of the following values:
2966 * @arg @ref LL_ADC_RESOLUTION_12B
2967 * @arg @ref LL_ADC_RESOLUTION_10B
2968 * @arg @ref LL_ADC_RESOLUTION_8B
2969 * @arg @ref LL_ADC_RESOLUTION_6B
2970 * @retval None
2971 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)2972 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2973 {
2974 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
2975 }
2976
2977 /**
2978 * @brief Get ADC resolution.
2979 * Refer to reference manual for alignments formats
2980 * dependencies to ADC resolutions.
2981 * @rmtoll CFGR RES LL_ADC_GetResolution
2982 * @param ADCx ADC instance
2983 * @retval Returned value can be one of the following values:
2984 * @arg @ref LL_ADC_RESOLUTION_12B
2985 * @arg @ref LL_ADC_RESOLUTION_10B
2986 * @arg @ref LL_ADC_RESOLUTION_8B
2987 * @arg @ref LL_ADC_RESOLUTION_6B
2988 */
LL_ADC_GetResolution(ADC_TypeDef * ADCx)2989 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
2990 {
2991 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
2992 }
2993
2994 /**
2995 * @brief Set ADC conversion data alignment.
2996 * @note Refer to reference manual for alignments formats
2997 * dependencies to ADC resolutions.
2998 * @note On this STM32 series, setting of this feature is conditioned to
2999 * ADC state:
3000 * ADC must be disabled or enabled without conversion on going
3001 * on either groups regular or injected.
3002 * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
3003 * @param ADCx ADC instance
3004 * @param DataAlignment This parameter can be one of the following values:
3005 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
3006 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
3007 * @retval None
3008 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)3009 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
3010 {
3011 MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
3012 }
3013
3014 /**
3015 * @brief Get ADC conversion data alignment.
3016 * @note Refer to reference manual for alignments formats
3017 * dependencies to ADC resolutions.
3018 * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
3019 * @param ADCx ADC instance
3020 * @retval Returned value can be one of the following values:
3021 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
3022 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
3023 */
LL_ADC_GetDataAlignment(ADC_TypeDef * ADCx)3024 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
3025 {
3026 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
3027 }
3028
3029 /**
3030 * @brief Set ADC low power mode.
3031 * @note Description of ADC low power modes:
3032 * - ADC low power mode "auto wait": Dynamic low power mode,
3033 * ADC conversions occurrences are limited to the minimum necessary
3034 * in order to reduce power consumption.
3035 * New ADC conversion starts only when the previous
3036 * unitary conversion data (for ADC group regular)
3037 * or previous sequence conversions data (for ADC group injected)
3038 * has been retrieved by user software.
3039 * In the meantime, ADC remains idle: does not performs any
3040 * other conversion.
3041 * This mode allows to automatically adapt the ADC conversions
3042 * triggers to the speed of the software that reads the data.
3043 * Moreover, this avoids risk of overrun for low frequency
3044 * applications.
3045 * How to use this low power mode:
3046 * - It is not recommended to use with interruption or DMA
3047 * since these modes have to clear immediately the EOC flag
3048 * (by CPU to free the IRQ pending event or by DMA).
3049 * Auto wait will work but fort a very short time, discarding
3050 * its intended benefit (except specific case of high load of CPU
3051 * or DMA transfers which can justify usage of auto wait).
3052 * - Do use with polling: 1. Start conversion,
3053 * 2. Later on, when conversion data is needed: poll for end of
3054 * conversion to ensure that conversion is completed and
3055 * retrieve ADC conversion data. This will trig another
3056 * ADC conversion start.
3057 * - ADC low power mode "auto power-off" (feature available on
3058 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
3059 * the ADC automatically powers-off after a conversion and
3060 * automatically wakes up when a new conversion is triggered
3061 * (with startup time between trigger and start of sampling).
3062 * This feature can be combined with low power mode "auto wait".
3063 * @note With ADC low power mode "auto wait", the ADC conversion data read
3064 * is corresponding to previous ADC conversion start, independently
3065 * of delay during which ADC was idle.
3066 * Therefore, the ADC conversion data may be outdated: does not
3067 * correspond to the current voltage level on the selected
3068 * ADC channel.
3069 * @note On this STM32 series, setting of this feature is conditioned to
3070 * ADC state:
3071 * ADC must be disabled or enabled without conversion on going
3072 * on either groups regular or injected.
3073 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
3074 * @param ADCx ADC instance
3075 * @param LowPowerMode This parameter can be one of the following values:
3076 * @arg @ref LL_ADC_LP_MODE_NONE
3077 * @arg @ref LL_ADC_LP_AUTOWAIT
3078 * @retval None
3079 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)3080 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
3081 {
3082 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
3083 }
3084
3085 /**
3086 * @brief Get ADC low power mode:
3087 * @note Description of ADC low power modes:
3088 * - ADC low power mode "auto wait": Dynamic low power mode,
3089 * ADC conversions occurrences are limited to the minimum necessary
3090 * in order to reduce power consumption.
3091 * New ADC conversion starts only when the previous
3092 * unitary conversion data (for ADC group regular)
3093 * or previous sequence conversions data (for ADC group injected)
3094 * has been retrieved by user software.
3095 * In the meantime, ADC remains idle: does not performs any
3096 * other conversion.
3097 * This mode allows to automatically adapt the ADC conversions
3098 * triggers to the speed of the software that reads the data.
3099 * Moreover, this avoids risk of overrun for low frequency
3100 * applications.
3101 * How to use this low power mode:
3102 * - It is not recommended to use with interruption or DMA
3103 * since these modes have to clear immediately the EOC flag
3104 * (by CPU to free the IRQ pending event or by DMA).
3105 * Auto wait will work but fort a very short time, discarding
3106 * its intended benefit (except specific case of high load of CPU
3107 * or DMA transfers which can justify usage of auto wait).
3108 * - Do use with polling: 1. Start conversion,
3109 * 2. Later on, when conversion data is needed: poll for end of
3110 * conversion to ensure that conversion is completed and
3111 * retrieve ADC conversion data. This will trig another
3112 * ADC conversion start.
3113 * - ADC low power mode "auto power-off" (feature available on
3114 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
3115 * the ADC automatically powers-off after a conversion and
3116 * automatically wakes up when a new conversion is triggered
3117 * (with startup time between trigger and start of sampling).
3118 * This feature can be combined with low power mode "auto wait".
3119 * @note With ADC low power mode "auto wait", the ADC conversion data read
3120 * is corresponding to previous ADC conversion start, independently
3121 * of delay during which ADC was idle.
3122 * Therefore, the ADC conversion data may be outdated: does not
3123 * correspond to the current voltage level on the selected
3124 * ADC channel.
3125 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
3126 * @param ADCx ADC instance
3127 * @retval Returned value can be one of the following values:
3128 * @arg @ref LL_ADC_LP_MODE_NONE
3129 * @arg @ref LL_ADC_LP_AUTOWAIT
3130 */
LL_ADC_GetLowPowerMode(ADC_TypeDef * ADCx)3131 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
3132 {
3133 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
3134 }
3135
3136 /**
3137 * @brief Set ADC selected offset number 1, 2, 3 or 4.
3138 * @note This function set the 2 items of offset configuration:
3139 * - ADC channel to which the offset programmed will be applied
3140 * (independently of channel mapped on ADC group regular
3141 * or group injected)
3142 * - Offset level (offset to be subtracted from the raw
3143 * converted data).
3144 * @note Caution: Offset format is dependent to ADC resolution:
3145 * offset has to be left-aligned on bit 11, the LSB (right bits)
3146 * are set to 0.
3147 * @note This function enables the offset, by default. It can be forced
3148 * to disable state using function LL_ADC_SetOffsetState().
3149 * @note If a channel is mapped on several offsets numbers, only the offset
3150 * with the lowest value is considered for the subtraction.
3151 * @note On this STM32 series, setting of this feature is conditioned to
3152 * ADC state:
3153 * ADC must be disabled or enabled without conversion on going
3154 * on either groups regular or injected.
3155 * @note On STM32G4, some fast channels are available: fast analog inputs
3156 * coming from GPIO pads (ADC_IN1..5).
3157 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
3158 * OFR1 OFFSET1 LL_ADC_SetOffset\n
3159 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
3160 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
3161 * OFR2 OFFSET2 LL_ADC_SetOffset\n
3162 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
3163 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
3164 * OFR3 OFFSET3 LL_ADC_SetOffset\n
3165 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
3166 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
3167 * OFR4 OFFSET4 LL_ADC_SetOffset\n
3168 * OFR4 OFFSET4_EN LL_ADC_SetOffset
3169 * @param ADCx ADC instance
3170 * @param Offsety This parameter can be one of the following values:
3171 * @arg @ref LL_ADC_OFFSET_1
3172 * @arg @ref LL_ADC_OFFSET_2
3173 * @arg @ref LL_ADC_OFFSET_3
3174 * @arg @ref LL_ADC_OFFSET_4
3175 * @param Channel This parameter can be one of the following values:
3176 * @arg @ref LL_ADC_CHANNEL_0
3177 * @arg @ref LL_ADC_CHANNEL_1 (8)
3178 * @arg @ref LL_ADC_CHANNEL_2 (8)
3179 * @arg @ref LL_ADC_CHANNEL_3 (8)
3180 * @arg @ref LL_ADC_CHANNEL_4 (8)
3181 * @arg @ref LL_ADC_CHANNEL_5 (8)
3182 * @arg @ref LL_ADC_CHANNEL_6
3183 * @arg @ref LL_ADC_CHANNEL_7
3184 * @arg @ref LL_ADC_CHANNEL_8
3185 * @arg @ref LL_ADC_CHANNEL_9
3186 * @arg @ref LL_ADC_CHANNEL_10
3187 * @arg @ref LL_ADC_CHANNEL_11
3188 * @arg @ref LL_ADC_CHANNEL_12
3189 * @arg @ref LL_ADC_CHANNEL_13
3190 * @arg @ref LL_ADC_CHANNEL_14
3191 * @arg @ref LL_ADC_CHANNEL_15
3192 * @arg @ref LL_ADC_CHANNEL_16
3193 * @arg @ref LL_ADC_CHANNEL_17
3194 * @arg @ref LL_ADC_CHANNEL_18
3195 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
3196 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
3197 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
3198 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
3199 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
3200 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
3201 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
3202 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
3203 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
3204 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
3205 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
3206 *
3207 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
3208 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
3209 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
3210 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
3211 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
3212 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
3213 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
3214 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
3215 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
3216 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
3217 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
3218 * @retval None
3219 */
LL_ADC_SetOffset(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t Channel,uint32_t OffsetLevel)3220 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
3221 {
3222 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3223
3224 MODIFY_REG(*preg,
3225 ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
3226 ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
3227 }
3228
3229 /**
3230 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3231 * Channel to which the offset programmed will be applied
3232 * (independently of channel mapped on ADC group regular
3233 * or group injected)
3234 * @note Usage of the returned channel number:
3235 * - To reinject this channel into another function LL_ADC_xxx:
3236 * the returned channel number is only partly formatted on definition
3237 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3238 * with parts of literals LL_ADC_CHANNEL_x or using
3239 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3240 * Then the selected literal LL_ADC_CHANNEL_x can be used
3241 * as parameter for another function.
3242 * - To get the channel number in decimal format:
3243 * process the returned value with the helper macro
3244 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3245 * @note On STM32G4, some fast channels are available: fast analog inputs
3246 * coming from GPIO pads (ADC_IN1..5).
3247 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
3248 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
3249 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
3250 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
3251 * @param ADCx ADC instance
3252 * @param Offsety This parameter can be one of the following values:
3253 * @arg @ref LL_ADC_OFFSET_1
3254 * @arg @ref LL_ADC_OFFSET_2
3255 * @arg @ref LL_ADC_OFFSET_3
3256 * @arg @ref LL_ADC_OFFSET_4
3257 * @retval Returned value can be one of the following values:
3258 * @arg @ref LL_ADC_CHANNEL_0
3259 * @arg @ref LL_ADC_CHANNEL_1 (8)
3260 * @arg @ref LL_ADC_CHANNEL_2 (8)
3261 * @arg @ref LL_ADC_CHANNEL_3 (8)
3262 * @arg @ref LL_ADC_CHANNEL_4 (8)
3263 * @arg @ref LL_ADC_CHANNEL_5 (8)
3264 * @arg @ref LL_ADC_CHANNEL_6
3265 * @arg @ref LL_ADC_CHANNEL_7
3266 * @arg @ref LL_ADC_CHANNEL_8
3267 * @arg @ref LL_ADC_CHANNEL_9
3268 * @arg @ref LL_ADC_CHANNEL_10
3269 * @arg @ref LL_ADC_CHANNEL_11
3270 * @arg @ref LL_ADC_CHANNEL_12
3271 * @arg @ref LL_ADC_CHANNEL_13
3272 * @arg @ref LL_ADC_CHANNEL_14
3273 * @arg @ref LL_ADC_CHANNEL_15
3274 * @arg @ref LL_ADC_CHANNEL_16
3275 * @arg @ref LL_ADC_CHANNEL_17
3276 * @arg @ref LL_ADC_CHANNEL_18
3277 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
3278 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
3279 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
3280 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
3281 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
3282 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
3283 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
3284 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
3285 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
3286 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
3287 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
3288 *
3289 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
3290 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
3291 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
3292 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
3293 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
3294 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
3295 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
3296 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
3297 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
3298 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
3299 * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
3300 * comparison with internal channel parameter to be done
3301 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3302 */
LL_ADC_GetOffsetChannel(ADC_TypeDef * ADCx,uint32_t Offsety)3303 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
3304 {
3305 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3306
3307 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
3308 }
3309
3310 /**
3311 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3312 * Offset level (offset to be subtracted from the raw
3313 * converted data).
3314 * @note Caution: Offset format is dependent to ADC resolution:
3315 * offset has to be left-aligned on bit 11, the LSB (right bits)
3316 * are set to 0.
3317 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
3318 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
3319 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
3320 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
3321 * @param ADCx ADC instance
3322 * @param Offsety This parameter can be one of the following values:
3323 * @arg @ref LL_ADC_OFFSET_1
3324 * @arg @ref LL_ADC_OFFSET_2
3325 * @arg @ref LL_ADC_OFFSET_3
3326 * @arg @ref LL_ADC_OFFSET_4
3327 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3328 */
LL_ADC_GetOffsetLevel(ADC_TypeDef * ADCx,uint32_t Offsety)3329 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
3330 {
3331 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3332
3333 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
3334 }
3335
3336 /**
3337 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3338 * force offset state disable or enable
3339 * without modifying offset channel or offset value.
3340 * @note This function should be needed only in case of offset to be
3341 * enabled-disabled dynamically, and should not be needed in other cases:
3342 * function LL_ADC_SetOffset() automatically enables the offset.
3343 * @note On this STM32 series, setting of this feature is conditioned to
3344 * ADC state:
3345 * ADC must be disabled or enabled without conversion on going
3346 * on either groups regular or injected.
3347 * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
3348 * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
3349 * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
3350 * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
3351 * @param ADCx ADC instance
3352 * @param Offsety This parameter can be one of the following values:
3353 * @arg @ref LL_ADC_OFFSET_1
3354 * @arg @ref LL_ADC_OFFSET_2
3355 * @arg @ref LL_ADC_OFFSET_3
3356 * @arg @ref LL_ADC_OFFSET_4
3357 * @param OffsetState This parameter can be one of the following values:
3358 * @arg @ref LL_ADC_OFFSET_DISABLE
3359 * @arg @ref LL_ADC_OFFSET_ENABLE
3360 * @retval None
3361 */
LL_ADC_SetOffsetState(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetState)3362 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
3363 {
3364 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3365
3366 MODIFY_REG(*preg,
3367 ADC_OFR1_OFFSET1_EN,
3368 OffsetState);
3369 }
3370
3371 /**
3372 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3373 * offset state disabled or enabled.
3374 * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
3375 * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
3376 * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
3377 * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
3378 * @param ADCx ADC instance
3379 * @param Offsety This parameter can be one of the following values:
3380 * @arg @ref LL_ADC_OFFSET_1
3381 * @arg @ref LL_ADC_OFFSET_2
3382 * @arg @ref LL_ADC_OFFSET_3
3383 * @arg @ref LL_ADC_OFFSET_4
3384 * @retval Returned value can be one of the following values:
3385 * @arg @ref LL_ADC_OFFSET_DISABLE
3386 * @arg @ref LL_ADC_OFFSET_ENABLE
3387 */
LL_ADC_GetOffsetState(ADC_TypeDef * ADCx,uint32_t Offsety)3388 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
3389 {
3390 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3391
3392 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
3393 }
3394
3395 /**
3396 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3397 * choose offset sign.
3398 * @note On this STM32 series, setting of this feature is conditioned to
3399 * ADC state:
3400 * ADC must be disabled or enabled without conversion on going
3401 * on either groups regular or injected.
3402 * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign\n
3403 * OFR2 OFFSETPOS LL_ADC_SetOffsetSign\n
3404 * OFR3 OFFSETPOS LL_ADC_SetOffsetSign\n
3405 * OFR4 OFFSETPOS LL_ADC_SetOffsetSign
3406 * @param ADCx ADC instance
3407 * @param Offsety This parameter can be one of the following values:
3408 * @arg @ref LL_ADC_OFFSET_1
3409 * @arg @ref LL_ADC_OFFSET_2
3410 * @arg @ref LL_ADC_OFFSET_3
3411 * @arg @ref LL_ADC_OFFSET_4
3412 * @param OffsetSign This parameter can be one of the following values:
3413 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
3414 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
3415 * @retval None
3416 */
LL_ADC_SetOffsetSign(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetSign)3417 __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
3418 {
3419 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3420
3421 MODIFY_REG(*preg,
3422 ADC_OFR1_OFFSETPOS,
3423 OffsetSign);
3424 }
3425
3426 /**
3427 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3428 * offset sign if positive or negative.
3429 * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n
3430 * OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n
3431 * OFR3 OFFSETPOS LL_ADC_GetOffsetSign\n
3432 * OFR4 OFFSETPOS LL_ADC_GetOffsetSign
3433 * @param ADCx ADC instance
3434 * @param Offsety This parameter can be one of the following values:
3435 * @arg @ref LL_ADC_OFFSET_1
3436 * @arg @ref LL_ADC_OFFSET_2
3437 * @arg @ref LL_ADC_OFFSET_3
3438 * @arg @ref LL_ADC_OFFSET_4
3439 * @retval Returned value can be one of the following values:
3440 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
3441 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
3442 */
LL_ADC_GetOffsetSign(ADC_TypeDef * ADCx,uint32_t Offsety)3443 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety)
3444 {
3445 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3446
3447 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS);
3448 }
3449
3450 /**
3451 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3452 * choose offset saturation mode.
3453 * @note On this STM32 series, setting of this feature is conditioned to
3454 * ADC state:
3455 * ADC must be disabled or enabled without conversion on going
3456 * on either groups regular or injected.
3457 * @rmtoll OFR1 SATEN LL_ADC_SetOffsetSaturation\n
3458 * OFR2 SATEN LL_ADC_SetOffsetSaturation\n
3459 * OFR3 SATEN LL_ADC_SetOffsetSaturation\n
3460 * OFR4 SATEN LL_ADC_SetOffsetSaturation
3461 * @param ADCx ADC instance
3462 * @param Offsety This parameter can be one of the following values:
3463 * @arg @ref LL_ADC_OFFSET_1
3464 * @arg @ref LL_ADC_OFFSET_2
3465 * @arg @ref LL_ADC_OFFSET_3
3466 * @arg @ref LL_ADC_OFFSET_4
3467 * @param OffsetSaturation This parameter can be one of the following values:
3468 * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
3469 * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
3470 * @retval None
3471 */
LL_ADC_SetOffsetSaturation(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetSaturation)3472 __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
3473 {
3474 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3475
3476 MODIFY_REG(*preg,
3477 ADC_OFR1_SATEN,
3478 OffsetSaturation);
3479 }
3480
3481 /**
3482 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3483 * offset saturation if enabled or disabled.
3484 * @rmtoll OFR1 SATEN LL_ADC_GetOffsetSaturation\n
3485 * OFR2 SATEN LL_ADC_GetOffsetSaturation\n
3486 * OFR3 SATEN LL_ADC_GetOffsetSaturation\n
3487 * OFR4 SATEN LL_ADC_GetOffsetSaturation
3488 * @param ADCx ADC instance
3489 * @param Offsety This parameter can be one of the following values:
3490 * @arg @ref LL_ADC_OFFSET_1
3491 * @arg @ref LL_ADC_OFFSET_2
3492 * @arg @ref LL_ADC_OFFSET_3
3493 * @arg @ref LL_ADC_OFFSET_4
3494 * @retval Returned value can be one of the following values:
3495 * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
3496 * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
3497 */
LL_ADC_GetOffsetSaturation(ADC_TypeDef * ADCx,uint32_t Offsety)3498 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
3499 {
3500 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3501
3502 return (uint32_t) READ_BIT(*preg, ADC_OFR1_SATEN);
3503 }
3504
3505 /**
3506 * @brief Set ADC gain compensation.
3507 * @note This function set the gain compensation coefficient
3508 * that is applied to raw converted data using the formula:
3509 * DATA = DATA(raw) * (gain compensation coef) / 4096
3510 * @note This function enables the gain compensation if given
3511 * coefficient is above 0, otherwise it disables it.
3512 * @note Gain compensation when enabled is applied to all channels.
3513 * @note On this STM32 series, setting of this feature is conditioned to
3514 * ADC state:
3515 * ADC must be disabled or enabled without conversion on going
3516 * on either groups regular or injected.
3517 * @rmtoll GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation\n
3518 * CFGR2 GCOMP LL_ADC_SetGainCompensation
3519 * @param ADCx ADC instance
3520 * @param GainCompensation This parameter can be:
3521 * 0 Gain compensation will be disabled and value set to 0
3522 * 1 -> 16393 Gain compensation will be enabled with specified value
3523 * @retval None
3524 */
LL_ADC_SetGainCompensation(ADC_TypeDef * ADCx,uint32_t GainCompensation)3525 __STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation)
3526 {
3527 MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation);
3528 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_GCOMP, ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_CFGR2_GCOMP_Pos);
3529 }
3530
3531 /**
3532 * @brief Get the ADC gain compensation value
3533 * @rmtoll GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation\n
3534 * CFGR2 GCOMP LL_ADC_GetGainCompensation
3535 * @param ADCx ADC instance
3536 * @retval Returned value can be:
3537 * 0 Gain compensation is disabled
3538 * 1 -> 16393 Gain compensation is enabled with returned value
3539 */
LL_ADC_GetGainCompensation(ADC_TypeDef * ADCx)3540 __STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(ADC_TypeDef *ADCx)
3541 {
3542 return ((READ_BIT(ADCx->CFGR2, ADC_CFGR2_GCOMP) == ADC_CFGR2_GCOMP) ? READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL);
3543 }
3544
3545 #if defined(ADC_SMPR1_SMPPLUS)
3546 /**
3547 * @brief Set ADC sampling time common configuration impacting
3548 * settings of sampling time channel wise.
3549 * @note On this STM32 series, setting of this feature is conditioned to
3550 * ADC state:
3551 * ADC must be disabled or enabled without conversion on going
3552 * on either groups regular or injected.
3553 * @rmtoll SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig
3554 * @param ADCx ADC instance
3555 * @param SamplingTimeCommonConfig This parameter can be one of the following values:
3556 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
3557 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
3558 * @retval None
3559 */
LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef * ADCx,uint32_t SamplingTimeCommonConfig)3560 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
3561 {
3562 MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
3563 }
3564
3565 /**
3566 * @brief Get ADC sampling time common configuration impacting
3567 * settings of sampling time channel wise.
3568 * @rmtoll SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig
3569 * @param ADCx ADC instance
3570 * @retval Returned value can be one of the following values:
3571 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
3572 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
3573 */
LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef * ADCx)3574 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx)
3575 {
3576 return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
3577 }
3578 #endif /* ADC_SMPR1_SMPPLUS */
3579
3580 /**
3581 * @}
3582 */
3583
3584 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
3585 * @{
3586 */
3587
3588 /**
3589 * @brief Set ADC group regular conversion trigger source:
3590 * internal (SW start) or from external peripheral (timer event,
3591 * external interrupt line).
3592 * @note On this STM32 series, setting trigger source to external trigger
3593 * also set trigger polarity to rising edge
3594 * (default setting for compatibility with some ADC on other
3595 * STM32 families having this setting set by HW default value).
3596 * In case of need to modify trigger edge, use
3597 * function @ref LL_ADC_REG_SetTriggerEdge().
3598 * @note Availability of parameters of trigger sources from timer
3599 * depends on timers availability on the selected device.
3600 * @note On this STM32 series, setting of this feature is conditioned to
3601 * ADC state:
3602 * ADC must be disabled or enabled without conversion on going
3603 * on group regular.
3604 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
3605 * CFGR EXTEN LL_ADC_REG_SetTriggerSource
3606 * @param ADCx ADC instance
3607 * @param TriggerSource This parameter can be one of the following values:
3608 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3609 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3610 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3611 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1)
3612 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1)
3613 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3614 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3615 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2)
3616 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1)
3617 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2)
3618 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3619 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2)
3620 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1)
3621 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3622 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2)
3623 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1)
3624 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3625 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
3626 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3627 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3628 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2)
3629 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3630 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
3631 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
3632 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
3633 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1)
3634 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1)
3635 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
3636 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2)
3637 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
3638 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2)
3639 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
3640 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
3641 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
3642 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
3643 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
3644 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
3645 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1)
3646 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2)
3647 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
3648 *
3649 * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
3650 * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
3651 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
3652 * @retval None
3653 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)3654 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3655 {
3656 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
3657 }
3658
3659 /**
3660 * @brief Get ADC group regular conversion trigger source:
3661 * internal (SW start) or from external peripheral (timer event,
3662 * external interrupt line).
3663 * @note To determine whether group regular trigger source is
3664 * internal (SW start) or external, without detail
3665 * of which peripheral is selected as external trigger,
3666 * (equivalent to
3667 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
3668 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
3669 * @note Availability of parameters of trigger sources from timer
3670 * depends on timers availability on the selected device.
3671 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
3672 * CFGR EXTEN LL_ADC_REG_GetTriggerSource
3673 * @param ADCx ADC instance
3674 * @retval Returned value can be one of the following values:
3675 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3676 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3677 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3678 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1)
3679 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1)
3680 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3681 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3682 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2)
3683 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1)
3684 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2)
3685 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3686 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2)
3687 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1)
3688 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3689 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2)
3690 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1)
3691 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3692 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
3693 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3694 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3695 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2)
3696 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3697 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
3698 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
3699 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
3700 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1)
3701 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1)
3702 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
3703 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2)
3704 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
3705 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2)
3706 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
3707 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
3708 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
3709 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
3710 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
3711 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
3712 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1)
3713 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2)
3714 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
3715 *
3716 * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
3717 * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
3718 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
3719 */
LL_ADC_REG_GetTriggerSource(ADC_TypeDef * ADCx)3720 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
3721 {
3722 __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
3723
3724 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3725 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
3726 uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3727
3728 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
3729 /* to match with triggers literals definition. */
3730 return ((TriggerSource
3731 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
3732 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
3733 );
3734 }
3735
3736 /**
3737 * @brief Get ADC group regular conversion trigger source internal (SW start)
3738 * or external.
3739 * @note In case of group regular trigger source set to external trigger,
3740 * to determine which peripheral is selected as external trigger,
3741 * use function @ref LL_ADC_REG_GetTriggerSource().
3742 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
3743 * @param ADCx ADC instance
3744 * @retval Value "0" if trigger source external trigger
3745 * Value "1" if trigger source SW start.
3746 */
LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)3747 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
3748 {
3749 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
3750 }
3751
3752 /**
3753 * @brief Set ADC group regular conversion trigger polarity.
3754 * @note Applicable only for trigger source set to external trigger.
3755 * @note On this STM32 series, setting of this feature is conditioned to
3756 * ADC state:
3757 * ADC must be disabled or enabled without conversion on going
3758 * on group regular.
3759 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
3760 * @param ADCx ADC instance
3761 * @param ExternalTriggerEdge This parameter can be one of the following values:
3762 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3763 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3764 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3765 * @retval None
3766 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3767 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3768 {
3769 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
3770 }
3771
3772 /**
3773 * @brief Get ADC group regular conversion trigger polarity.
3774 * @note Applicable only for trigger source set to external trigger.
3775 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
3776 * @param ADCx ADC instance
3777 * @retval Returned value can be one of the following values:
3778 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3779 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3780 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3781 */
LL_ADC_REG_GetTriggerEdge(ADC_TypeDef * ADCx)3782 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
3783 {
3784 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
3785 }
3786
3787 /**
3788 * @brief Set ADC sampling mode.
3789 * @note This function set the ADC conversion sampling mode
3790 * @note This mode applies to regular group only.
3791 * @note Set sampling mode is applied to all conversion of regular group.
3792 * @note On this STM32 series, setting of this feature is conditioned to
3793 * ADC state:
3794 * ADC must be disabled or enabled without conversion on going
3795 * on group regular.
3796 * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n
3797 * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode
3798 * @param ADCx ADC instance
3799 * @param SamplingMode This parameter can be one of the following values:
3800 * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
3801 * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
3802 * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
3803 * @retval None
3804 */
LL_ADC_REG_SetSamplingMode(ADC_TypeDef * ADCx,uint32_t SamplingMode)3805 __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
3806 {
3807 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
3808 }
3809
3810 /**
3811 * @brief Get the ADC sampling mode
3812 * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode\n
3813 * CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode
3814 * @param ADCx ADC instance
3815 * @retval Returned value can be one of the following values:
3816 * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
3817 * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
3818 * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
3819 */
LL_ADC_REG_GetSamplingMode(ADC_TypeDef * ADCx)3820 __STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(ADC_TypeDef *ADCx)
3821 {
3822 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
3823 }
3824
3825 /**
3826 * @brief Set ADC group regular sequencer length and scan direction.
3827 * @note Description of ADC group regular sequencer features:
3828 * - For devices with sequencer fully configurable
3829 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3830 * sequencer length and each rank affectation to a channel
3831 * are configurable.
3832 * This function performs configuration of:
3833 * - Sequence length: Number of ranks in the scan sequence.
3834 * - Sequence direction: Unless specified in parameters, sequencer
3835 * scan direction is forward (from rank 1 to rank n).
3836 * Sequencer ranks are selected using
3837 * function "LL_ADC_REG_SetSequencerRanks()".
3838 * - For devices with sequencer not fully configurable
3839 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3840 * sequencer length and each rank affectation to a channel
3841 * are defined by channel number.
3842 * This function performs configuration of:
3843 * - Sequence length: Number of ranks in the scan sequence is
3844 * defined by number of channels set in the sequence,
3845 * rank of each channel is fixed by channel HW number.
3846 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3847 * - Sequence direction: Unless specified in parameters, sequencer
3848 * scan direction is forward (from lowest channel number to
3849 * highest channel number).
3850 * Sequencer ranks are selected using
3851 * function "LL_ADC_REG_SetSequencerChannels()".
3852 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3853 * ADC conversion on only 1 channel.
3854 * @note On this STM32 series, setting of this feature is conditioned to
3855 * ADC state:
3856 * ADC must be disabled or enabled without conversion on going
3857 * on group regular.
3858 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
3859 * @param ADCx ADC instance
3860 * @param SequencerNbRanks This parameter can be one of the following values:
3861 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3862 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3863 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3864 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3865 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3866 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3867 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3868 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3869 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3870 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3871 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3872 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3873 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3874 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3875 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3876 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3877 * @retval None
3878 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)3879 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
3880 {
3881 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
3882 }
3883
3884 /**
3885 * @brief Get ADC group regular sequencer length and scan direction.
3886 * @note Description of ADC group regular sequencer features:
3887 * - For devices with sequencer fully configurable
3888 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3889 * sequencer length and each rank affectation to a channel
3890 * are configurable.
3891 * This function retrieves:
3892 * - Sequence length: Number of ranks in the scan sequence.
3893 * - Sequence direction: Unless specified in parameters, sequencer
3894 * scan direction is forward (from rank 1 to rank n).
3895 * Sequencer ranks are selected using
3896 * function "LL_ADC_REG_SetSequencerRanks()".
3897 * - For devices with sequencer not fully configurable
3898 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3899 * sequencer length and each rank affectation to a channel
3900 * are defined by channel number.
3901 * This function retrieves:
3902 * - Sequence length: Number of ranks in the scan sequence is
3903 * defined by number of channels set in the sequence,
3904 * rank of each channel is fixed by channel HW number.
3905 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3906 * - Sequence direction: Unless specified in parameters, sequencer
3907 * scan direction is forward (from lowest channel number to
3908 * highest channel number).
3909 * Sequencer ranks are selected using
3910 * function "LL_ADC_REG_SetSequencerChannels()".
3911 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3912 * ADC conversion on only 1 channel.
3913 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
3914 * @param ADCx ADC instance
3915 * @retval Returned value can be one of the following values:
3916 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3917 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3918 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3919 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3920 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3921 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3922 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3923 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3924 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3925 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3926 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3927 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3928 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3929 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3930 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3931 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3932 */
LL_ADC_REG_GetSequencerLength(ADC_TypeDef * ADCx)3933 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
3934 {
3935 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
3936 }
3937
3938 /**
3939 * @brief Set ADC group regular sequencer discontinuous mode:
3940 * sequence subdivided and scan conversions interrupted every selected
3941 * number of ranks.
3942 * @note It is not possible to enable both ADC group regular
3943 * continuous mode and sequencer discontinuous mode.
3944 * @note It is not possible to enable both ADC auto-injected mode
3945 * and ADC group regular sequencer discontinuous mode.
3946 * @note On this STM32 series, setting of this feature is conditioned to
3947 * ADC state:
3948 * ADC must be disabled or enabled without conversion on going
3949 * on group regular.
3950 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
3951 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
3952 * @param ADCx ADC instance
3953 * @param SeqDiscont This parameter can be one of the following values:
3954 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3955 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3956 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3957 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
3958 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
3959 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
3960 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
3961 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
3962 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
3963 * @retval None
3964 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)3965 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
3966 {
3967 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
3968 }
3969
3970 /**
3971 * @brief Get ADC group regular sequencer discontinuous mode:
3972 * sequence subdivided and scan conversions interrupted every selected
3973 * number of ranks.
3974 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
3975 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
3976 * @param ADCx ADC instance
3977 * @retval Returned value can be one of the following values:
3978 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3979 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3980 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3981 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
3982 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
3983 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
3984 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
3985 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
3986 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
3987 */
LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef * ADCx)3988 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
3989 {
3990 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
3991 }
3992
3993 /**
3994 * @brief Set ADC group regular sequence: channel on the selected
3995 * scan sequence rank.
3996 * @note This function performs configuration of:
3997 * - Channels ordering into each rank of scan sequence:
3998 * whatever channel can be placed into whatever rank.
3999 * @note On this STM32 series, ADC group regular sequencer is
4000 * fully configurable: sequencer length and each rank
4001 * affectation to a channel are configurable.
4002 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4003 * @note Depending on devices and packages, some channels may not be available.
4004 * Refer to device datasheet for channels availability.
4005 * @note On this STM32 series, to measure internal channels (VrefInt,
4006 * TempSensor, ...), measurement paths to internal channels must be
4007 * enabled separately.
4008 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4009 * @note On this STM32 series, setting of this feature is conditioned to
4010 * ADC state:
4011 * ADC must be disabled or enabled without conversion on going
4012 * on group regular.
4013 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
4014 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
4015 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
4016 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
4017 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
4018 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
4019 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
4020 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
4021 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
4022 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
4023 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
4024 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
4025 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
4026 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
4027 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
4028 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
4029 * @param ADCx ADC instance
4030 * @param Rank This parameter can be one of the following values:
4031 * @arg @ref LL_ADC_REG_RANK_1
4032 * @arg @ref LL_ADC_REG_RANK_2
4033 * @arg @ref LL_ADC_REG_RANK_3
4034 * @arg @ref LL_ADC_REG_RANK_4
4035 * @arg @ref LL_ADC_REG_RANK_5
4036 * @arg @ref LL_ADC_REG_RANK_6
4037 * @arg @ref LL_ADC_REG_RANK_7
4038 * @arg @ref LL_ADC_REG_RANK_8
4039 * @arg @ref LL_ADC_REG_RANK_9
4040 * @arg @ref LL_ADC_REG_RANK_10
4041 * @arg @ref LL_ADC_REG_RANK_11
4042 * @arg @ref LL_ADC_REG_RANK_12
4043 * @arg @ref LL_ADC_REG_RANK_13
4044 * @arg @ref LL_ADC_REG_RANK_14
4045 * @arg @ref LL_ADC_REG_RANK_15
4046 * @arg @ref LL_ADC_REG_RANK_16
4047 * @param Channel This parameter can be one of the following values:
4048 * @arg @ref LL_ADC_CHANNEL_0
4049 * @arg @ref LL_ADC_CHANNEL_1 (8)
4050 * @arg @ref LL_ADC_CHANNEL_2 (8)
4051 * @arg @ref LL_ADC_CHANNEL_3 (8)
4052 * @arg @ref LL_ADC_CHANNEL_4 (8)
4053 * @arg @ref LL_ADC_CHANNEL_5 (8)
4054 * @arg @ref LL_ADC_CHANNEL_6
4055 * @arg @ref LL_ADC_CHANNEL_7
4056 * @arg @ref LL_ADC_CHANNEL_8
4057 * @arg @ref LL_ADC_CHANNEL_9
4058 * @arg @ref LL_ADC_CHANNEL_10
4059 * @arg @ref LL_ADC_CHANNEL_11
4060 * @arg @ref LL_ADC_CHANNEL_12
4061 * @arg @ref LL_ADC_CHANNEL_13
4062 * @arg @ref LL_ADC_CHANNEL_14
4063 * @arg @ref LL_ADC_CHANNEL_15
4064 * @arg @ref LL_ADC_CHANNEL_16
4065 * @arg @ref LL_ADC_CHANNEL_17
4066 * @arg @ref LL_ADC_CHANNEL_18
4067 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
4068 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
4069 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
4070 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
4071 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4072 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4073 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
4074 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
4075 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
4076 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
4077 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
4078 *
4079 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
4080 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
4081 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
4082 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
4083 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
4084 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
4085 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
4086 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
4087 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
4088 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
4089 * @retval None
4090 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4091 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4092 {
4093 /* Set bits with content of parameter "Channel" with bits position */
4094 /* in register and register position depending on parameter "Rank". */
4095 /* Parameters "Rank" and "Channel" are used with masks because containing */
4096 /* other bits reserved for other purpose. */
4097 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4098
4099 MODIFY_REG(*preg,
4100 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
4101 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
4102 }
4103
4104 /**
4105 * @brief Get ADC group regular sequence: channel on the selected
4106 * scan sequence rank.
4107 * @note On this STM32 series, ADC group regular sequencer is
4108 * fully configurable: sequencer length and each rank
4109 * affectation to a channel are configurable.
4110 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
4111 * @note Depending on devices and packages, some channels may not be available.
4112 * Refer to device datasheet for channels availability.
4113 * @note Usage of the returned channel number:
4114 * - To reinject this channel into another function LL_ADC_xxx:
4115 * the returned channel number is only partly formatted on definition
4116 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4117 * with parts of literals LL_ADC_CHANNEL_x or using
4118 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4119 * Then the selected literal LL_ADC_CHANNEL_x can be used
4120 * as parameter for another function.
4121 * - To get the channel number in decimal format:
4122 * process the returned value with the helper macro
4123 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4124 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
4125 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
4126 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
4127 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
4128 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
4129 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
4130 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
4131 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
4132 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
4133 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
4134 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
4135 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
4136 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
4137 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
4138 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
4139 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
4140 * @param ADCx ADC instance
4141 * @param Rank This parameter can be one of the following values:
4142 * @arg @ref LL_ADC_REG_RANK_1
4143 * @arg @ref LL_ADC_REG_RANK_2
4144 * @arg @ref LL_ADC_REG_RANK_3
4145 * @arg @ref LL_ADC_REG_RANK_4
4146 * @arg @ref LL_ADC_REG_RANK_5
4147 * @arg @ref LL_ADC_REG_RANK_6
4148 * @arg @ref LL_ADC_REG_RANK_7
4149 * @arg @ref LL_ADC_REG_RANK_8
4150 * @arg @ref LL_ADC_REG_RANK_9
4151 * @arg @ref LL_ADC_REG_RANK_10
4152 * @arg @ref LL_ADC_REG_RANK_11
4153 * @arg @ref LL_ADC_REG_RANK_12
4154 * @arg @ref LL_ADC_REG_RANK_13
4155 * @arg @ref LL_ADC_REG_RANK_14
4156 * @arg @ref LL_ADC_REG_RANK_15
4157 * @arg @ref LL_ADC_REG_RANK_16
4158 * @retval Returned value can be one of the following values:
4159 * @arg @ref LL_ADC_CHANNEL_0
4160 * @arg @ref LL_ADC_CHANNEL_1 (8)
4161 * @arg @ref LL_ADC_CHANNEL_2 (8)
4162 * @arg @ref LL_ADC_CHANNEL_3 (8)
4163 * @arg @ref LL_ADC_CHANNEL_4 (8)
4164 * @arg @ref LL_ADC_CHANNEL_5 (8)
4165 * @arg @ref LL_ADC_CHANNEL_6
4166 * @arg @ref LL_ADC_CHANNEL_7
4167 * @arg @ref LL_ADC_CHANNEL_8
4168 * @arg @ref LL_ADC_CHANNEL_9
4169 * @arg @ref LL_ADC_CHANNEL_10
4170 * @arg @ref LL_ADC_CHANNEL_11
4171 * @arg @ref LL_ADC_CHANNEL_12
4172 * @arg @ref LL_ADC_CHANNEL_13
4173 * @arg @ref LL_ADC_CHANNEL_14
4174 * @arg @ref LL_ADC_CHANNEL_15
4175 * @arg @ref LL_ADC_CHANNEL_16
4176 * @arg @ref LL_ADC_CHANNEL_17
4177 * @arg @ref LL_ADC_CHANNEL_18
4178 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
4179 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
4180 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
4181 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
4182 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4183 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4184 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
4185 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
4186 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
4187 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
4188 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
4189 *
4190 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
4191 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
4192 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
4193 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
4194 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
4195 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
4196 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
4197 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
4198 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
4199 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
4200 * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
4201 * comparison with internal channel parameter to be done
4202 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4203 */
LL_ADC_REG_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)4204 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
4205 {
4206 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4207
4208 return (uint32_t)((READ_BIT(*preg,
4209 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
4210 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4211 );
4212 }
4213
4214 /**
4215 * @brief Set ADC continuous conversion mode on ADC group regular.
4216 * @note Description of ADC continuous conversion mode:
4217 * - single mode: one conversion per trigger
4218 * - continuous mode: after the first trigger, following
4219 * conversions launched successively automatically.
4220 * @note It is not possible to enable both ADC group regular
4221 * continuous mode and sequencer discontinuous mode.
4222 * @note On this STM32 series, setting of this feature is conditioned to
4223 * ADC state:
4224 * ADC must be disabled or enabled without conversion on going
4225 * on group regular.
4226 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
4227 * @param ADCx ADC instance
4228 * @param Continuous This parameter can be one of the following values:
4229 * @arg @ref LL_ADC_REG_CONV_SINGLE
4230 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4231 * @retval None
4232 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)4233 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
4234 {
4235 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
4236 }
4237
4238 /**
4239 * @brief Get ADC continuous conversion mode on ADC group regular.
4240 * @note Description of ADC continuous conversion mode:
4241 * - single mode: one conversion per trigger
4242 * - continuous mode: after the first trigger, following
4243 * conversions launched successively automatically.
4244 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
4245 * @param ADCx ADC instance
4246 * @retval Returned value can be one of the following values:
4247 * @arg @ref LL_ADC_REG_CONV_SINGLE
4248 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4249 */
LL_ADC_REG_GetContinuousMode(ADC_TypeDef * ADCx)4250 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
4251 {
4252 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
4253 }
4254
4255 /**
4256 * @brief Set ADC group regular conversion data transfer: no transfer or
4257 * transfer by DMA, and DMA requests mode.
4258 * @note If transfer by DMA selected, specifies the DMA requests
4259 * mode:
4260 * - Limited mode (One shot mode): DMA transfer requests are stopped
4261 * when number of DMA data transfers (number of
4262 * ADC conversions) is reached.
4263 * This ADC mode is intended to be used with DMA mode non-circular.
4264 * - Unlimited mode: DMA transfer requests are unlimited,
4265 * whatever number of DMA data transfers (number of
4266 * ADC conversions).
4267 * This ADC mode is intended to be used with DMA mode circular.
4268 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
4269 * mode non-circular:
4270 * when DMA transfers size will be reached, DMA will stop transfers of
4271 * ADC conversions data ADC will raise an overrun error
4272 * (overrun flag and interruption if enabled).
4273 * @note For devices with several ADC instances: ADC multimode DMA
4274 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
4275 * @note To configure DMA source address (peripheral address),
4276 * use function @ref LL_ADC_DMA_GetRegAddr().
4277 * @note On this STM32 series, setting of this feature is conditioned to
4278 * ADC state:
4279 * ADC must be disabled or enabled without conversion on going
4280 * on either groups regular or injected.
4281 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
4282 * CFGR DMACFG LL_ADC_REG_SetDMATransfer
4283 * @param ADCx ADC instance
4284 * @param DMATransfer This parameter can be one of the following values:
4285 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
4286 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
4287 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
4288 * @retval None
4289 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)4290 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
4291 {
4292 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
4293 }
4294
4295 /**
4296 * @brief Get ADC group regular conversion data transfer: no transfer or
4297 * transfer by DMA, and DMA requests mode.
4298 * @note If transfer by DMA selected, specifies the DMA requests
4299 * mode:
4300 * - Limited mode (One shot mode): DMA transfer requests are stopped
4301 * when number of DMA data transfers (number of
4302 * ADC conversions) is reached.
4303 * This ADC mode is intended to be used with DMA mode non-circular.
4304 * - Unlimited mode: DMA transfer requests are unlimited,
4305 * whatever number of DMA data transfers (number of
4306 * ADC conversions).
4307 * This ADC mode is intended to be used with DMA mode circular.
4308 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
4309 * mode non-circular:
4310 * when DMA transfers size will be reached, DMA will stop transfers of
4311 * ADC conversions data ADC will raise an overrun error
4312 * (overrun flag and interruption if enabled).
4313 * @note For devices with several ADC instances: ADC multimode DMA
4314 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
4315 * @note To configure DMA source address (peripheral address),
4316 * use function @ref LL_ADC_DMA_GetRegAddr().
4317 * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
4318 * CFGR DMACFG LL_ADC_REG_GetDMATransfer
4319 * @param ADCx ADC instance
4320 * @retval Returned value can be one of the following values:
4321 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
4322 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
4323 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
4324 */
LL_ADC_REG_GetDMATransfer(ADC_TypeDef * ADCx)4325 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
4326 {
4327 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
4328 }
4329
4330 /**
4331 * @brief Set ADC group regular behavior in case of overrun:
4332 * data preserved or overwritten.
4333 * @note Compatibility with devices without feature overrun:
4334 * other devices without this feature have a behavior
4335 * equivalent to data overwritten.
4336 * The default setting of overrun is data preserved.
4337 * Therefore, for compatibility with all devices, parameter
4338 * overrun should be set to data overwritten.
4339 * @note On this STM32 series, setting of this feature is conditioned to
4340 * ADC state:
4341 * ADC must be disabled or enabled without conversion on going
4342 * on group regular.
4343 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
4344 * @param ADCx ADC instance
4345 * @param Overrun This parameter can be one of the following values:
4346 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4347 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4348 * @retval None
4349 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)4350 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
4351 {
4352 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
4353 }
4354
4355 /**
4356 * @brief Get ADC group regular behavior in case of overrun:
4357 * data preserved or overwritten.
4358 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
4359 * @param ADCx ADC instance
4360 * @retval Returned value can be one of the following values:
4361 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4362 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4363 */
LL_ADC_REG_GetOverrun(ADC_TypeDef * ADCx)4364 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
4365 {
4366 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
4367 }
4368
4369 /**
4370 * @}
4371 */
4372
4373 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
4374 * @{
4375 */
4376
4377 /**
4378 * @brief Set ADC group injected conversion trigger source:
4379 * internal (SW start) or from external peripheral (timer event,
4380 * external interrupt line).
4381 * @note On this STM32 series, setting trigger source to external trigger
4382 * also set trigger polarity to rising edge
4383 * (default setting for compatibility with some ADC on other
4384 * STM32 families having this setting set by HW default value).
4385 * In case of need to modify trigger edge, use
4386 * function @ref LL_ADC_INJ_SetTriggerEdge().
4387 * @note Availability of parameters of trigger sources from timer
4388 * depends on timers availability on the selected device.
4389 * @note On this STM32 series, setting of this feature is conditioned to
4390 * ADC state:
4391 * ADC must not be disabled. Can be enabled with or without conversion
4392 * on going on either groups regular or injected.
4393 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
4394 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
4395 * @param ADCx ADC instance
4396 * @param TriggerSource This parameter can be one of the following values:
4397 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4398 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4399 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4400 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
4401 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4402 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4403 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
4404 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4405 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
4406 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
4407 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
4408 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4409 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
4410 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
4411 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4412 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
4413 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4414 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4415 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
4416 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4417 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4418 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
4419 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
4420 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
4421 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
4422 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
4423 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
4424 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
4425 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
4426 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
4427 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
4428 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
4429 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
4430 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
4431 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
4432 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
4433 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
4434 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
4435 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
4436 *
4437 * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
4438 * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
4439 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
4440 * @retval None
4441 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)4442 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
4443 {
4444 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
4445 }
4446
4447 /**
4448 * @brief Get ADC group injected conversion trigger source:
4449 * internal (SW start) or from external peripheral (timer event,
4450 * external interrupt line).
4451 * @note To determine whether group injected trigger source is
4452 * internal (SW start) or external, without detail
4453 * of which peripheral is selected as external trigger,
4454 * (equivalent to
4455 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
4456 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
4457 * @note Availability of parameters of trigger sources from timer
4458 * depends on timers availability on the selected device.
4459 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
4460 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
4461 * @param ADCx ADC instance
4462 * @retval Returned value can be one of the following values:
4463 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4464 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4465 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4466 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
4467 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4468 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4469 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
4470 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4471 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
4472 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
4473 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
4474 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4475 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
4476 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
4477 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4478 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
4479 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4480 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4481 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
4482 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4483 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4484 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
4485 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
4486 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
4487 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
4488 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
4489 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
4490 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
4491 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
4492 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
4493 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
4494 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
4495 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
4496 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
4497 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
4498 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
4499 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
4500 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
4501 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
4502 *
4503 * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
4504 * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
4505 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
4506 */
LL_ADC_INJ_GetTriggerSource(ADC_TypeDef * ADCx)4507 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
4508 {
4509 __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
4510
4511 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4512 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
4513 uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
4514
4515 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
4516 /* to match with triggers literals definition. */
4517 return ((TriggerSource
4518 & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
4519 | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
4520 );
4521 }
4522
4523 /**
4524 * @brief Get ADC group injected conversion trigger source internal (SW start)
4525 or external
4526 * @note In case of group injected trigger source set to external trigger,
4527 * to determine which peripheral is selected as external trigger,
4528 * use function @ref LL_ADC_INJ_GetTriggerSource.
4529 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
4530 * @param ADCx ADC instance
4531 * @retval Value "0" if trigger source external trigger
4532 * Value "1" if trigger source SW start.
4533 */
LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)4534 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
4535 {
4536 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
4537 }
4538
4539 /**
4540 * @brief Set ADC group injected conversion trigger polarity.
4541 * Applicable only for trigger source set to external trigger.
4542 * @note On this STM32 series, setting of this feature is conditioned to
4543 * ADC state:
4544 * ADC must not be disabled. Can be enabled with or without conversion
4545 * on going on either groups regular or injected.
4546 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
4547 * @param ADCx ADC instance
4548 * @param ExternalTriggerEdge This parameter can be one of the following values:
4549 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4550 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4551 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4552 * @retval None
4553 */
LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4554 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4555 {
4556 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
4557 }
4558
4559 /**
4560 * @brief Get ADC group injected conversion trigger polarity.
4561 * Applicable only for trigger source set to external trigger.
4562 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
4563 * @param ADCx ADC instance
4564 * @retval Returned value can be one of the following values:
4565 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4566 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4567 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4568 */
LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef * ADCx)4569 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
4570 {
4571 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
4572 }
4573
4574 /**
4575 * @brief Set ADC group injected sequencer length and scan direction.
4576 * @note This function performs configuration of:
4577 * - Sequence length: Number of ranks in the scan sequence.
4578 * - Sequence direction: Unless specified in parameters, sequencer
4579 * scan direction is forward (from rank 1 to rank n).
4580 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4581 * ADC conversion on only 1 channel.
4582 * @note On this STM32 series, setting of this feature is conditioned to
4583 * ADC state:
4584 * ADC must not be disabled. Can be enabled with or without conversion
4585 * on going on either groups regular or injected.
4586 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
4587 * @param ADCx ADC instance
4588 * @param SequencerNbRanks This parameter can be one of the following values:
4589 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4590 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4591 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4592 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4593 * @retval None
4594 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)4595 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4596 {
4597 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
4598 }
4599
4600 /**
4601 * @brief Get ADC group injected sequencer length and scan direction.
4602 * @note This function retrieves:
4603 * - Sequence length: Number of ranks in the scan sequence.
4604 * - Sequence direction: Unless specified in parameters, sequencer
4605 * scan direction is forward (from rank 1 to rank n).
4606 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4607 * ADC conversion on only 1 channel.
4608 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
4609 * @param ADCx ADC instance
4610 * @retval Returned value can be one of the following values:
4611 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4612 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4613 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4614 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4615 */
LL_ADC_INJ_GetSequencerLength(ADC_TypeDef * ADCx)4616 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
4617 {
4618 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
4619 }
4620
4621 /**
4622 * @brief Set ADC group injected sequencer discontinuous mode:
4623 * sequence subdivided and scan conversions interrupted every selected
4624 * number of ranks.
4625 * @note It is not possible to enable both ADC group injected
4626 * auto-injected mode and sequencer discontinuous mode.
4627 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
4628 * @param ADCx ADC instance
4629 * @param SeqDiscont This parameter can be one of the following values:
4630 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4631 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4632 * @retval None
4633 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)4634 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4635 {
4636 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
4637 }
4638
4639 /**
4640 * @brief Get ADC group injected sequencer discontinuous mode:
4641 * sequence subdivided and scan conversions interrupted every selected
4642 * number of ranks.
4643 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
4644 * @param ADCx ADC instance
4645 * @retval Returned value can be one of the following values:
4646 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4647 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4648 */
LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef * ADCx)4649 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
4650 {
4651 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
4652 }
4653
4654 /**
4655 * @brief Set ADC group injected sequence: channel on the selected
4656 * sequence rank.
4657 * @note Depending on devices and packages, some channels may not be available.
4658 * Refer to device datasheet for channels availability.
4659 * @note On this STM32 series, to measure internal channels (VrefInt,
4660 * TempSensor, ...), measurement paths to internal channels must be
4661 * enabled separately.
4662 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4663 * @note On STM32G4, some fast channels are available: fast analog inputs
4664 * coming from GPIO pads (ADC_IN1..5).
4665 * @note On this STM32 series, setting of this feature is conditioned to
4666 * ADC state:
4667 * ADC must not be disabled. Can be enabled with or without conversion
4668 * on going on either groups regular or injected.
4669 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
4670 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
4671 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
4672 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
4673 * @param ADCx ADC instance
4674 * @param Rank This parameter can be one of the following values:
4675 * @arg @ref LL_ADC_INJ_RANK_1
4676 * @arg @ref LL_ADC_INJ_RANK_2
4677 * @arg @ref LL_ADC_INJ_RANK_3
4678 * @arg @ref LL_ADC_INJ_RANK_4
4679 * @param Channel This parameter can be one of the following values:
4680 * @arg @ref LL_ADC_CHANNEL_0
4681 * @arg @ref LL_ADC_CHANNEL_1 (8)
4682 * @arg @ref LL_ADC_CHANNEL_2 (8)
4683 * @arg @ref LL_ADC_CHANNEL_3 (8)
4684 * @arg @ref LL_ADC_CHANNEL_4 (8)
4685 * @arg @ref LL_ADC_CHANNEL_5 (8)
4686 * @arg @ref LL_ADC_CHANNEL_6
4687 * @arg @ref LL_ADC_CHANNEL_7
4688 * @arg @ref LL_ADC_CHANNEL_8
4689 * @arg @ref LL_ADC_CHANNEL_9
4690 * @arg @ref LL_ADC_CHANNEL_10
4691 * @arg @ref LL_ADC_CHANNEL_11
4692 * @arg @ref LL_ADC_CHANNEL_12
4693 * @arg @ref LL_ADC_CHANNEL_13
4694 * @arg @ref LL_ADC_CHANNEL_14
4695 * @arg @ref LL_ADC_CHANNEL_15
4696 * @arg @ref LL_ADC_CHANNEL_16
4697 * @arg @ref LL_ADC_CHANNEL_17
4698 * @arg @ref LL_ADC_CHANNEL_18
4699 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
4700 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
4701 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
4702 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
4703 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4704 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4705 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
4706 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
4707 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
4708 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
4709 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
4710 *
4711 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
4712 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
4713 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
4714 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
4715 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
4716 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
4717 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
4718 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
4719 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
4720 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
4721 * @retval None
4722 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4723 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4724 {
4725 /* Set bits with content of parameter "Channel" with bits position */
4726 /* in register depending on parameter "Rank". */
4727 /* Parameters "Rank" and "Channel" are used with masks because containing */
4728 /* other bits reserved for other purpose. */
4729 MODIFY_REG(ADCx->JSQR,
4730 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
4731 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
4732 }
4733
4734 /**
4735 * @brief Get ADC group injected sequence: channel on the selected
4736 * sequence rank.
4737 * @note Depending on devices and packages, some channels may not be available.
4738 * Refer to device datasheet for channels availability.
4739 * @note Usage of the returned channel number:
4740 * - To reinject this channel into another function LL_ADC_xxx:
4741 * the returned channel number is only partly formatted on definition
4742 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4743 * with parts of literals LL_ADC_CHANNEL_x or using
4744 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4745 * Then the selected literal LL_ADC_CHANNEL_x can be used
4746 * as parameter for another function.
4747 * - To get the channel number in decimal format:
4748 * process the returned value with the helper macro
4749 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4750 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
4751 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
4752 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
4753 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
4754 * @param ADCx ADC instance
4755 * @param Rank This parameter can be one of the following values:
4756 * @arg @ref LL_ADC_INJ_RANK_1
4757 * @arg @ref LL_ADC_INJ_RANK_2
4758 * @arg @ref LL_ADC_INJ_RANK_3
4759 * @arg @ref LL_ADC_INJ_RANK_4
4760 * @retval Returned value can be one of the following values:
4761 * @arg @ref LL_ADC_CHANNEL_0
4762 * @arg @ref LL_ADC_CHANNEL_1 (8)
4763 * @arg @ref LL_ADC_CHANNEL_2 (8)
4764 * @arg @ref LL_ADC_CHANNEL_3 (8)
4765 * @arg @ref LL_ADC_CHANNEL_4 (8)
4766 * @arg @ref LL_ADC_CHANNEL_5 (8)
4767 * @arg @ref LL_ADC_CHANNEL_6
4768 * @arg @ref LL_ADC_CHANNEL_7
4769 * @arg @ref LL_ADC_CHANNEL_8
4770 * @arg @ref LL_ADC_CHANNEL_9
4771 * @arg @ref LL_ADC_CHANNEL_10
4772 * @arg @ref LL_ADC_CHANNEL_11
4773 * @arg @ref LL_ADC_CHANNEL_12
4774 * @arg @ref LL_ADC_CHANNEL_13
4775 * @arg @ref LL_ADC_CHANNEL_14
4776 * @arg @ref LL_ADC_CHANNEL_15
4777 * @arg @ref LL_ADC_CHANNEL_16
4778 * @arg @ref LL_ADC_CHANNEL_17
4779 * @arg @ref LL_ADC_CHANNEL_18
4780 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
4781 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
4782 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
4783 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
4784 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4785 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4786 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
4787 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
4788 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
4789 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
4790 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
4791 *
4792 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
4793 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
4794 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
4795 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
4796 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
4797 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
4798 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
4799 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
4800 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
4801 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
4802 * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
4803 * comparison with internal channel parameter to be done
4804 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4805 */
LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)4806 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
4807 {
4808 return (uint32_t)((READ_BIT(ADCx->JSQR,
4809 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
4810 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4811 );
4812 }
4813
4814 /**
4815 * @brief Set ADC group injected conversion trigger:
4816 * independent or from ADC group regular.
4817 * @note This mode can be used to extend number of data registers
4818 * updated after one ADC conversion trigger and with data
4819 * permanently kept (not erased by successive conversions of scan of
4820 * ADC sequencer ranks), up to 5 data registers:
4821 * 1 data register on ADC group regular, 4 data registers
4822 * on ADC group injected.
4823 * @note If ADC group injected injected trigger source is set to an
4824 * external trigger, this feature must be must be set to
4825 * independent trigger.
4826 * ADC group injected automatic trigger is compliant only with
4827 * group injected trigger source set to SW start, without any
4828 * further action on ADC group injected conversion start or stop:
4829 * in this case, ADC group injected is controlled only
4830 * from ADC group regular.
4831 * @note It is not possible to enable both ADC group injected
4832 * auto-injected mode and sequencer discontinuous mode.
4833 * @note On this STM32 series, setting of this feature is conditioned to
4834 * ADC state:
4835 * ADC must be disabled or enabled without conversion on going
4836 * on either groups regular or injected.
4837 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
4838 * @param ADCx ADC instance
4839 * @param TrigAuto This parameter can be one of the following values:
4840 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4841 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4842 * @retval None
4843 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)4844 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
4845 {
4846 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
4847 }
4848
4849 /**
4850 * @brief Get ADC group injected conversion trigger:
4851 * independent or from ADC group regular.
4852 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
4853 * @param ADCx ADC instance
4854 * @retval Returned value can be one of the following values:
4855 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4856 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4857 */
LL_ADC_INJ_GetTrigAuto(ADC_TypeDef * ADCx)4858 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
4859 {
4860 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
4861 }
4862
4863 /**
4864 * @brief Set ADC group injected contexts queue mode.
4865 * @note A context is a setting of group injected sequencer:
4866 * - group injected trigger
4867 * - sequencer length
4868 * - sequencer ranks
4869 * If contexts queue is disabled:
4870 * - only 1 sequence can be configured
4871 * and is active perpetually.
4872 * If contexts queue is enabled:
4873 * - up to 2 contexts can be queued
4874 * and are checked in and out as a FIFO stack (first-in, first-out).
4875 * - If a new context is set when queues is full, error is triggered
4876 * by interruption "Injected Queue Overflow".
4877 * - Two behaviors are possible when all contexts have been processed:
4878 * the contexts queue can maintain the last context active perpetually
4879 * or can be empty and injected group triggers are disabled.
4880 * - Triggers can be only external (not internal SW start)
4881 * - Caution: The sequence must be fully configured in one time
4882 * (one write of register JSQR makes a check-in of a new context
4883 * into the queue).
4884 * Therefore functions to set separately injected trigger and
4885 * sequencer channels cannot be used, register JSQR must be set
4886 * using function @ref LL_ADC_INJ_ConfigQueueContext().
4887 * @note This parameter can be modified only when no conversion is on going
4888 * on either groups regular or injected.
4889 * @note A modification of the context mode (bit JQDIS) causes the contexts
4890 * queue to be flushed and the register JSQR is cleared.
4891 * @note On this STM32 series, setting of this feature is conditioned to
4892 * ADC state:
4893 * ADC must be disabled or enabled without conversion on going
4894 * on either groups regular or injected.
4895 * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
4896 * CFGR JQDIS LL_ADC_INJ_SetQueueMode
4897 * @param ADCx ADC instance
4898 * @param QueueMode This parameter can be one of the following values:
4899 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
4900 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4901 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4902 * @retval None
4903 */
LL_ADC_INJ_SetQueueMode(ADC_TypeDef * ADCx,uint32_t QueueMode)4904 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
4905 {
4906 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
4907 }
4908
4909 /**
4910 * @brief Get ADC group injected context queue mode.
4911 * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
4912 * CFGR JQDIS LL_ADC_INJ_GetQueueMode
4913 * @param ADCx ADC instance
4914 * @retval Returned value can be one of the following values:
4915 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
4916 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4917 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4918 */
LL_ADC_INJ_GetQueueMode(ADC_TypeDef * ADCx)4919 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
4920 {
4921 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
4922 }
4923
4924 /**
4925 * @brief Set one context on ADC group injected that will be checked in
4926 * contexts queue.
4927 * @note A context is a setting of group injected sequencer:
4928 * - group injected trigger
4929 * - sequencer length
4930 * - sequencer ranks
4931 * This function is intended to be used when contexts queue is enabled,
4932 * because the sequence must be fully configured in one time
4933 * (functions to set separately injected trigger and sequencer channels
4934 * cannot be used):
4935 * Refer to function @ref LL_ADC_INJ_SetQueueMode().
4936 * @note In the contexts queue, only the active context can be read.
4937 * The parameters of this function can be read using functions:
4938 * @arg @ref LL_ADC_INJ_GetTriggerSource()
4939 * @arg @ref LL_ADC_INJ_GetTriggerEdge()
4940 * @arg @ref LL_ADC_INJ_GetSequencerRanks()
4941 * @note On this STM32 series, to measure internal channels (VrefInt,
4942 * TempSensor, ...), measurement paths to internal channels must be
4943 * enabled separately.
4944 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4945 * @note On STM32G4, some fast channels are available: fast analog inputs
4946 * coming from GPIO pads (ADC_IN1..5).
4947 * @note On this STM32 series, setting of this feature is conditioned to
4948 * ADC state:
4949 * ADC must not be disabled. Can be enabled with or without conversion
4950 * on going on either groups regular or injected.
4951 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
4952 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
4953 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
4954 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
4955 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
4956 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
4957 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
4958 * @param ADCx ADC instance
4959 * @param TriggerSource This parameter can be one of the following values:
4960 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4961 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4962 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4963 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
4964 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4965 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4966 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
4967 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4968 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
4969 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
4970 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
4971 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4972 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
4973 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
4974 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4975 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
4976 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4977 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4978 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
4979 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4980 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4981 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
4982 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
4983 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
4984 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
4985 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
4986 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
4987 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
4988 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
4989 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
4990 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
4991 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
4992 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
4993 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
4994 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
4995 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
4996 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
4997 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
4998 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
4999 *
5000 * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
5001 * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
5002 * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
5003 * @param ExternalTriggerEdge This parameter can be one of the following values:
5004 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
5005 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
5006 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
5007 *
5008 * Note: This parameter is discarded in case of SW start:
5009 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
5010 * @param SequencerNbRanks This parameter can be one of the following values:
5011 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
5012 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
5013 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
5014 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
5015 * @param Rank1_Channel This parameter can be one of the following values:
5016 * @arg @ref LL_ADC_CHANNEL_0
5017 * @arg @ref LL_ADC_CHANNEL_1 (8)
5018 * @arg @ref LL_ADC_CHANNEL_2 (8)
5019 * @arg @ref LL_ADC_CHANNEL_3 (8)
5020 * @arg @ref LL_ADC_CHANNEL_4 (8)
5021 * @arg @ref LL_ADC_CHANNEL_5 (8)
5022 * @arg @ref LL_ADC_CHANNEL_6
5023 * @arg @ref LL_ADC_CHANNEL_7
5024 * @arg @ref LL_ADC_CHANNEL_8
5025 * @arg @ref LL_ADC_CHANNEL_9
5026 * @arg @ref LL_ADC_CHANNEL_10
5027 * @arg @ref LL_ADC_CHANNEL_11
5028 * @arg @ref LL_ADC_CHANNEL_12
5029 * @arg @ref LL_ADC_CHANNEL_13
5030 * @arg @ref LL_ADC_CHANNEL_14
5031 * @arg @ref LL_ADC_CHANNEL_15
5032 * @arg @ref LL_ADC_CHANNEL_16
5033 * @arg @ref LL_ADC_CHANNEL_17
5034 * @arg @ref LL_ADC_CHANNEL_18
5035 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
5036 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
5037 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
5038 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
5039 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
5040 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
5041 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
5042 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
5043 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
5044 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
5045 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
5046 *
5047 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
5048 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
5049 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
5050 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
5051 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
5052 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
5053 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
5054 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
5055 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
5056 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
5057 * @param Rank2_Channel This parameter can be one of the following values:
5058 * @arg @ref LL_ADC_CHANNEL_0
5059 * @arg @ref LL_ADC_CHANNEL_1 (8)
5060 * @arg @ref LL_ADC_CHANNEL_2 (8)
5061 * @arg @ref LL_ADC_CHANNEL_3 (8)
5062 * @arg @ref LL_ADC_CHANNEL_4 (8)
5063 * @arg @ref LL_ADC_CHANNEL_5 (8)
5064 * @arg @ref LL_ADC_CHANNEL_6
5065 * @arg @ref LL_ADC_CHANNEL_7
5066 * @arg @ref LL_ADC_CHANNEL_8
5067 * @arg @ref LL_ADC_CHANNEL_9
5068 * @arg @ref LL_ADC_CHANNEL_10
5069 * @arg @ref LL_ADC_CHANNEL_11
5070 * @arg @ref LL_ADC_CHANNEL_12
5071 * @arg @ref LL_ADC_CHANNEL_13
5072 * @arg @ref LL_ADC_CHANNEL_14
5073 * @arg @ref LL_ADC_CHANNEL_15
5074 * @arg @ref LL_ADC_CHANNEL_16
5075 * @arg @ref LL_ADC_CHANNEL_17
5076 * @arg @ref LL_ADC_CHANNEL_18
5077 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
5078 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
5079 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
5080 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
5081 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
5082 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
5083 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
5084 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
5085 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
5086 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
5087 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
5088 *
5089 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
5090 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
5091 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
5092 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
5093 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
5094 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
5095 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
5096 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
5097 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
5098 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
5099 * @param Rank3_Channel This parameter can be one of the following values:
5100 * @arg @ref LL_ADC_CHANNEL_0
5101 * @arg @ref LL_ADC_CHANNEL_1 (8)
5102 * @arg @ref LL_ADC_CHANNEL_2 (8)
5103 * @arg @ref LL_ADC_CHANNEL_3 (8)
5104 * @arg @ref LL_ADC_CHANNEL_4 (8)
5105 * @arg @ref LL_ADC_CHANNEL_5 (8)
5106 * @arg @ref LL_ADC_CHANNEL_6
5107 * @arg @ref LL_ADC_CHANNEL_7
5108 * @arg @ref LL_ADC_CHANNEL_8
5109 * @arg @ref LL_ADC_CHANNEL_9
5110 * @arg @ref LL_ADC_CHANNEL_10
5111 * @arg @ref LL_ADC_CHANNEL_11
5112 * @arg @ref LL_ADC_CHANNEL_12
5113 * @arg @ref LL_ADC_CHANNEL_13
5114 * @arg @ref LL_ADC_CHANNEL_14
5115 * @arg @ref LL_ADC_CHANNEL_15
5116 * @arg @ref LL_ADC_CHANNEL_16
5117 * @arg @ref LL_ADC_CHANNEL_17
5118 * @arg @ref LL_ADC_CHANNEL_18
5119 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
5120 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
5121 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
5122 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
5123 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
5124 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
5125 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
5126 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
5127 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
5128 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
5129 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
5130 *
5131 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
5132 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
5133 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
5134 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
5135 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
5136 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
5137 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
5138 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
5139 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
5140 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
5141 * @param Rank4_Channel This parameter can be one of the following values:
5142 * @arg @ref LL_ADC_CHANNEL_0
5143 * @arg @ref LL_ADC_CHANNEL_1 (8)
5144 * @arg @ref LL_ADC_CHANNEL_2 (8)
5145 * @arg @ref LL_ADC_CHANNEL_3 (8)
5146 * @arg @ref LL_ADC_CHANNEL_4 (8)
5147 * @arg @ref LL_ADC_CHANNEL_5 (8)
5148 * @arg @ref LL_ADC_CHANNEL_6
5149 * @arg @ref LL_ADC_CHANNEL_7
5150 * @arg @ref LL_ADC_CHANNEL_8
5151 * @arg @ref LL_ADC_CHANNEL_9
5152 * @arg @ref LL_ADC_CHANNEL_10
5153 * @arg @ref LL_ADC_CHANNEL_11
5154 * @arg @ref LL_ADC_CHANNEL_12
5155 * @arg @ref LL_ADC_CHANNEL_13
5156 * @arg @ref LL_ADC_CHANNEL_14
5157 * @arg @ref LL_ADC_CHANNEL_15
5158 * @arg @ref LL_ADC_CHANNEL_16
5159 * @arg @ref LL_ADC_CHANNEL_17
5160 * @arg @ref LL_ADC_CHANNEL_18
5161 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
5162 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
5163 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
5164 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
5165 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
5166 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
5167 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
5168 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
5169 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
5170 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
5171 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
5172 *
5173 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
5174 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
5175 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
5176 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
5177 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
5178 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
5179 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
5180 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
5181 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
5182 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
5183 * @retval None
5184 */
LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef * ADCx,uint32_t TriggerSource,uint32_t ExternalTriggerEdge,uint32_t SequencerNbRanks,uint32_t Rank1_Channel,uint32_t Rank2_Channel,uint32_t Rank3_Channel,uint32_t Rank4_Channel)5185 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
5186 uint32_t TriggerSource,
5187 uint32_t ExternalTriggerEdge,
5188 uint32_t SequencerNbRanks,
5189 uint32_t Rank1_Channel,
5190 uint32_t Rank2_Channel,
5191 uint32_t Rank3_Channel,
5192 uint32_t Rank4_Channel)
5193 {
5194 /* Set bits with content of parameter "Rankx_Channel" with bits position */
5195 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
5196 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
5197 /* because containing other bits reserved for other purpose. */
5198 /* If parameter "TriggerSource" is set to SW start, then parameter */
5199 /* "ExternalTriggerEdge" is discarded. */
5200 uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
5201 MODIFY_REG(ADCx->JSQR,
5202 ADC_JSQR_JEXTSEL |
5203 ADC_JSQR_JEXTEN |
5204 ADC_JSQR_JSQ4 |
5205 ADC_JSQR_JSQ3 |
5206 ADC_JSQR_JSQ2 |
5207 ADC_JSQR_JSQ1 |
5208 ADC_JSQR_JL,
5209 (TriggerSource & ADC_JSQR_JEXTSEL) |
5210 (ExternalTriggerEdge * (is_trigger_not_sw)) |
5211 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5212 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5213 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5214 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5215 SequencerNbRanks
5216 );
5217 }
5218
5219 /**
5220 * @}
5221 */
5222
5223 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
5224 * @{
5225 */
5226
5227 /**
5228 * @brief Set sampling time of the selected ADC channel
5229 * Unit: ADC clock cycles.
5230 * @note On this device, sampling time is on channel scope: independently
5231 * of channel mapped on ADC group regular or injected.
5232 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
5233 * converted:
5234 * sampling time constraints must be respected (sampling time can be
5235 * adjusted in function of ADC clock frequency and sampling time
5236 * setting).
5237 * Refer to device datasheet for timings values (parameters TS_vrefint,
5238 * TS_temp, ...).
5239 * @note Conversion time is the addition of sampling time and processing time.
5240 * On this STM32 series, ADC processing time is:
5241 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5242 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5243 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5244 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5245 * @note In case of ADC conversion of internal channel (VrefInt,
5246 * temperature sensor, ...), a sampling time minimum value
5247 * is required.
5248 * Refer to device datasheet.
5249 * @note On this STM32 series, setting of this feature is conditioned to
5250 * ADC state:
5251 * ADC must be disabled or enabled without conversion on going
5252 * on either groups regular or injected.
5253 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
5254 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
5255 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
5256 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
5257 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
5258 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
5259 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
5260 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
5261 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
5262 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
5263 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
5264 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
5265 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
5266 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
5267 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
5268 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
5269 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
5270 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
5271 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
5272 * @param ADCx ADC instance
5273 * @param Channel This parameter can be one of the following values:
5274 * @arg @ref LL_ADC_CHANNEL_0
5275 * @arg @ref LL_ADC_CHANNEL_1 (8)
5276 * @arg @ref LL_ADC_CHANNEL_2 (8)
5277 * @arg @ref LL_ADC_CHANNEL_3 (8)
5278 * @arg @ref LL_ADC_CHANNEL_4 (8)
5279 * @arg @ref LL_ADC_CHANNEL_5 (8)
5280 * @arg @ref LL_ADC_CHANNEL_6
5281 * @arg @ref LL_ADC_CHANNEL_7
5282 * @arg @ref LL_ADC_CHANNEL_8
5283 * @arg @ref LL_ADC_CHANNEL_9
5284 * @arg @ref LL_ADC_CHANNEL_10
5285 * @arg @ref LL_ADC_CHANNEL_11
5286 * @arg @ref LL_ADC_CHANNEL_12
5287 * @arg @ref LL_ADC_CHANNEL_13
5288 * @arg @ref LL_ADC_CHANNEL_14
5289 * @arg @ref LL_ADC_CHANNEL_15
5290 * @arg @ref LL_ADC_CHANNEL_16
5291 * @arg @ref LL_ADC_CHANNEL_17
5292 * @arg @ref LL_ADC_CHANNEL_18
5293 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
5294 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
5295 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
5296 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
5297 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
5298 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
5299 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
5300 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
5301 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
5302 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
5303 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
5304 *
5305 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
5306 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
5307 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
5308 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
5309 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
5310 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
5311 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
5312 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
5313 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
5314 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
5315 * @param SamplingTime This parameter can be one of the following values:
5316 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
5317 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
5318 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
5319 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
5320 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
5321 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
5322 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
5323 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
5324 *
5325 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
5326 * can be replaced by 3.5 ADC clock cycles.
5327 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
5328 * @retval None
5329 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)5330 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
5331 {
5332 /* Set bits with content of parameter "SamplingTime" with bits position */
5333 /* in register and register position depending on parameter "Channel". */
5334 /* Parameter "Channel" is used with masks because containing */
5335 /* other bits reserved for other purpose. */
5336 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5337
5338 MODIFY_REG(*preg,
5339 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
5340 SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
5341 }
5342
5343 /**
5344 * @brief Get sampling time of the selected ADC channel
5345 * Unit: ADC clock cycles.
5346 * @note On this device, sampling time is on channel scope: independently
5347 * of channel mapped on ADC group regular or injected.
5348 * @note Conversion time is the addition of sampling time and processing time.
5349 * On this STM32 series, ADC processing time is:
5350 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5351 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5352 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5353 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5354 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
5355 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
5356 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
5357 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
5358 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
5359 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
5360 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
5361 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
5362 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
5363 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
5364 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
5365 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
5366 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
5367 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
5368 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
5369 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
5370 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
5371 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
5372 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
5373 * @param ADCx ADC instance
5374 * @param Channel This parameter can be one of the following values:
5375 * @arg @ref LL_ADC_CHANNEL_0
5376 * @arg @ref LL_ADC_CHANNEL_1 (8)
5377 * @arg @ref LL_ADC_CHANNEL_2 (8)
5378 * @arg @ref LL_ADC_CHANNEL_3 (8)
5379 * @arg @ref LL_ADC_CHANNEL_4 (8)
5380 * @arg @ref LL_ADC_CHANNEL_5 (8)
5381 * @arg @ref LL_ADC_CHANNEL_6
5382 * @arg @ref LL_ADC_CHANNEL_7
5383 * @arg @ref LL_ADC_CHANNEL_8
5384 * @arg @ref LL_ADC_CHANNEL_9
5385 * @arg @ref LL_ADC_CHANNEL_10
5386 * @arg @ref LL_ADC_CHANNEL_11
5387 * @arg @ref LL_ADC_CHANNEL_12
5388 * @arg @ref LL_ADC_CHANNEL_13
5389 * @arg @ref LL_ADC_CHANNEL_14
5390 * @arg @ref LL_ADC_CHANNEL_15
5391 * @arg @ref LL_ADC_CHANNEL_16
5392 * @arg @ref LL_ADC_CHANNEL_17
5393 * @arg @ref LL_ADC_CHANNEL_18
5394 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
5395 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
5396 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
5397 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
5398 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
5399 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
5400 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
5401 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
5402 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
5403 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
5404 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
5405 *
5406 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
5407 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
5408 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
5409 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
5410 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
5411 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
5412 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
5413 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
5414 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
5415 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
5416 * @retval Returned value can be one of the following values:
5417 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
5418 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
5419 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
5420 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
5421 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
5422 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
5423 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
5424 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
5425 *
5426 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
5427 * can be replaced by 3.5 ADC clock cycles.
5428 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
5429 */
LL_ADC_GetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel)5430 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
5431 {
5432 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5433
5434 return (uint32_t)(READ_BIT(*preg,
5435 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
5436 >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
5437 );
5438 }
5439
5440 /**
5441 * @brief Set mode single-ended or differential input of the selected
5442 * ADC channel.
5443 * @note Channel ending is on channel scope: independently of channel mapped
5444 * on ADC group regular or injected.
5445 * In differential mode: Differential measurement is carried out
5446 * between the selected channel 'i' (positive input) and
5447 * channel 'i+1' (negative input). Only channel 'i' has to be
5448 * configured, channel 'i+1' is configured automatically.
5449 * @note Refer to Reference Manual to ensure the selected channel is
5450 * available in differential mode.
5451 * For example, internal channels (VrefInt, TempSensor, ...) are
5452 * not available in differential mode.
5453 * @note When configuring a channel 'i' in differential mode,
5454 * the channel 'i+1' is not usable separately.
5455 * @note On STM32G4, some channels are internally fixed to single-ended inputs
5456 * configuration:
5457 * - ADC1: Channels 12, 15, 16, 17 and 18
5458 * - ADC2: Channels 15, 17 and 18
5459 * - ADC3: Channels 12, 16, 17 and 18 (1)
5460 * - ADC4: Channels 16, 17 and 18 (1)
5461 * - ADC5: Channels 2, 3, 4, 16, 17 and 18 (1)
5462 * (1) ADC3/4/5 are not available on all devices, refer to device datasheet
5463 * for more details.
5464 * @note For ADC channels configured in differential mode, both inputs
5465 * should be biased at (Vref+)/2 +/-200mV.
5466 * (Vref+ is the analog voltage reference)
5467 * @note On this STM32 series, setting of this feature is conditioned to
5468 * ADC state:
5469 * ADC must be ADC disabled.
5470 * @note One or several values can be selected.
5471 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5472 * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
5473 * @param ADCx ADC instance
5474 * @param Channel This parameter can be one of the following values:
5475 * @arg @ref LL_ADC_CHANNEL_1
5476 * @arg @ref LL_ADC_CHANNEL_2
5477 * @arg @ref LL_ADC_CHANNEL_3
5478 * @arg @ref LL_ADC_CHANNEL_4
5479 * @arg @ref LL_ADC_CHANNEL_5
5480 * @arg @ref LL_ADC_CHANNEL_6
5481 * @arg @ref LL_ADC_CHANNEL_7
5482 * @arg @ref LL_ADC_CHANNEL_8
5483 * @arg @ref LL_ADC_CHANNEL_9
5484 * @arg @ref LL_ADC_CHANNEL_10
5485 * @arg @ref LL_ADC_CHANNEL_11
5486 * @arg @ref LL_ADC_CHANNEL_12
5487 * @arg @ref LL_ADC_CHANNEL_13
5488 * @arg @ref LL_ADC_CHANNEL_14
5489 * @arg @ref LL_ADC_CHANNEL_15
5490 * @param SingleDiff This parameter can be a combination of the following values:
5491 * @arg @ref LL_ADC_SINGLE_ENDED
5492 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
5493 * @retval None
5494 */
LL_ADC_SetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SingleDiff)5495 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
5496 {
5497 /* Bits for single or differential mode selection for each channel are set */
5498 /* to 1 only when the differential mode is selected, and to 0 when the */
5499 /* single mode is selected. */
5500
5501 if (SingleDiff == LL_ADC_DIFFERENTIAL_ENDED)
5502 {
5503 SET_BIT(ADCx->DIFSEL,
5504 Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
5505 }
5506 else
5507 {
5508 CLEAR_BIT(ADCx->DIFSEL,
5509 Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
5510 }
5511 }
5512
5513 /**
5514 * @brief Get mode single-ended or differential input of the selected
5515 * ADC channel.
5516 * @note When configuring a channel 'i' in differential mode,
5517 * the channel 'i+1' is not usable separately.
5518 * Therefore, to ensure a channel is configured in single-ended mode,
5519 * the configuration of channel itself and the channel 'i-1' must be
5520 * read back (to ensure that the selected channel channel has not been
5521 * configured in differential mode by the previous channel).
5522 * @note Refer to Reference Manual to ensure the selected channel is
5523 * available in differential mode.
5524 * For example, internal channels (VrefInt, TempSensor, ...) are
5525 * not available in differential mode.
5526 * @note When configuring a channel 'i' in differential mode,
5527 * the channel 'i+1' is not usable separately.
5528 * @note On STM32G4, some channels are internally fixed to single-ended inputs
5529 * configuration:
5530 * - ADC1: Channels 12, 15, 16, 17 and 18
5531 * - ADC2: Channels 15, 17 and 18
5532 * - ADC3: Channels 12, 16, 17 and 18 (1)
5533 * - ADC4: Channels 16, 17 and 18 (1)
5534 * - ADC5: Channels 2, 3, 4, 16, 17 and 18 (1)
5535 * (1) ADC3/4/5 are not available on all devices, refer to device datasheet
5536 * for more details.
5537 * @note One or several values can be selected. In this case, the value
5538 * returned is null if all channels are in single ended-mode.
5539 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5540 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
5541 * @param ADCx ADC instance
5542 * @param Channel This parameter can be a combination of the following values:
5543 * @arg @ref LL_ADC_CHANNEL_1
5544 * @arg @ref LL_ADC_CHANNEL_2
5545 * @arg @ref LL_ADC_CHANNEL_3
5546 * @arg @ref LL_ADC_CHANNEL_4
5547 * @arg @ref LL_ADC_CHANNEL_5
5548 * @arg @ref LL_ADC_CHANNEL_6
5549 * @arg @ref LL_ADC_CHANNEL_7
5550 * @arg @ref LL_ADC_CHANNEL_8
5551 * @arg @ref LL_ADC_CHANNEL_9
5552 * @arg @ref LL_ADC_CHANNEL_10
5553 * @arg @ref LL_ADC_CHANNEL_11
5554 * @arg @ref LL_ADC_CHANNEL_12
5555 * @arg @ref LL_ADC_CHANNEL_13
5556 * @arg @ref LL_ADC_CHANNEL_14
5557 * @arg @ref LL_ADC_CHANNEL_15
5558 * @retval 0: channel in single-ended mode, else: channel in differential mode
5559 */
LL_ADC_GetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel)5560 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
5561 {
5562 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
5563 }
5564
5565 /**
5566 * @}
5567 */
5568
5569 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
5570 * @{
5571 */
5572
5573 /**
5574 * @brief Set ADC analog watchdog monitored channels:
5575 * a single channel, multiple channels or all channels,
5576 * on ADC groups regular and-or injected.
5577 * @note Once monitored channels are selected, analog watchdog
5578 * is enabled.
5579 * @note In case of need to define a single channel to monitor
5580 * with analog watchdog from sequencer channel definition,
5581 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
5582 * @note On this STM32 series, there are 2 kinds of analog watchdog
5583 * instance:
5584 * - AWD standard (instance AWD1):
5585 * - channels monitored: can monitor 1 channel or all channels.
5586 * - groups monitored: ADC groups regular and-or injected.
5587 * - resolution: resolution is not limited (corresponds to
5588 * ADC resolution configured).
5589 * - AWD flexible (instances AWD2, AWD3):
5590 * - channels monitored: flexible on channels monitored, selection is
5591 * channel wise, from from 1 to all channels.
5592 * Specificity of this analog watchdog: Multiple channels can
5593 * be selected. For example:
5594 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5595 * - groups monitored: not selection possible (monitoring on both
5596 * groups regular and injected).
5597 * Channels selected are monitored on groups regular and injected:
5598 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5599 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5600 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5601 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5602 * the 2 LSB are ignored.
5603 * @note On this STM32 series, setting of this feature is conditioned to
5604 * ADC state:
5605 * ADC must be disabled or enabled without conversion on going
5606 * on either groups regular or injected.
5607 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
5608 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
5609 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5610 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5611 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
5612 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
5613 * @param ADCx ADC instance
5614 * @param AWDy This parameter can be one of the following values:
5615 * @arg @ref LL_ADC_AWD1
5616 * @arg @ref LL_ADC_AWD2
5617 * @arg @ref LL_ADC_AWD3
5618 * @param AWDChannelGroup This parameter can be one of the following values:
5619 * @arg @ref LL_ADC_AWD_DISABLE
5620 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5621 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5622 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5623 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5624 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5625 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5626 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5627 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5628 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5629 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5630 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5631 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5632 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5633 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5634 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5635 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5636 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5637 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5638 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5639 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5640 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5641 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5642 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5643 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5644 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5645 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5646 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5647 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5648 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5649 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5650 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5651 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5652 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5653 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5654 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5655 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5656 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5657 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5658 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5659 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5660 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5661 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5662 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5663 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5664 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5665 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5666 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5667 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5668 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5669 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5670 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5671 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5672 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5673 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5674 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5675 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5676 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5677 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5678 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5679 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5680 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
5681 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)
5682 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
5683 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1)
5684 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1)
5685 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
5686 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5)
5687 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5)
5688 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
5689 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(6)
5690 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(6)
5691 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (6)
5692 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
5693 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
5694 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
5695 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
5696 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
5697 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
5698 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2)
5699 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2)
5700 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2)
5701 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3)
5702 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3)
5703 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3)
5704 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(5)
5705 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5)
5706 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5)
5707 * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG (0)(5)
5708 * @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5)
5709 * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5)
5710 * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG (0)(4)
5711 * @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4)
5712 * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4)
5713 *
5714 * (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n
5715 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
5716 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
5717 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
5718 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
5719 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
5720 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
5721 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
5722 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
5723 * @retval None
5724 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)5725 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
5726 {
5727 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
5728 /* in register and register position depending on parameter "AWDy". */
5729 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
5730 /* containing other bits reserved for other purpose. */
5731 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5732 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5733
5734 MODIFY_REG(*preg,
5735 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
5736 AWDChannelGroup & AWDy);
5737 }
5738
5739 /**
5740 * @brief Get ADC analog watchdog monitored channel.
5741 * @note Usage of the returned channel number:
5742 * - To reinject this channel into another function LL_ADC_xxx:
5743 * the returned channel number is only partly formatted on definition
5744 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5745 * with parts of literals LL_ADC_CHANNEL_x or using
5746 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5747 * Then the selected literal LL_ADC_CHANNEL_x can be used
5748 * as parameter for another function.
5749 * - To get the channel number in decimal format:
5750 * process the returned value with the helper macro
5751 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5752 * Applicable only when the analog watchdog is set to monitor
5753 * one channel.
5754 * @note On this STM32 series, there are 2 kinds of analog watchdog
5755 * instance:
5756 * - AWD standard (instance AWD1):
5757 * - channels monitored: can monitor 1 channel or all channels.
5758 * - groups monitored: ADC groups regular and-or injected.
5759 * - resolution: resolution is not limited (corresponds to
5760 * ADC resolution configured).
5761 * - AWD flexible (instances AWD2, AWD3):
5762 * - channels monitored: flexible on channels monitored, selection is
5763 * channel wise, from from 1 to all channels.
5764 * Specificity of this analog watchdog: Multiple channels can
5765 * be selected. For example:
5766 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5767 * - groups monitored: not selection possible (monitoring on both
5768 * groups regular and injected).
5769 * Channels selected are monitored on groups regular and injected:
5770 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5771 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5772 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5773 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5774 * the 2 LSB are ignored.
5775 * @note On this STM32 series, setting of this feature is conditioned to
5776 * ADC state:
5777 * ADC must be disabled or enabled without conversion on going
5778 * on either groups regular or injected.
5779 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
5780 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
5781 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5782 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5783 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
5784 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
5785 * @param ADCx ADC instance
5786 * @param AWDy This parameter can be one of the following values:
5787 * @arg @ref LL_ADC_AWD1
5788 * @arg @ref LL_ADC_AWD2 (1)
5789 * @arg @ref LL_ADC_AWD3 (1)
5790 *
5791 * (1) On this AWD number, monitored channel can be retrieved
5792 * if only 1 channel is programmed (or none or all channels).
5793 * This function cannot retrieve monitored channel if
5794 * multiple channels are programmed simultaneously
5795 * by bitfield.
5796 * @retval Returned value can be one of the following values:
5797 * @arg @ref LL_ADC_AWD_DISABLE
5798 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5799 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5800 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5801 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5802 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5803 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5804 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5805 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5806 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5807 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5808 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5809 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5810 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5811 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5812 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5813 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5814 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5815 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5816 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5817 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5818 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5819 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5820 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5821 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5822 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5823 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5824 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5825 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5826 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5827 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5828 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5829 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5830 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5831 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5832 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5833 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5834 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5835 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5836 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5837 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5838 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5839 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5840 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5841 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5842 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5843 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5844 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5845 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5846 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5847 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5848 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5849 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5850 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5851 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5852 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5853 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5854 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5855 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5856 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5857 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5858 *
5859 * (0) On STM32G4, parameter available only on analog watchdog number: AWD1.
5860 */
LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy)5861 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
5862 {
5863 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5864 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5865
5866 uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & ADC_AWD_CR_ALL_CHANNEL_MASK);
5867
5868 /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
5869 /* (parameter value LL_ADC_AWD_DISABLE). */
5870 /* Else, the selected AWD is enabled and is monitoring a group of channels */
5871 /* or a single channel. */
5872 if (AnalogWDMonitChannels != 0UL)
5873 {
5874 if (AWDy == LL_ADC_AWD1)
5875 {
5876 if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
5877 {
5878 /* AWD monitoring a group of channels */
5879 AnalogWDMonitChannels = ((AnalogWDMonitChannels
5880 | (ADC_AWD_CR23_CHANNEL_MASK)
5881 )
5882 & (~(ADC_CFGR_AWD1CH))
5883 );
5884 }
5885 else
5886 {
5887 /* AWD monitoring a single channel */
5888 AnalogWDMonitChannels = (AnalogWDMonitChannels
5889 | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))
5890 );
5891 }
5892 }
5893 else
5894 {
5895 if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
5896 {
5897 /* AWD monitoring a group of channels */
5898 AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
5899 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
5900 );
5901 }
5902 else
5903 {
5904 /* AWD monitoring a single channel */
5905 /* AWD monitoring a group of channels */
5906 AnalogWDMonitChannels = (AnalogWDMonitChannels
5907 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
5908 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)
5909 );
5910 }
5911 }
5912 }
5913
5914 return AnalogWDMonitChannels;
5915 }
5916
5917 /**
5918 * @brief Set ADC analog watchdog thresholds value of both thresholds
5919 * high and low.
5920 * @note If value of only one threshold high or low must be set,
5921 * use function @ref LL_ADC_SetAnalogWDThresholds().
5922 * @note In case of ADC resolution different of 12 bits,
5923 * analog watchdog thresholds data require a specific shift.
5924 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5925 * @note On this STM32 series, there are 2 kinds of analog watchdog
5926 * instance:
5927 * - AWD standard (instance AWD1):
5928 * - channels monitored: can monitor 1 channel or all channels.
5929 * - groups monitored: ADC groups regular and-or injected.
5930 * - resolution: resolution is not limited (corresponds to
5931 * ADC resolution configured).
5932 * - AWD flexible (instances AWD2, AWD3):
5933 * - channels monitored: flexible on channels monitored, selection is
5934 * channel wise, from from 1 to all channels.
5935 * Specificity of this analog watchdog: Multiple channels can
5936 * be selected. For example:
5937 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5938 * - groups monitored: not selection possible (monitoring on both
5939 * groups regular and injected).
5940 * Channels selected are monitored on groups regular and injected:
5941 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5942 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5943 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5944 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5945 * the 2 LSB are ignored.
5946 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
5947 * impacted: the comparison of analog watchdog thresholds is done on
5948 * oversampling final computation (after ratio and shift application):
5949 * ADC data register bitfield [15:4] (12 most significant bits).
5950 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
5951 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
5952 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
5953 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
5954 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
5955 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
5956 * @param ADCx ADC instance
5957 * @param AWDy This parameter can be one of the following values:
5958 * @arg @ref LL_ADC_AWD1
5959 * @arg @ref LL_ADC_AWD2
5960 * @arg @ref LL_ADC_AWD3
5961 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
5962 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
5963 * @retval None
5964 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)5965 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
5966 uint32_t AWDThresholdLowValue)
5967 {
5968 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
5969 /* position in register and register position depending on parameter */
5970 /* "AWDy". */
5971 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
5972 /* containing other bits reserved for other purpose. */
5973 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5974
5975 MODIFY_REG(*preg,
5976 ADC_TR1_HT1 | ADC_TR1_LT1,
5977 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
5978 }
5979
5980 /**
5981 * @brief Set ADC analog watchdog threshold value of threshold
5982 * high or low.
5983 * @note If values of both thresholds high or low must be set,
5984 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
5985 * @note In case of ADC resolution different of 12 bits,
5986 * analog watchdog thresholds data require a specific shift.
5987 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5988 * @note On this STM32 series, there are 2 kinds of analog watchdog
5989 * instance:
5990 * - AWD standard (instance AWD1):
5991 * - channels monitored: can monitor 1 channel or all channels.
5992 * - groups monitored: ADC groups regular and-or injected.
5993 * - resolution: resolution is not limited (corresponds to
5994 * ADC resolution configured).
5995 * - AWD flexible (instances AWD2, AWD3):
5996 * - channels monitored: flexible on channels monitored, selection is
5997 * channel wise, from from 1 to all channels.
5998 * Specificity of this analog watchdog: Multiple channels can
5999 * be selected. For example:
6000 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
6001 * - groups monitored: not selection possible (monitoring on both
6002 * groups regular and injected).
6003 * Channels selected are monitored on groups regular and injected:
6004 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
6005 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
6006 * - resolution: resolution is limited to 8 bits: if ADC resolution is
6007 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
6008 * the 2 LSB are ignored.
6009 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
6010 * impacted: the comparison of analog watchdog thresholds is done on
6011 * oversampling final computation (after ratio and shift application):
6012 * ADC data register bitfield [15:4] (12 most significant bits).
6013 * @note On this STM32 series, setting of this feature is not conditioned to
6014 * ADC state:
6015 * ADC can be disabled, enabled with or without conversion on going
6016 * on either ADC groups regular or injected.
6017 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
6018 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
6019 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
6020 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
6021 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
6022 * TR3 LT3 LL_ADC_SetAnalogWDThresholds
6023 * @param ADCx ADC instance
6024 * @param AWDy This parameter can be one of the following values:
6025 * @arg @ref LL_ADC_AWD1
6026 * @arg @ref LL_ADC_AWD2
6027 * @arg @ref LL_ADC_AWD3
6028 * @param AWDThresholdsHighLow This parameter can be one of the following values:
6029 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
6030 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
6031 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
6032 * @retval None
6033 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)6034 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
6035 uint32_t AWDThresholdValue)
6036 {
6037 /* Set bits with content of parameter "AWDThresholdValue" with bits */
6038 /* position in register and register position depending on parameters */
6039 /* "AWDThresholdsHighLow" and "AWDy". */
6040 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
6041 /* containing other bits reserved for other purpose. */
6042 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
6043 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6044
6045 MODIFY_REG(*preg,
6046 AWDThresholdsHighLow,
6047 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
6048 }
6049
6050 /**
6051 * @brief Get ADC analog watchdog threshold value of threshold high,
6052 * threshold low or raw data with ADC thresholds high and low
6053 * concatenated.
6054 * @note If raw data with ADC thresholds high and low is retrieved,
6055 * the data of each threshold high or low can be isolated
6056 * using helper macro:
6057 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
6058 * @note In case of ADC resolution different of 12 bits,
6059 * analog watchdog thresholds data require a specific shift.
6060 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
6061 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
6062 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
6063 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
6064 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
6065 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
6066 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
6067 * @param ADCx ADC instance
6068 * @param AWDy This parameter can be one of the following values:
6069 * @arg @ref LL_ADC_AWD1
6070 * @arg @ref LL_ADC_AWD2
6071 * @arg @ref LL_ADC_AWD3
6072 * @param AWDThresholdsHighLow This parameter can be one of the following values:
6073 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
6074 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
6075 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
6076 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6077 */
LL_ADC_GetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)6078 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
6079 {
6080 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
6081 ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
6082
6083 return (uint32_t)(READ_BIT(*preg,
6084 (AWDThresholdsHighLow | ADC_TR1_LT1))
6085 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
6086 & ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
6087 }
6088
6089 /**
6090 * @brief Set ADC analog watchdog filtering configuration
6091 * @note On this STM32 series, setting of this feature is conditioned to
6092 * ADC state:
6093 * ADC must be disabled or enabled without conversion on going
6094 * on either groups regular or injected.
6095 * @note On this STM32 series, this feature is only available on first
6096 * analog watchdog (AWD1)
6097 * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration
6098 * @param ADCx ADC instance
6099 * @param AWDy This parameter can be one of the following values:
6100 * @arg @ref LL_ADC_AWD1
6101 * @param FilteringConfig This parameter can be one of the following values:
6102 * @arg @ref LL_ADC_AWD_FILTERING_NONE
6103 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
6104 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
6105 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
6106 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
6107 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
6108 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
6109 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
6110 * @retval None
6111 */
LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t FilteringConfig)6112 __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
6113 {
6114 /* Prevent unused argument(s) compilation warning */
6115 (void)(AWDy);
6116 MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT, FilteringConfig);
6117 }
6118
6119 /**
6120 * @brief Get ADC analog watchdog filtering configuration
6121 * @note On this STM32 series, this feature is only available on first
6122 * analog watchdog (AWD1)
6123 * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration
6124 * @param ADCx ADC instance
6125 * @param AWDy This parameter can be one of the following values:
6126 * @arg @ref LL_ADC_AWD1
6127 * @retval Returned value can be:
6128 * @arg @ref LL_ADC_AWD_FILTERING_NONE
6129 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
6130 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
6131 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
6132 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
6133 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
6134 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
6135 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
6136 */
LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef * ADCx,uint32_t AWDy)6137 __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy)
6138 {
6139 /* Prevent unused argument(s) compilation warning */
6140 (void)(AWDy);
6141 return (uint32_t)(READ_BIT(ADCx->TR1, ADC_TR1_AWDFILT));
6142 }
6143
6144 /**
6145 * @}
6146 */
6147
6148 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
6149 * @{
6150 */
6151
6152 /**
6153 * @brief Set ADC oversampling scope: ADC groups regular and-or injected
6154 * (availability of ADC group injected depends on STM32 families).
6155 * @note If both groups regular and injected are selected,
6156 * specify behavior of ADC group injected interrupting
6157 * group regular: when ADC group injected is triggered,
6158 * the oversampling on ADC group regular is either
6159 * temporary stopped and continued, or resumed from start
6160 * (oversampler buffer reset).
6161 * @note On this STM32 series, setting of this feature is conditioned to
6162 * ADC state:
6163 * ADC must be disabled or enabled without conversion on going
6164 * on either groups regular or injected.
6165 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
6166 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
6167 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
6168 * @param ADCx ADC instance
6169 * @param OvsScope This parameter can be one of the following values:
6170 * @arg @ref LL_ADC_OVS_DISABLE
6171 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
6172 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
6173 * @arg @ref LL_ADC_OVS_GRP_INJECTED
6174 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
6175 * @retval None
6176 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)6177 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
6178 {
6179 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
6180 }
6181
6182 /**
6183 * @brief Get ADC oversampling scope: ADC groups regular and-or injected
6184 * (availability of ADC group injected depends on STM32 families).
6185 * @note If both groups regular and injected are selected,
6186 * specify behavior of ADC group injected interrupting
6187 * group regular: when ADC group injected is triggered,
6188 * the oversampling on ADC group regular is either
6189 * temporary stopped and continued, or resumed from start
6190 * (oversampler buffer reset).
6191 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
6192 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
6193 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
6194 * @param ADCx ADC instance
6195 * @retval Returned value can be one of the following values:
6196 * @arg @ref LL_ADC_OVS_DISABLE
6197 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
6198 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
6199 * @arg @ref LL_ADC_OVS_GRP_INJECTED
6200 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
6201 */
LL_ADC_GetOverSamplingScope(ADC_TypeDef * ADCx)6202 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
6203 {
6204 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
6205 }
6206
6207 /**
6208 * @brief Set ADC oversampling discontinuous mode (triggered mode)
6209 * on the selected ADC group.
6210 * @note Number of oversampled conversions are done either in:
6211 * - continuous mode (all conversions of oversampling ratio
6212 * are done from 1 trigger)
6213 * - discontinuous mode (each conversion of oversampling ratio
6214 * needs a trigger)
6215 * @note On this STM32 series, setting of this feature is conditioned to
6216 * ADC state:
6217 * ADC must be disabled or enabled without conversion on going
6218 * on group regular.
6219 * @note On this STM32 series, oversampling discontinuous mode
6220 * (triggered mode) can be used only when oversampling is
6221 * set on group regular only and in resumed mode.
6222 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
6223 * @param ADCx ADC instance
6224 * @param OverSamplingDiscont This parameter can be one of the following values:
6225 * @arg @ref LL_ADC_OVS_REG_CONT
6226 * @arg @ref LL_ADC_OVS_REG_DISCONT
6227 * @retval None
6228 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)6229 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
6230 {
6231 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
6232 }
6233
6234 /**
6235 * @brief Get ADC oversampling discontinuous mode (triggered mode)
6236 * on the selected ADC group.
6237 * @note Number of oversampled conversions are done either in:
6238 * - continuous mode (all conversions of oversampling ratio
6239 * are done from 1 trigger)
6240 * - discontinuous mode (each conversion of oversampling ratio
6241 * needs a trigger)
6242 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
6243 * @param ADCx ADC instance
6244 * @retval Returned value can be one of the following values:
6245 * @arg @ref LL_ADC_OVS_REG_CONT
6246 * @arg @ref LL_ADC_OVS_REG_DISCONT
6247 */
LL_ADC_GetOverSamplingDiscont(ADC_TypeDef * ADCx)6248 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
6249 {
6250 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
6251 }
6252
6253 /**
6254 * @brief Set ADC oversampling
6255 * (impacting both ADC groups regular and injected)
6256 * @note This function set the 2 items of oversampling configuration:
6257 * - ratio
6258 * - shift
6259 * @note On this STM32 series, setting of this feature is conditioned to
6260 * ADC state:
6261 * ADC must be disabled or enabled without conversion on going
6262 * on either groups regular or injected.
6263 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
6264 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
6265 * @param ADCx ADC instance
6266 * @param Ratio This parameter can be one of the following values:
6267 * @arg @ref LL_ADC_OVS_RATIO_2
6268 * @arg @ref LL_ADC_OVS_RATIO_4
6269 * @arg @ref LL_ADC_OVS_RATIO_8
6270 * @arg @ref LL_ADC_OVS_RATIO_16
6271 * @arg @ref LL_ADC_OVS_RATIO_32
6272 * @arg @ref LL_ADC_OVS_RATIO_64
6273 * @arg @ref LL_ADC_OVS_RATIO_128
6274 * @arg @ref LL_ADC_OVS_RATIO_256
6275 * @param Shift This parameter can be one of the following values:
6276 * @arg @ref LL_ADC_OVS_SHIFT_NONE
6277 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
6278 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
6279 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
6280 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
6281 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
6282 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
6283 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
6284 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
6285 * @retval None
6286 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)6287 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
6288 {
6289 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
6290 }
6291
6292 /**
6293 * @brief Get ADC oversampling ratio
6294 * (impacting both ADC groups regular and injected)
6295 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
6296 * @param ADCx ADC instance
6297 * @retval Ratio This parameter can be one of the following values:
6298 * @arg @ref LL_ADC_OVS_RATIO_2
6299 * @arg @ref LL_ADC_OVS_RATIO_4
6300 * @arg @ref LL_ADC_OVS_RATIO_8
6301 * @arg @ref LL_ADC_OVS_RATIO_16
6302 * @arg @ref LL_ADC_OVS_RATIO_32
6303 * @arg @ref LL_ADC_OVS_RATIO_64
6304 * @arg @ref LL_ADC_OVS_RATIO_128
6305 * @arg @ref LL_ADC_OVS_RATIO_256
6306 */
LL_ADC_GetOverSamplingRatio(ADC_TypeDef * ADCx)6307 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
6308 {
6309 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
6310 }
6311
6312 /**
6313 * @brief Get ADC oversampling shift
6314 * (impacting both ADC groups regular and injected)
6315 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
6316 * @param ADCx ADC instance
6317 * @retval Shift This parameter can be one of the following values:
6318 * @arg @ref LL_ADC_OVS_SHIFT_NONE
6319 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
6320 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
6321 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
6322 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
6323 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
6324 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
6325 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
6326 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
6327 */
LL_ADC_GetOverSamplingShift(ADC_TypeDef * ADCx)6328 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
6329 {
6330 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
6331 }
6332
6333 /**
6334 * @}
6335 */
6336
6337 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
6338 * @{
6339 */
6340
6341 #if defined(ADC_MULTIMODE_SUPPORT)
6342 /**
6343 * @brief Set ADC multimode configuration to operate in independent mode
6344 * or multimode (for devices with several ADC instances).
6345 * @note If multimode configuration: the selected ADC instance is
6346 * either master or slave depending on hardware.
6347 * Refer to reference manual.
6348 * @note On this STM32 series, setting of this feature is conditioned to
6349 * ADC state:
6350 * All ADC instances of the ADC common group must be disabled.
6351 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6352 * ADC instance or by using helper macro
6353 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
6354 * @rmtoll CCR DUAL LL_ADC_SetMultimode
6355 * @param ADCxy_COMMON ADC common instance
6356 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6357 * @param Multimode This parameter can be one of the following values:
6358 * @arg @ref LL_ADC_MULTI_INDEPENDENT
6359 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
6360 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
6361 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
6362 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
6363 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
6364 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
6365 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
6366 * @retval None
6367 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)6368 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
6369 {
6370 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
6371 }
6372
6373 /**
6374 * @brief Get ADC multimode configuration to operate in independent mode
6375 * or multimode (for devices with several ADC instances).
6376 * @note If multimode configuration: the selected ADC instance is
6377 * either master or slave depending on hardware.
6378 * Refer to reference manual.
6379 * @rmtoll CCR DUAL LL_ADC_GetMultimode
6380 * @param ADCxy_COMMON ADC common instance
6381 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6382 * @retval Returned value can be one of the following values:
6383 * @arg @ref LL_ADC_MULTI_INDEPENDENT
6384 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
6385 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
6386 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
6387 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
6388 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
6389 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
6390 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
6391 */
LL_ADC_GetMultimode(ADC_Common_TypeDef * ADCxy_COMMON)6392 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
6393 {
6394 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
6395 }
6396
6397 /**
6398 * @brief Set ADC multimode conversion data transfer: no transfer
6399 * or transfer by DMA.
6400 * @note If ADC multimode transfer by DMA is not selected:
6401 * each ADC uses its own DMA channel, with its individual
6402 * DMA transfer settings.
6403 * If ADC multimode transfer by DMA is selected:
6404 * One DMA channel is used for both ADC (DMA of ADC master)
6405 * Specifies the DMA requests mode:
6406 * - Limited mode (One shot mode): DMA transfer requests are stopped
6407 * when number of DMA data transfers (number of
6408 * ADC conversions) is reached.
6409 * This ADC mode is intended to be used with DMA mode non-circular.
6410 * - Unlimited mode: DMA transfer requests are unlimited,
6411 * whatever number of DMA data transfers (number of
6412 * ADC conversions).
6413 * This ADC mode is intended to be used with DMA mode circular.
6414 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
6415 * mode non-circular:
6416 * when DMA transfers size will be reached, DMA will stop transfers of
6417 * ADC conversions data ADC will raise an overrun error
6418 * (overrun flag and interruption if enabled).
6419 * @note How to retrieve multimode conversion data:
6420 * Whatever multimode transfer by DMA setting: using function
6421 * @ref LL_ADC_REG_ReadMultiConversionData32().
6422 * If ADC multimode transfer by DMA is selected: conversion data
6423 * is a raw data with ADC master and slave concatenated.
6424 * A macro is available to get the conversion data of
6425 * ADC master or ADC slave: see helper macro
6426 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6427 * @note On this STM32 series, setting of this feature is conditioned to
6428 * ADC state:
6429 * All ADC instances of the ADC common group must be disabled
6430 * or enabled without conversion on going on group regular.
6431 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
6432 * CCR DMACFG LL_ADC_SetMultiDMATransfer
6433 * @param ADCxy_COMMON ADC common instance
6434 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6435 * @param MultiDMATransfer This parameter can be one of the following values:
6436 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
6437 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
6438 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
6439 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
6440 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
6441 * @retval None
6442 */
LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)6443 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
6444 {
6445 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
6446 }
6447
6448 /**
6449 * @brief Get ADC multimode conversion data transfer: no transfer
6450 * or transfer by DMA.
6451 * @note If ADC multimode transfer by DMA is not selected:
6452 * each ADC uses its own DMA channel, with its individual
6453 * DMA transfer settings.
6454 * If ADC multimode transfer by DMA is selected:
6455 * One DMA channel is used for both ADC (DMA of ADC master)
6456 * Specifies the DMA requests mode:
6457 * - Limited mode (One shot mode): DMA transfer requests are stopped
6458 * when number of DMA data transfers (number of
6459 * ADC conversions) is reached.
6460 * This ADC mode is intended to be used with DMA mode non-circular.
6461 * - Unlimited mode: DMA transfer requests are unlimited,
6462 * whatever number of DMA data transfers (number of
6463 * ADC conversions).
6464 * This ADC mode is intended to be used with DMA mode circular.
6465 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
6466 * mode non-circular:
6467 * when DMA transfers size will be reached, DMA will stop transfers of
6468 * ADC conversions data ADC will raise an overrun error
6469 * (overrun flag and interruption if enabled).
6470 * @note How to retrieve multimode conversion data:
6471 * Whatever multimode transfer by DMA setting: using function
6472 * @ref LL_ADC_REG_ReadMultiConversionData32().
6473 * If ADC multimode transfer by DMA is selected: conversion data
6474 * is a raw data with ADC master and slave concatenated.
6475 * A macro is available to get the conversion data of
6476 * ADC master or ADC slave: see helper macro
6477 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6478 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
6479 * CCR DMACFG LL_ADC_GetMultiDMATransfer
6480 * @param ADCxy_COMMON ADC common instance
6481 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6482 * @retval Returned value can be one of the following values:
6483 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
6484 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
6485 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
6486 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
6487 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
6488 */
LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON)6489 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
6490 {
6491 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
6492 }
6493
6494 /**
6495 * @brief Set ADC multimode delay between 2 sampling phases.
6496 * @note The sampling delay range depends on ADC resolution:
6497 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
6498 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
6499 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
6500 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
6501 * @note On this STM32 series, setting of this feature is conditioned to
6502 * ADC state:
6503 * All ADC instances of the ADC common group must be disabled.
6504 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6505 * ADC instance or by using helper macro helper macro
6506 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
6507 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
6508 * @param ADCxy_COMMON ADC common instance
6509 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6510 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
6511 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
6512 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
6513 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
6514 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
6515 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
6516 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
6517 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
6518 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
6519 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
6520 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
6521 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
6522 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
6523 *
6524 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
6525 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
6526 * (3) Parameter available only if ADC resolution is 12 bits.
6527 * @retval None
6528 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)6529 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
6530 {
6531 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
6532 }
6533
6534 /**
6535 * @brief Get ADC multimode delay between 2 sampling phases.
6536 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
6537 * @param ADCxy_COMMON ADC common instance
6538 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6539 * @retval Returned value can be one of the following values:
6540 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
6541 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
6542 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
6543 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
6544 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
6545 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
6546 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
6547 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
6548 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
6549 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
6550 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
6551 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
6552 *
6553 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
6554 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
6555 * (3) Parameter available only if ADC resolution is 12 bits.
6556 */
LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON)6557 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
6558 {
6559 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
6560 }
6561 #endif /* ADC_MULTIMODE_SUPPORT */
6562
6563 /**
6564 * @}
6565 */
6566 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
6567 * @{
6568 */
6569
6570 /**
6571 * @brief Put ADC instance in deep power down state.
6572 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6573 * state, the internal analog calibration is lost. After exiting from
6574 * deep power down, calibration must be relaunched or calibration factor
6575 * (preliminarily saved) must be set back into calibration register.
6576 * @note On this STM32 series, setting of this feature is conditioned to
6577 * ADC state:
6578 * ADC must be ADC disabled.
6579 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
6580 * @param ADCx ADC instance
6581 * @retval None
6582 */
LL_ADC_EnableDeepPowerDown(ADC_TypeDef * ADCx)6583 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
6584 {
6585 /* Note: Write register with some additional bits forced to state reset */
6586 /* instead of modifying only the selected bit for this function, */
6587 /* to not interfere with bits with HW property "rs". */
6588 MODIFY_REG(ADCx->CR,
6589 ADC_CR_BITS_PROPERTY_RS,
6590 ADC_CR_DEEPPWD);
6591 }
6592
6593 /**
6594 * @brief Disable ADC deep power down mode.
6595 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6596 * state, the internal analog calibration is lost. After exiting from
6597 * deep power down, calibration must be relaunched or calibration factor
6598 * (preliminarily saved) must be set back into calibration register.
6599 * @note On this STM32 series, setting of this feature is conditioned to
6600 * ADC state:
6601 * ADC must be ADC disabled.
6602 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
6603 * @param ADCx ADC instance
6604 * @retval None
6605 */
LL_ADC_DisableDeepPowerDown(ADC_TypeDef * ADCx)6606 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
6607 {
6608 /* Note: Write register with some additional bits forced to state reset */
6609 /* instead of modifying only the selected bit for this function, */
6610 /* to not interfere with bits with HW property "rs". */
6611 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
6612 }
6613
6614 /**
6615 * @brief Get the selected ADC instance deep power down state.
6616 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
6617 * @param ADCx ADC instance
6618 * @retval 0: deep power down is disabled, 1: deep power down is enabled.
6619 */
LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef * ADCx)6620 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
6621 {
6622 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
6623 }
6624
6625 /**
6626 * @brief Enable ADC instance internal voltage regulator.
6627 * @note On this STM32 series, after ADC internal voltage regulator enable,
6628 * a delay for ADC internal voltage regulator stabilization
6629 * is required before performing a ADC calibration or ADC enable.
6630 * Refer to device datasheet, parameter tADCVREG_STUP.
6631 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
6632 * @note On this STM32 series, setting of this feature is conditioned to
6633 * ADC state:
6634 * ADC must be ADC disabled.
6635 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
6636 * @param ADCx ADC instance
6637 * @retval None
6638 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)6639 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
6640 {
6641 /* Note: Write register with some additional bits forced to state reset */
6642 /* instead of modifying only the selected bit for this function, */
6643 /* to not interfere with bits with HW property "rs". */
6644 MODIFY_REG(ADCx->CR,
6645 ADC_CR_BITS_PROPERTY_RS,
6646 ADC_CR_ADVREGEN);
6647 }
6648
6649 /**
6650 * @brief Disable ADC internal voltage regulator.
6651 * @note On this STM32 series, setting of this feature is conditioned to
6652 * ADC state:
6653 * ADC must be ADC disabled.
6654 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
6655 * @param ADCx ADC instance
6656 * @retval None
6657 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)6658 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
6659 {
6660 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
6661 }
6662
6663 /**
6664 * @brief Get the selected ADC instance internal voltage regulator state.
6665 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
6666 * @param ADCx ADC instance
6667 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
6668 */
LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef * ADCx)6669 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
6670 {
6671 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
6672 }
6673
6674 /**
6675 * @brief Enable the selected ADC instance.
6676 * @note On this STM32 series, after ADC enable, a delay for
6677 * ADC internal analog stabilization is required before performing a
6678 * ADC conversion start.
6679 * Refer to device datasheet, parameter tSTAB.
6680 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6681 * is enabled and when conversion clock is active.
6682 * (not only core clock: this ADC has a dual clock domain)
6683 * @note On this STM32 series, setting of this feature is conditioned to
6684 * ADC state:
6685 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
6686 * @rmtoll CR ADEN LL_ADC_Enable
6687 * @param ADCx ADC instance
6688 * @retval None
6689 */
LL_ADC_Enable(ADC_TypeDef * ADCx)6690 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
6691 {
6692 /* Note: Write register with some additional bits forced to state reset */
6693 /* instead of modifying only the selected bit for this function, */
6694 /* to not interfere with bits with HW property "rs". */
6695 MODIFY_REG(ADCx->CR,
6696 ADC_CR_BITS_PROPERTY_RS,
6697 ADC_CR_ADEN);
6698 }
6699
6700 /**
6701 * @brief Disable the selected ADC instance.
6702 * @note On this STM32 series, setting of this feature is conditioned to
6703 * ADC state:
6704 * ADC must be not disabled. Must be enabled without conversion on going
6705 * on either groups regular or injected.
6706 * @rmtoll CR ADDIS LL_ADC_Disable
6707 * @param ADCx ADC instance
6708 * @retval None
6709 */
LL_ADC_Disable(ADC_TypeDef * ADCx)6710 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
6711 {
6712 /* Note: Write register with some additional bits forced to state reset */
6713 /* instead of modifying only the selected bit for this function, */
6714 /* to not interfere with bits with HW property "rs". */
6715 MODIFY_REG(ADCx->CR,
6716 ADC_CR_BITS_PROPERTY_RS,
6717 ADC_CR_ADDIS);
6718 }
6719
6720 /**
6721 * @brief Get the selected ADC instance enable state.
6722 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6723 * is enabled and when conversion clock is active.
6724 * (not only core clock: this ADC has a dual clock domain)
6725 * @rmtoll CR ADEN LL_ADC_IsEnabled
6726 * @param ADCx ADC instance
6727 * @retval 0: ADC is disabled, 1: ADC is enabled.
6728 */
LL_ADC_IsEnabled(ADC_TypeDef * ADCx)6729 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
6730 {
6731 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
6732 }
6733
6734 /**
6735 * @brief Get the selected ADC instance disable state.
6736 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
6737 * @param ADCx ADC instance
6738 * @retval 0: no ADC disable command on going.
6739 */
LL_ADC_IsDisableOngoing(ADC_TypeDef * ADCx)6740 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
6741 {
6742 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
6743 }
6744
6745 /**
6746 * @brief Start ADC calibration in the mode single-ended
6747 * or differential (for devices with differential mode available).
6748 * @note On this STM32 series, a minimum number of ADC clock cycles
6749 * are required between ADC end of calibration and ADC enable.
6750 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
6751 * @note For devices with differential mode available:
6752 * Calibration of offset is specific to each of
6753 * single-ended and differential modes
6754 * (calibration run must be performed for each of these
6755 * differential modes, if used afterwards and if the application
6756 * requires their calibration).
6757 * @note On this STM32 series, setting of this feature is conditioned to
6758 * ADC state:
6759 * ADC must be ADC disabled.
6760 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
6761 * CR ADCALDIF LL_ADC_StartCalibration
6762 * @param ADCx ADC instance
6763 * @param SingleDiff This parameter can be one of the following values:
6764 * @arg @ref LL_ADC_SINGLE_ENDED
6765 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
6766 * @retval None
6767 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx,uint32_t SingleDiff)6768 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
6769 {
6770 /* Note: Write register with some additional bits forced to state reset */
6771 /* instead of modifying only the selected bit for this function, */
6772 /* to not interfere with bits with HW property "rs". */
6773 MODIFY_REG(ADCx->CR,
6774 ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
6775 ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
6776 }
6777
6778 /**
6779 * @brief Get ADC calibration state.
6780 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
6781 * @param ADCx ADC instance
6782 * @retval 0: calibration complete, 1: calibration in progress.
6783 */
LL_ADC_IsCalibrationOnGoing(ADC_TypeDef * ADCx)6784 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
6785 {
6786 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
6787 }
6788
6789 /**
6790 * @}
6791 */
6792
6793 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
6794 * @{
6795 */
6796
6797 /**
6798 * @brief Start ADC group regular conversion.
6799 * @note On this STM32 series, this function is relevant for both
6800 * internal trigger (SW start) and external trigger:
6801 * - If ADC trigger has been set to software start, ADC conversion
6802 * starts immediately.
6803 * - If ADC trigger has been set to external trigger, ADC conversion
6804 * will start at next trigger event (on the selected trigger edge)
6805 * following the ADC start conversion command.
6806 * @note On this STM32 series, setting of this feature is conditioned to
6807 * ADC state:
6808 * ADC must be enabled without conversion on going on group regular,
6809 * without conversion stop command on going on group regular,
6810 * without ADC disable command on going.
6811 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
6812 * @param ADCx ADC instance
6813 * @retval None
6814 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)6815 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
6816 {
6817 /* Note: Write register with some additional bits forced to state reset */
6818 /* instead of modifying only the selected bit for this function, */
6819 /* to not interfere with bits with HW property "rs". */
6820 MODIFY_REG(ADCx->CR,
6821 ADC_CR_BITS_PROPERTY_RS,
6822 ADC_CR_ADSTART);
6823 }
6824
6825 /**
6826 * @brief Stop ADC group regular conversion.
6827 * @note On this STM32 series, setting of this feature is conditioned to
6828 * ADC state:
6829 * ADC must be enabled with conversion on going on group regular,
6830 * without ADC disable command on going.
6831 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
6832 * @param ADCx ADC instance
6833 * @retval None
6834 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)6835 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
6836 {
6837 /* Note: Write register with some additional bits forced to state reset */
6838 /* instead of modifying only the selected bit for this function, */
6839 /* to not interfere with bits with HW property "rs". */
6840 MODIFY_REG(ADCx->CR,
6841 ADC_CR_BITS_PROPERTY_RS,
6842 ADC_CR_ADSTP);
6843 }
6844
6845 /**
6846 * @brief Get ADC group regular conversion state.
6847 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
6848 * @param ADCx ADC instance
6849 * @retval 0: no conversion is on going on ADC group regular.
6850 */
LL_ADC_REG_IsConversionOngoing(ADC_TypeDef * ADCx)6851 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
6852 {
6853 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
6854 }
6855
6856 /**
6857 * @brief Get ADC group regular command of conversion stop state
6858 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
6859 * @param ADCx ADC instance
6860 * @retval 0: no command of conversion stop is on going on ADC group regular.
6861 */
LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef * ADCx)6862 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
6863 {
6864 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
6865 }
6866
6867 /**
6868 * @brief Start ADC sampling phase for sampling time trigger mode
6869 * @note This function is relevant only when
6870 * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
6871 * using @ref LL_ADC_REG_SetSamplingMode
6872 * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
6873 * @note On this STM32 series, setting of this feature is conditioned to
6874 * ADC state:
6875 * ADC must be enabled without conversion on going on group regular,
6876 * without conversion stop command on going on group regular,
6877 * without ADC disable command on going.
6878 * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase
6879 * @param ADCx ADC instance
6880 * @retval None
6881 */
LL_ADC_REG_StartSamplingPhase(ADC_TypeDef * ADCx)6882 __STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx)
6883 {
6884 SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
6885 }
6886
6887 /**
6888 * @brief Stop ADC sampling phase for sampling time trigger mode and start conversion
6889 * @note This function is relevant only when
6890 * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
6891 * using @ref LL_ADC_REG_SetSamplingMode
6892 * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
6893 * - @ref LL_ADC_REG_StartSamplingPhase has been called to start
6894 * the sampling phase
6895 * @note On this STM32 series, setting of this feature is conditioned to
6896 * ADC state:
6897 * ADC must be enabled without conversion on going on group regular,
6898 * without conversion stop command on going on group regular,
6899 * without ADC disable command on going.
6900 * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase
6901 * @param ADCx ADC instance
6902 * @retval None
6903 */
LL_ADC_REG_StopSamplingPhase(ADC_TypeDef * ADCx)6904 __STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx)
6905 {
6906 CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
6907 }
6908
6909 /**
6910 * @brief Get ADC group regular conversion data, range fit for
6911 * all ADC configurations: all ADC resolutions and
6912 * all oversampling increased data width (for devices
6913 * with feature oversampling).
6914 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
6915 * @param ADCx ADC instance
6916 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6917 */
LL_ADC_REG_ReadConversionData32(ADC_TypeDef * ADCx)6918 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
6919 {
6920 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6921 }
6922
6923 /**
6924 * @brief Get ADC group regular conversion data, range fit for
6925 * ADC resolution 12 bits.
6926 * @note For devices with feature oversampling: Oversampling
6927 * can increase data width, function for extended range
6928 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6929 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
6930 * @param ADCx ADC instance
6931 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6932 */
LL_ADC_REG_ReadConversionData12(ADC_TypeDef * ADCx)6933 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
6934 {
6935 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6936 }
6937
6938 /**
6939 * @brief Get ADC group regular conversion data, range fit for
6940 * ADC resolution 10 bits.
6941 * @note For devices with feature oversampling: Oversampling
6942 * can increase data width, function for extended range
6943 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6944 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
6945 * @param ADCx ADC instance
6946 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6947 */
LL_ADC_REG_ReadConversionData10(ADC_TypeDef * ADCx)6948 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
6949 {
6950 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6951 }
6952
6953 /**
6954 * @brief Get ADC group regular conversion data, range fit for
6955 * ADC resolution 8 bits.
6956 * @note For devices with feature oversampling: Oversampling
6957 * can increase data width, function for extended range
6958 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6959 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
6960 * @param ADCx ADC instance
6961 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6962 */
LL_ADC_REG_ReadConversionData8(ADC_TypeDef * ADCx)6963 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
6964 {
6965 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6966 }
6967
6968 /**
6969 * @brief Get ADC group regular conversion data, range fit for
6970 * ADC resolution 6 bits.
6971 * @note For devices with feature oversampling: Oversampling
6972 * can increase data width, function for extended range
6973 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6974 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
6975 * @param ADCx ADC instance
6976 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
6977 */
LL_ADC_REG_ReadConversionData6(ADC_TypeDef * ADCx)6978 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
6979 {
6980 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6981 }
6982
6983 #if defined(ADC_MULTIMODE_SUPPORT)
6984 /**
6985 * @brief Get ADC multimode conversion data of ADC master, ADC slave
6986 * or raw data with ADC master and slave concatenated.
6987 * @note If raw data with ADC master and slave concatenated is retrieved,
6988 * a macro is available to get the conversion data of
6989 * ADC master or ADC slave: see helper macro
6990 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6991 * (however this macro is mainly intended for multimode
6992 * transfer by DMA, because this function can do the same
6993 * by getting multimode conversion data of ADC master or ADC slave
6994 * separately).
6995 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
6996 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
6997 * @param ADCxy_COMMON ADC common instance
6998 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6999 * @param ConversionData This parameter can be one of the following values:
7000 * @arg @ref LL_ADC_MULTI_MASTER
7001 * @arg @ref LL_ADC_MULTI_SLAVE
7002 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
7003 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
7004 */
LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)7005 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
7006 {
7007 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
7008 ConversionData)
7009 >> (POSITION_VAL(ConversionData) & 0x1FUL)
7010 );
7011 }
7012 #endif /* ADC_MULTIMODE_SUPPORT */
7013
7014 /**
7015 * @}
7016 */
7017
7018 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
7019 * @{
7020 */
7021
7022 /**
7023 * @brief Start ADC group injected conversion.
7024 * @note On this STM32 series, this function is relevant for both
7025 * internal trigger (SW start) and external trigger:
7026 * - If ADC trigger has been set to software start, ADC conversion
7027 * starts immediately.
7028 * - If ADC trigger has been set to external trigger, ADC conversion
7029 * will start at next trigger event (on the selected trigger edge)
7030 * following the ADC start conversion command.
7031 * @note On this STM32 series, setting of this feature is conditioned to
7032 * ADC state:
7033 * ADC must be enabled without conversion on going on group injected,
7034 * without conversion stop command on going on group injected,
7035 * without ADC disable command on going.
7036 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
7037 * @param ADCx ADC instance
7038 * @retval None
7039 */
LL_ADC_INJ_StartConversion(ADC_TypeDef * ADCx)7040 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
7041 {
7042 /* Note: Write register with some additional bits forced to state reset */
7043 /* instead of modifying only the selected bit for this function, */
7044 /* to not interfere with bits with HW property "rs". */
7045 MODIFY_REG(ADCx->CR,
7046 ADC_CR_BITS_PROPERTY_RS,
7047 ADC_CR_JADSTART);
7048 }
7049
7050 /**
7051 * @brief Stop ADC group injected conversion.
7052 * @note On this STM32 series, setting of this feature is conditioned to
7053 * ADC state:
7054 * ADC must be enabled with conversion on going on group injected,
7055 * without ADC disable command on going.
7056 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
7057 * @param ADCx ADC instance
7058 * @retval None
7059 */
LL_ADC_INJ_StopConversion(ADC_TypeDef * ADCx)7060 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
7061 {
7062 /* Note: Write register with some additional bits forced to state reset */
7063 /* instead of modifying only the selected bit for this function, */
7064 /* to not interfere with bits with HW property "rs". */
7065 MODIFY_REG(ADCx->CR,
7066 ADC_CR_BITS_PROPERTY_RS,
7067 ADC_CR_JADSTP);
7068 }
7069
7070 /**
7071 * @brief Get ADC group injected conversion state.
7072 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
7073 * @param ADCx ADC instance
7074 * @retval 0: no conversion is on going on ADC group injected.
7075 */
LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef * ADCx)7076 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
7077 {
7078 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
7079 }
7080
7081 /**
7082 * @brief Get ADC group injected command of conversion stop state
7083 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
7084 * @param ADCx ADC instance
7085 * @retval 0: no command of conversion stop is on going on ADC group injected.
7086 */
LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef * ADCx)7087 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
7088 {
7089 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
7090 }
7091
7092 /**
7093 * @brief Get ADC group injected conversion data, range fit for
7094 * all ADC configurations: all ADC resolutions and
7095 * all oversampling increased data width (for devices
7096 * with feature oversampling).
7097 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
7098 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
7099 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
7100 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
7101 * @param ADCx ADC instance
7102 * @param Rank This parameter can be one of the following values:
7103 * @arg @ref LL_ADC_INJ_RANK_1
7104 * @arg @ref LL_ADC_INJ_RANK_2
7105 * @arg @ref LL_ADC_INJ_RANK_3
7106 * @arg @ref LL_ADC_INJ_RANK_4
7107 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
7108 */
LL_ADC_INJ_ReadConversionData32(ADC_TypeDef * ADCx,uint32_t Rank)7109 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
7110 {
7111 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7112
7113 return (uint32_t)(READ_BIT(*preg,
7114 ADC_JDR1_JDATA)
7115 );
7116 }
7117
7118 /**
7119 * @brief Get ADC group injected conversion data, range fit for
7120 * ADC resolution 12 bits.
7121 * @note For devices with feature oversampling: Oversampling
7122 * can increase data width, function for extended range
7123 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7124 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
7125 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
7126 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
7127 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
7128 * @param ADCx ADC instance
7129 * @param Rank This parameter can be one of the following values:
7130 * @arg @ref LL_ADC_INJ_RANK_1
7131 * @arg @ref LL_ADC_INJ_RANK_2
7132 * @arg @ref LL_ADC_INJ_RANK_3
7133 * @arg @ref LL_ADC_INJ_RANK_4
7134 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
7135 */
LL_ADC_INJ_ReadConversionData12(ADC_TypeDef * ADCx,uint32_t Rank)7136 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
7137 {
7138 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7139
7140 return (uint16_t)(READ_BIT(*preg,
7141 ADC_JDR1_JDATA)
7142 );
7143 }
7144
7145 /**
7146 * @brief Get ADC group injected conversion data, range fit for
7147 * ADC resolution 10 bits.
7148 * @note For devices with feature oversampling: Oversampling
7149 * can increase data width, function for extended range
7150 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7151 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
7152 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
7153 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
7154 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
7155 * @param ADCx ADC instance
7156 * @param Rank This parameter can be one of the following values:
7157 * @arg @ref LL_ADC_INJ_RANK_1
7158 * @arg @ref LL_ADC_INJ_RANK_2
7159 * @arg @ref LL_ADC_INJ_RANK_3
7160 * @arg @ref LL_ADC_INJ_RANK_4
7161 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
7162 */
LL_ADC_INJ_ReadConversionData10(ADC_TypeDef * ADCx,uint32_t Rank)7163 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
7164 {
7165 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7166
7167 return (uint16_t)(READ_BIT(*preg,
7168 ADC_JDR1_JDATA)
7169 );
7170 }
7171
7172 /**
7173 * @brief Get ADC group injected conversion data, range fit for
7174 * ADC resolution 8 bits.
7175 * @note For devices with feature oversampling: Oversampling
7176 * can increase data width, function for extended range
7177 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7178 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
7179 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
7180 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
7181 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
7182 * @param ADCx ADC instance
7183 * @param Rank This parameter can be one of the following values:
7184 * @arg @ref LL_ADC_INJ_RANK_1
7185 * @arg @ref LL_ADC_INJ_RANK_2
7186 * @arg @ref LL_ADC_INJ_RANK_3
7187 * @arg @ref LL_ADC_INJ_RANK_4
7188 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
7189 */
LL_ADC_INJ_ReadConversionData8(ADC_TypeDef * ADCx,uint32_t Rank)7190 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
7191 {
7192 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7193
7194 return (uint8_t)(READ_BIT(*preg,
7195 ADC_JDR1_JDATA)
7196 );
7197 }
7198
7199 /**
7200 * @brief Get ADC group injected conversion data, range fit for
7201 * ADC resolution 6 bits.
7202 * @note For devices with feature oversampling: Oversampling
7203 * can increase data width, function for extended range
7204 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7205 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
7206 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
7207 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
7208 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
7209 * @param ADCx ADC instance
7210 * @param Rank This parameter can be one of the following values:
7211 * @arg @ref LL_ADC_INJ_RANK_1
7212 * @arg @ref LL_ADC_INJ_RANK_2
7213 * @arg @ref LL_ADC_INJ_RANK_3
7214 * @arg @ref LL_ADC_INJ_RANK_4
7215 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
7216 */
LL_ADC_INJ_ReadConversionData6(ADC_TypeDef * ADCx,uint32_t Rank)7217 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
7218 {
7219 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7220
7221 return (uint8_t)(READ_BIT(*preg,
7222 ADC_JDR1_JDATA)
7223 );
7224 }
7225
7226 /**
7227 * @}
7228 */
7229
7230 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
7231 * @{
7232 */
7233
7234 /**
7235 * @brief Get flag ADC ready.
7236 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7237 * is enabled and when conversion clock is active.
7238 * (not only core clock: this ADC has a dual clock domain)
7239 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
7240 * @param ADCx ADC instance
7241 * @retval State of bit (1 or 0).
7242 */
LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef * ADCx)7243 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
7244 {
7245 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
7246 }
7247
7248 /**
7249 * @brief Get flag ADC group regular end of unitary conversion.
7250 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
7251 * @param ADCx ADC instance
7252 * @retval State of bit (1 or 0).
7253 */
LL_ADC_IsActiveFlag_EOC(ADC_TypeDef * ADCx)7254 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
7255 {
7256 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
7257 }
7258
7259 /**
7260 * @brief Get flag ADC group regular end of sequence conversions.
7261 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
7262 * @param ADCx ADC instance
7263 * @retval State of bit (1 or 0).
7264 */
LL_ADC_IsActiveFlag_EOS(ADC_TypeDef * ADCx)7265 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
7266 {
7267 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
7268 }
7269
7270 /**
7271 * @brief Get flag ADC group regular overrun.
7272 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
7273 * @param ADCx ADC instance
7274 * @retval State of bit (1 or 0).
7275 */
LL_ADC_IsActiveFlag_OVR(ADC_TypeDef * ADCx)7276 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
7277 {
7278 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
7279 }
7280
7281 /**
7282 * @brief Get flag ADC group regular end of sampling phase.
7283 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
7284 * @param ADCx ADC instance
7285 * @retval State of bit (1 or 0).
7286 */
LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef * ADCx)7287 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
7288 {
7289 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
7290 }
7291
7292 /**
7293 * @brief Get flag ADC group injected end of unitary conversion.
7294 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
7295 * @param ADCx ADC instance
7296 * @retval State of bit (1 or 0).
7297 */
LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef * ADCx)7298 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
7299 {
7300 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
7301 }
7302
7303 /**
7304 * @brief Get flag ADC group injected end of sequence conversions.
7305 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
7306 * @param ADCx ADC instance
7307 * @retval State of bit (1 or 0).
7308 */
LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef * ADCx)7309 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
7310 {
7311 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
7312 }
7313
7314 /**
7315 * @brief Get flag ADC group injected contexts queue overflow.
7316 * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
7317 * @param ADCx ADC instance
7318 * @retval State of bit (1 or 0).
7319 */
LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef * ADCx)7320 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
7321 {
7322 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
7323 }
7324
7325 /**
7326 * @brief Get flag ADC analog watchdog 1 flag
7327 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
7328 * @param ADCx ADC instance
7329 * @retval State of bit (1 or 0).
7330 */
LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef * ADCx)7331 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
7332 {
7333 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
7334 }
7335
7336 /**
7337 * @brief Get flag ADC analog watchdog 2.
7338 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
7339 * @param ADCx ADC instance
7340 * @retval State of bit (1 or 0).
7341 */
LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef * ADCx)7342 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
7343 {
7344 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
7345 }
7346
7347 /**
7348 * @brief Get flag ADC analog watchdog 3.
7349 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
7350 * @param ADCx ADC instance
7351 * @retval State of bit (1 or 0).
7352 */
LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef * ADCx)7353 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
7354 {
7355 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
7356 }
7357
7358 /**
7359 * @brief Clear flag ADC ready.
7360 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7361 * is enabled and when conversion clock is active.
7362 * (not only core clock: this ADC has a dual clock domain)
7363 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
7364 * @param ADCx ADC instance
7365 * @retval None
7366 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)7367 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
7368 {
7369 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
7370 }
7371
7372 /**
7373 * @brief Clear flag ADC group regular end of unitary conversion.
7374 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
7375 * @param ADCx ADC instance
7376 * @retval None
7377 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)7378 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
7379 {
7380 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
7381 }
7382
7383 /**
7384 * @brief Clear flag ADC group regular end of sequence conversions.
7385 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
7386 * @param ADCx ADC instance
7387 * @retval None
7388 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)7389 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
7390 {
7391 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
7392 }
7393
7394 /**
7395 * @brief Clear flag ADC group regular overrun.
7396 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
7397 * @param ADCx ADC instance
7398 * @retval None
7399 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)7400 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
7401 {
7402 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
7403 }
7404
7405 /**
7406 * @brief Clear flag ADC group regular end of sampling phase.
7407 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
7408 * @param ADCx ADC instance
7409 * @retval None
7410 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)7411 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
7412 {
7413 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
7414 }
7415
7416 /**
7417 * @brief Clear flag ADC group injected end of unitary conversion.
7418 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
7419 * @param ADCx ADC instance
7420 * @retval None
7421 */
LL_ADC_ClearFlag_JEOC(ADC_TypeDef * ADCx)7422 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
7423 {
7424 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
7425 }
7426
7427 /**
7428 * @brief Clear flag ADC group injected end of sequence conversions.
7429 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
7430 * @param ADCx ADC instance
7431 * @retval None
7432 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)7433 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
7434 {
7435 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
7436 }
7437
7438 /**
7439 * @brief Clear flag ADC group injected contexts queue overflow.
7440 * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
7441 * @param ADCx ADC instance
7442 * @retval None
7443 */
LL_ADC_ClearFlag_JQOVF(ADC_TypeDef * ADCx)7444 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
7445 {
7446 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
7447 }
7448
7449 /**
7450 * @brief Clear flag ADC analog watchdog 1.
7451 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
7452 * @param ADCx ADC instance
7453 * @retval None
7454 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)7455 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
7456 {
7457 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
7458 }
7459
7460 /**
7461 * @brief Clear flag ADC analog watchdog 2.
7462 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
7463 * @param ADCx ADC instance
7464 * @retval None
7465 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)7466 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
7467 {
7468 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
7469 }
7470
7471 /**
7472 * @brief Clear flag ADC analog watchdog 3.
7473 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
7474 * @param ADCx ADC instance
7475 * @retval None
7476 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)7477 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
7478 {
7479 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
7480 }
7481
7482 #if defined(ADC_MULTIMODE_SUPPORT)
7483 /**
7484 * @brief Get flag multimode ADC ready of the ADC master.
7485 * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
7486 * @param ADCxy_COMMON ADC common instance
7487 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7488 * @retval State of bit (1 or 0).
7489 */
LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef * ADCxy_COMMON)7490 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
7491 {
7492 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
7493 }
7494
7495 /**
7496 * @brief Get flag multimode ADC ready of the ADC slave.
7497 * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
7498 * @param ADCxy_COMMON ADC common instance
7499 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7500 * @retval State of bit (1 or 0).
7501 */
LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef * ADCxy_COMMON)7502 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
7503 {
7504 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
7505 }
7506
7507 /**
7508 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
7509 * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
7510 * @param ADCxy_COMMON ADC common instance
7511 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7512 * @retval State of bit (1 or 0).
7513 */
LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef * ADCxy_COMMON)7514 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
7515 {
7516 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7517 }
7518
7519 /**
7520 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
7521 * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
7522 * @param ADCxy_COMMON ADC common instance
7523 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7524 * @retval State of bit (1 or 0).
7525 */
LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef * ADCxy_COMMON)7526 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
7527 {
7528 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7529 }
7530
7531 /**
7532 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
7533 * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
7534 * @param ADCxy_COMMON ADC common instance
7535 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7536 * @retval State of bit (1 or 0).
7537 */
LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef * ADCxy_COMMON)7538 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
7539 {
7540 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
7541 }
7542
7543 /**
7544 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
7545 * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
7546 * @param ADCxy_COMMON ADC common instance
7547 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7548 * @retval State of bit (1 or 0).
7549 */
LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef * ADCxy_COMMON)7550 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
7551 {
7552 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
7553 }
7554
7555 /**
7556 * @brief Get flag multimode ADC group regular overrun of the ADC master.
7557 * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
7558 * @param ADCxy_COMMON ADC common instance
7559 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7560 * @retval State of bit (1 or 0).
7561 */
LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef * ADCxy_COMMON)7562 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
7563 {
7564 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
7565 }
7566
7567 /**
7568 * @brief Get flag multimode ADC group regular overrun of the ADC slave.
7569 * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
7570 * @param ADCxy_COMMON ADC common instance
7571 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7572 * @retval State of bit (1 or 0).
7573 */
LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef * ADCxy_COMMON)7574 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
7575 {
7576 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
7577 }
7578
7579 /**
7580 * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
7581 * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
7582 * @param ADCxy_COMMON ADC common instance
7583 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7584 * @retval State of bit (1 or 0).
7585 */
LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef * ADCxy_COMMON)7586 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
7587 {
7588 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
7589 }
7590
7591 /**
7592 * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
7593 * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
7594 * @param ADCxy_COMMON ADC common instance
7595 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7596 * @retval State of bit (1 or 0).
7597 */
LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef * ADCxy_COMMON)7598 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
7599 {
7600 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
7601 }
7602
7603 /**
7604 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
7605 * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
7606 * @param ADCxy_COMMON ADC common instance
7607 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7608 * @retval State of bit (1 or 0).
7609 */
LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef * ADCxy_COMMON)7610 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
7611 {
7612 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
7613 }
7614
7615 /**
7616 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
7617 * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
7618 * @param ADCxy_COMMON ADC common instance
7619 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7620 * @retval State of bit (1 or 0).
7621 */
LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef * ADCxy_COMMON)7622 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
7623 {
7624 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
7625 }
7626
7627 /**
7628 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
7629 * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
7630 * @param ADCxy_COMMON ADC common instance
7631 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7632 * @retval State of bit (1 or 0).
7633 */
LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)7634 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
7635 {
7636 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
7637 }
7638
7639 /**
7640 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
7641 * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
7642 * @param ADCxy_COMMON ADC common instance
7643 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7644 * @retval State of bit (1 or 0).
7645 */
LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)7646 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
7647 {
7648 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
7649 }
7650
7651 /**
7652 * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
7653 * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
7654 * @param ADCxy_COMMON ADC common instance
7655 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7656 * @retval State of bit (1 or 0).
7657 */
LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef * ADCxy_COMMON)7658 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
7659 {
7660 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
7661 }
7662
7663 /**
7664 * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
7665 * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
7666 * @param ADCxy_COMMON ADC common instance
7667 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7668 * @retval State of bit (1 or 0).
7669 */
LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef * ADCxy_COMMON)7670 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
7671 {
7672 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
7673 }
7674
7675 /**
7676 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
7677 * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
7678 * @param ADCxy_COMMON ADC common instance
7679 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7680 * @retval State of bit (1 or 0).
7681 */
LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)7682 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
7683 {
7684 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
7685 }
7686
7687 /**
7688 * @brief Get flag multimode analog watchdog 1 of the ADC slave.
7689 * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
7690 * @param ADCxy_COMMON ADC common instance
7691 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7692 * @retval State of bit (1 or 0).
7693 */
LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)7694 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
7695 {
7696 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
7697 }
7698
7699 /**
7700 * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
7701 * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
7702 * @param ADCxy_COMMON ADC common instance
7703 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7704 * @retval State of bit (1 or 0).
7705 */
LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef * ADCxy_COMMON)7706 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
7707 {
7708 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
7709 }
7710
7711 /**
7712 * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
7713 * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
7714 * @param ADCxy_COMMON ADC common instance
7715 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7716 * @retval State of bit (1 or 0).
7717 */
LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef * ADCxy_COMMON)7718 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
7719 {
7720 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
7721 }
7722
7723 /**
7724 * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
7725 * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
7726 * @param ADCxy_COMMON ADC common instance
7727 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7728 * @retval State of bit (1 or 0).
7729 */
LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef * ADCxy_COMMON)7730 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
7731 {
7732 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
7733 }
7734
7735 /**
7736 * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
7737 * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
7738 * @param ADCxy_COMMON ADC common instance
7739 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7740 * @retval State of bit (1 or 0).
7741 */
LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef * ADCxy_COMMON)7742 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
7743 {
7744 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
7745 }
7746 #endif /* ADC_MULTIMODE_SUPPORT */
7747
7748 /**
7749 * @}
7750 */
7751
7752 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
7753 * @{
7754 */
7755
7756 /**
7757 * @brief Enable ADC ready.
7758 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
7759 * @param ADCx ADC instance
7760 * @retval None
7761 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)7762 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
7763 {
7764 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7765 }
7766
7767 /**
7768 * @brief Enable interruption ADC group regular end of unitary conversion.
7769 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
7770 * @param ADCx ADC instance
7771 * @retval None
7772 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)7773 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
7774 {
7775 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
7776 }
7777
7778 /**
7779 * @brief Enable interruption ADC group regular end of sequence conversions.
7780 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
7781 * @param ADCx ADC instance
7782 * @retval None
7783 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)7784 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
7785 {
7786 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
7787 }
7788
7789 /**
7790 * @brief Enable ADC group regular interruption overrun.
7791 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
7792 * @param ADCx ADC instance
7793 * @retval None
7794 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)7795 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
7796 {
7797 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
7798 }
7799
7800 /**
7801 * @brief Enable interruption ADC group regular end of sampling.
7802 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
7803 * @param ADCx ADC instance
7804 * @retval None
7805 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)7806 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
7807 {
7808 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7809 }
7810
7811 /**
7812 * @brief Enable interruption ADC group injected end of unitary conversion.
7813 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
7814 * @param ADCx ADC instance
7815 * @retval None
7816 */
LL_ADC_EnableIT_JEOC(ADC_TypeDef * ADCx)7817 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
7818 {
7819 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7820 }
7821
7822 /**
7823 * @brief Enable interruption ADC group injected end of sequence conversions.
7824 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
7825 * @param ADCx ADC instance
7826 * @retval None
7827 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)7828 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
7829 {
7830 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7831 }
7832
7833 /**
7834 * @brief Enable interruption ADC group injected context queue overflow.
7835 * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
7836 * @param ADCx ADC instance
7837 * @retval None
7838 */
LL_ADC_EnableIT_JQOVF(ADC_TypeDef * ADCx)7839 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
7840 {
7841 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7842 }
7843
7844 /**
7845 * @brief Enable interruption ADC analog watchdog 1.
7846 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
7847 * @param ADCx ADC instance
7848 * @retval None
7849 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)7850 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
7851 {
7852 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7853 }
7854
7855 /**
7856 * @brief Enable interruption ADC analog watchdog 2.
7857 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
7858 * @param ADCx ADC instance
7859 * @retval None
7860 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)7861 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
7862 {
7863 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7864 }
7865
7866 /**
7867 * @brief Enable interruption ADC analog watchdog 3.
7868 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
7869 * @param ADCx ADC instance
7870 * @retval None
7871 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)7872 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
7873 {
7874 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7875 }
7876
7877 /**
7878 * @brief Disable interruption ADC ready.
7879 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
7880 * @param ADCx ADC instance
7881 * @retval None
7882 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)7883 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
7884 {
7885 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7886 }
7887
7888 /**
7889 * @brief Disable interruption ADC group regular end of unitary conversion.
7890 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
7891 * @param ADCx ADC instance
7892 * @retval None
7893 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)7894 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
7895 {
7896 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
7897 }
7898
7899 /**
7900 * @brief Disable interruption ADC group regular end of sequence conversions.
7901 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
7902 * @param ADCx ADC instance
7903 * @retval None
7904 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)7905 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
7906 {
7907 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
7908 }
7909
7910 /**
7911 * @brief Disable interruption ADC group regular overrun.
7912 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
7913 * @param ADCx ADC instance
7914 * @retval None
7915 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)7916 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
7917 {
7918 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
7919 }
7920
7921 /**
7922 * @brief Disable interruption ADC group regular end of sampling.
7923 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
7924 * @param ADCx ADC instance
7925 * @retval None
7926 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)7927 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
7928 {
7929 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7930 }
7931
7932 /**
7933 * @brief Disable interruption ADC group regular end of unitary conversion.
7934 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
7935 * @param ADCx ADC instance
7936 * @retval None
7937 */
LL_ADC_DisableIT_JEOC(ADC_TypeDef * ADCx)7938 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
7939 {
7940 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7941 }
7942
7943 /**
7944 * @brief Disable interruption ADC group injected end of sequence conversions.
7945 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
7946 * @param ADCx ADC instance
7947 * @retval None
7948 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)7949 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
7950 {
7951 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7952 }
7953
7954 /**
7955 * @brief Disable interruption ADC group injected context queue overflow.
7956 * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
7957 * @param ADCx ADC instance
7958 * @retval None
7959 */
LL_ADC_DisableIT_JQOVF(ADC_TypeDef * ADCx)7960 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
7961 {
7962 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7963 }
7964
7965 /**
7966 * @brief Disable interruption ADC analog watchdog 1.
7967 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
7968 * @param ADCx ADC instance
7969 * @retval None
7970 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)7971 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
7972 {
7973 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7974 }
7975
7976 /**
7977 * @brief Disable interruption ADC analog watchdog 2.
7978 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
7979 * @param ADCx ADC instance
7980 * @retval None
7981 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)7982 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
7983 {
7984 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7985 }
7986
7987 /**
7988 * @brief Disable interruption ADC analog watchdog 3.
7989 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
7990 * @param ADCx ADC instance
7991 * @retval None
7992 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)7993 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
7994 {
7995 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7996 }
7997
7998 /**
7999 * @brief Get state of interruption ADC ready
8000 * (0: interrupt disabled, 1: interrupt enabled).
8001 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
8002 * @param ADCx ADC instance
8003 * @retval State of bit (1 or 0).
8004 */
LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef * ADCx)8005 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
8006 {
8007 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
8008 }
8009
8010 /**
8011 * @brief Get state of interruption ADC group regular end of unitary conversion
8012 * (0: interrupt disabled, 1: interrupt enabled).
8013 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
8014 * @param ADCx ADC instance
8015 * @retval State of bit (1 or 0).
8016 */
LL_ADC_IsEnabledIT_EOC(ADC_TypeDef * ADCx)8017 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
8018 {
8019 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
8020 }
8021
8022 /**
8023 * @brief Get state of interruption ADC group regular end of sequence conversions
8024 * (0: interrupt disabled, 1: interrupt enabled).
8025 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
8026 * @param ADCx ADC instance
8027 * @retval State of bit (1 or 0).
8028 */
LL_ADC_IsEnabledIT_EOS(ADC_TypeDef * ADCx)8029 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
8030 {
8031 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
8032 }
8033
8034 /**
8035 * @brief Get state of interruption ADC group regular overrun
8036 * (0: interrupt disabled, 1: interrupt enabled).
8037 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
8038 * @param ADCx ADC instance
8039 * @retval State of bit (1 or 0).
8040 */
LL_ADC_IsEnabledIT_OVR(ADC_TypeDef * ADCx)8041 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
8042 {
8043 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
8044 }
8045
8046 /**
8047 * @brief Get state of interruption ADC group regular end of sampling
8048 * (0: interrupt disabled, 1: interrupt enabled).
8049 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
8050 * @param ADCx ADC instance
8051 * @retval State of bit (1 or 0).
8052 */
LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef * ADCx)8053 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
8054 {
8055 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
8056 }
8057
8058 /**
8059 * @brief Get state of interruption ADC group injected end of unitary conversion
8060 * (0: interrupt disabled, 1: interrupt enabled).
8061 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
8062 * @param ADCx ADC instance
8063 * @retval State of bit (1 or 0).
8064 */
LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef * ADCx)8065 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
8066 {
8067 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
8068 }
8069
8070 /**
8071 * @brief Get state of interruption ADC group injected end of sequence conversions
8072 * (0: interrupt disabled, 1: interrupt enabled).
8073 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
8074 * @param ADCx ADC instance
8075 * @retval State of bit (1 or 0).
8076 */
LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef * ADCx)8077 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
8078 {
8079 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
8080 }
8081
8082 /**
8083 * @brief Get state of interruption ADC group injected context queue overflow interrupt state
8084 * (0: interrupt disabled, 1: interrupt enabled).
8085 * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
8086 * @param ADCx ADC instance
8087 * @retval State of bit (1 or 0).
8088 */
LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef * ADCx)8089 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
8090 {
8091 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
8092 }
8093
8094 /**
8095 * @brief Get state of interruption ADC analog watchdog 1
8096 * (0: interrupt disabled, 1: interrupt enabled).
8097 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
8098 * @param ADCx ADC instance
8099 * @retval State of bit (1 or 0).
8100 */
LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef * ADCx)8101 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
8102 {
8103 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
8104 }
8105
8106 /**
8107 * @brief Get state of interruption Get ADC analog watchdog 2
8108 * (0: interrupt disabled, 1: interrupt enabled).
8109 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
8110 * @param ADCx ADC instance
8111 * @retval State of bit (1 or 0).
8112 */
LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef * ADCx)8113 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
8114 {
8115 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
8116 }
8117
8118 /**
8119 * @brief Get state of interruption Get ADC analog watchdog 3
8120 * (0: interrupt disabled, 1: interrupt enabled).
8121 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
8122 * @param ADCx ADC instance
8123 * @retval State of bit (1 or 0).
8124 */
LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef * ADCx)8125 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
8126 {
8127 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
8128 }
8129
8130 /**
8131 * @}
8132 */
8133
8134 #if defined(USE_FULL_LL_DRIVER)
8135 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
8136 * @{
8137 */
8138
8139 /* Initialization of some features of ADC common parameters and multimode */
8140 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
8141 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
8142 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
8143
8144 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
8145 /* (availability of ADC group injected depends on STM32 families) */
8146 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
8147
8148 /* Initialization of some features of ADC instance */
8149 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
8150 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
8151
8152 /* Initialization of some features of ADC instance and ADC group regular */
8153 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
8154 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
8155
8156 /* Initialization of some features of ADC instance and ADC group injected */
8157 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
8158 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
8159
8160 /**
8161 * @}
8162 */
8163 #endif /* USE_FULL_LL_DRIVER */
8164
8165 /**
8166 * @}
8167 */
8168
8169 /**
8170 * @}
8171 */
8172
8173 #endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */
8174
8175 /**
8176 * @}
8177 */
8178
8179 #ifdef __cplusplus
8180 }
8181 #endif
8182
8183 #endif /* STM32G4xx_LL_ADC_H */
8184
