1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32G4xx_HAL_RCC_EX_H 20 #define STM32G4xx_HAL_RCC_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32g4xx_hal_def.h" 28 29 /** @addtogroup STM32G4xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCCEx 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 39 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief RCC extended clocks structure definition 45 */ 46 typedef struct 47 { 48 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 49 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 50 51 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. 52 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ 53 54 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. 55 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ 56 57 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. 58 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ 59 60 #if defined(UART4) 61 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. 62 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ 63 #endif /* UART4 */ 64 65 #if defined(UART5) 66 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. 67 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ 68 69 #endif /* UART5 */ 70 71 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. 72 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 73 74 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. 75 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ 76 77 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. 78 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ 79 80 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. 81 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ 82 83 #if defined(I2C4) 84 85 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. 86 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ 87 #endif /* I2C4 */ 88 89 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. 90 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ 91 92 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. 93 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ 94 95 uint32_t I2sClockSelection; /*!< Specifies I2S clock source. 96 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ 97 #if defined(FDCAN1) 98 99 uint32_t FdcanClockSelection; /*!< Specifies FDCAN clock source. 100 This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ 101 #endif /* FDCAN1 */ 102 #if defined(USB) 103 104 uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for RNG). 105 This parameter can be a value of @ref RCCEx_USB_Clock_Source */ 106 #endif /* USB */ 107 108 uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB). 109 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ 110 111 uint32_t Adc12ClockSelection; /*!< Specifies ADC12 interface clock source. 112 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ 113 114 #if defined(ADC345_COMMON) 115 uint32_t Adc345ClockSelection; /*!< Specifies ADC345 interface clock source. 116 This parameter can be a value of @ref RCCEx_ADC345_Clock_Source */ 117 #endif /* ADC345_COMMON */ 118 119 #if defined(QUADSPI) 120 uint32_t QspiClockSelection; /*!< Specifies QuadSPI clock source. 121 This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */ 122 #endif 123 124 uint32_t RTCClockSelection; /*!< Specifies RTC clock source. 125 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 126 }RCC_PeriphCLKInitTypeDef; 127 128 /** 129 * @brief RCC_CRS Init structure definition 130 */ 131 typedef struct 132 { 133 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. 134 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ 135 136 uint32_t Source; /*!< Specifies the SYNC signal source. 137 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ 138 139 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. 140 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ 141 142 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. 143 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) 144 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ 145 146 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. 147 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ 148 149 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. 150 This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ 151 152 }RCC_CRSInitTypeDef; 153 154 /** 155 * @brief RCC_CRS Synchronization structure definition 156 */ 157 typedef struct 158 { 159 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. 160 This parameter must be a number between 0 and 0xFFFF */ 161 162 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. 163 This parameter must be a number between 0 and 0x7F */ 164 165 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter 166 value latched in the time of the last SYNC event. 167 This parameter must be a number between 0 and 0xFFFF */ 168 169 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the 170 frequency error counter latched in the time of the last SYNC event. 171 It shows whether the actual frequency is below or above the target. 172 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ 173 174 }RCC_CRSSynchroInfoTypeDef; 175 176 /** 177 * @} 178 */ 179 180 /* Exported constants --------------------------------------------------------*/ 181 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 182 * @{ 183 */ 184 185 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source 186 * @{ 187 */ 188 #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ 189 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ 190 /** 191 * @} 192 */ 193 194 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 195 * @{ 196 */ 197 #define RCC_PERIPHCLK_USART1 0x00000001U 198 #define RCC_PERIPHCLK_USART2 0x00000002U 199 #define RCC_PERIPHCLK_USART3 0x00000004U 200 #if defined(UART4) 201 #define RCC_PERIPHCLK_UART4 0x00000008U 202 #endif /* UART4 */ 203 #if defined(UART5) 204 #define RCC_PERIPHCLK_UART5 0x00000010U 205 #endif /* UART5 */ 206 #define RCC_PERIPHCLK_LPUART1 0x00000020U 207 #define RCC_PERIPHCLK_I2C1 0x00000040U 208 #define RCC_PERIPHCLK_I2C2 0x00000080U 209 #define RCC_PERIPHCLK_I2C3 0x00000100U 210 #define RCC_PERIPHCLK_LPTIM1 0x00000200U 211 #define RCC_PERIPHCLK_SAI1 0x00000400U 212 #define RCC_PERIPHCLK_I2S 0x00000800U 213 #if defined(FDCAN1) 214 #define RCC_PERIPHCLK_FDCAN 0x00001000U 215 #endif /* FDCAN1 */ 216 #define RCC_PERIPHCLK_USB 0x00002000U 217 #define RCC_PERIPHCLK_RNG 0x00004000U 218 #define RCC_PERIPHCLK_ADC12 0x00008000U 219 #if defined(ADC345_COMMON) 220 #define RCC_PERIPHCLK_ADC345 0x00010000U 221 #endif /* ADC345_COMMON */ 222 #if defined(I2C4) 223 #define RCC_PERIPHCLK_I2C4 0x00020000U 224 #endif /* I2C4 */ 225 #if defined(QUADSPI) 226 #define RCC_PERIPHCLK_QSPI 0x00040000U 227 #endif /* QUADSPI */ 228 #define RCC_PERIPHCLK_RTC 0x00080000U 229 /** 230 * @} 231 */ 232 233 234 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source 235 * @{ 236 */ 237 #define RCC_USART1CLKSOURCE_PCLK2 0x00000000U 238 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 239 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 240 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) 241 /** 242 * @} 243 */ 244 245 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source 246 * @{ 247 */ 248 #define RCC_USART2CLKSOURCE_PCLK1 0x00000000U 249 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 250 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 251 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) 252 /** 253 * @} 254 */ 255 256 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source 257 * @{ 258 */ 259 #define RCC_USART3CLKSOURCE_PCLK1 0x00000000U 260 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 261 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 262 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) 263 /** 264 * @} 265 */ 266 267 #if defined(UART4) 268 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source 269 * @{ 270 */ 271 #define RCC_UART4CLKSOURCE_PCLK1 0x00000000U 272 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 273 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 274 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) 275 /** 276 * @} 277 */ 278 #endif /* UART4 */ 279 280 #if defined(UART5) 281 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source 282 * @{ 283 */ 284 #define RCC_UART5CLKSOURCE_PCLK1 0x00000000U 285 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 286 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 287 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) 288 /** 289 * @} 290 */ 291 #endif /* UART5 */ 292 293 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 294 * @{ 295 */ 296 #define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U 297 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 298 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 299 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) 300 /** 301 * @} 302 */ 303 304 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source 305 * @{ 306 */ 307 #define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U 308 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 309 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 310 /** 311 * @} 312 */ 313 314 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source 315 * @{ 316 */ 317 #define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U 318 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 319 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 320 /** 321 * @} 322 */ 323 324 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source 325 * @{ 326 */ 327 #define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U 328 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 329 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 330 /** 331 * @} 332 */ 333 334 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source 335 * @{ 336 */ 337 #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U 338 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 339 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 340 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL 341 /** 342 * @} 343 */ 344 345 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source 346 * @{ 347 */ 348 #define RCC_SAI1CLKSOURCE_SYSCLK 0x00000000U 349 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0 350 #define RCC_SAI1CLKSOURCE_EXT RCC_CCIPR_SAI1SEL_1 351 #define RCC_SAI1CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_1 | RCC_CCIPR_SAI1SEL_0) 352 /** 353 * @} 354 */ 355 356 /** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source 357 * @{ 358 */ 359 #define RCC_I2SCLKSOURCE_SYSCLK 0x00000000U 360 #define RCC_I2SCLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0 361 #define RCC_I2SCLKSOURCE_EXT RCC_CCIPR_I2S23SEL_1 362 #define RCC_I2SCLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_1 | RCC_CCIPR_I2S23SEL_0) 363 /** 364 * @} 365 */ 366 #if defined(FDCAN1) 367 /** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source 368 * @{ 369 */ 370 #define RCC_FDCANCLKSOURCE_HSE 0x00000000U 371 #define RCC_FDCANCLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0 372 #define RCC_FDCANCLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1 373 /** 374 * @} 375 */ 376 #endif /* FDCAN1 */ 377 378 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source 379 * @{ 380 */ 381 #define RCC_RNGCLKSOURCE_HSI48 0x00000000U 382 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 383 /** 384 * @} 385 */ 386 387 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source 388 * @{ 389 */ 390 #define RCC_USBCLKSOURCE_HSI48 0x00000000U 391 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 392 /** 393 * @} 394 */ 395 396 /** @defgroup RCCEx_ADC12_Clock_Source ADC12 Clock Source 397 * @{ 398 */ 399 #define RCC_ADC12CLKSOURCE_NONE 0x00000000U 400 #define RCC_ADC12CLKSOURCE_PLL RCC_CCIPR_ADC12SEL_0 401 #define RCC_ADC12CLKSOURCE_SYSCLK RCC_CCIPR_ADC12SEL_1 402 /** 403 * @} 404 */ 405 406 #if defined(ADC345_COMMON) 407 /** @defgroup RCCEx_ADC345_Clock_Source ADC345 Clock Source 408 * @{ 409 */ 410 #define RCC_ADC345CLKSOURCE_NONE 0x00000000U 411 #define RCC_ADC345CLKSOURCE_PLL RCC_CCIPR_ADC345SEL_0 412 #define RCC_ADC345CLKSOURCE_SYSCLK RCC_CCIPR_ADC345SEL_1 413 /** 414 * @} 415 */ 416 #endif /* ADC345_COMMON */ 417 418 #if defined(I2C4) 419 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source 420 * @{ 421 */ 422 #define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U 423 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 424 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 425 /** 426 * @} 427 */ 428 #endif /* I2C4 */ 429 430 #if defined(QUADSPI) 431 /** @defgroup RCCEx_QSPI_Clock_Source QuadSPI Clock Source 432 * @{ 433 */ 434 #define RCC_QSPICLKSOURCE_SYSCLK 0x00000000U 435 #define RCC_QSPICLKSOURCE_HSI RCC_CCIPR2_QSPISEL_0 436 #define RCC_QSPICLKSOURCE_PLL RCC_CCIPR2_QSPISEL_1 437 /** 438 * @} 439 */ 440 #endif /* QUADSPI */ 441 442 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line 443 * @{ 444 */ 445 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ 446 /** 447 * @} 448 */ 449 450 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status 451 * @{ 452 */ 453 #define RCC_CRS_NONE 0x00000000U 454 #define RCC_CRS_TIMEOUT 0x00000001U 455 #define RCC_CRS_SYNCOK 0x00000002U 456 #define RCC_CRS_SYNCWARN 0x00000004U 457 #define RCC_CRS_SYNCERR 0x00000008U 458 #define RCC_CRS_SYNCMISS 0x00000010U 459 #define RCC_CRS_TRIMOVF 0x00000020U 460 /** 461 * @} 462 */ 463 464 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource 465 * @{ 466 */ 467 #define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ 468 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 469 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 470 /** 471 * @} 472 */ 473 474 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider 475 * @{ 476 */ 477 #define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ 478 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 479 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 480 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 481 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 482 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 483 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 484 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 485 /** 486 * @} 487 */ 488 489 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity 490 * @{ 491 */ 492 #define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ 493 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 494 /** 495 * @} 496 */ 497 498 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault 499 * @{ 500 */ 501 #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds 502 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ 503 /** 504 * @} 505 */ 506 507 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault 508 * @{ 509 */ 510 #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ 511 /** 512 * @} 513 */ 514 515 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault 516 * @{ 517 */ 518 #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. 519 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value 520 corresponds to a higher output frequency */ 521 /** 522 * @} 523 */ 524 525 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection 526 * @{ 527 */ 528 #define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ 529 #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ 530 /** 531 * @} 532 */ 533 534 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources 535 * @{ 536 */ 537 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ 538 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ 539 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ 540 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ 541 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ 542 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ 543 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ 544 545 /** 546 * @} 547 */ 548 549 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags 550 * @{ 551 */ 552 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ 553 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ 554 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ 555 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ 556 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 557 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 558 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 559 560 /** 561 * @} 562 */ 563 564 /** 565 * @} 566 */ 567 568 /* Exported macros -----------------------------------------------------------*/ 569 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 570 * @{ 571 */ 572 573 /** @brief Macro to configure the USART1 clock (USART1CLK). 574 * 575 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. 576 * This parameter can be one of the following values: 577 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 578 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 579 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 580 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 581 * @retval None 582 */ 583 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ 584 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__)) 585 586 /** @brief Macro to get the USART1 clock source. 587 * @retval The clock source can be one of the following values: 588 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock 589 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock 590 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock 591 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock 592 */ 593 #define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)) 594 595 /** @brief Macro to configure the USART2 clock (USART2CLK). 596 * 597 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. 598 * This parameter can be one of the following values: 599 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 600 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 601 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 602 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 603 * @retval None 604 */ 605 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ 606 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__)) 607 608 /** @brief Macro to get the USART2 clock source. 609 * @retval The clock source can be one of the following values: 610 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock 611 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock 612 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock 613 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock 614 */ 615 #define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)) 616 617 /** @brief Macro to configure the USART3 clock (USART3CLK). 618 * 619 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. 620 * This parameter can be one of the following values: 621 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 622 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 623 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 624 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 625 * @retval None 626 */ 627 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ 628 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__)) 629 630 /** @brief Macro to get the USART3 clock source. 631 * @retval The clock source can be one of the following values: 632 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock 633 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock 634 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock 635 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock 636 */ 637 #define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)) 638 639 #if defined(UART4) 640 /** @brief Macro to configure the UART4 clock (UART4CLK). 641 * 642 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. 643 * This parameter can be one of the following values: 644 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 645 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 646 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 647 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 648 * @retval None 649 */ 650 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ 651 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__)) 652 653 /** @brief Macro to get the UART4 clock source. 654 * @retval The clock source can be one of the following values: 655 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock 656 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock 657 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock 658 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock 659 */ 660 #define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)) 661 #endif /* UART4 */ 662 663 #if defined(UART5) 664 665 /** @brief Macro to configure the UART5 clock (UART5CLK). 666 * 667 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. 668 * This parameter can be one of the following values: 669 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 670 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 671 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 672 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 673 * @retval None 674 */ 675 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ 676 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__)) 677 678 /** @brief Macro to get the UART5 clock source. 679 * @retval The clock source can be one of the following values: 680 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock 681 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock 682 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock 683 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock 684 */ 685 #define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)) 686 687 #endif /* UART5 */ 688 689 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). 690 * 691 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 692 * This parameter can be one of the following values: 693 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 694 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 695 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 696 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 697 * @retval None 698 */ 699 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ 700 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__)) 701 702 /** @brief Macro to get the LPUART1 clock source. 703 * @retval The clock source can be one of the following values: 704 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 705 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock 706 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock 707 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock 708 */ 709 #define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)) 710 711 /** @brief Macro to configure the I2C1 clock (I2C1CLK). 712 * 713 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. 714 * This parameter can be one of the following values: 715 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 716 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 717 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 718 * @retval None 719 */ 720 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ 721 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__)) 722 723 /** @brief Macro to get the I2C1 clock source. 724 * @retval The clock source can be one of the following values: 725 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock 726 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock 727 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock 728 */ 729 #define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)) 730 731 732 /** @brief Macro to configure the I2C2 clock (I2C2CLK). 733 * 734 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. 735 * This parameter can be one of the following values: 736 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 737 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 738 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 739 * @retval None 740 */ 741 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ 742 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__)) 743 744 /** @brief Macro to get the I2C2 clock source. 745 * @retval The clock source can be one of the following values: 746 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock 747 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock 748 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock 749 */ 750 #define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)) 751 752 /** @brief Macro to configure the I2C3 clock (I2C3CLK). 753 * 754 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. 755 * This parameter can be one of the following values: 756 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 757 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 758 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 759 * @retval None 760 */ 761 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ 762 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__)) 763 764 /** @brief Macro to get the I2C3 clock source. 765 * @retval The clock source can be one of the following values: 766 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock 767 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock 768 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock 769 */ 770 #define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)) 771 772 #if defined(I2C4) 773 774 /** @brief Macro to configure the I2C4 clock (I2C4CLK). 775 * 776 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. 777 * This parameter can be one of the following values: 778 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 779 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 780 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 781 * @retval None 782 */ 783 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ 784 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__)) 785 786 /** @brief Macro to get the I2C4 clock source. 787 * @retval The clock source can be one of the following values: 788 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock 789 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock 790 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock 791 */ 792 #define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)) 793 794 #endif /* I2C4 */ 795 796 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). 797 * 798 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. 799 * This parameter can be one of the following values: 800 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock 801 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock 802 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock 803 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock 804 * @retval None 805 */ 806 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ 807 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__)) 808 809 /** @brief Macro to get the LPTIM1 clock source. 810 * @retval The clock source can be one of the following values: 811 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock 812 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock 813 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock 814 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock 815 */ 816 #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)) 817 818 /** 819 * @brief Macro to configure the SAI1 clock source. 820 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived 821 * from the HSI, system PLL, System Clock or external clock. 822 * This parameter can be one of the following values: 823 * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock 824 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock 825 * @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT 826 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI 827 * 828 * @retval None 829 */ 830 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ 831 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__)) 832 833 /** @brief Macro to get the SAI1 clock source. 834 * @retval The clock source can be one of the following values: 835 * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock 836 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock 837 * @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT 838 * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI 839 * 840 */ 841 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) 842 843 /** 844 * @brief Macro to configure the I2S clock source. 845 * @param __I2S_CLKSOURCE__ defines the I2S clock source. This clock is derived 846 * from the HSI, system PLL, System Clock or external clock. 847 * This parameter can be one of the following values: 848 * @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock 849 * @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock 850 * @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT 851 * @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI 852 * 853 * @retval None 854 */ 855 #define __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__)\ 856 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, (__I2S_CLKSOURCE__)) 857 858 /** @brief Macro to get the I2S clock source. 859 * @retval The clock source can be one of the following values: 860 * @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock 861 * @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock 862 * @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT 863 * @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI 864 * 865 */ 866 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S23SEL))) 867 868 #if defined(FDCAN1) 869 /** 870 * @brief Macro to configure the FDCAN clock source. 871 * @param __FDCAN_CLKSOURCE__ defines the FDCAN clock source. This clock is derived 872 * from the HSE, system PLL or PCLK1. 873 * This parameter can be one of the following values: 874 * @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE 875 * @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock 876 * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1 877 * 878 * @retval None 879 */ 880 #define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__)\ 881 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) 882 883 /** @brief Macro to get the FDCAN clock source. 884 * @retval The clock source can be one of the following values: 885 * @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE 886 * @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock 887 * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1 888 * 889 */ 890 #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_FDCANSEL))) 891 #endif /* FDCAN1 */ 892 893 /** @brief Macro to configure the RNG clock. 894 * 895 * @note USB and RNG peripherals share the same 48MHz clock source. 896 * 897 * @param __RNG_CLKSOURCE__ specifies the RNG clock source. 898 * This parameter can be one of the following values: 899 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for devices with HSI48 900 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock 901 * @retval None 902 */ 903 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ 904 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__)) 905 906 /** @brief Macro to get the RNG clock. 907 * @retval The clock source can be one of the following values: 908 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for devices with HSI48 909 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock selected as RNG clock 910 */ 911 #define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) 912 913 #if defined(USB) 914 915 /** @brief Macro to configure the USB clock (USBCLK). 916 * 917 * @note USB, RNG peripherals share the same 48MHz clock source. 918 * 919 * @param __USB_CLKSOURCE__ specifies the USB clock source. 920 * This parameter can be one of the following values: 921 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 922 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 923 * @retval None 924 */ 925 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ 926 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__)) 927 928 /** @brief Macro to get the USB clock source. 929 * @retval The clock source can be one of the following values: 930 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 931 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock 932 */ 933 #define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) 934 935 #endif /* USB */ 936 937 /** @brief Macro to configure the ADC12 interface clock. 938 * @param __ADC12_CLKSOURCE__ specifies the ADC12 digital interface clock source. 939 * This parameter can be one of the following values: 940 * @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12 clock 941 * @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12 clock 942 * @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as ADC12 clock 943 * @retval None 944 */ 945 #define __HAL_RCC_ADC12_CONFIG(__ADC12_CLKSOURCE__) \ 946 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC12SEL, (__ADC12_CLKSOURCE__)) 947 948 /** @brief Macro to get the ADC12 clock source. 949 * @retval The clock source can be one of the following values: 950 * @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12 clock 951 * @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12 clock 952 * @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as ADC12 clock 953 */ 954 #define __HAL_RCC_GET_ADC12_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC12SEL)) 955 956 #if defined(ADC345_COMMON) 957 /** @brief Macro to configure the ADC345 interface clock. 958 * @param __ADC345_CLKSOURCE__ specifies the ADC345 digital interface clock source. 959 * This parameter can be one of the following values: 960 * @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345 clock 961 * @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345 clock 962 * @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as ADC345 clock 963 * @retval None 964 */ 965 #define __HAL_RCC_ADC345_CONFIG(__ADC345_CLKSOURCE__) \ 966 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC345SEL, __ADC345_CLKSOURCE__) 967 968 /** @brief Macro to get the ADC345 clock source. 969 * @retval The clock source can be one of the following values: 970 * @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345 clock 971 * @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345 clock 972 * @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as ADC345 clock 973 */ 974 #define __HAL_RCC_GET_ADC345_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC345SEL)) 975 #endif /* ADC345_COMMON */ 976 977 #if defined(QUADSPI) 978 979 /** @brief Macro to configure the QuadSPI clock. 980 * @param __QSPI_CLKSOURCE__ specifies the QuadSPI clock source. 981 * This parameter can be one of the following values: 982 * @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as QuadSPI clock 983 * @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI clock 984 * @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected as QuadSPI clock 985 * @retval None 986 */ 987 #define __HAL_RCC_QSPI_CONFIG(__QSPI_CLKSOURCE__) \ 988 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, __QSPI_CLKSOURCE__) 989 990 /** @brief Macro to get the QuadSPI clock source. 991 * @retval The clock source can be one of the following values: 992 * @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as QuadSPI clock 993 * @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI clock 994 * @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected as QuadSPI clock 995 */ 996 #define __HAL_RCC_GET_QSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_QSPISEL)) 997 998 #endif /* QUADSPI */ 999 1000 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management 1001 * @brief macros to manage the specified RCC Flags and interrupts. 1002 * @{ 1003 */ 1004 1005 /** 1006 * @brief Enable the RCC LSE CSS Extended Interrupt Line. 1007 * @retval None 1008 */ 1009 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 1010 1011 /** 1012 * @brief Disable the RCC LSE CSS Extended Interrupt Line. 1013 * @retval None 1014 */ 1015 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) 1016 1017 /** 1018 * @brief Enable the RCC LSE CSS Event Line. 1019 * @retval None. 1020 */ 1021 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 1022 1023 /** 1024 * @brief Disable the RCC LSE CSS Event Line. 1025 * @retval None. 1026 */ 1027 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) 1028 1029 1030 /** 1031 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. 1032 * @retval None. 1033 */ 1034 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 1035 1036 1037 /** 1038 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. 1039 * @retval None. 1040 */ 1041 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) 1042 1043 1044 /** 1045 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. 1046 * @retval None. 1047 */ 1048 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 1049 1050 /** 1051 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. 1052 * @retval None. 1053 */ 1054 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) 1055 1056 /** 1057 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 1058 * @retval None. 1059 */ 1060 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ 1061 do { \ 1062 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ 1063 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ 1064 } while(0) 1065 1066 /** 1067 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. 1068 * @retval None. 1069 */ 1070 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ 1071 do { \ 1072 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ 1073 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ 1074 } while(0) 1075 1076 /** 1077 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. 1078 * @retval EXTI RCC LSE CSS Line Status. 1079 */ 1080 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) 1081 1082 /** 1083 * @brief Clear the RCC LSE CSS EXTI flag. 1084 * @retval None. 1085 */ 1086 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) 1087 1088 /** 1089 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. 1090 * @retval None. 1091 */ 1092 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) 1093 1094 1095 /** 1096 * @brief Enable the specified CRS interrupts. 1097 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. 1098 * This parameter can be any combination of the following values: 1099 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1100 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1101 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1102 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1103 * @retval None 1104 */ 1105 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) 1106 1107 /** 1108 * @brief Disable the specified CRS interrupts. 1109 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. 1110 * This parameter can be any combination of the following values: 1111 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1112 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1113 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1114 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1115 * @retval None 1116 */ 1117 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) 1118 1119 /** @brief Check whether the CRS interrupt has occurred or not. 1120 * @param __INTERRUPT__ specifies the CRS interrupt source to check. 1121 * This parameter can be one of the following values: 1122 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1123 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1124 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1125 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1126 * @retval The new state of __INTERRUPT__ (SET or RESET). 1127 */ 1128 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) 1129 1130 /** @brief Clear the CRS interrupt pending bits 1131 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1132 * This parameter can be any combination of the following values: 1133 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt 1134 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt 1135 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt 1136 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt 1137 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt 1138 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt 1139 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt 1140 */ 1141 /* CRS IT Error Mask */ 1142 #define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) 1143 1144 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ 1145 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ 1146 { \ 1147 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ 1148 } \ 1149 else \ 1150 { \ 1151 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ 1152 } \ 1153 } while(0) 1154 1155 /** 1156 * @brief Check whether the specified CRS flag is set or not. 1157 * @param __FLAG__ specifies the flag to check. 1158 * This parameter can be one of the following values: 1159 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1160 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1161 * @arg @ref RCC_CRS_FLAG_ERR Error 1162 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1163 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1164 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1165 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1166 * @retval The new state of _FLAG_ (TRUE or FALSE). 1167 */ 1168 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) 1169 1170 /** 1171 * @brief Clear the CRS specified FLAG. 1172 * @param __FLAG__ specifies the flag to clear. 1173 * This parameter can be one of the following values: 1174 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK 1175 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning 1176 * @arg @ref RCC_CRS_FLAG_ERR Error 1177 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC 1178 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow 1179 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error 1180 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed 1181 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR 1182 * @retval None 1183 */ 1184 1185 /* CRS Flag Error Mask */ 1186 #define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) 1187 1188 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ 1189 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ 1190 { \ 1191 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ 1192 } \ 1193 else \ 1194 { \ 1195 WRITE_REG(CRS->ICR, (__FLAG__)); \ 1196 } \ 1197 } while(0) 1198 1199 1200 /** 1201 * @} 1202 */ 1203 1204 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features 1205 * @{ 1206 */ 1207 /** 1208 * @brief Enable the oscillator clock for frequency error counter. 1209 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. 1210 * @retval None 1211 */ 1212 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) 1213 1214 /** 1215 * @brief Disable the oscillator clock for frequency error counter. 1216 * @retval None 1217 */ 1218 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) 1219 1220 /** 1221 * @brief Enable the automatic hardware adjustment of TRIM bits. 1222 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. 1223 * @retval None 1224 */ 1225 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1226 1227 /** 1228 * @brief Enable or disable the automatic hardware adjustment of TRIM bits. 1229 * @retval None 1230 */ 1231 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) 1232 1233 /** 1234 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 1235 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency 1236 * of the synchronization source after prescaling. It is then decreased by one in order to 1237 * reach the expected synchronization on the zero value. The formula is the following: 1238 * RELOAD = (fTARGET / fSYNC) -1 1239 * @param __FTARGET__ Target frequency (value in Hz) 1240 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 1241 * @retval None 1242 */ 1243 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 1244 1245 /** 1246 * @} 1247 */ 1248 1249 /** 1250 * @} 1251 */ 1252 1253 /* Exported functions --------------------------------------------------------*/ 1254 /** @addtogroup RCCEx_Exported_Functions 1255 * @{ 1256 */ 1257 1258 /** @addtogroup RCCEx_Exported_Functions_Group1 1259 * @{ 1260 */ 1261 1262 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1263 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1264 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 1265 1266 /** 1267 * @} 1268 */ 1269 1270 /** @addtogroup RCCEx_Exported_Functions_Group2 1271 * @{ 1272 */ 1273 1274 void HAL_RCCEx_EnableLSECSS(void); 1275 void HAL_RCCEx_DisableLSECSS(void); 1276 void HAL_RCCEx_EnableLSECSS_IT(void); 1277 void HAL_RCCEx_LSECSS_IRQHandler(void); 1278 void HAL_RCCEx_LSECSS_Callback(void); 1279 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); 1280 void HAL_RCCEx_DisableLSCO(void); 1281 1282 /** 1283 * @} 1284 */ 1285 1286 /** @addtogroup RCCEx_Exported_Functions_Group3 1287 * @{ 1288 */ 1289 1290 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); 1291 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); 1292 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); 1293 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); 1294 void HAL_RCCEx_CRS_IRQHandler(void); 1295 void HAL_RCCEx_CRS_SyncOkCallback(void); 1296 void HAL_RCCEx_CRS_SyncWarnCallback(void); 1297 void HAL_RCCEx_CRS_ExpectedSyncCallback(void); 1298 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); 1299 1300 /** 1301 * @} 1302 */ 1303 1304 /** 1305 * @} 1306 */ 1307 1308 /* Private macros ------------------------------------------------------------*/ 1309 /** @addtogroup RCCEx_Private_Macros 1310 * @{ 1311 */ 1312 1313 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 1314 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 1315 1316 #if defined(STM32G474xx) || defined(STM32G484xx) 1317 1318 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1319 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1320 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1321 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1322 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 1323 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 1324 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1325 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1326 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1327 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1328 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 1329 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1330 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1331 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1332 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1333 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1334 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1335 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1336 (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ 1337 (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ 1338 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1339 #elif defined(STM32G491xx) || defined(STM32G4A1xx) 1340 1341 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1342 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1343 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1344 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1345 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 1346 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 1347 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1348 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1349 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1350 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1351 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1352 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1353 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1354 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1355 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1356 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1357 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1358 (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ 1359 (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ 1360 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1361 #elif defined(STM32G473xx) || defined(STM32G483xx) 1362 1363 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1364 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1365 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1366 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1367 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 1368 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 1369 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1370 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1371 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1372 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1373 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 1374 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1375 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1376 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1377 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1378 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1379 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1380 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1381 (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ 1382 (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ 1383 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1384 1385 #elif defined(STM32G471xx) 1386 1387 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1388 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1389 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1390 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1391 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 1392 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ 1393 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1394 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1395 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1396 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1397 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ 1398 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1399 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1400 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1401 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1402 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1403 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1404 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1405 1406 #elif defined(STM32G431xx) || defined(STM32G441xx) 1407 1408 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1409 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1410 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1411 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1412 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ 1413 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1414 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1415 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1416 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1417 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1418 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1419 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1420 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1421 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1422 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1423 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1424 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1425 1426 #elif defined(STM32GBK1CB) 1427 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 1428 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ 1429 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ 1430 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ 1431 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ 1432 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ 1433 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ 1434 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ 1435 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ 1436 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ 1437 (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ 1438 (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ 1439 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ 1440 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ 1441 (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ 1442 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) 1443 1444 #endif /* STM32G474xx || STM32G484xx */ 1445 1446 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ 1447 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ 1448 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ 1449 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ 1450 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) 1451 1452 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ 1453 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ 1454 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ 1455 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ 1456 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) 1457 1458 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ 1459 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ 1460 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ 1461 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ 1462 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) 1463 1464 #if defined(UART4) 1465 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ 1466 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ 1467 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ 1468 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ 1469 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) 1470 #endif /* UART4 */ 1471 1472 #if defined(UART5) 1473 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ 1474 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ 1475 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ 1476 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ 1477 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) 1478 1479 #endif /* UART5 */ 1480 1481 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ 1482 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ 1483 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ 1484 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ 1485 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) 1486 1487 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ 1488 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ 1489 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ 1490 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) 1491 1492 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ 1493 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ 1494 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ 1495 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) 1496 1497 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ 1498 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ 1499 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ 1500 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) 1501 1502 #if defined(I2C4) 1503 1504 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ 1505 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ 1506 ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ 1507 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) 1508 1509 #endif /* I2C4 */ 1510 1511 #define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \ 1512 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ 1513 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ 1514 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ 1515 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) 1516 1517 #define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \ 1518 (((__SOURCE__) == RCC_SAI1CLKSOURCE_SYSCLK) || \ 1519 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ 1520 ((__SOURCE__) == RCC_SAI1CLKSOURCE_EXT) || \ 1521 ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) 1522 1523 #define IS_RCC_I2SCLKSOURCE(__SOURCE__) \ 1524 (((__SOURCE__) == RCC_I2SCLKSOURCE_SYSCLK) || \ 1525 ((__SOURCE__) == RCC_I2SCLKSOURCE_PLL) || \ 1526 ((__SOURCE__) == RCC_I2SCLKSOURCE_EXT) || \ 1527 ((__SOURCE__) == RCC_I2SCLKSOURCE_HSI)) 1528 1529 #if defined(FDCAN1) 1530 #define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \ 1531 (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ 1532 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \ 1533 ((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1)) 1534 1535 #endif /* FDCAN1 */ 1536 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ 1537 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ 1538 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)) 1539 1540 #if defined(USB) 1541 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ 1542 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ 1543 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)) 1544 1545 #endif /* USB */ 1546 1547 #define IS_RCC_ADC12CLKSOURCE(__SOURCE__) \ 1548 (((__SOURCE__) == RCC_ADC12CLKSOURCE_NONE) || \ 1549 ((__SOURCE__) == RCC_ADC12CLKSOURCE_PLL) || \ 1550 ((__SOURCE__) == RCC_ADC12CLKSOURCE_SYSCLK)) 1551 1552 #if defined(ADC345_COMMON) 1553 #define IS_RCC_ADC345CLKSOURCE(__SOURCE__) \ 1554 (((__SOURCE__) == RCC_ADC345CLKSOURCE_NONE) || \ 1555 ((__SOURCE__) == RCC_ADC345CLKSOURCE_PLL) || \ 1556 ((__SOURCE__) == RCC_ADC345CLKSOURCE_SYSCLK)) 1557 #endif /* ADC345_COMMON */ 1558 1559 #if defined(QUADSPI) 1560 1561 #define IS_RCC_QSPICLKSOURCE(__SOURCE__) \ 1562 (((__SOURCE__) == RCC_QSPICLKSOURCE_HSI) || \ 1563 ((__SOURCE__) == RCC_QSPICLKSOURCE_SYSCLK)|| \ 1564 ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL)) 1565 1566 #endif /* QUADSPI */ 1567 1568 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ 1569 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ 1570 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) 1571 1572 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ 1573 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ 1574 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ 1575 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) 1576 1577 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ 1578 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) 1579 1580 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) 1581 1582 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) 1583 1584 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) 1585 1586 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ 1587 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) 1588 1589 /** 1590 * @} 1591 */ 1592 1593 /** 1594 * @} 1595 */ 1596 1597 /** 1598 * @} 1599 */ 1600 1601 #ifdef __cplusplus 1602 } 1603 #endif 1604 1605 #endif /* STM32G4xx_HAL_RCC_EX_H */ 1606 1607
