1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_hal_pwr_ex.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32G4xx_HAL_PWR_EX_H 21 #define STM32G4xx_HAL_PWR_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32g4xx_hal_def.h" 29 30 /** @addtogroup STM32G4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup PWREx 35 * @{ 36 */ 37 38 39 /* Exported types ------------------------------------------------------------*/ 40 41 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types 42 * @{ 43 */ 44 45 46 /** 47 * @brief PWR PVM configuration structure definition 48 */ 49 typedef struct 50 { 51 uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. 52 This parameter can be a value of @ref PWREx_PVM_Type. */ 53 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 54 This parameter can be a value of @ref PWREx_PVM_Mode. */ 55 }PWR_PVMTypeDef; 56 57 /** 58 * @} 59 */ 60 61 /* Exported constants --------------------------------------------------------*/ 62 63 /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants 64 * @{ 65 */ 66 67 /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants 68 * @{ 69 */ 70 #define PWR_WUP_POLARITY_SHIFT 0x05U /*!< Internal constant used to retrieve wakeup pin polariry */ 71 /** 72 * @} 73 */ 74 75 76 /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins 77 * @{ 78 */ 79 #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 80 #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 81 #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 82 #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 83 #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 84 #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ 85 #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ 86 #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ 87 #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ 88 #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ 89 #define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */ 90 #define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */ 91 #define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */ 92 #define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */ 93 #define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */ 94 /** 95 * @} 96 */ 97 98 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type 99 * @{ 100 */ 101 #if defined(PWR_CR2_PVME1) 102 #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */ 103 #endif /* PWR_CR2_PVME1 */ 104 #if defined(PWR_CR2_PVME2) 105 #define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */ 106 #endif /* PWR_CR2_PVME2 */ 107 #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */ 108 #define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */ 109 /** 110 * @} 111 */ 112 113 /** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode 114 * @{ 115 */ 116 #define PWR_PVM_MODE_NORMAL 0x00000000U /*!< basic mode is used */ 117 #define PWR_PVM_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ 118 #define PWR_PVM_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ 119 #define PWR_PVM_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 120 #define PWR_PVM_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ 121 #define PWR_PVM_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ 122 #define PWR_PVM_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ 123 /** 124 * @} 125 */ 126 127 128 129 /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale 130 * @{ 131 */ 132 #if defined(PWR_CR5_R1MODE) 133 #define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST ((uint32_t)0x00000000) /*!< Voltage scaling range 1 boost mode */ 134 #endif /*PWR_CR5_R1MODE */ 135 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 normal mode */ 136 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */ 137 /** 138 * @} 139 */ 140 141 142 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection 143 * @{ 144 */ 145 #define PWR_BATTERY_CHARGING_RESISTOR_5 0x00000000U /*!< VBAT charging through a 5 kOhms resistor */ 146 #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ 147 /** 148 * @} 149 */ 150 151 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging 152 * @{ 153 */ 154 #define PWR_BATTERY_CHARGING_DISABLE 0x00000000U 155 #define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE 156 /** 157 * @} 158 */ 159 160 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode 161 * @{ 162 */ 163 #define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */ 164 #define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */ 165 #define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */ 166 #define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */ 167 #define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */ 168 #define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */ 169 #define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */ 170 #define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */ 171 #define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */ 172 #define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */ 173 #define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */ 174 #define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */ 175 #define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */ 176 #define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 13 */ 177 #define PWR_GPIO_BIT_14 PWR_PDCRA_PA14 /*!< GPIO port I/O pin 14 */ 178 #define PWR_GPIO_BIT_15 PWR_PUCRA_PA15 /*!< GPIO port I/O pin 15 */ 179 /** 180 * @} 181 */ 182 183 /** @defgroup PWREx_GPIO GPIO port 184 * @{ 185 */ 186 #define PWR_GPIO_A 0x00000000U /*!< GPIO port A */ 187 #define PWR_GPIO_B 0x00000001U /*!< GPIO port B */ 188 #define PWR_GPIO_C 0x00000002U /*!< GPIO port C */ 189 #define PWR_GPIO_D 0x00000003U /*!< GPIO port D */ 190 #define PWR_GPIO_E 0x00000004U /*!< GPIO port E */ 191 #define PWR_GPIO_F 0x00000005U /*!< GPIO port F */ 192 #define PWR_GPIO_G 0x00000006U /*!< GPIO port G */ 193 /** 194 * @} 195 */ 196 197 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines 198 * @{ 199 */ 200 #if defined(PWR_CR2_PVME1) 201 #define PWR_EXTI_LINE_PVM1 0x00000008U /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */ 202 #endif /* PWR_CR2_PVME1 */ 203 #if defined(PWR_CR2_PVME2) 204 #define PWR_EXTI_LINE_PVM2 0x00000010U /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */ 205 #endif /* PWR_CR2_PVME2 */ 206 #define PWR_EXTI_LINE_PVM3 0x00000020U /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */ 207 #define PWR_EXTI_LINE_PVM4 0x00000040U /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */ 208 /** 209 * @} 210 */ 211 212 /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines 213 * @{ 214 */ 215 #if defined(PWR_CR2_PVME1) 216 #define PWR_EVENT_LINE_PVM1 0x00000008U /*!< Event line 35 Connected to the PVM1 EXTI Line */ 217 #endif /* PWR_CR2_PVME1 */ 218 #if defined(PWR_CR2_PVME2) 219 #define PWR_EVENT_LINE_PVM2 0x00000010U /*!< Event line 36 Connected to the PVM2 EXTI Line */ 220 #endif /* PWR_CR2_PVME2 */ 221 #define PWR_EVENT_LINE_PVM3 0x00000020U /*!< Event line 37 Connected to the PVM3 EXTI Line */ 222 #define PWR_EVENT_LINE_PVM4 0x00000040U /*!< Event line 38 Connected to the PVM4 EXTI Line */ 223 /** 224 * @} 225 */ 226 227 /** @defgroup PWREx_Flag PWR Status Flags 228 * Elements values convention: 0000 0000 0XXY YYYYb 229 * - Y YYYY : Flag position in the XX register (5 bits) 230 * - XX : Status register (2 bits) 231 * - 01: SR1 register 232 * - 10: SR2 register 233 * The only exception is PWR_FLAG_WU, encompassing all 234 * wake-up flags and set to PWR_SR1_WUF. 235 * @{ 236 */ 237 #define PWR_FLAG_WUF1 0x0020U /*!< Wakeup event on wakeup pin 1 */ 238 #define PWR_FLAG_WUF2 0x0021U /*!< Wakeup event on wakeup pin 2 */ 239 #define PWR_FLAG_WUF3 0x0022U /*!< Wakeup event on wakeup pin 3 */ 240 #define PWR_FLAG_WUF4 0x0023U /*!< Wakeup event on wakeup pin 4 */ 241 #define PWR_FLAG_WUF5 0x0024U /*!< Wakeup event on wakeup pin 5 */ 242 #define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */ 243 #define PWR_FLAG_SB 0x0028U /*!< Standby flag */ 244 #define PWR_FLAG_WUFI 0x002FU /*!< Wakeup on internal wakeup line */ 245 246 #define PWR_FLAG_REGLPS 0x0048U /*!< Low-power regulator start flag */ 247 #define PWR_FLAG_REGLPF 0x0049U /*!< Low-power regulator flag */ 248 #define PWR_FLAG_VOSF 0x004AU /*!< Voltage scaling flag */ 249 #define PWR_FLAG_PVDO 0x004BU /*!< Power Voltage Detector output flag */ 250 #if defined(PWR_CR2_PVME1) 251 #define PWR_FLAG_PVMO1 0x004CU /*!< Power Voltage Monitoring 1 output flag */ 252 #endif /* PWR_CR2_PVME1 */ 253 #if defined(PWR_CR2_PVME2) 254 #define PWR_FLAG_PVMO2 0x004DU /*!< Power Voltage Monitoring 2 output flag */ 255 #endif /* PWR_CR2_PVME2 */ 256 #define PWR_FLAG_PVMO3 0x004EU /*!< Power Voltage Monitoring 3 output flag */ 257 #define PWR_FLAG_PVMO4 0x004FU /*!< Power Voltage Monitoring 4 output flag */ 258 /** 259 * @} 260 */ 261 262 /** 263 * @} 264 */ 265 266 /* Exported macros -----------------------------------------------------------*/ 267 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros 268 * @{ 269 */ 270 271 #if defined(PWR_CR2_PVME1) 272 /** 273 * @brief Enable the PVM1 Extended Interrupt Line. 274 * @retval None 275 */ 276 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) 277 278 /** 279 * @brief Disable the PVM1 Extended Interrupt Line. 280 * @retval None 281 */ 282 #define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) 283 284 /** 285 * @brief Enable the PVM1 Event Line. 286 * @retval None 287 */ 288 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) 289 290 /** 291 * @brief Disable the PVM1 Event Line. 292 * @retval None 293 */ 294 #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) 295 296 /** 297 * @brief Enable the PVM1 Extended Interrupt Rising Trigger. 298 * @retval None 299 */ 300 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) 301 302 /** 303 * @brief Disable the PVM1 Extended Interrupt Rising Trigger. 304 * @retval None 305 */ 306 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) 307 308 /** 309 * @brief Enable the PVM1 Extended Interrupt Falling Trigger. 310 * @retval None 311 */ 312 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) 313 314 315 /** 316 * @brief Disable the PVM1 Extended Interrupt Falling Trigger. 317 * @retval None 318 */ 319 #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) 320 321 322 /** 323 * @brief PVM1 EXTI line configuration: set rising & falling edge trigger. 324 * @retval None 325 */ 326 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ 327 do { \ 328 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \ 329 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \ 330 } while(0) 331 332 /** 333 * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger. 334 * @retval None 335 */ 336 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ 337 do { \ 338 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \ 339 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \ 340 } while(0) 341 342 /** 343 * @brief Generate a Software interrupt on selected EXTI line. 344 * @retval None 345 */ 346 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1) 347 348 /** 349 * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not. 350 * @retval EXTI PVM1 Line Status. 351 */ 352 #define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1) 353 354 /** 355 * @brief Clear the PVM1 EXTI flag. 356 * @retval None 357 */ 358 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1) 359 360 #endif /* PWR_CR2_PVME1 */ 361 362 363 #if defined(PWR_CR2_PVME2) 364 /** 365 * @brief Enable the PVM2 Extended Interrupt Line. 366 * @retval None 367 */ 368 #define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) 369 370 /** 371 * @brief Disable the PVM2 Extended Interrupt Line. 372 * @retval None 373 */ 374 #define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) 375 376 /** 377 * @brief Enable the PVM2 Event Line. 378 * @retval None 379 */ 380 #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) 381 382 /** 383 * @brief Disable the PVM2 Event Line. 384 * @retval None 385 */ 386 #define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) 387 388 /** 389 * @brief Enable the PVM2 Extended Interrupt Rising Trigger. 390 * @retval None 391 */ 392 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) 393 394 /** 395 * @brief Disable the PVM2 Extended Interrupt Rising Trigger. 396 * @retval None 397 */ 398 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) 399 400 /** 401 * @brief Enable the PVM2 Extended Interrupt Falling Trigger. 402 * @retval None 403 */ 404 #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) 405 406 407 /** 408 * @brief Disable the PVM2 Extended Interrupt Falling Trigger. 409 * @retval None 410 */ 411 #define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) 412 413 414 /** 415 * @brief PVM2 EXTI line configuration: set rising & falling edge trigger. 416 * @retval None 417 */ 418 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \ 419 do { \ 420 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \ 421 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \ 422 } while(0) 423 424 /** 425 * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger. 426 * @retval None 427 */ 428 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \ 429 do { \ 430 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \ 431 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \ 432 } while(0) 433 434 /** 435 * @brief Generate a Software interrupt on selected EXTI line. 436 * @retval None 437 */ 438 #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2) 439 440 /** 441 * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not. 442 * @retval EXTI PVM2 Line Status. 443 */ 444 #define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2) 445 446 /** 447 * @brief Clear the PVM2 EXTI flag. 448 * @retval None 449 */ 450 #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2) 451 452 #endif /* PWR_CR2_PVME2 */ 453 454 455 /** 456 * @brief Enable the PVM3 Extended Interrupt Line. 457 * @retval None 458 */ 459 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) 460 461 /** 462 * @brief Disable the PVM3 Extended Interrupt Line. 463 * @retval None 464 */ 465 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) 466 467 /** 468 * @brief Enable the PVM3 Event Line. 469 * @retval None 470 */ 471 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) 472 473 /** 474 * @brief Disable the PVM3 Event Line. 475 * @retval None 476 */ 477 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) 478 479 /** 480 * @brief Enable the PVM3 Extended Interrupt Rising Trigger. 481 * @retval None 482 */ 483 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) 484 485 /** 486 * @brief Disable the PVM3 Extended Interrupt Rising Trigger. 487 * @retval None 488 */ 489 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) 490 491 /** 492 * @brief Enable the PVM3 Extended Interrupt Falling Trigger. 493 * @retval None 494 */ 495 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) 496 497 498 /** 499 * @brief Disable the PVM3 Extended Interrupt Falling Trigger. 500 * @retval None 501 */ 502 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) 503 504 505 /** 506 * @brief PVM3 EXTI line configuration: set rising & falling edge trigger. 507 * @retval None 508 */ 509 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \ 510 do { \ 511 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ 512 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ 513 } while(0) 514 515 /** 516 * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. 517 * @retval None 518 */ 519 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \ 520 do { \ 521 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \ 522 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \ 523 } while(0) 524 525 /** 526 * @brief Generate a Software interrupt on selected EXTI line. 527 * @retval None 528 */ 529 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3) 530 531 /** 532 * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not. 533 * @retval EXTI PVM3 Line Status. 534 */ 535 #define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3) 536 537 /** 538 * @brief Clear the PVM3 EXTI flag. 539 * @retval None 540 */ 541 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3) 542 543 544 545 546 /** 547 * @brief Enable the PVM4 Extended Interrupt Line. 548 * @retval None 549 */ 550 #define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) 551 552 /** 553 * @brief Disable the PVM4 Extended Interrupt Line. 554 * @retval None 555 */ 556 #define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) 557 558 /** 559 * @brief Enable the PVM4 Event Line. 560 * @retval None 561 */ 562 #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) 563 564 /** 565 * @brief Disable the PVM4 Event Line. 566 * @retval None 567 */ 568 #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) 569 570 /** 571 * @brief Enable the PVM4 Extended Interrupt Rising Trigger. 572 * @retval None 573 */ 574 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) 575 576 /** 577 * @brief Disable the PVM4 Extended Interrupt Rising Trigger. 578 * @retval None 579 */ 580 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) 581 582 /** 583 * @brief Enable the PVM4 Extended Interrupt Falling Trigger. 584 * @retval None 585 */ 586 #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) 587 588 589 /** 590 * @brief Disable the PVM4 Extended Interrupt Falling Trigger. 591 * @retval None 592 */ 593 #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) 594 595 596 /** 597 * @brief PVM4 EXTI line configuration: set rising & falling edge trigger. 598 * @retval None 599 */ 600 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \ 601 do { \ 602 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \ 603 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \ 604 } while(0) 605 606 /** 607 * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger. 608 * @retval None 609 */ 610 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \ 611 do { \ 612 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \ 613 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \ 614 } while(0) 615 616 /** 617 * @brief Generate a Software interrupt on selected EXTI line. 618 * @retval None 619 */ 620 #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4) 621 622 /** 623 * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set. 624 * @retval EXTI PVM4 Line Status. 625 */ 626 #define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4) 627 628 /** 629 * @brief Clear the PVM4 EXTI flag. 630 * @retval None 631 */ 632 #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4) 633 634 635 /** 636 * @brief Configure the main internal regulator output voltage. 637 * @param __REGULATOR__: specifies the regulator output voltage to achieve 638 * a tradeoff between performance and power consumption. 639 * This parameter can be one of the following values: 640 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST Regulator voltage output range 1 mode, 641 * typical output voltage at 1.28 V, 642 * system frequency up to 170 MHz. 643 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, 644 * typical output voltage at 1.2 V, 645 * system frequency up to 150 MHz. 646 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, 647 * typical output voltage at 1.0 V, 648 * system frequency up to 26 MHz. 649 * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check 650 * whether or not VOSF flag is cleared when moving from range 2 to range 1. User 651 * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. 652 * @retval None 653 */ 654 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ 655 __IO uint32_t tmpreg; \ 656 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ 657 /* Delay after an RCC peripheral clock enabling */ \ 658 tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ 659 UNUSED(tmpreg); \ 660 } while(0) 661 662 /** 663 * @} 664 */ 665 666 /* Private macros --------------------------------------------------------*/ 667 /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros 668 * @{ 669 */ 670 671 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ 672 ((PIN) == PWR_WAKEUP_PIN2) || \ 673 ((PIN) == PWR_WAKEUP_PIN3) || \ 674 ((PIN) == PWR_WAKEUP_PIN4) || \ 675 ((PIN) == PWR_WAKEUP_PIN5) || \ 676 ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ 677 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ 678 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ 679 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ 680 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ 681 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ 682 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ 683 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ 684 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ 685 ((PIN) == PWR_WAKEUP_PIN5_LOW)) 686 687 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ 688 ((TYPE) == PWR_PVM_2) ||\ 689 ((TYPE) == PWR_PVM_3) ||\ 690 ((TYPE) == PWR_PVM_4)) 691 692 #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ 693 ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ 694 ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ 695 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ 696 ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ 697 ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ 698 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) 699 700 #if defined(PWR_CR5_R1MODE) 701 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \ 702 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 703 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) 704 #else 705 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 706 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) 707 #endif 708 709 710 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ 711 ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) 712 713 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ 714 ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) 715 716 #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00U) 717 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ 718 ((GPIO) == PWR_GPIO_B) ||\ 719 ((GPIO) == PWR_GPIO_C) ||\ 720 ((GPIO) == PWR_GPIO_D) ||\ 721 ((GPIO) == PWR_GPIO_E) ||\ 722 ((GPIO) == PWR_GPIO_F) ||\ 723 ((GPIO) == PWR_GPIO_G)) 724 725 726 /** 727 * @} 728 */ 729 730 731 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions 732 * @{ 733 */ 734 735 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions 736 * @{ 737 */ 738 739 740 /* Peripheral Control functions **********************************************/ 741 uint32_t HAL_PWREx_GetVoltageRange(void); 742 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); 743 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); 744 void HAL_PWREx_DisableBatteryCharging(void); 745 void HAL_PWREx_EnableInternalWakeUpLine(void); 746 void HAL_PWREx_DisableInternalWakeUpLine(void); 747 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 748 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); 749 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 750 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); 751 void HAL_PWREx_EnablePullUpPullDownConfig(void); 752 void HAL_PWREx_DisablePullUpPullDownConfig(void); 753 void HAL_PWREx_EnableSRAM2ContentRetention(void); 754 void HAL_PWREx_DisableSRAM2ContentRetention(void); 755 #if defined(PWR_CR2_PVME1) 756 void HAL_PWREx_EnablePVM1(void); 757 void HAL_PWREx_DisablePVM1(void); 758 #endif /* PWR_CR2_PVME1 */ 759 #if defined(PWR_CR2_PVME2) 760 void HAL_PWREx_EnablePVM2(void); 761 void HAL_PWREx_DisablePVM2(void); 762 #endif /* PWR_CR2_PVME2 */ 763 void HAL_PWREx_EnablePVM3(void); 764 void HAL_PWREx_DisablePVM3(void); 765 void HAL_PWREx_EnablePVM4(void); 766 void HAL_PWREx_DisablePVM4(void); 767 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); 768 769 /* Low Power modes configuration functions ************************************/ 770 void HAL_PWREx_EnableLowPowerRunMode(void); 771 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); 772 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry); 773 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); 774 void HAL_PWREx_EnterSHUTDOWNMode(void); 775 776 void HAL_PWREx_PVD_PVM_IRQHandler(void); 777 #if defined(PWR_CR2_PVME1) 778 void HAL_PWREx_PVM1Callback(void); 779 #endif /* PWR_CR2_PVME1 */ 780 #if defined(PWR_CR2_PVME2) 781 void HAL_PWREx_PVM2Callback(void); 782 #endif /* PWR_CR2_PVME2 */ 783 void HAL_PWREx_PVM3Callback(void); 784 void HAL_PWREx_PVM4Callback(void); 785 786 #if defined(PWR_CR3_UCPD_STDBY) 787 void HAL_PWREx_EnableUCPDStandbyMode(void); 788 void HAL_PWREx_DisableUCPDStandbyMode(void); 789 #endif /* PWR_CR3_UCPD_STDBY */ 790 #if defined(PWR_CR3_UCPD_DBDIS) 791 void HAL_PWREx_EnableUCPDDeadBattery(void); 792 void HAL_PWREx_DisableUCPDDeadBattery(void); 793 #endif /* PWR_CR3_UCPD_DBDIS */ 794 795 /** 796 * @} 797 */ 798 799 /** 800 * @} 801 */ 802 803 /** 804 * @} 805 */ 806 807 /** 808 * @} 809 */ 810 811 #ifdef __cplusplus 812 } 813 #endif 814 815 816 #endif /* STM32G4xx_HAL_PWR_EX_H */ 817 818
