1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_hal_hrtim.h 4 * @author MCD Application Team 5 * @brief Header file of HRTIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32G4xx_HAL_HRTIM_H 21 #define STM32G4xx_HAL_HRTIM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32g4xx_hal_def.h" 29 30 #if defined(HRTIM1) 31 /** @addtogroup STM32G4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup HRTIM HRTIM 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants 41 * @{ 42 */ 43 /** @defgroup HRTIM_Max_Timer HRTIM Max Timer 44 * @{ 45 */ 46 #define MAX_HRTIM_TIMER 7U 47 /** 48 * @} 49 */ 50 /** 51 * @} 52 */ 53 54 /** @defgroup HRTIM_Exported_Types HRTIM Exported Types 55 * @{ 56 */ 57 58 /** 59 * @brief HRTIM Configuration Structure definition - Time base related parameters 60 */ 61 typedef struct 62 { 63 uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance. 64 This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */ 65 uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals. 66 The HRTIM instance can be configured to act as a slave (waiting for a trigger 67 to be synchronized) or a master (generating a synchronization signal) or both. 68 This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/ 69 uint32_t SyncInputSource; /*!< Specifies the external synchronization input source (significant only when 70 the HRTIM instance is configured as a slave). 71 This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */ 72 uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs 73 (significant only when the HRTIM instance is configured as a master). 74 This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */ 75 uint32_t SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization 76 outputs (significant only when the HRTIM instance is configured as a master). 77 This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */ 78 } HRTIM_InitTypeDef; 79 80 /** 81 * @brief HAL State structures definition 82 */ 83 typedef enum 84 { 85 HAL_HRTIM_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ 86 HAL_HRTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 87 HAL_HRTIM_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ 88 HAL_HRTIM_STATE_TIMEOUT = 0x06U, /*!< Timeout state */ 89 HAL_HRTIM_STATE_ERROR = 0x07U, /*!< Error state */ 90 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 91 HAL_HRTIM_STATE_INVALID_CALLBACK = 0x08U /*!< Invalid Callback error */ 92 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 93 } HAL_HRTIM_StateTypeDef; 94 95 /** 96 * @brief HRTIM Timer Structure definition 97 */ 98 typedef struct 99 { 100 uint32_t CaptureTrigger1; /*!< Event(s) triggering capture unit 1. 101 When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels. 102 When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */ 103 uint32_t CaptureTrigger2; /*!< Event(s) triggering capture unit 2. 104 When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels. 105 When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */ 106 uint32_t InterruptRequests; /*!< Interrupts requests enabled for the timer. */ 107 uint32_t DMARequests; /*!< DMA requests enabled for the timer. */ 108 uint32_t DMASrcAddress; /*!< Address of the source address of the DMA transfer. */ 109 uint32_t DMADstAddress; /*!< Address of the destination address of the DMA transfer. */ 110 uint32_t DMASize; /*!< Size of the DMA transfer */ 111 } HRTIM_TimerParamTypeDef; 112 113 /** 114 * @brief HRTIM Handle Structure definition 115 */ 116 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 117 typedef struct __HRTIM_HandleTypeDef 118 #else 119 typedef struct 120 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 121 { 122 HRTIM_TypeDef * Instance; /*!< Register base address */ 123 124 HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */ 125 126 HRTIM_TimerParamTypeDef TimerParam[MAX_HRTIM_TIMER]; /*!< HRTIM timers - including the master - parameters */ 127 128 HAL_LockTypeDef Lock; /*!< Locking object */ 129 130 __IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */ 131 132 DMA_HandleTypeDef * hdmaMaster; /*!< Master timer DMA handle parameters */ 133 DMA_HandleTypeDef * hdmaTimerA; /*!< Timer A DMA handle parameters */ 134 DMA_HandleTypeDef * hdmaTimerB; /*!< Timer B DMA handle parameters */ 135 DMA_HandleTypeDef * hdmaTimerC; /*!< Timer C DMA handle parameters */ 136 DMA_HandleTypeDef * hdmaTimerD; /*!< Timer D DMA handle parameters */ 137 DMA_HandleTypeDef * hdmaTimerE; /*!< Timer E DMA handle parameters */ 138 DMA_HandleTypeDef * hdmaTimerF; /*!< Timer F DMA handle parameters */ 139 140 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 141 void (* Fault1Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 1 interrupt callback function pointer */ 142 void (* Fault2Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 2 interrupt callback function pointer */ 143 void (* Fault3Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 3 interrupt callback function pointer */ 144 void (* Fault4Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 4 interrupt callback function pointer */ 145 void (* Fault5Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 5 interrupt callback function pointer */ 146 void (* Fault6Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 6 interrupt callback function pointer */ 147 void (* SystemFaultCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< System fault interrupt callback function pointer */ 148 void (* DLLCalibrationReadyCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< DLL Ready interrupt callback function pointer */ 149 void (* BurstModePeriodCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Burst mode period interrupt callback function pointer */ 150 void (* SynchronizationEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Sync Input interrupt callback function pointer */ 151 void (* ErrorCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< DMA error callback function pointer */ 152 153 void (* RegistersUpdateCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Update interrupt callback function pointer */ 154 void (* RepetitionEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Repetition interrupt callback function pointer */ 155 void (* Compare1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 1 match interrupt callback function pointer */ 156 void (* Compare2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 2 match interrupt callback function pointer */ 157 void (* Compare3EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 3 match interrupt callback function pointer */ 158 void (* Compare4EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 4 match interrupt callback function pointer */ 159 void (* Capture1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Capture 1 interrupts callback function pointer */ 160 void (* Capture2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Capture 2 interrupts callback function pointer */ 161 void (* DelayedProtectionCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Delayed protection interrupt callback function pointer */ 162 void (* CounterResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x counter reset/roll-over interrupt callback function pointer */ 163 void (* Output1SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 1 set interrupt callback function pointer */ 164 void (* Output1ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 1 reset interrupt callback function pointer */ 165 void (* Output2SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 2 set interrupt callback function pointer */ 166 void (* Output2ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 2 reset interrupt callback function pointer */ 167 void (* BurstDMATransferCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Burst DMA completed interrupt callback function pointer */ 168 169 void (* MspInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< HRTIM MspInit callback function pointer */ 170 void (* MspDeInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< HRTIM MspInit callback function pointer */ 171 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 172 } HRTIM_HandleTypeDef; 173 174 /** 175 * @brief Simple output compare mode configuration definition 176 */ 177 typedef struct 178 { 179 uint32_t Period; /*!< Specifies the timer period. 180 The period value must be above 3 periods of the fHRTIM clock. 181 Maximum value is = 0xFFDFU */ 182 uint32_t RepetitionCounter; /*!< Specifies the timer repetition period. 183 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ 184 uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio. 185 This parameter can be any value of @ref HRTIM_Prescaler_Ratio */ 186 uint32_t Mode; /*!< Specifies the counter operating mode. 187 This parameter can be any value of @ref HRTIM_Counter_Operating_Mode */ 188 } HRTIM_TimeBaseCfgTypeDef; 189 190 /** 191 * @brief Simple output compare mode configuration definition 192 */ 193 typedef struct 194 { 195 uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive). 196 This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */ 197 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register. 198 The compare value must be above or equal to 3 periods of the fHRTIM clock */ 199 uint32_t Polarity; /*!< Specifies the output polarity. 200 This parameter can be any value of @ref HRTIM_Output_Polarity */ 201 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 202 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 203 } HRTIM_SimpleOCChannelCfgTypeDef; 204 205 /** 206 * @brief Simple PWM output mode configuration definition 207 */ 208 typedef struct 209 { 210 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register. 211 The compare value must be above or equal to 3 periods of the fHRTIM clock */ 212 uint32_t Polarity; /*!< Specifies the output polarity. 213 This parameter can be any value of @ref HRTIM_Output_Polarity */ 214 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 215 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 216 } HRTIM_SimplePWMChannelCfgTypeDef; 217 218 /** 219 * @brief Simple capture mode configuration definition 220 */ 221 typedef struct 222 { 223 uint32_t Event; /*!< Specifies the external event triggering the capture. 224 This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */ 225 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity). 226 This parameter can be a value of @ref HRTIM_External_Event_Polarity */ 227 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event. 228 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */ 229 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter. 230 This parameter can be a value of @ref HRTIM_External_Event_Filter */ 231 } HRTIM_SimpleCaptureChannelCfgTypeDef; 232 233 /** 234 * @brief Simple One Pulse mode configuration definition 235 */ 236 typedef struct 237 { 238 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register. 239 The compare value must be above or equal to 3 periods of the fHRTIM clock */ 240 uint32_t OutputPolarity; /*!< Specifies the output polarity. 241 This parameter can be any value of @ref HRTIM_Output_Polarity */ 242 uint32_t OutputIdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 243 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 244 uint32_t Event; /*!< Specifies the external event triggering the pulse generation. 245 This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */ 246 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity). 247 This parameter can be a value of @ref HRTIM_External_Event_Polarity */ 248 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event. 249 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */ 250 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter. 251 This parameter can be a value of @ref HRTIM_External_Event_Filter */ 252 } HRTIM_SimpleOnePulseChannelCfgTypeDef; 253 254 /** 255 * @brief Timer configuration definition 256 */ 257 typedef struct 258 { 259 uint32_t InterruptRequests; /*!< Relevant for all HRTIM timers, including the master. 260 Specifies which interrupts requests must enabled for the timer. 261 This parameter can be any combination of @ref HRTIM_Master_Interrupt_Enable 262 or @ref HRTIM_Timing_Unit_Interrupt_Enable */ 263 uint32_t DMARequests; /*!< Relevant for all HRTIM timers, including the master. 264 Specifies which DMA requests must be enabled for the timer. 265 This parameter can be any combination of @ref HRTIM_Master_DMA_Request_Enable 266 or @ref HRTIM_Timing_Unit_DMA_Request_Enable */ 267 uint32_t DMASrcAddress; /*!< Relevant for all HRTIM timers, including the master. 268 Specifies the address of the source address of the DMA transfer */ 269 uint32_t DMADstAddress; /*!< Relevant for all HRTIM timers, including the master. 270 Specifies the address of the destination address of the DMA transfer */ 271 uint32_t DMASize; /*!< Relevant for all HRTIM timers, including the master. 272 Specifies the size of the DMA transfer */ 273 uint32_t HalfModeEnable; /*!< Relevant for all HRTIM timers, including the master. 274 Specifies whether or not half mode is enabled 275 This parameter can be any value of @ref HRTIM_Half_Mode_Enable */ 276 uint32_t InterleavedMode; /*!< Relevant for all HRTIM timers, including the master. 277 Specifies whether or not half mode is enabled 278 This parameter can be any value of @ref HRTIM_Interleaved_Mode */ 279 uint32_t StartOnSync; /*!< Relevant for all HRTIM timers, including the master. 280 Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled). 281 This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event */ 282 uint32_t ResetOnSync; /*!< Relevant for all HRTIM timers, including the master. 283 Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled). 284 This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event */ 285 uint32_t DACSynchro; /*!< Relevant for all HRTIM timers, including the master. 286 Indicates whether or not the a DAC synchronization event is generated. 287 This parameter can be any value of @ref HRTIM_DAC_Synchronization */ 288 uint32_t PreloadEnable; /*!< Relevant for all HRTIM timers, including the master. 289 Specifies whether or not register preload is enabled. 290 This parameter can be any value of @ref HRTIM_Register_Preload_Enable */ 291 uint32_t UpdateGating; /*!< Relevant for all HRTIM timers, including the master. 292 Specifies how the update occurs with respect to a burst DMA transaction or 293 update enable inputs (Slave timers only). 294 This parameter can be any value of @ref HRTIM_Update_Gating */ 295 uint32_t BurstMode; /*!< Relevant for all HRTIM timers, including the master. 296 Specifies how the timer behaves during a burst mode operation. 297 This parameter can be any value of @ref HRTIM_Timer_Burst_Mode */ 298 uint32_t RepetitionUpdate; /*!< Relevant for all HRTIM timers, including the master. 299 Specifies whether or not registers update is triggered by the repetition event. 300 This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */ 301 uint32_t PushPull; /*!< Relevant for Timer A to Timer F. 302 Specifies whether or not the push-pull mode is enabled. 303 This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */ 304 uint32_t FaultEnable; /*!< Relevant for Timer A to Timer F. 305 Specifies which fault channels are enabled for the timer. 306 This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling */ 307 uint32_t FaultLock; /*!< Relevant for Timer A to Timer F. 308 Specifies whether or not fault enabling status is write protected. 309 This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */ 310 uint32_t DeadTimeInsertion; /*!< Relevant for Timer A to Timer F. 311 Specifies whether or not dead-time insertion is enabled for the timer. 312 This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */ 313 uint32_t DelayedProtectionMode; /*!< Relevant for Timer A to Timer F. 314 Specifies the delayed protection mode. 315 This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */ 316 uint32_t BalancedIdleAutomaticResume; /*!< Indicates whether or not outputs are automatically re-enabled after a balanced idle event. 317 This parameters can be any value of @ref HRTIM_Output_Balanced_Idle_Auto_Resume */ 318 uint32_t UpdateTrigger; /*!< Relevant for Timer A to Timer F. 319 Specifies source(s) triggering the timer registers update. 320 This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */ 321 uint32_t ResetTrigger; /*!< Relevant for Timer A to Timer F. 322 Specifies source(s) triggering the timer counter reset. 323 This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */ 324 uint32_t ResetUpdate; /*!< Relevant for Timer A to Timer F. 325 Specifies whether or not registers update is triggered when the timer counter is reset. 326 This parameter can be a value of @ref HRTIM_Timer_Reset_Update */ 327 uint32_t ReSyncUpdate; /*!< Relevant for Timer A to Timer F. 328 Specifies whether update source is coming from the timing unit @ref HRTIM_Timer_ReSyncUpdate */ 329 330 } HRTIM_TimerCfgTypeDef; 331 332 /** 333 * @brief Timer control definition 334 */ 335 typedef struct 336 { 337 uint32_t UpDownMode; /*!< Relevant for Timer A to Timer F. 338 Specifies whether or not counter is operating in up or up-down counting mode. 339 This parameter can be a value of @ref HRTIM_Timer_UpDown_Mode */ 340 uint32_t TrigHalf; /*!< Relevant for Timer A to Timer F. 341 Specifies whether or not compare 2 is operating in Trigger half mode. 342 This parameter can be a value of @ref HRTIM_Timer_TrigHalf_Mode */ 343 uint32_t GreaterCMP3; /*!< Relevant for Timer A to Timer F. 344 Specifies whether or not compare 3 is operating in compare match or greater mode. 345 This parameter can be a value of @ref HRTIM_Timer_GreaterCMP3_Mode */ 346 uint32_t GreaterCMP1; /*!< Relevant for Timer A to Timer F. 347 Specifies whether or not compare 1 is operating in compare match or greater mode. 348 This parameter can be a value of @ref HRTIM_Timer_GreaterCMP1_Mode */ 349 uint32_t DualChannelDacReset; /*!< Relevant for Timer A to Timer F. 350 Specifies how the hrtim_dac_reset_trgx trigger is generated. 351 This parameter can be a value of @ref HRTIM_Timer_DualChannelDac_Reset */ 352 uint32_t DualChannelDacStep; /*!< Relevant for Timer A to Timer F. 353 Specifies how the hrtim_dac_step_trgx trigger is generated. 354 This parameter can be a value of @ref HRTIM_Timer_DualChannelDac_Step */ 355 uint32_t DualChannelDacEnable; /*!< Relevant for Timer A to Timer F. 356 Enables or not the dual channel DAC triggering mechanism. 357 This parameter can be a value of @ref HRTIM_Timer_DualChannelDac_Enable */ 358 } HRTIM_TimerCtlTypeDef; 359 360 /** 361 * @brief Compare unit configuration definition 362 */ 363 typedef struct 364 { 365 uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit. 366 The minimum value must be greater than or equal to 3 periods of the fHRTIM clock. 367 The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */ 368 uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4. 369 This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */ 370 uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected. 371 CompareValue + AutoDelayedTimeout must be less than 0xFFFFU */ 372 } HRTIM_CompareCfgTypeDef; 373 374 /** 375 * @brief Capture unit content definition 376 */ 377 typedef struct 378 { 379 uint32_t Value; /*!< Holds the counter value when the capture event occurred. 380 This parameter can be a number between 0x0 and 0xFFFFU */ 381 uint32_t Dir ; /*!< Holds the counting direction value when the capture event occurred. 382 This parameter can be a value of @ref HRTIM_Timer_UpDown_Mode */ 383 } HRTIM_CaptureValueTypeDef; 384 385 /** 386 * @brief Capture unit configuration definition 387 */ 388 typedef struct 389 { 390 uint64_t Trigger; /*!< Specifies source(s) triggering the capture. 391 This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */ 392 } HRTIM_CaptureCfgTypeDef; 393 394 /** 395 * @brief Output configuration definition 396 */ 397 typedef struct 398 { 399 uint32_t Polarity; /*!< Specifies the output polarity. 400 This parameter can be any value of @ref HRTIM_Output_Polarity */ 401 uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level. 402 This parameter can be a combination of @ref HRTIM_Output_Set_Source */ 403 uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level. 404 This parameter can be a combination of @ref HRTIM_Output_Reset_Source */ 405 uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation. 406 This parameter can be any value of @ref HRTIM_Output_Idle_Mode */ 407 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 408 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 409 uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state. 410 This parameter can be any value of @ref HRTIM_Output_FAULT_Level */ 411 uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled 412 This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */ 413 uint32_t BurstModeEntryDelayed; /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation. 414 This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */ 415 } HRTIM_OutputCfgTypeDef; 416 417 /** 418 * @brief External event filtering in timing units configuration definition 419 */ 420 typedef struct 421 { 422 uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit. 423 This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */ 424 uint32_t Latch; /*!< Specifies whether or not the signal is latched. 425 This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */ 426 } HRTIM_TimerEventFilteringCfgTypeDef; 427 428 /** 429 * @brief Dead time feature configuration definition 430 */ 431 typedef struct 432 { 433 uint32_t Prescaler; /*!< Specifies the dead-time prescaler. 434 This parameter can be a value of @ref HRTIM_Deadtime_Prescaler_Ratio */ 435 uint32_t RisingValue; /*!< Specifies the dead-time following a rising edge. 436 This parameter can be a number between 0x0 and 0x1FFU */ 437 uint32_t RisingSign; /*!< Specifies whether the dead-time is positive or negative on rising edge. 438 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */ 439 uint32_t RisingLock; /*!< Specifies whether or not dead-time rising settings (value and sign) are write protected. 440 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */ 441 uint32_t RisingSignLock; /*!< Specifies whether or not dead-time rising sign is write protected. 442 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */ 443 uint32_t FallingValue; /*!< Specifies the dead-time following a falling edge. 444 This parameter can be a number between 0x0 and 0x1FFU */ 445 uint32_t FallingSign; /*!< Specifies whether the dead-time is positive or negative on falling edge. 446 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */ 447 uint32_t FallingLock; /*!< Specifies whether or not dead-time falling settings (value and sign) are write protected. 448 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */ 449 uint32_t FallingSignLock; /*!< Specifies whether or not dead-time falling sign is write protected. 450 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */ 451 } HRTIM_DeadTimeCfgTypeDef; 452 453 /** 454 * @brief Chopper mode configuration definition 455 */ 456 typedef struct 457 { 458 uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value. 459 This parameter can be a value of @ref HRTIM_Chopper_Frequency */ 460 uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value. 461 This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */ 462 uint32_t StartPulse; /*!< Specifies the Timer pulse width value. 463 This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */ 464 } HRTIM_ChopperModeCfgTypeDef; 465 466 /** 467 * @brief External event channel configuration definition 468 */ 469 typedef struct 470 { 471 uint32_t Source; /*!< Identifies the source of the external event. 472 This parameter can be a value of @ref HRTIM_External_Event_Sources */ 473 uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity). 474 This parameter can be a value of @ref HRTIM_External_Event_Polarity */ 475 uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event. 476 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */ 477 uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter. 478 This parameter can be a value of @ref HRTIM_External_Event_Filter */ 479 uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event. 480 This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */ 481 } HRTIM_EventCfgTypeDef; 482 483 /** 484 * @brief Fault channel configuration definition 485 */ 486 typedef struct 487 { 488 uint32_t Source; /*!< Identifies the source of the fault. 489 This parameter can be a value of @ref HRTIM_Fault_Sources */ 490 uint32_t Polarity; /*!< Specifies the polarity of the fault event. 491 This parameter can be a value of @ref HRTIM_Fault_Polarity */ 492 uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter. 493 This parameter can be a value of @ref HRTIM_Fault_Filter */ 494 uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected. 495 This parameter can be a value of @ref HRTIM_Fault_Lock */ 496 } HRTIM_FaultCfgTypeDef; 497 498 typedef struct 499 { 500 uint32_t Threshold; /*!< Specifies the Fault counter Threshold. 501 This parameter can be a number between 0x0 and 0xF */ 502 uint32_t ResetMode; /*!< Specifies the reset mode of a fault event counter. 503 This parameter can be a value of @ref HRTIM_Fault_ResetMode */ 504 uint32_t BlankingSource;/*!< Specifies the blanking source of a fault event. 505 This parameter can be a value of @ref HRTIM_Fault_Blanking */ 506 } HRTIM_FaultBlankingCfgTypeDef; 507 508 /** 509 * @brief Burst mode configuration definition 510 */ 511 typedef struct 512 { 513 uint32_t Mode; /*!< Specifies the burst mode operating mode. 514 This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */ 515 uint32_t ClockSource; /*!< Specifies the burst mode clock source. 516 This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */ 517 uint32_t Prescaler; /*!< Specifies the burst mode prescaler. 518 This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */ 519 uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER). 520 This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable */ 521 uint32_t Trigger; /*!< Specifies the event(s) triggering the burst operation. 522 This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger */ 523 uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state. 524 This parameter can be a number between 0x0 and 0xFFFF */ 525 uint32_t Period; /*!< Specifies burst mode repetition period. 526 This parameter can be a number between 0x1 and 0xFFFF */ 527 } HRTIM_BurstModeCfgTypeDef; 528 529 /** 530 * @brief ADC trigger configuration definition 531 */ 532 typedef struct 533 { 534 uint32_t UpdateSource; /*!< Specifies the ADC trigger update source. 535 This parameter can be a value of @ref HRTIM_ADC_Trigger_Update_Source */ 536 uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion. 537 This parameter can be a combination of @ref HRTIM_ADC_Trigger_Event */ 538 } HRTIM_ADCTriggerCfgTypeDef; 539 540 /** 541 * @brief External Event Counter A or B configuration definition 542 */ 543 typedef struct 544 { 545 uint32_t ResetMode; /*!< Specifies the External Event Counter A or B Reset Mode. 546 This parameter can be a value of @ref HRTIM_Timer_External_Event_ResetMode */ 547 uint32_t Source; /*!< Specifies the External Event Counter source selection. 548 This parameter can be one of @ref HRTIM_External_Event_Channels */ 549 uint32_t Counter; /*!< Specifies the External Event Counter Threshold. 550 This parameter can be a number between 0x0 and 0x3F */ 551 } HRTIM_ExternalEventCfgTypeDef; 552 553 554 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 555 /** 556 * @brief HAL HRTIM Callback ID enumeration definition 557 */ 558 typedef enum { 559 HAL_HRTIM_FAULT1CALLBACK_CB_ID = 0x00U, /*!< Fault 1 interrupt callback ID */ 560 HAL_HRTIM_FAULT2CALLBACK_CB_ID = 0x01U, /*!< Fault 2 interrupt callback ID */ 561 HAL_HRTIM_FAULT3CALLBACK_CB_ID = 0x02U, /*!< Fault 3 interrupt callback ID */ 562 HAL_HRTIM_FAULT4CALLBACK_CB_ID = 0x03U, /*!< Fault 4 interrupt callback ID */ 563 HAL_HRTIM_FAULT5CALLBACK_CB_ID = 0x04U, /*!< Fault 5 interrupt callback ID */ 564 HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID = 0x05U, /*!< System fault interrupt callback ID */ 565 HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID = 0x06U, /*!< DLL Ready interrupt callback ID */ 566 HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID = 0x07U, /*!< Burst mode period interrupt callback ID */ 567 HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID = 0x08U, /*!< Sync Input interrupt callback ID */ 568 HAL_HRTIM_ERRORCALLBACK_CB_ID = 0x09U, /*!< DMA error callback ID */ 569 570 HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID = 0x10U, /*!< Timer x Update interrupt callback ID */ 571 HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID = 0x11U, /*!< Timer x Repetition interrupt callback ID */ 572 HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID = 0x12U, /*!< Timer x Compare 1 match interrupt callback ID */ 573 HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID = 0x13U, /*!< Timer x Compare 2 match interrupt callback ID */ 574 HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID = 0x14U, /*!< Timer x Compare 3 match interrupt callback ID */ 575 HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID = 0x15U, /*!< Timer x Compare 4 match interrupt callback ID */ 576 HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID = 0x16U, /*!< Timer x Capture 1 interrupts callback ID */ 577 HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID = 0x17U, /*!< Timer x Capture 2 interrupts callback ID */ 578 HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID = 0x18U, /*!< Timer x Delayed protection interrupt callback ID */ 579 HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID = 0x19U, /*!< Timer x counter reset/roll-over interrupt callback ID */ 580 HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID = 0x1AU, /*!< Timer x output 1 set interrupt callback ID */ 581 HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID = 0x1BU, /*!< Timer x output 1 reset interrupt callback ID */ 582 HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID = 0x1CU, /*!< Timer x output 2 set interrupt callback ID */ 583 HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID = 0x1DU, /*!< Timer x output 2 reset interrupt callback ID */ 584 HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID = 0x1EU, /*!< Timer x Burst DMA completed interrupt callback ID */ 585 586 HAL_HRTIM_MSPINIT_CB_ID = 0x20U, /*!< HRTIM MspInit callback ID */ 587 HAL_HRTIM_MSPDEINIT_CB_ID = 0x21U, /*!< HRTIM MspInit callback ID */ 588 HAL_HRTIM_FAULT6CALLBACK_CB_ID = 0x22U, /*!< Fault 6 interrupt callback ID */ 589 }HAL_HRTIM_CallbackIDTypeDef; 590 591 /** 592 * @brief HAL HRTIM Callback function pointer definitions 593 */ 594 typedef void (* pHRTIM_CallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim); /*!< HRTIM related callback function pointer */ 595 596 typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< HRTIM Timer x related callback function pointer */ 597 uint32_t TimerIdx); 598 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 599 600 /** 601 * @} 602 */ 603 604 /* Exported constants --------------------------------------------------------*/ 605 /** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants 606 * @{ 607 */ 608 609 /** @defgroup HRTIM_Timer_Index HRTIM Timer Index 610 * @{ 611 * @brief Constants defining the timer indexes 612 */ 613 #define HRTIM_TIMERINDEX_TIMER_A 0x0U /*!< Index used to access timer A registers */ 614 #define HRTIM_TIMERINDEX_TIMER_B 0x1U /*!< Index used to access timer B registers */ 615 #define HRTIM_TIMERINDEX_TIMER_C 0x2U /*!< Index used to access timer C registers */ 616 #define HRTIM_TIMERINDEX_TIMER_D 0x3U /*!< Index used to access timer D registers */ 617 #define HRTIM_TIMERINDEX_TIMER_E 0x4U /*!< Index used to access timer E registers */ 618 #define HRTIM_TIMERINDEX_TIMER_F 0x5U /*!< Index used to access timer F registers */ 619 #define HRTIM_TIMERINDEX_MASTER 0x6U /*!< Index used to access master registers */ 620 #define HRTIM_TIMERINDEX_COMMON 0xFFU /*!< Index used to access HRTIM common registers */ 621 /** 622 * @} 623 */ 624 625 /** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier 626 * @{ 627 * @brief Constants defining timer identifiers 628 */ 629 #define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /*!< Master identifier */ 630 #define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /*!< Timer A identifier */ 631 #define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /*!< Timer B identifier */ 632 #define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /*!< Timer C identifier */ 633 #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */ 634 #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */ 635 #define HRTIM_TIMERID_TIMER_F (HRTIM_MCR_TFCEN) /*!< Timer F identifier */ 636 /** 637 * @} 638 */ 639 640 /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit 641 * @{ 642 * @brief Constants defining compare unit identifiers 643 */ 644 #define HRTIM_COMPAREUNIT_1 0x00000001U /*!< Compare unit 1 identifier */ 645 #define HRTIM_COMPAREUNIT_2 0x00000002U /*!< Compare unit 2 identifier */ 646 #define HRTIM_COMPAREUNIT_3 0x00000004U /*!< Compare unit 3 identifier */ 647 #define HRTIM_COMPAREUNIT_4 0x00000008U /*!< Compare unit 4 identifier */ 648 /** 649 * @} 650 */ 651 652 /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit 653 * @{ 654 * @brief Constants defining capture unit identifiers 655 */ 656 #define HRTIM_CAPTUREUNIT_1 0x00000001U /*!< Capture unit 1 identifier */ 657 #define HRTIM_CAPTUREUNIT_2 0x00000002U /*!< Capture unit 2 identifier */ 658 /** 659 * @} 660 */ 661 662 /** @defgroup HRTIM_Timer_Output HRTIM Timer Output 663 * @{ 664 * @brief Constants defining timer output identifiers 665 */ 666 #define HRTIM_OUTPUT_TA1 0x00000001U /*!< Timer A - Output 1 identifier */ 667 #define HRTIM_OUTPUT_TA2 0x00000002U /*!< Timer A - Output 2 identifier */ 668 #define HRTIM_OUTPUT_TB1 0x00000004U /*!< Timer B - Output 1 identifier */ 669 #define HRTIM_OUTPUT_TB2 0x00000008U /*!< Timer B - Output 2 identifier */ 670 #define HRTIM_OUTPUT_TC1 0x00000010U /*!< Timer C - Output 1 identifier */ 671 #define HRTIM_OUTPUT_TC2 0x00000020U /*!< Timer C - Output 2 identifier */ 672 #define HRTIM_OUTPUT_TD1 0x00000040U /*!< Timer D - Output 1 identifier */ 673 #define HRTIM_OUTPUT_TD2 0x00000080U /*!< Timer D - Output 2 identifier */ 674 #define HRTIM_OUTPUT_TE1 0x00000100U /*!< Timer E - Output 1 identifier */ 675 #define HRTIM_OUTPUT_TE2 0x00000200U /*!< Timer E - Output 2 identifier */ 676 #define HRTIM_OUTPUT_TF1 0x00000400U /*!< Timer F - Output 1 identifier */ 677 #define HRTIM_OUTPUT_TF2 0x00000800U /*!< Timer F - Output 2 identifier */ 678 /** 679 * @} 680 */ 681 682 /** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger 683 * @{ 684 * @brief Constants defining ADC triggers identifiers 685 */ 686 #define HRTIM_ADCTRIGGER_1 0x00000001U /*!< ADC trigger 1 identifier */ 687 #define HRTIM_ADCTRIGGER_2 0x00000002U /*!< ADC trigger 2 identifier */ 688 #define HRTIM_ADCTRIGGER_3 0x00000004U /*!< ADC trigger 3 identifier */ 689 #define HRTIM_ADCTRIGGER_4 0x00000008U /*!< ADC trigger 4 identifier */ 690 /** 691 * @} 692 */ 693 694 /** @defgroup HRTIM_ADC_Ext_Trigger HRTIM ADC Extended Trigger 695 * @{ 696 * @brief Constants defining ADC Extended triggers identifiers 697 */ 698 #define HRTIM_ADCTRIGGER_5 0x00000010U /*!< ADC trigger 5 identifier */ 699 #define HRTIM_ADCTRIGGER_6 0x00000020U /*!< ADC trigger 6 identifier */ 700 #define HRTIM_ADCTRIGGER_7 0x00000040U /*!< ADC trigger 7 identifier */ 701 #define HRTIM_ADCTRIGGER_8 0x00000080U /*!< ADC trigger 8 identifier */ 702 #define HRTIM_ADCTRIGGER_9 0x00000100U /*!< ADC trigger 9 identifier */ 703 #define HRTIM_ADCTRIGGER_10 0x00000200U /*!< ADC trigger 10 identifier */ 704 705 #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\ 706 (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ 707 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ 708 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ 709 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4) || \ 710 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_5) || \ 711 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_6) || \ 712 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_7) || \ 713 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_8) || \ 714 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_9) || \ 715 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_10)) 716 #define IS_HRTIM_ADCEXTTRIGGER(ADCTRIGGER)\ 717 (((ADCTRIGGER) == HRTIM_ADCTRIGGER_5) || \ 718 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_6) || \ 719 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_7) || \ 720 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_8) || \ 721 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_9) || \ 722 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_10)) 723 /** 724 * @} 725 */ 726 727 /** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels 728 * @{ 729 * @brief Constants defining external event channel identifiers 730 */ 731 #define HRTIM_EVENT_NONE (0x00000000U) /*!< Undefined event channel */ 732 #define HRTIM_EVENT_1 (0x00000001U) /*!< External event channel 1 identifier */ 733 #define HRTIM_EVENT_2 (0x00000002U) /*!< External event channel 2 identifier */ 734 #define HRTIM_EVENT_3 (0x00000003U) /*!< External event channel 3 identifier */ 735 #define HRTIM_EVENT_4 (0x00000004U) /*!< External event channel 4 identifier */ 736 #define HRTIM_EVENT_5 (0x00000005U) /*!< External event channel 5 identifier */ 737 #define HRTIM_EVENT_6 (0x00000006U) /*!< External event channel 6 identifier */ 738 #define HRTIM_EVENT_7 (0x00000007U) /*!< External event channel 7 identifier */ 739 #define HRTIM_EVENT_8 (0x00000008U) /*!< External event channel 8 identifier */ 740 #define HRTIM_EVENT_9 (0x00000009U) /*!< External event channel 9 identifier */ 741 #define HRTIM_EVENT_10 (0x0000000AU) /*!< External event channel 10 identifier */ 742 /** 743 * @} 744 */ 745 746 /** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel 747 * @{ 748 * @brief Constants defining fault channel identifiers 749 */ 750 #define HRTIM_FAULT_1 (0x01U) /*!< Fault channel 1 identifier */ 751 #define HRTIM_FAULT_2 (0x02U) /*!< Fault channel 2 identifier */ 752 #define HRTIM_FAULT_3 (0x04U) /*!< Fault channel 3 identifier */ 753 #define HRTIM_FAULT_4 (0x08U) /*!< Fault channel 4 identifier */ 754 #define HRTIM_FAULT_5 (0x10U) /*!< Fault channel 5 identifier */ 755 #define HRTIM_FAULT_6 (0x20U) /*!< Fault channel 6 identifier */ 756 /** 757 * @} 758 */ 759 760 761 /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio 762 * @{ 763 * @brief Constants defining timer high-resolution clock prescaler ratio. 764 */ 765 #define HRTIM_PRESCALERRATIO_MUL32 (0x00000000U) /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */ 766 #define HRTIM_PRESCALERRATIO_MUL16 (0x00000001U) /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */ 767 #define HRTIM_PRESCALERRATIO_MUL8 (0x00000002U) /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */ 768 #define HRTIM_PRESCALERRATIO_MUL4 (0x00000003U) /*!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */ 769 #define HRTIM_PRESCALERRATIO_MUL2 (0x00000004U) /*!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */ 770 #define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */ 771 #define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */ 772 #define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */ 773 /** 774 * @} 775 */ 776 777 /** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode 778 * @{ 779 * @brief Constants defining timer counter operating mode. 780 */ 781 #define HRTIM_MODE_CONTINUOUS (0x00000008U) /*!< The timer operates in continuous (free-running) mode */ 782 #define HRTIM_MODE_SINGLESHOT (0x00000000U) /*!< The timer operates in non retriggerable single-shot mode */ 783 #define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE (0x00000010U) /*!< The timer operates in retriggerable single-shot mode */ 784 /** 785 * @} 786 */ 787 788 /** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable 789 * @{ 790 * @brief Constants defining half mode enabling status. 791 */ 792 #define HRTIM_HALFMODE_DISABLED (0x00000000U) /*!< Half mode is disabled */ 793 #define HRTIM_HALFMODE_ENABLED (0x00000020U) /*!< Half mode is enabled */ 794 /** 795 * @} 796 */ 797 798 /** @defgroup HRTIM_Interleaved_Mode HRTIM Interleaved Mode 799 * @{ 800 * @brief Constants defining interleaved mode enabling status. 801 */ 802 #define HRTIM_INTERLEAVED_MODE_DISABLED 0x000U /*!< HRTIM interleaved Mode is disabled */ 803 #define HRTIM_INTERLEAVED_MODE_DUAL 0x002U /*!< HRTIM interleaved Mode is Half */ 804 #define HRTIM_INTERLEAVED_MODE_TRIPLE 0x003U /*!< HRTIM interleaved Mode is Triple */ 805 #define HRTIM_INTERLEAVED_MODE_QUAD 0x004U /*!< HRTIM interleaved Mode is Quad */ 806 /** 807 * @} 808 */ 809 810 /** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event 811 * @{ 812 * @brief Constants defining the timer behavior following the synchronization event 813 */ 814 #define HRTIM_SYNCSTART_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */ 815 #define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /*!< Synchronization input event starts the timer */ 816 /** 817 * @} 818 */ 819 820 /** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event 821 * @{ 822 * @brief Constants defining the timer behavior following the synchronization event 823 */ 824 #define HRTIM_SYNCRESET_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */ 825 #define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /*!< Synchronization input event resets the timer */ 826 /** 827 * @} 828 */ 829 830 /** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization 831 * @{ 832 * @brief Constants defining on which output the DAC synchronization event is sent 833 */ 834 #define HRTIM_DACSYNC_NONE 0x00000000U /*!< No DAC synchronization event generated */ 835 #define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */ 836 #define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */ 837 #define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */ 838 /** 839 * @} 840 */ 841 842 /** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable 843 * @{ 844 * @brief Constants defining whether a write access into a preloadable 845 * register is done into the active or the preload register. 846 */ 847 #define HRTIM_PRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into the active register */ 848 #define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /*!< Preload enabled: the write access is done into the preload register */ 849 /** 850 * @} 851 */ 852 853 /** @defgroup HRTIM_Update_Gating HRTIM Update Gating 854 * @{ 855 * @brief Constants defining how the update occurs relatively to the burst DMA 856 * transaction and the external update request on update enable inputs 1 to 3. 857 */ 858 #define HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */ 859 #define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */ 860 #define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/ 861 #define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1U */ 862 #define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2U */ 863 #define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3U */ 864 #define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1U */ 865 #define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2U */ 866 #define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3U */ 867 /** 868 * @} 869 */ 870 871 /** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode 872 * @{ 873 * @brief Constants defining how the timer behaves during a burst 874 mode operation. 875 */ 876 #define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK 0x00000000U /*!< Timer counter clock is maintained and the timer operates normally */ 877 #define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */ 878 /** 879 * @} 880 */ 881 882 /** @defgroup HRTIM_Timer_UpDown_Mode HRTIM Timer UpDown Mode 883 * @{ 884 * @brief Constants defining how the timer counter operates 885 */ 886 #define HRTIM_TIMERUPDOWNMODE_UP 0x00000000U /*!< Timer counter is operating in up-counting mode */ 887 #define HRTIM_TIMERUPDOWNMODE_UPDOWN 0x00000001U /*!< Timer counter is operating in up-down counting mode */ 888 /** 889 * @} 890 */ 891 892 /** @defgroup HRTIM_Timer_TrigHalf_Mode HRTIM Timer Triggered-Half Mode 893 * @{ 894 * @brief Constants defining how the timer counter operates 895 */ 896 #define HRTIM_TIMERTRIGHALF_DISABLED 0x00000000U /*!< Timer Compare 2 register is behaving in standard mode */ 897 #define HRTIM_TIMERTRIGHALF_ENABLED (HRTIM_TIMCR2_TRGHLF) /*!< Timer Compare 2 register is behaving in triggered-half mode */ 898 /** 899 * @} 900 */ 901 902 /** @defgroup HRTIM_Timer_GreaterCMP3_Mode HRTIM Timer Greater than Compare 3 PWM Mode 903 * @{ 904 * @brief Constants defining how the timer compare operates 905 */ 906 #define HRTIM_TIMERGTCMP3_EQUAL 0x00000000U /*!< Timer Compare 3 event is generated when counter is equal */ 907 #define HRTIM_TIMERGTCMP3_GREATER (HRTIM_TIMCR2_GTCMP3) /*!< Timer Compare 3 Reset event is generated when counter is greater */ 908 /** 909 * @} 910 */ 911 912 /** @defgroup HRTIM_Timer_GreaterCMP1_Mode HRTIM Timer Greater than Compare 1 PWM Mode 913 * @{ 914 * @brief Constants defining how the timer compare operates 915 */ 916 #define HRTIM_TIMERGTCMP1_EQUAL 0x00000000U /*!< Timer Compare 1 event is generated when counter is equal */ 917 #define HRTIM_TIMERGTCMP1_GREATER (HRTIM_TIMCR2_GTCMP1) /*!< Timer Compare 1 event is generated when counter is greater */ 918 /** 919 * @} 920 */ 921 922 /** @defgroup HRTIM_Timer_DualChannelDac_Reset HRTIM Dual Channel Dac Reset Trigger 923 * @{ 924 * @brief Constants defining when the hrtim_dac_reset_trgx trigger is generated 925 */ 926 #define HRTIM_TIMER_DCDR_COUNTER 0x00000000U /*!< the trigger is generated on counter reset or roll-over event */ 927 #define HRTIM_TIMER_DCDR_OUT1SET (HRTIM_TIMCR2_DCDR) /*!< the trigger is generated on output 1 set event */ 928 /** 929 * @} 930 */ 931 932 /** @defgroup HRTIM_Timer_DualChannelDac_Step HRTIM Dual Channel Dac Step Trigger 933 * @{ 934 * @brief Constants defining when the hrtim_dac_step_trgx trigger is generated 935 is generated 936 */ 937 #define HRTIM_TIMER_DCDS_CMP2 0x00000000U /*!< the trigger is generated on compare 2 event */ 938 #define HRTIM_TIMER_DCDS_OUT1RST (HRTIM_TIMCR2_DCDS) /*!< the trigger is generated on output 1 reset event */ 939 /** 940 * @} 941 */ 942 943 /** @defgroup HRTIM_Timer_DualChannelDac_Enable HRTIM Dual Channel DAC Trigger Enable 944 * @{ 945 * @brief Constants enabling the dual channel DAC triggering mechanism 946 */ 947 #define HRTIM_TIMER_DCDE_DISABLED 0x00000000U /*!< the Dual channel DAC trigger is disabled */ 948 #define HRTIM_TIMER_DCDE_ENABLED (HRTIM_TIMCR2_DCDE) /*!< the Dual channel DAC trigger is enabled */ 949 /** 950 * @} 951 */ 952 953 /** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update 954 * @{ 955 * @brief Constants defining whether registers are updated when the timer 956 * repetition period is completed (either due to roll-over or 957 * reset events) 958 */ 959 #define HRTIM_UPDATEONREPETITION_DISABLED 0x00000000U /*!< Update on repetition disabled */ 960 #define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /*!< Update on repetition enabled */ 961 /** 962 * @} 963 */ 964 965 966 /** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode 967 * @{ 968 * @brief Constants defining whether or not the push-pull mode is enabled for 969 * a timer. 970 */ 971 #define HRTIM_TIMPUSHPULLMODE_DISABLED 0x00000000U /*!< Push-Pull mode disabled */ 972 #define HRTIM_TIMPUSHPULLMODE_ENABLED (HRTIM_TIMCR_PSHPLL) /*!< Push-Pull mode enabled */ 973 /** 974 * @} 975 */ 976 977 /** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling 978 * @{ 979 * @brief Constants defining whether a fault channel is enabled for a timer 980 */ 981 #define HRTIM_TIMFAULTENABLE_NONE 0x00000000U /*!< No fault enabled */ 982 #define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /*!< Fault 1 enabled */ 983 #define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /*!< Fault 2 enabled */ 984 #define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /*!< Fault 3 enabled */ 985 #define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /*!< Fault 4 enabled */ 986 #define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /*!< Fault 5 enabled */ 987 #define HRTIM_TIMFAULTENABLE_FAULT6 (HRTIM_FLTR_FLT6EN) /*!< Fault 6 enabled */ 988 /** 989 * @} 990 */ 991 992 /** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock 993 * @{ 994 * @brief Constants defining whether or not fault enabling bits are write 995 * protected for a timer 996 */ 997 #define HRTIM_TIMFAULTLOCK_READWRITE (0x00000000U) /*!< Timer fault enabling bits are read/write */ 998 #define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK) /*!< Timer fault enabling bits are read only */ 999 /** 1000 * @} 1001 */ 1002 1003 /** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Dead-time Insertion 1004 * @{ 1005 * @brief Constants defining whether or not fault the dead time insertion 1006 * feature is enabled for a timer 1007 */ 1008 #define HRTIM_TIMDEADTIMEINSERTION_DISABLED (0x00000000U) /*!< Output 1 and output 2 signals are independent */ 1009 #define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Dead-time is inserted between output 1 and output 2U */ 1010 /** 1011 * @} 1012 */ 1013 1014 /** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode 1015 * @{ 1016 * @brief Constants defining all possible delayed protection modes 1017 * for a timer. Also define the source and outputs on which the delayed 1018 * protection schemes are applied 1019 */ 1020 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */ 1021 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 (HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6U */ 1022 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6U */ 1023 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6U */ 1024 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 6U */ 1025 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7U */ 1026 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7U */ 1027 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U */ 1028 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7U */ 1029 1030 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */ 1031 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */ 1032 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */ 1033 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */ 1034 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 6U */ 1035 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */ 1036 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */ 1037 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */ 1038 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 7U */ 1039 1040 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */ 1041 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Output 1 delayed Idle on external Event 6U */ 1042 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Output 2 delayed Idle on external Event 6U */ 1043 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Output 1 and output 2 delayed Idle on external Event 6U */ 1044 #define HRTIM_TIMER_F_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Balanced Idle on external Event 6U */ 1045 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Output 1 delayed Idle on external Event 7U */ 1046 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Output 2 delayed Idle on external Event 7U */ 1047 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Output 1 and output2 delayed Idle on external Event 7U */ 1048 #define HRTIM_TIMER_F_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Balanced Idle on external Event 7U */ 1049 /** 1050 * @} 1051 */ 1052 1053 /** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger 1054 * @{ 1055 * @brief Constants defining whether the registers update is done synchronously 1056 * with any other timer or master update 1057 */ 1058 #define HRTIM_TIMUPDATETRIGGER_NONE 0x00000000U /*!< Register update is disabled */ 1059 #define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /*!< Register update is triggered by the master timer update */ 1060 #define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /*!< Register update is triggered by the timer A update */ 1061 #define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /*!< Register update is triggered by the timer B update */ 1062 #define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /*!< Register update is triggered by the timer C update*/ 1063 #define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /*!< Register update is triggered by the timer D update */ 1064 #define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /*!< Register update is triggered by the timer E update */ 1065 #define HRTIM_TIMUPDATETRIGGER_TIMER_F (HRTIM_TIMCR_TFU) /*!< Register update is triggered by the timer F update */ 1066 /** 1067 * @} 1068 */ 1069 1070 /** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger 1071 * @{ 1072 * @brief Constants defining the events that can be selected to trigger the reset 1073 * of the timer counter 1074 */ 1075 #define HRTIM_TIMRESETTRIGGER_NONE 0x00000000U /*!< No counter reset trigger */ 1076 #define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /*!< The timer counter is reset upon update event */ 1077 #define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /*!< The timer counter is reset upon Timer Compare 2 event */ 1078 #define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /*!< The timer counter is reset upon Timer Compare 4 event */ 1079 #define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /*!< The timer counter is reset upon master timer period event */ 1080 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /*!< The timer counter is reset upon master timer Compare 1 event */ 1081 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /*!< The timer counter is reset upon master timer Compare 2 event */ 1082 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /*!< The timer counter is reset upon master timer Compare 3 event */ 1083 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /*!< The timer counter is reset upon master timer Compare 4 event */ 1084 #define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1U */ 1085 #define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2U */ 1086 #define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3U */ 1087 #define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4U */ 1088 #define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5U */ 1089 #define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6U */ 1090 #define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7U */ 1091 #define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8U */ 1092 #define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9U */ 1093 #define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10U */ 1094 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 1095 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 1096 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 1097 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 1098 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 1099 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 1100 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 1101 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 1102 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 1103 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 1104 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 1105 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 1106 #define HRTIM_TIMRESETTRIGGER_OTHER5_CMP1 (HRTIM_RSTR_TIMFCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 1107 #define HRTIM_TIMRESETTRIGGER_OTHER5_CMP2 (HRTIM_RSTR_TIMFCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 1108 /** 1109 * @} 1110 */ 1111 1112 /** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update 1113 * @{ 1114 * @brief Constants defining whether the register are updated upon Timerx 1115 * counter reset or roll-over to 0 after reaching the period value 1116 * in continuous mode 1117 */ 1118 #define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U /*!< Update by timer x reset / roll-over disabled */ 1119 #define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / roll-over enabled */ 1120 /** 1121 * @} 1122 */ 1123 1124 /** @defgroup HRTIM_Timer_RollOver_Mode HRTIM Timer RollOver Mode 1125 * @{ 1126 * @brief Constants defining when the roll-over is generated upon Timerx 1127 * event generated when the counter is equal to 0 ('VALLEY' mode) or to HRTIM_PERxR value ('CREST' mode) or BOTH 1128 * This setting only applies when the UDM bit is set. It is not significant otherwise. 1129 */ 1130 #define HRTIM_TIM_FEROM_BOTH 0x00000000U /*!< Roll-over event used by */ 1131 #define HRTIM_TIM_FEROM_CREST (HRTIM_TIMCR2_FEROM_1) /*!< the Fault and */ 1132 #define HRTIM_TIM_FEROM_VALLEY (HRTIM_TIMCR2_FEROM_0) /*!< Event counters */ 1133 #define HRTIM_TIM_BMROM_BOTH 0x00000000U /*!< Roll-over event used in the Burst mode controller */ 1134 #define HRTIM_TIM_BMROM_CREST (HRTIM_TIMCR2_BMROM_1) /*!< as clock */ 1135 #define HRTIM_TIM_BMROM_VALLEY (HRTIM_TIMCR2_BMROM_0) /*!< and as burst mode trigger */ 1136 #define HRTIM_TIM_ADROM_BOTH 0x00000000U /*!< Roll-over event which triggers */ 1137 #define HRTIM_TIM_ADROM_CREST (HRTIM_TIMCR2_ADROM_1) /*!< the */ 1138 #define HRTIM_TIM_ADROM_VALLEY (HRTIM_TIMCR2_ADROM_0) /*!< ADC */ 1139 #define HRTIM_TIM_OUTROM_BOTH 0x00000000U /*!< Roll-over event which sets and/or resets the outputs */ 1140 #define HRTIM_TIM_OUTROM_CREST (HRTIM_TIMCR2_OUTROM_1) /*!< as per HRTIM_SETxyR */ 1141 #define HRTIM_TIM_OUTROM_VALLEY (HRTIM_TIMCR2_OUTROM_0) /*!< and HRTIM_RSTxyR settings */ 1142 #define HRTIM_TIM_ROM_BOTH 0x00000000U /*!< Roll-over event with the following destinations: IRQ and DMA requests,*/ 1143 #define HRTIM_TIM_ROM_CREST (HRTIM_TIMCR2_ROM_1) /*!< Update trigger (to transfer content from preload to active registers), */ 1144 #define HRTIM_TIM_ROM_VALLEY (HRTIM_TIMCR2_ROM_0) /*!< repetition counter decrement and External Event filtering */ 1145 1146 #define IS_HRTIM_ROLLOVERMODE(ROLLOVER)\ 1147 ((((ROLLOVER) == HRTIM_TIM_FEROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_FEROM_CREST) || ((ROLLOVER) == HRTIM_TIM_FEROM_VALLEY)) ||\ 1148 (((ROLLOVER) == HRTIM_TIM_ADROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_ADROM_CREST) || ((ROLLOVER) == HRTIM_TIM_ADROM_VALLEY)) ||\ 1149 (((ROLLOVER) == HRTIM_TIM_BMROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_BMROM_CREST) || ((ROLLOVER) == HRTIM_TIM_BMROM_VALLEY)) ||\ 1150 (((ROLLOVER) == HRTIM_TIM_OUTROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_OUTROM_CREST) || ((ROLLOVER) == HRTIM_TIM_OUTROM_VALLEY)) ||\ 1151 (((ROLLOVER) == HRTIM_TIM_ROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_ROM_CREST) || ((ROLLOVER) == HRTIM_TIM_ROM_VALLEY))) 1152 /** 1153 * @} 1154 */ 1155 1156 /** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode 1157 * @{ 1158 * @brief Constants defining whether the compare register is behaving in 1159 * regular mode (compare match issued as soon as counter equal compare), 1160 * or in auto-delayed mode 1161 */ 1162 #define HRTIM_AUTODELAYEDMODE_REGULAR (0x00000000U) /*!< standard compare mode */ 1163 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */ 1164 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */ 1165 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */ 1166 /** 1167 * @} 1168 */ 1169 1170 /** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode 1171 * @{ 1172 * @brief Constants defining the behavior of the output signal when the timer 1173 operates in basic output compare mode 1174 */ 1175 #define HRTIM_BASICOCMODE_TOGGLE (0x00000001U) /*!< Output toggles when the timer counter reaches the compare value */ 1176 #define HRTIM_BASICOCMODE_INACTIVE (0x00000002U) /*!< Output forced to active level when the timer counter reaches the compare value */ 1177 #define HRTIM_BASICOCMODE_ACTIVE (0x00000003U) /*!< Output forced to inactive level when the timer counter reaches the compare value */ 1178 1179 #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\ 1180 (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ 1181 ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ 1182 ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) 1183 /** 1184 * @} 1185 */ 1186 1187 /** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity 1188 * @{ 1189 * @brief Constants defining the polarity of a timer output 1190 */ 1191 #define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /*!< Output is active HIGH */ 1192 #define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */ 1193 /** 1194 * @} 1195 */ 1196 1197 /** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source 1198 * @{ 1199 * @brief Constants defining the events that can be selected to configure the 1200 * set crossbar of a timer output 1201 */ 1202 #define HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */ 1203 #define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */ 1204 #define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */ 1205 #define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */ 1206 #define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */ 1207 #define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */ 1208 #define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */ 1209 #define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */ 1210 #define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */ 1211 #define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */ 1212 #define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */ 1213 #define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */ 1214 /* Timer Events mapping for Timer A */ 1215 #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ 1216 #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ 1217 #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ 1218 #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ 1219 #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ 1220 #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ 1221 #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ 1222 #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ 1223 #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ 1224 /* Timer Events mapping for Timer B */ 1225 #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ 1226 #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ 1227 #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ 1228 #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ 1229 #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ 1230 #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ 1231 #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ 1232 #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ 1233 #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ 1234 /* Timer Events mapping for Timer C */ 1235 #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ 1236 #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ 1237 #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ 1238 #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ 1239 #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ 1240 #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ 1241 #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ 1242 #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ 1243 #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ 1244 /* Timer Events mapping for Timer D */ 1245 #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ 1246 #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ 1247 #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ 1248 #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ 1249 #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ 1250 #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ 1251 #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ 1252 #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ 1253 #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ 1254 /* Timer Events mapping for Timer E */ 1255 #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ 1256 #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ 1257 #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ 1258 #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ 1259 #define HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ 1260 #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ 1261 #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ 1262 #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ 1263 #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ 1264 /* Timer Events mapping for Timer F */ 1265 #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ 1266 #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ 1267 #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ 1268 #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ 1269 #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ 1270 #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ 1271 #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ 1272 #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ 1273 #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ 1274 #define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */ 1275 #define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */ 1276 #define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */ 1277 #define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */ 1278 #define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */ 1279 #define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */ 1280 #define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */ 1281 #define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */ 1282 #define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */ 1283 #define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */ 1284 #define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */ 1285 /** 1286 * @} 1287 */ 1288 1289 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source 1290 * @{ 1291 * @brief Constants defining the events that can be selected to configure the 1292 * reset crossbar of a timer output 1293 */ 1294 #define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */ 1295 #define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */ 1296 #define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */ 1297 #define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */ 1298 #define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */ 1299 #define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */ 1300 #define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */ 1301 #define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */ 1302 #define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */ 1303 #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */ 1304 #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */ 1305 #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */ 1306 /* Timer Events mapping for Timer A */ 1307 #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ 1308 #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ 1309 #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ 1310 #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ 1311 #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ 1312 #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ 1313 #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ 1314 #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ 1315 #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ 1316 /* Timer Events mapping for Timer B */ 1317 #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ 1318 #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ 1319 #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ 1320 #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ 1321 #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ 1322 #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ 1323 #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ 1324 #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ 1325 #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ 1326 /* Timer Events mapping for Timer C */ 1327 #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ 1328 #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ 1329 #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ 1330 #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ 1331 #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ 1332 #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ 1333 #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ 1334 #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ 1335 #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ 1336 /* Timer Events mapping for Timer D */ 1337 #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ 1338 #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ 1339 #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ 1340 #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ 1341 #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ 1342 #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ 1343 #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ 1344 #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ 1345 #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ 1346 /* Timer Events mapping for Timer E */ 1347 #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ 1348 #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ 1349 #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ 1350 #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ 1351 #define HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ 1352 #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ 1353 #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ 1354 #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ 1355 #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ 1356 /* Timer Events mapping for Timer F */ 1357 #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ 1358 #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ 1359 #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ 1360 #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ 1361 #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ 1362 #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ 1363 #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ 1364 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ 1365 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ 1366 #define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */ 1367 #define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */ 1368 #define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */ 1369 #define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */ 1370 #define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */ 1371 #define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */ 1372 #define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */ 1373 #define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */ 1374 #define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */ 1375 #define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */ 1376 #define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */ 1377 /** 1378 * @} 1379 */ 1380 1381 /** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode 1382 * @{ 1383 * @brief Constants defining whether or not the timer output transition to its 1384 IDLE state when burst mode is entered 1385 */ 1386 #define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */ 1387 #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */ 1388 /** 1389 * @} 1390 */ 1391 1392 /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level 1393 * @{ 1394 * @brief Constants defining the output level when output is in IDLE state 1395 */ 1396 #define HRTIM_OUTPUTIDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */ 1397 #define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */ 1398 /** 1399 * @} 1400 */ 1401 1402 /** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level 1403 * @{ 1404 * @brief Constants defining the output level when output is in FAULT state 1405 */ 1406 #define HRTIM_OUTPUTFAULTLEVEL_NONE 0x00000000U /*!< The output is not affected by the fault input */ 1407 #define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */ 1408 #define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */ 1409 #define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */ 1410 /** 1411 * @} 1412 */ 1413 1414 /** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable 1415 * @{ 1416 * @brief Constants defining whether or not chopper mode is enabled for a timer 1417 output 1418 */ 1419 #define HRTIM_OUTPUTCHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */ 1420 #define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */ 1421 /** 1422 * @} 1423 */ 1424 1425 /** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed 1426 * @{ 1427 * @brief Constants defining the idle mode entry is delayed by forcing a 1428 dead-time insertion before switching the outputs to their idle state 1429 */ 1430 #define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */ 1431 #define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Dead-time is inserted on output before entering the idle mode */ 1432 /** 1433 * @} 1434 */ 1435 1436 /** @defgroup HRTIM_Output_Balanced_Idle_Auto_Resume HRTIM Output Balanced Idle Automatic Resume 1437 * @{ 1438 * @brief Constants defining if the outputs are automatically 1439 re-enabled after a balanced idle event. 1440 */ 1441 #define HRTIM_OUTPUTBIAR_DISABLED 0x00000000U /*!< output is not automatically re-enabled */ 1442 #define HRTIM_OUTPUTBIAR_ENABLED (HRTIM_OUTR_BIAR) /*!< output is automatically re-enabled */ 1443 /** 1444 * @} 1445 */ 1446 1447 1448 /** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger 1449 * @{ 1450 * @brief Constants defining the events that can be selected to trigger the 1451 * capture of the timing unit counter 1452 */ 1453 #define HRTIM_CAPTURETRIGGER_NONE 0x00000000U /*!< Capture trigger is disabled */ 1454 #define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */ 1455 #define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */ 1456 #define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */ 1457 #define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /*!< The External event 3 triggers the Capture */ 1458 #define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /*!< The External event 4 triggers the Capture */ 1459 #define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /*!< The External event 5 triggers the Capture */ 1460 #define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /*!< The External event 6 triggers the Capture */ 1461 #define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /*!< The External event 7 triggers the Capture */ 1462 #define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /*!< The External event 8 triggers the Capture */ 1463 #define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /*!< The External event 9 triggers the Capture */ 1464 #define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */ 1465 #define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /*!< Capture is triggered by TA1 output inactive to active transition */ 1466 #define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /*!< Capture is triggered by TA1 output active to inactive transition */ 1467 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1) /*!< Timer A Compare 1 triggers Capture */ 1468 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2) /*!< Timer A Compare 2 triggers Capture */ 1469 #define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /*!< Capture is triggered by TB1 output inactive to active transition */ 1470 #define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /*!< Capture is triggered by TB1 output active to inactive transition */ 1471 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1) /*!< Timer B Compare 1 triggers Capture */ 1472 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2) /*!< Timer B Compare 2 triggers Capture */ 1473 #define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /*!< Capture is triggered by TC1 output inactive to active transition */ 1474 #define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /*!< Capture is triggered by TC1 output active to inactive transition */ 1475 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1) /*!< Timer C Compare 1 triggers Capture */ 1476 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2) /*!< Timer C Compare 2 triggers Capture */ 1477 #define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /*!< Capture is triggered by TD1 output inactive to active transition */ 1478 #define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /*!< Capture is triggered by TD1 output active to inactive transition */ 1479 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1) /*!< Timer D Compare 1 triggers Capture */ 1480 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2) /*!< Timer D Compare 2 triggers Capture */ 1481 #define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /*!< Capture is triggered by TE1 output inactive to active transition */ 1482 #define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /*!< Capture is triggered by TE1 output active to inactive transition */ 1483 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1) /*!< Timer E Compare 1 triggers Capture */ 1484 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2) /*!< Timer E Compare 2 triggers Capture */ 1485 /** 1486 * @} 1487 */ 1488 /** @defgroup HRTIM_Capture_Unit_TimerF_Trigger HRTIM Capture Unit TimerF Trigger 1489 * @{ 1490 * @brief Constants defining the events that can be selected to trigger the 1491 * capture of the timing unit counter 1492 */ 1493 #define HRTIM_CAPTURETRIGGER_TF1_SET ((uint64_t)(HRTIM_CPT1CR_TF1SET ) << 32) /*!< Capture is triggered by TF1 output inactive to active transition */ 1494 #define HRTIM_CAPTURETRIGGER_TF1_RESET ((uint64_t)(HRTIM_CPT1CR_TF1RST ) << 32) /*!< Capture is triggered by TF1 output active to inactive transition */ 1495 #define HRTIM_CAPTURETRIGGER_TIMERF_CMP1 ((uint64_t)(HRTIM_CPT1CR_TIMFCMP1) << 32) /*!< Timer F Compare 1 triggers Capture */ 1496 #define HRTIM_CAPTURETRIGGER_TIMERF_CMP2 ((uint64_t)(HRTIM_CPT1CR_TIMFCMP2) << 32) /*!< Timer F Compare 2 triggers Capture */ 1497 /** 1498 * @} 1499 */ 1500 1501 /** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter 1502 * @{ 1503 * @brief Constants defining the event filtering applied to external events 1504 * by a timer 1505 */ 1506 #define HRTIM_TIMEEVFLT_NONE (0x00000000U) 1507 #define HRTIM_TIMEEVFLT_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */ 1508 #define HRTIM_TIMEEVFLT_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */ 1509 #define HRTIM_TIMEEVFLT_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */ 1510 #define HRTIM_TIMEEVFLT_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */ 1511 /* Blanking Filter for TIMER A */ 1512 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF1_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ 1513 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF2_TIMBCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ 1514 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF3_TIMBOUT2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ 1515 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF4_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ 1516 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF5_TIMCCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ 1517 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF6_TIMFCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ 1518 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF7_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ 1519 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF8_TIMECMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ 1520 /* Blanking Filter for TIMER B */ 1521 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF1_TIMACMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ 1522 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF2_TIMACMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ 1523 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF3_TIMAOUT2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ 1524 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF4_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ 1525 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF5_TIMCCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ 1526 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF6_TIMFCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ 1527 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF7_TIMDCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ 1528 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF8_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ 1529 /* Blanking Filter for TIMER C */ 1530 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF1_TIMACMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ 1531 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF2_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ 1532 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF3_TIMBCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ 1533 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF4_TIMFCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ 1534 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF5_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ 1535 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF6_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ 1536 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF7_TIMDOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ 1537 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF8_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ 1538 /* Blanking Filter for TIMER D */ 1539 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF1_TIMACMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ 1540 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF2_TIMBCMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ 1541 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF3_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ 1542 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF4_TIMCCMP2 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ 1543 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF5_TIMCOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ 1544 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF6_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ 1545 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF7_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ 1546 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF8_TIMFCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ 1547 /* Blanking Filter for TIMER E */ 1548 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF1_TIMACMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ 1549 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF2_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ 1550 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF3_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ 1551 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF4_TIMFCMP4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ 1552 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF5_TIMFOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ 1553 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF6_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ 1554 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF7_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ 1555 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF8_TIMDOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ 1556 /* Blanking Filter for TIMER F */ 1557 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF1_TIMACMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ 1558 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF2_TIMBCMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ 1559 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF3_TIMCCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ 1560 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF4_TIMDCMP2 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ 1561 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF5_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ 1562 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF6_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ 1563 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF7_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ 1564 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF8_TIMEOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ 1565 1566 #define HRTIM_TIMEEVFLT_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */ 1567 #define HRTIM_TIMEEVFLT_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */ 1568 #define HRTIM_TIMEEVFLT_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1\ 1569 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */ 1570 /** 1571 * @} 1572 */ 1573 1574 /** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch 1575 * @{ 1576 * @brief Constants defining whether or not the external event is 1577 * memorized (latched) and generated as soon as the blanking period 1578 * is completed or the window ends 1579 */ 1580 #define HRTIM_TIMEVENTLATCH_DISABLED (0x00000000U) /*!< Event is ignored if it happens during a blank, or passed through during a window */ 1581 #define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */ 1582 /** 1583 * @} 1584 */ 1585 1586 /** @defgroup HRTIM_Timer_External_Event HRTIM Timer External Event Counter A or B 1587 * @{ 1588 * @brief Constants defining the External Event Counter A or B 1589 */ 1590 #define HRTIM_EVENTCOUNTER_A (HRTIM_EEFR3_EEVACE) /*!< External Event Counter A */ 1591 #define HRTIM_EVENTCOUNTER_B (HRTIM_EEFR3_EEVBCE) /*!< External Event Counter B */ 1592 /** 1593 * @} 1594 */ 1595 1596 /** @defgroup HRTIM_Timer_External_Event_ResetMode HRTIM Timer External Counter Reset Mode 1597 * @{ 1598 * @brief Constants enabling the External Event Counter A or B Reset Mode 1599 */ 1600 #define HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL (0x00000000U) /*!< External Event Counter is reset on each reset / roll-over event */ 1601 #define HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL (0x00000001U) /*!< External Event Counter is reset on each reset / roll-over event only 1602 if no event occurs during last counting period */ 1603 /** 1604 * @} 1605 */ 1606 1607 /** @defgroup HRTIM_Timer_ReSyncUpdate HRTIM Timer Re-Synchronized update 1608 * @{ 1609 * @brief Constants defining the update coming condition 1610 */ 1611 #define HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL (0x00000000U) /*!< update taken into account immediately */ 1612 #define HRTIM_TIMERESYNC_UPDATE_CONDITIONAL (0x00000001U) /*!< update taken into account on the following Reset/Roll-over event */ 1613 /** 1614 * @} 1615 */ 1616 1617 /** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Dead-time Prescaler Ratio 1618 * @{ 1619 * @brief Constants defining division ratio between the timer clock frequency 1620 * (fHRTIM) and the dead-time generator clock (fDTG) 1621 */ 1622 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 (0x00000000U) /*!< fDTG = fHRTIM * 8U */ 1623 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4U */ 1624 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2U */ 1625 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */ 1626 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2U */ 1627 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4U */ 1628 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8U */ 1629 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16U */ 1630 /** 1631 * @} 1632 */ 1633 1634 /** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Dead-time Rising Sign 1635 * @{ 1636 * @brief Constants defining whether the dead-time is positive or negative 1637 * (overlapping signal) on rising edge 1638 */ 1639 #define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE (0x00000000U) /*!< Positive dead-time on rising edge */ 1640 #define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative dead-time on rising edge */ 1641 /** 1642 * @} 1643 */ 1644 1645 /** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Dead-time Rising Lock 1646 * @{ 1647 * @brief Constants defining whether or not the dead-time (rising sign and 1648 * value) is write protected 1649 */ 1650 #define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE (0x00000000U) /*!< Dead-time rising value and sign is writeable */ 1651 #define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /*!< Dead-time rising value and sign is read-only */ 1652 /** 1653 * @} 1654 */ 1655 1656 /** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Dead-time Rising Sign Lock 1657 * @{ 1658 * @brief Constants defining whether or not the dead-time rising sign is write 1659 * protected 1660 */ 1661 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE (0x00000000U) /*!< Dead-time rising sign is writeable */ 1662 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /*!< Dead-time rising sign is read-only */ 1663 /** 1664 * @} 1665 */ 1666 1667 /** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Dead-time Falling Sign 1668 * @{ 1669 * @brief Constants defining whether the dead-time is positive or negative 1670 * (overlapping signal) on falling edge 1671 */ 1672 #define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE (0x00000000U) /*!< Positive dead-time on falling edge */ 1673 #define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative dead-time on falling edge */ 1674 /** 1675 * @} 1676 */ 1677 1678 /** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Dead-time Falling Lock 1679 * @{ 1680 * @brief Constants defining whether or not the dead-time (falling sign and 1681 * value) is write protected 1682 */ 1683 #define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE (0x00000000U) /*!< Dead-time falling value and sign is writeable */ 1684 #define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Dead-time falling value and sign is read-only */ 1685 /** 1686 * @} 1687 */ 1688 1689 /** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Dead-time Falling Sign Lock 1690 * @{ 1691 * @brief Constants defining whether or not the dead-time falling sign is write 1692 * protected 1693 */ 1694 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE (0x00000000U) /*!< Dead-time falling sign is writeable */ 1695 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Dead-time falling sign is read-only */ 1696 /** 1697 * @} 1698 */ 1699 1700 /** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency 1701 * @{ 1702 * @brief Constants defining the frequency of the generated high frequency carrier 1703 */ 1704 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV16 (0x000000U) /*!< fCHPFRQ = fHRTIM / 16 */ 1705 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */ 1706 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */ 1707 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */ 1708 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */ 1709 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */ 1710 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */ 1711 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */ 1712 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */ 1713 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */ 1714 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */ 1715 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */ 1716 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */ 1717 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */ 1718 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */ 1719 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */ 1720 /** 1721 * @} 1722 */ 1723 1724 /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle 1725 * @{ 1726 * @brief Constants defining the duty cycle of the generated high frequency carrier 1727 * Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8) 1728 */ 1729 #define HRTIM_CHOPPER_DUTYCYCLE_0 (0x000000U) /*!< Only 1st pulse is present */ 1730 #define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5U % */ 1731 #define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25U % */ 1732 #define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5U % */ 1733 #define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50U % */ 1734 #define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5U % */ 1735 #define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75U % */ 1736 #define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5U % */ 1737 /** 1738 * @} 1739 */ 1740 1741 /** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width 1742 * @{ 1743 * @brief Constants defining the pulse width of the first pulse of the generated 1744 * high frequency carrier 1745 */ 1746 #define HRTIM_CHOPPER_PULSEWIDTH_16 (0x000000U) /*!< tSTPW = tHRTIM x 16 */ 1747 #define HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */ 1748 #define HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */ 1749 #define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */ 1750 #define HRTIM_CHOPPER_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */ 1751 #define HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */ 1752 #define HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */ 1753 #define HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */ 1754 #define HRTIM_CHOPPER_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */ 1755 #define HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */ 1756 #define HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */ 1757 #define HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */ 1758 #define HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */ 1759 #define HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */ 1760 #define HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */ 1761 #define HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */ 1762 /** 1763 * @} 1764 */ 1765 1766 /** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options 1767 * @{ 1768 * @brief Constants defining the options for synchronizing multiple HRTIM 1769 * instances, as a master unit (generating a synchronization signal) 1770 * or as a slave (waiting for a trigger to be synchronized) 1771 */ 1772 #define HRTIM_SYNCOPTION_NONE 0x00000000U /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */ 1773 #define HRTIM_SYNCOPTION_MASTER 0x00000001U /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/ 1774 #define HRTIM_SYNCOPTION_SLAVE 0x00000002U /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */ 1775 /** 1776 * @} 1777 */ 1778 1779 /** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source 1780 * @{ 1781 * @brief Constants defining defining the synchronization input source 1782 */ 1783 #define HRTIM_SYNCINPUTSOURCE_NONE 0x00000000U /*!< disabled. HRTIM is not synchronized and runs in standalone mode */ 1784 #define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */ 1785 #define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */ 1786 /** 1787 * @} 1788 */ 1789 1790 /** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source 1791 * @{ 1792 * @brief Constants defining the source and event to be sent on the 1793 * synchronization outputs 1794 */ 1795 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */ 1796 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */ 1797 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */ 1798 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */ 1799 /** 1800 * @} 1801 */ 1802 1803 /** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity 1804 * @{ 1805 * @brief Constants defining the routing and conditioning of the synchronization output event 1806 */ 1807 #define HRTIM_SYNCOUTPUTPOLARITY_NONE 0x00000000U /*!< Synchronization output event is disabled */ 1808 #define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */ 1809 #define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */ 1810 /** 1811 * @} 1812 */ 1813 1814 /** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources 1815 * @{ 1816 * @brief Constants defining available sources associated to external events 1817 */ 1818 #define HRTIM_EEV1SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 1 */ 1819 #define HRTIM_EEV2SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 2 */ 1820 #define HRTIM_EEV3SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 3 */ 1821 #define HRTIM_EEV4SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 4 */ 1822 #define HRTIM_EEV5SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 5 */ 1823 #define HRTIM_EEV6SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 6 */ 1824 #define HRTIM_EEV7SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 7 */ 1825 #define HRTIM_EEV8SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 8 */ 1826 #define HRTIM_EEV9SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 9 */ 1827 #define HRTIM_EEV10SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 10 */ 1828 #define HRTIM_EEV1SRC_COMP2_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 1 */ 1829 #define HRTIM_EEV2SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 2 */ 1830 #define HRTIM_EEV3SRC_COMP6_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 3 */ 1831 #define HRTIM_EEV4SRC_COMP1_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 4 */ 1832 #define HRTIM_EEV5SRC_COMP3_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 5 */ 1833 #define HRTIM_EEV6SRC_COMP2_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 6 */ 1834 #define HRTIM_EEV7SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 7 */ 1835 #define HRTIM_EEV8SRC_COMP6_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 8 */ 1836 #define HRTIM_EEV9SRC_COMP5_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 9 */ 1837 #define HRTIM_EEV10SRC_COMP7_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 10 */ 1838 #define HRTIM_EEV1SRC_TIM1_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 1 */ 1839 #define HRTIM_EEV2SRC_TIM2_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 2 */ 1840 #define HRTIM_EEV3SRC_TIM3_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 3 */ 1841 #define HRTIM_EEV4SRC_COMP5_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 4 */ 1842 #define HRTIM_EEV5SRC_COMP7_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 5 */ 1843 #define HRTIM_EEV6SRC_COMP1_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 6 */ 1844 #define HRTIM_EEV7SRC_TIM7_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 7 */ 1845 #define HRTIM_EEV8SRC_COMP3_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 8 */ 1846 #define HRTIM_EEV9SRC_TIM15_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 9 */ 1847 #define HRTIM_EEV10SRC_TIM6_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 10 */ 1848 #define HRTIM_EEV1SRC_ADC1_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 1 */ 1849 #define HRTIM_EEV2SRC_ADC1_AWD2 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 2 */ 1850 #define HRTIM_EEV3SRC_ADC1_AWD3 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 3 */ 1851 #define HRTIM_EEV4SRC_ADC2_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 4 */ 1852 #define HRTIM_EEV5SRC_ADC2_AWD2 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 5 */ 1853 #define HRTIM_EEV6SRC_ADC2_AWD3 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 6 */ 1854 #define HRTIM_EEV7SRC_ADC3_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 7 */ 1855 #define HRTIM_EEV8SRC_ADC4_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 8 */ 1856 #define HRTIM_EEV9SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 9 */ 1857 #define HRTIM_EEV10SRC_ADC5_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 10 */ 1858 /** 1859 * @} 1860 */ 1861 1862 /** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity 1863 * @{ 1864 * @brief Constants defining the polarity of an external event 1865 */ 1866 #define HRTIM_EVENTPOLARITY_HIGH (0x00000000U) /*!< External event is active high */ 1867 #define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */ 1868 /** 1869 * @} 1870 */ 1871 1872 /** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity 1873 * @{ 1874 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) 1875 * of an external event 1876 */ 1877 #define HRTIM_EVENTSENSITIVITY_LEVEL (0x00000000U) /*!< External event is active on level */ 1878 #define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */ 1879 #define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */ 1880 #define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */ 1881 /** 1882 * @} 1883 */ 1884 1885 /** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode 1886 * @{ 1887 * @brief Constants defining whether or not an external event is programmed in 1888 fast mode 1889 */ 1890 #define HRTIM_EVENTFASTMODE_DISABLE (0x00000000U) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */ 1891 #define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */ 1892 /** 1893 * @} 1894 */ 1895 1896 /** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter 1897 * @{ 1898 * @brief Constants defining the frequency used to sample an external event 6 1899 * input and the length (N) of the digital filter applied 1900 */ 1901 #define HRTIM_EVENTFILTER_NONE (0x00000000U) /*!< Filter disabled */ 1902 #define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=2U */ 1903 #define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fHRTIM, N=4U */ 1904 #define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8U */ 1905 #define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/2U, N=6U */ 1906 #define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2U, N=8U */ 1907 #define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4U, N=6U */ 1908 #define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4U, N=8U */ 1909 #define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING= fEEVS/8U, N=6U */ 1910 #define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8U, N=8U */ 1911 #define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16U, N=5U */ 1912 #define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16U, N=6U */ 1913 #define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16U, N=8U */ 1914 #define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=5U */ 1915 #define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32U, N=6U */ 1916 #define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=8U */ 1917 /** 1918 * @} 1919 */ 1920 1921 /** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler 1922 * @{ 1923 * @brief Constants defining division ratio between the timer clock frequency 1924 * fHRTIM) and the external event signal sampling clock (fEEVS) 1925 * used by the digital filters 1926 */ 1927 #define HRTIM_EVENTPRESCALER_DIV1 (0x00000000U) /*!< fEEVS=fHRTIM */ 1928 #define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 2U */ 1929 #define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS=fHRTIM / 4U */ 1930 #define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8U */ 1931 /** 1932 * @} 1933 */ 1934 1935 /** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources 1936 * @{ 1937 * @brief Constants defining whether a fault is triggered by any external 1938 * or internal fault source 1939 */ 1940 #define HRTIM_FAULTSOURCE_DIGITALINPUT (0x00000000U) /*!< Fault input is FLT input pin */ 1941 #define HRTIM_FAULTSOURCE_INTERNAL (0x00000001U) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */ 1942 #define HRTIM_FAULTSOURCE_EEVINPUT (0x00000002U) /*!< Fault input is EEV pin */ 1943 /** 1944 * @} 1945 */ 1946 1947 /** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity 1948 * @{ 1949 * @brief Constants defining the polarity of a fault event 1950 */ 1951 #define HRTIM_FAULTPOLARITY_LOW (0x00000000U) /*!< Fault input is active low */ 1952 #define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */ 1953 /** 1954 * @} 1955 */ 1956 1957 /** @defgroup HRTIM_Fault_Blanking HRTIM Fault Blanking Source 1958 * @{ 1959 * @brief Constants defining the blanking source of a fault event 1960 */ 1961 #define HRTIM_FAULTBLANKINGMODE_RSTALIGNED (0x00000000U) /*!< Fault blanking source is Reset-aligned window */ 1962 #define HRTIM_FAULTBLANKINGMODE_MOVING (0x00000001U) /*!< Fault blanking source is Moving window */ 1963 /** 1964 * @} 1965 */ 1966 1967 /** @defgroup HRTIM_Fault_ResetMode HRTIM Fault Reset Mode 1968 * @{ 1969 * @brief Constants defining the Counter reset mode of a fault event 1970 */ 1971 #define HRTIM_FAULTCOUNTERRST_UNCONDITIONAL (0x00000000U) /*!< Fault counter is reset on each reset / roll-over event */ 1972 #define HRTIM_FAULTCOUNTERRST_CONDITIONAL (0x00000001U) /*!< Fault counter is reset on each reset / roll-over event only if no fault occurred during last countingperiod.*/ 1973 /** 1974 * @} 1975 */ 1976 1977 /** @defgroup HRTIM_Fault_Blanking_Control HRTIM Fault Blanking Control 1978 * @{ 1979 * @brief Constants used to enable or disable the blanking mode of a fault channel 1980 */ 1981 #define HRTIM_FAULTBLANKINGCTL_DISABLED 0x00000000U /*!< No blanking on Fault */ 1982 #define HRTIM_FAULTBLANKINGCTL_ENABLED 0x00000001U /*!< Fault blanking mode */ 1983 /** 1984 * @} 1985 */ 1986 1987 /** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter 1988 * @{ 1989 * @ brief Constants defining the frequency used to sample the fault input and 1990 * the length (N) of the digital filter applied 1991 */ 1992 #define HRTIM_FAULTFILTER_NONE (0x00000000U) /*!< Filter disabled */ 1993 #define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2U */ 1994 #define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4U */ 1995 #define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8U */ 1996 #define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2U, N=6U */ 1997 #define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2U, N=8U */ 1998 #define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4U, N=6U */ 1999 #define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4U, N=8U */ 2000 #define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8U, N=6U */ 2001 #define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8U, N=8U */ 2002 #define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16U, N=5U */ 2003 #define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16U, N=6U */ 2004 #define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16U, N=8U */ 2005 #define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=5U */ 2006 #define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32U, N=6U */ 2007 #define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=8U */ 2008 /** 2009 * @} 2010 */ 2011 2012 /** @defgroup HRTIM_Fault_Counter HRTIM Fault counter threshold value 2013 * @{ 2014 * @ brief Constants defining the FAULT Counter threshold 2015 */ 2016 #define HRTIM_FAULTCOUNTER_NONE ((uint32_t)0U ) /*!< Counter threshold = 0U */ 2017 #define HRTIM_FAULTCOUNTER_1 ((uint32_t)1U ) /*!< Counter threshold = 1U */ 2018 #define HRTIM_FAULTCOUNTER_2 ((uint32_t)2U ) /*!< Counter threshold = 2U */ 2019 #define HRTIM_FAULTCOUNTER_3 ((uint32_t)3U ) /*!< Counter threshold = 3U */ 2020 #define HRTIM_FAULTCOUNTER_4 ((uint32_t)4U ) /*!< Counter threshold = 4U */ 2021 #define HRTIM_FAULTCOUNTER_5 ((uint32_t)5U ) /*!< Counter threshold = 5U */ 2022 #define HRTIM_FAULTCOUNTER_6 ((uint32_t)6U ) /*!< Counter threshold = 6U */ 2023 #define HRTIM_FAULTCOUNTER_7 ((uint32_t)7U ) /*!< Counter threshold = 7U */ 2024 #define HRTIM_FAULTCOUNTER_8 ((uint32_t)8U ) /*!< Counter threshold = 8U */ 2025 #define HRTIM_FAULTCOUNTER_9 ((uint32_t)9U ) /*!< Counter threshold = 9U */ 2026 #define HRTIM_FAULTCOUNTER_10 ((uint32_t)10U) /*!< Counter threshold = 10U */ 2027 #define HRTIM_FAULTCOUNTER_11 ((uint32_t)11U) /*!< Counter threshold = 11U */ 2028 #define HRTIM_FAULTCOUNTER_12 ((uint32_t)12U) /*!< Counter threshold = 12U */ 2029 #define HRTIM_FAULTCOUNTER_13 ((uint32_t)13U) /*!< Counter threshold = 13U */ 2030 #define HRTIM_FAULTCOUNTER_14 ((uint32_t)14U) /*!< Counter threshold = 14U */ 2031 #define HRTIM_FAULTCOUNTER_15 ((uint32_t)15U) /*!< Counter threshold = 15U */ 2032 /** 2033 * @} 2034 */ 2035 2036 /** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock 2037 * @{ 2038 * @brief Constants defining whether or not the fault programming bits are 2039 write protected 2040 */ 2041 #define HRTIM_FAULTLOCK_READWRITE (0x00000000U) /*!< Fault settings bits are read/write */ 2042 #define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */ 2043 /** 2044 * @} 2045 */ 2046 2047 /** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler 2048 * @{ 2049 * @brief Constants defining the division ratio between the timer clock 2050 * frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used 2051 * by the digital filters. 2052 */ 2053 #define HRTIM_FAULTPRESCALER_DIV1 (0x00000000U) /*!< fFLTS=fHRTIM */ 2054 #define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 2U */ 2055 #define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS=fHRTIM / 4U */ 2056 #define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8U */ 2057 /** 2058 * @} 2059 */ 2060 2061 /** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode 2062 * @{ 2063 * @brief Constants defining if the burst mode is entered once or if it is 2064 * continuously operating 2065 */ 2066 #define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U) /*!< Burst mode operates in single shot mode */ 2067 #define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */ 2068 /** 2069 * @} 2070 */ 2071 2072 /** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source 2073 * @{ 2074 * @brief Constants defining the clock source for the burst mode counter 2075 */ 2076 #define HRTIM_BURSTMODECLOCKSOURCE_MASTER (0x00000000U) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */ 2077 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */ 2078 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */ 2079 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */ 2080 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */ 2081 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */ 2082 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_F (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer F counter reset/roll-over is used as clock source for the burst mode counter */ 2083 #define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */ 2084 #define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */ 2085 #define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */ 2086 #define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */ 2087 /** 2088 * @} 2089 */ 2090 2091 /** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler 2092 * @{ 2093 * @brief Constants defining the prescaling ratio of the fHRTIM clock 2094 * for the burst mode controller 2095 */ 2096 #define HRTIM_BURSTMODEPRESCALER_DIV1 (0x00000000U) /*!< fBRST = fHRTIM */ 2097 #define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2U */ 2098 #define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4U */ 2099 #define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8U */ 2100 #define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16U */ 2101 #define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32U */ 2102 #define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64U */ 2103 #define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128U */ 2104 #define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256U */ 2105 #define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512U */ 2106 #define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024U */ 2107 #define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048U*/ 2108 #define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096U */ 2109 #define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192U */ 2110 #define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384U */ 2111 #define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768U */ 2112 /** 2113 * @} 2114 */ 2115 2116 /** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable 2117 * @{ 2118 * @brief Constants defining whether or not burst mode registers preload 2119 mechanism is enabled, i.e. a write access into a preloadable register 2120 (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register 2121 */ 2122 #define HRIM_BURSTMODEPRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into active registers */ 2123 #define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /*!< Preload enabled: the write access is done into preload registers */ 2124 /** 2125 * @} 2126 */ 2127 2128 /** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger 2129 * @{ 2130 * @brief Constants defining the events that can be used to trig the burst 2131 * mode operation 2132 */ 2133 #define HRTIM_BURSTMODETRIGGER_NONE 0x00000000U /*!< No trigger */ 2134 #define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master reset */ 2135 #define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */ 2136 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1U */ 2137 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master compare 2U */ 2138 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master compare 3U */ 2139 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master compare 4U */ 2140 #define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset */ 2141 #define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition */ 2142 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 */ 2143 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 */ 2144 #define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset */ 2145 #define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition */ 2146 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 */ 2147 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 */ 2148 #define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C reset */ 2149 #define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition */ 2150 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 */ 2151 #define HRTIM_BURSTMODETRIGGER_TIMERF_RESET (HRTIM_BMTRGR_TFRST) /*!< Timer F reset */ 2152 #define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset */ 2153 #define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition */ 2154 #define HRTIM_BURSTMODETRIGGER_TIMERF_REPETITION (HRTIM_BMTRGR_TFREP) /*!< Timer F repetition */ 2155 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 */ 2156 #define HRTIM_BURSTMODETRIGGER_TIMERF_CMP1 (HRTIM_BMTRGR_TFCMP1) /*!< Timer F compare 1 */ 2157 #define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition */ 2158 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 */ 2159 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 */ 2160 #define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following External Event 7 */ 2161 #define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following External Event 8 */ 2162 #define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External Event 7 (timer A filters applied) */ 2163 #define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External Event 8 (timer D filters applied)*/ 2164 #define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< On-chip Event */ 2165 /** 2166 * @} 2167 */ 2168 2169 /** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source 2170 * @{ 2171 * @brief constants defining the source triggering the update of the 2172 HRTIM_ADCxR register (transfer from preload to active register). 2173 */ 2174 #define HRTIM_ADCTRIGGERUPDATE_MASTER 0x00000000U /*!< Master timer */ 2175 #define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< Timer A */ 2176 #define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< Timer B */ 2177 #define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */ 2178 #define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< Timer D */ 2179 #define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */ 2180 #define HRTIM_ADCTRIGGERUPDATE_TIMER_F (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_1) /*!< Timer F */ 2181 /** 2182 * @} 2183 */ 2184 2185 /** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event 2186 * @{ 2187 * @brief constants defining the events triggering ADC conversion. 2188 * HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3 2189 * HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4 2190 * HRTIM_ADCTRIGGEREVENT579_*: ADC Triggers 5 and 7 and 9 2191 * HRTIM_ADCTRIGGEREVENT6810_*: ADC Triggers 6 and 8 and 10 2192 */ 2193 #define HRTIM_ADCTRIGGEREVENT13_NONE 0x00000000U /*!< No ADC trigger event */ 2194 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1U */ 2195 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2U */ 2196 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3U */ 2197 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4U */ 2198 #define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /*!< ADC Trigger on master period */ 2199 #define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1U */ 2200 #define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2U */ 2201 #define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3U */ 2202 #define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4U */ 2203 #define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5U */ 2204 #define HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP2 (HRTIM_ADC1R_AD1TFC2) /*!< ADC Trigger on Timer F compare 2U */ 2205 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3U */ 2206 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4U */ 2207 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /*!< ADC Trigger on Timer A period */ 2208 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /*!< ADC Trigger on Timer A reset */ 2209 #define HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP3 (HRTIM_ADC1R_AD1TFC3) /*!< ADC Trigger on Timer F compare 3U */ 2210 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3U */ 2211 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4U */ 2212 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /*!< ADC Trigger on Timer B period */ 2213 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /*!< ADC Trigger on Timer B reset */ 2214 #define HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP4 (HRTIM_ADC1R_AD1TFC4) /*!< ADC Trigger on Timer F compare 4U */ 2215 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3U */ 2216 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4U */ 2217 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /*!< ADC Trigger on Timer C period */ 2218 #define HRTIM_ADCTRIGGEREVENT13_TIMERF_PERIOD (HRTIM_ADC1R_AD1TFPER) /*!< ADC Trigger on Timer F period */ 2219 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3U */ 2220 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4U */ 2221 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /*!< ADC Trigger on Timer D period */ 2222 #define HRTIM_ADCTRIGGEREVENT13_TIMERF_RESET (HRTIM_ADC1R_AD1TFRST) /*!< ADC Trigger on Timer F reset */ 2223 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3U */ 2224 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4U */ 2225 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /*!< ADC Trigger on Timer E period */ 2226 2227 #define HRTIM_ADCTRIGGEREVENT24_NONE 0x00000000U /*!< No ADC trigger event */ 2228 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1U */ 2229 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2U */ 2230 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3U */ 2231 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4U */ 2232 #define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /*!< ADC Trigger on master period */ 2233 #define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6U */ 2234 #define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7U */ 2235 #define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8U */ 2236 #define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9U */ 2237 #define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10U */ 2238 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2U */ 2239 #define HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP2 (HRTIM_ADC2R_AD2TFC2) /*!< ADC Trigger on Timer F compare 2U */ 2240 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4U */ 2241 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /*!< ADC Trigger on Timer A period */ 2242 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2U */ 2243 #define HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP3 (HRTIM_ADC2R_AD2TFC3) /*!< ADC Trigger on Timer F compare 3U */ 2244 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4U */ 2245 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /*!< ADC Trigger on Timer B period */ 2246 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2U */ 2247 #define HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP4 (HRTIM_ADC2R_AD2TFC4) /*!< ADC Trigger on Timer F compare 4U */ 2248 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4U */ 2249 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /*!< ADC Trigger on Timer C period */ 2250 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /*!< ADC Trigger on Timer C reset */ 2251 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2U */ 2252 #define HRTIM_ADCTRIGGEREVENT24_TIMERF_PERIOD (HRTIM_ADC2R_AD2TFPER) /*!< ADC Trigger on Timer F period */ 2253 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4U */ 2254 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /*!< ADC Trigger on Timer D period */ 2255 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /*!< ADC Trigger on Timer D reset */ 2256 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2U */ 2257 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3U */ 2258 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4U */ 2259 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */ 2260 2261 2262 #define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP1 ((uint32_t)0x00U) /*!< ADC Trigger on master compare 1U */ 2263 #define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP2 ((uint32_t)0x01U) /*!< ADC Trigger on master compare 2U */ 2264 #define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP3 ((uint32_t)0x02U) /*!< ADC Trigger on master compare 3U */ 2265 #define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP4 ((uint32_t)0x03U) /*!< ADC Trigger on master compare 4U */ 2266 #define HRTIM_ADCTRIGGEREVENT6810_MASTER_PERIOD ((uint32_t)0x04U) /*!< ADC Trigger on master period */ 2267 #define HRTIM_ADCTRIGGEREVENT6810_EVENT_6 ((uint32_t)0x05U) /*!< ADC Trigger on external event 6U */ 2268 #define HRTIM_ADCTRIGGEREVENT6810_EVENT_7 ((uint32_t)0x06U) /*!< ADC Trigger on external event 7U */ 2269 #define HRTIM_ADCTRIGGEREVENT6810_EVENT_8 ((uint32_t)0x07U) /*!< ADC Trigger on external event 8U */ 2270 #define HRTIM_ADCTRIGGEREVENT6810_EVENT_9 ((uint32_t)0x08U) /*!< ADC Trigger on external event 9U */ 2271 #define HRTIM_ADCTRIGGEREVENT6810_EVENT_10 ((uint32_t)0x09U) /*!< ADC Trigger on external event 10U */ 2272 #define HRTIM_ADCTRIGGEREVENT6810_TIMERA_CMP2 ((uint32_t)0x0AU) /*!< ADC Trigger on Timer A compare 2U */ 2273 #define HRTIM_ADCTRIGGEREVENT6810_TIMERA_CMP4 ((uint32_t)0x0BU) /*!< ADC Trigger on Timer A compare 4U */ 2274 #define HRTIM_ADCTRIGGEREVENT6810_TIMERA_PERIOD ((uint32_t)0x0CU) /*!< ADC Trigger on Timer A period */ 2275 #define HRTIM_ADCTRIGGEREVENT6810_TIMERB_CMP2 ((uint32_t)0x0DU) /*!< ADC Trigger on Timer B compare 2U */ 2276 #define HRTIM_ADCTRIGGEREVENT6810_TIMERB_CMP4 ((uint32_t)0x0EU) /*!< ADC Trigger on Timer B compare 4U */ 2277 #define HRTIM_ADCTRIGGEREVENT6810_TIMERB_PERIOD ((uint32_t)0x0FU) /*!< ADC Trigger on Timer B period */ 2278 #define HRTIM_ADCTRIGGEREVENT6810_TIMERC_CMP2 ((uint32_t)0x10U) /*!< ADC Trigger on Timer C compare 2U */ 2279 #define HRTIM_ADCTRIGGEREVENT6810_TIMERC_CMP4 ((uint32_t)0x11U) /*!< ADC Trigger on Timer C compare 4U */ 2280 #define HRTIM_ADCTRIGGEREVENT6810_TIMERC_PERIOD ((uint32_t)0x12U) /*!< ADC Trigger on Timer C period */ 2281 #define HRTIM_ADCTRIGGEREVENT6810_TIMERC_RESET ((uint32_t)0x13U) /*!< ADC Trigger on Timer C reset */ 2282 #define HRTIM_ADCTRIGGEREVENT6810_TIMERD_CMP2 ((uint32_t)0x14U) /*!< ADC Trigger on Timer D compare 2U */ 2283 #define HRTIM_ADCTRIGGEREVENT6810_TIMERD_CMP4 ((uint32_t)0x15U) /*!< ADC Trigger on Timer D compare 4U */ 2284 #define HRTIM_ADCTRIGGEREVENT6810_TIMERD_PERIOD ((uint32_t)0x16U) /*!< ADC Trigger on Timer D period */ 2285 #define HRTIM_ADCTRIGGEREVENT6810_TIMERD_RESET ((uint32_t)0x17U) /*!< ADC Trigger on Timer D reset */ 2286 #define HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP2 ((uint32_t)0x18U) /*!< ADC Trigger on Timer E compare 2U */ 2287 #define HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP3 ((uint32_t)0x19U) /*!< ADC Trigger on Timer E compare 3U */ 2288 #define HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP4 ((uint32_t)0x1AU) /*!< ADC Trigger on Timer E compare 4U */ 2289 #define HRTIM_ADCTRIGGEREVENT6810_TIMERE_RESET ((uint32_t)0x1BU) /*!< ADC Trigger on Timer E reset */ 2290 #define HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP2 ((uint32_t)0x1CU) /*!< ADC Trigger on Timer F compare 2U */ 2291 #define HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP3 ((uint32_t)0x1DU) /*!< ADC Trigger on Timer F compare 3U */ 2292 #define HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP4 ((uint32_t)0x1EU) /*!< ADC Trigger on Timer F compare 4U */ 2293 #define HRTIM_ADCTRIGGEREVENT6810_TIMERF_PERIOD ((uint32_t)0x1FU) /*!< ADC Trigger on Timer F period */ 2294 2295 #define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP1 ((uint32_t)0x00U) /*!< ADC Trigger on master compare 1U */ 2296 #define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP2 ((uint32_t)0x01U) /*!< ADC Trigger on master compare 2U */ 2297 #define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP3 ((uint32_t)0x02U) /*!< ADC Trigger on master compare 3U */ 2298 #define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP4 ((uint32_t)0x03U) /*!< ADC Trigger on master compare 4U */ 2299 #define HRTIM_ADCTRIGGEREVENT579_MASTER_PERIOD ((uint32_t)0x04U) /*!< ADC Trigger on master period */ 2300 #define HRTIM_ADCTRIGGEREVENT579_EVENT_1 ((uint32_t)0x05U) /*!< ADC Trigger on external event 1U */ 2301 #define HRTIM_ADCTRIGGEREVENT579_EVENT_2 ((uint32_t)0x06U) /*!< ADC Trigger on external event 2U */ 2302 #define HRTIM_ADCTRIGGEREVENT579_EVENT_3 ((uint32_t)0x07U) /*!< ADC Trigger on external event 3U */ 2303 #define HRTIM_ADCTRIGGEREVENT579_EVENT_4 ((uint32_t)0x08U) /*!< ADC Trigger on external event 4U */ 2304 #define HRTIM_ADCTRIGGEREVENT579_EVENT_5 ((uint32_t)0x09U) /*!< ADC Trigger on external event 5U */ 2305 #define HRTIM_ADCTRIGGEREVENT579_TIMERA_CMP3 ((uint32_t)0x0AU) /*!< ADC Trigger on Timer A compare 3U */ 2306 #define HRTIM_ADCTRIGGEREVENT579_TIMERA_CMP4 ((uint32_t)0x0BU) /*!< ADC Trigger on Timer A compare 4U */ 2307 #define HRTIM_ADCTRIGGEREVENT579_TIMERA_PERIOD ((uint32_t)0x0CU) /*!< ADC Trigger on Timer A period */ 2308 #define HRTIM_ADCTRIGGEREVENT579_TIMERA_RESET ((uint32_t)0x0DU) /*!< ADC Trigger on Timer A reset */ 2309 #define HRTIM_ADCTRIGGEREVENT579_TIMERB_CMP3 ((uint32_t)0x0EU) /*!< ADC Trigger on Timer B compare 3U */ 2310 #define HRTIM_ADCTRIGGEREVENT579_TIMERB_CMP4 ((uint32_t)0x0FU) /*!< ADC Trigger on Timer B compare 4U */ 2311 #define HRTIM_ADCTRIGGEREVENT579_TIMERB_PERIOD ((uint32_t)0x10U) /*!< ADC Trigger on Timer B period */ 2312 #define HRTIM_ADCTRIGGEREVENT579_TIMERB_RESET ((uint32_t)0x11U) /*!< ADC Trigger on Timer B reset */ 2313 #define HRTIM_ADCTRIGGEREVENT579_TIMERC_CMP3 ((uint32_t)0x12U) /*!< ADC Trigger on Timer C compare 3U */ 2314 #define HRTIM_ADCTRIGGEREVENT579_TIMERC_CMP4 ((uint32_t)0x13U) /*!< ADC Trigger on Timer C compare 4U */ 2315 #define HRTIM_ADCTRIGGEREVENT579_TIMERC_PERIOD ((uint32_t)0x14U) /*!< ADC Trigger on Timer C period */ 2316 #define HRTIM_ADCTRIGGEREVENT579_TIMERD_CMP3 ((uint32_t)0x15U) /*!< ADC Trigger on Timer D compare 3U */ 2317 #define HRTIM_ADCTRIGGEREVENT579_TIMERD_CMP4 ((uint32_t)0x16U) /*!< ADC Trigger on Timer D compare 4U */ 2318 #define HRTIM_ADCTRIGGEREVENT579_TIMERD_PERIOD ((uint32_t)0x17U) /*!< ADC Trigger on Timer D period */ 2319 #define HRTIM_ADCTRIGGEREVENT579_TIMERE_CMP3 ((uint32_t)0x18U) /*!< ADC Trigger on Timer E compare 3U */ 2320 #define HRTIM_ADCTRIGGEREVENT579_TIMERE_CMP4 ((uint32_t)0x19U) /*!< ADC Trigger on Timer E compare 4U */ 2321 #define HRTIM_ADCTRIGGEREVENT579_TIMERE_PERIOD ((uint32_t)0x1AU) /*!< ADC Trigger on Timer E period */ 2322 #define HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP2 ((uint32_t)0x1BU) /*!< ADC Trigger on Timer F compare 2U */ 2323 #define HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP3 ((uint32_t)0x1CU) /*!< ADC Trigger on Timer F compare 3U */ 2324 #define HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP4 ((uint32_t)0x1DU) /*!< ADC Trigger on Timer F compare 4U */ 2325 #define HRTIM_ADCTRIGGEREVENT579_TIMERF_PERIOD ((uint32_t)0x1EU) /*!< ADC Trigger on Timer F period */ 2326 #define HRTIM_ADCTRIGGEREVENT579_TIMERF_RESET ((uint32_t)0x1FU) /*!< ADC Trigger on Timer F reset */ 2327 /** 2328 * @} 2329 */ 2330 2331 /** @defgroup HRTIM_DLL_Calibration_Rate HRTIM DLL Calibration Rate 2332 * @{ 2333 * @brief Constants defining the DLL calibration periods (in micro seconds) 2334 */ 2335 #define HRTIM_SINGLE_CALIBRATION 0xFFFFFFFFU /*!< Non periodic DLL calibration */ 2336 #define HRTIM_CALIBRATIONRATE_0 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (6.168 ms) */ 2337 #define HRTIM_CALIBRATIONRATE_1 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.771 ms) */ 2338 #define HRTIM_CALIBRATIONRATE_2 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.096 ms) */ 2339 #define HRTIM_CALIBRATIONRATE_3 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048U * tHRTIM (0.012 ms) */ 2340 /** 2341 * @} 2342 */ 2343 2344 /** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update 2345 * @{ 2346 * @brief Constants defining the registers that can be written during a burst 2347 * DMA operation 2348 */ 2349 #define HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */ 2350 #define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */ 2351 #define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */ 2352 #define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */ 2353 #define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */ 2354 #define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /*!< MPER or PERxR register is updated by Burst DMA accesses */ 2355 #define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /*!< MREPR or REPxR register is updated by Burst DMA accesses */ 2356 #define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */ 2357 #define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */ 2358 #define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */ 2359 #define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */ 2360 #define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /*!< TDxR register is updated by Burst DMA accesses */ 2361 #define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */ 2362 #define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */ 2363 #define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */ 2364 #define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */ 2365 #define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */ 2366 #define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */ 2367 #define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */ 2368 #define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */ 2369 #define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */ 2370 #define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */ 2371 #define HRTIM_BURSTDMA_CR2 (HRTIM_BDTUPR_TIMCR2) /*!< TIMxCR2 register is updated by Burst DMA accesses */ 2372 #define HRTIM_BURSTDMA_EEFR3 (HRTIM_BDTUPR_TIMEEFR3) /*!< EEFxR3 register is updated by Burst DMA accesses */ 2373 /** 2374 * @} 2375 */ 2376 2377 /** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control 2378 * @{ 2379 * @brief Constants used to enable or disable the burst mode controller 2380 */ 2381 #define HRTIM_BURSTMODECTL_DISABLED 0x00000000U /*!< Burst mode disabled */ 2382 #define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /*!< Burst mode enabled */ 2383 /** 2384 * @} 2385 */ 2386 2387 /** @defgroup HRTIM_Fault_Mode_Control HRTIM Fault Mode Control 2388 * @{ 2389 * @brief Constants used to enable or disable a fault channel 2390 */ 2391 #define HRTIM_FAULTMODECTL_DISABLED 0x00000000U /*!< Fault channel is disabled */ 2392 #define HRTIM_FAULTMODECTL_ENABLED 0x00000001U /*!< Fault channel is enabled */ 2393 /** 2394 * @} 2395 */ 2396 2397 /** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update 2398 * @{ 2399 * @brief Constants used to force timer registers update 2400 */ 2401 #define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /*!< Force an immediate transfer from the preload to the active register in the master timer */ 2402 #define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /*!< Force an immediate transfer from the preload to the active register in the timer A */ 2403 #define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /*!< Force an immediate transfer from the preload to the active register in the timer B */ 2404 #define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /*!< Force an immediate transfer from the preload to the active register in the timer C */ 2405 #define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /*!< Force an immediate transfer from the preload to the active register in the timer D */ 2406 #define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /*!< Force an immediate transfer from the preload to the active register in the timer E */ 2407 #define HRTIM_TIMERUPDATE_F (HRTIM_CR2_TFSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer F */ 2408 /** 2409 * @} 2410 */ 2411 2412 /** @defgroup HRTIM_Software_Timer_SwapOutput HRTIM Software Timer swap Output 2413 * @{ 2414 * @brief Constants used to swap the output of the timer registers 2415 */ 2416 #define HRTIM_TIMERSWAP_A (HRTIM_CR2_SWPA) /*!< Swap the output of the Timer A */ 2417 #define HRTIM_TIMERSWAP_B (HRTIM_CR2_SWPB) /*!< Swap the output of the Timer B */ 2418 #define HRTIM_TIMERSWAP_C (HRTIM_CR2_SWPC) /*!< Swap the output of the Timer C */ 2419 #define HRTIM_TIMERSWAP_D (HRTIM_CR2_SWPD) /*!< Swap the output of the Timer D */ 2420 #define HRTIM_TIMERSWAP_E (HRTIM_CR2_SWPE) /*!< Swap the output of the Timer E */ 2421 #define HRTIM_TIMERSWAP_F (HRTIM_CR2_SWPF) /*!< Swap the output of the Timer F */ 2422 /** 2423 * @} 2424 */ 2425 2426 /** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset 2427 * @{ 2428 * @brief Constants used to force timer counter reset 2429 */ 2430 #define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /*!< Reset the master timer counter */ 2431 #define HRTIM_TIMERRESET_TIMER_A (HRTIM_CR2_TARST) /*!< Reset the timer A counter */ 2432 #define HRTIM_TIMERRESET_TIMER_B (HRTIM_CR2_TBRST) /*!< Reset the timer B counter */ 2433 #define HRTIM_TIMERRESET_TIMER_C (HRTIM_CR2_TCRST) /*!< Reset the timer C counter */ 2434 #define HRTIM_TIMERRESET_TIMER_D (HRTIM_CR2_TDRST) /*!< Reset the timer D counter */ 2435 #define HRTIM_TIMERRESET_TIMER_E (HRTIM_CR2_TERST) /*!< Reset the timer E counter */ 2436 #define HRTIM_TIMERRESET_TIMER_F (HRTIM_CR2_TFRST) /*!< Reset the timer F counter */ 2437 /** 2438 * @} 2439 */ 2440 2441 /** @defgroup HRTIM_Output_Level HRTIM Output Level 2442 * @{ 2443 * @brief Constants defining the level of a timer output 2444 */ 2445 #define HRTIM_OUTPUTLEVEL_ACTIVE (0x00000001U) /*!< Force the output to its active state */ 2446 #define HRTIM_OUTPUTLEVEL_INACTIVE (0x00000002U) /*!< Force the output to its inactive state */ 2447 2448 #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\ 2449 (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ 2450 ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) 2451 /** 2452 * @} 2453 */ 2454 2455 /** @defgroup HRTIM_Output_State HRTIM Output State 2456 * @{ 2457 * @brief Constants defining the state of a timer output 2458 */ 2459 #define HRTIM_OUTPUTSTATE_IDLE (0x00000001U) /*!< Main operating mode, where the output can take the active or 2460 inactive level as programmed in the crossbar unit */ 2461 #define HRTIM_OUTPUTSTATE_RUN (0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the 2462 outputs are disabled by software or during a burst mode operation */ 2463 #define HRTIM_OUTPUTSTATE_FAULT (0x00000003U) /*!< Safety state, entered in case of a shut-down request on 2464 FAULTx inputs */ 2465 /** 2466 * @} 2467 */ 2468 2469 /** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status 2470 * @{ 2471 * @brief Constants defining the operating state of the burst mode controller 2472 */ 2473 #define HRTIM_BURSTMODESTATUS_NORMAL 0x00000000U /*!< Normal operation */ 2474 #define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */ 2475 /** 2476 * @} 2477 */ 2478 2479 /** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status 2480 * @{ 2481 * @brief Constants defining on which output the signal is currently applied 2482 * in push-pull mode 2483 */ 2484 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 0x00000000U /*!< Signal applied on output 1 and output 2 forced inactive */ 2485 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */ 2486 /** 2487 * @} 2488 */ 2489 2490 /** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status 2491 * @{ 2492 * @brief Constants defining on which output the signal was applied, in 2493 * push-pull mode balanced fault mode or delayed idle mode, when the 2494 * protection was triggered 2495 */ 2496 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 0x00000000U /*!< Protection occurred when the output 1 was active and output 2 forced inactive */ 2497 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */ 2498 /** 2499 * @} 2500 */ 2501 2502 /** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable 2503 * @{ 2504 */ 2505 #define HRTIM_IT_NONE 0x00000000U /*!< No interrupt enabled */ 2506 #define HRTIM_IT_FLT1 HRTIM_IER_FLT1 /*!< Fault 1 interrupt enable */ 2507 #define HRTIM_IT_FLT2 HRTIM_IER_FLT2 /*!< Fault 2 interrupt enable */ 2508 #define HRTIM_IT_FLT3 HRTIM_IER_FLT3 /*!< Fault 3 interrupt enable */ 2509 #define HRTIM_IT_FLT4 HRTIM_IER_FLT4 /*!< Fault 4 interrupt enable */ 2510 #define HRTIM_IT_FLT5 HRTIM_IER_FLT5 /*!< Fault 5 interrupt enable */ 2511 #define HRTIM_IT_FLT6 HRTIM_IER_FLT6 /*!< Fault 6 interrupt enable */ 2512 #define HRTIM_IT_SYSFLT HRTIM_IER_SYSFLT /*!< System Fault interrupt enable */ 2513 #define HRTIM_IT_DLLRDY HRTIM_IER_DLLRDY /*!< DLL ready interrupt enable */ 2514 #define HRTIM_IT_BMPER HRTIM_IER_BMPER /*!< Burst mode period interrupt enable */ 2515 /** 2516 * @} 2517 */ 2518 2519 /** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable 2520 * @{ 2521 */ 2522 #define HRTIM_MASTER_IT_NONE 0x00000000U /*!< No interrupt enabled */ 2523 #define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /*!< Master compare 1 interrupt enable */ 2524 #define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /*!< Master compare 2 interrupt enable */ 2525 #define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /*!< Master compare 3 interrupt enable */ 2526 #define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /*!< Master compare 4 interrupt enable */ 2527 #define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /*!< Master Repetition interrupt enable */ 2528 #define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /*!< Synchronization input interrupt enable */ 2529 #define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /*!< Master update interrupt enable */ 2530 /** 2531 * @} 2532 */ 2533 2534 /** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable 2535 * @{ 2536 */ 2537 #define HRTIM_TIM_IT_NONE 0x00000000U /*!< No interrupt enabled */ 2538 #define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /*!< Timer compare 1 interrupt enable */ 2539 #define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /*!< Timer compare 2 interrupt enable */ 2540 #define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /*!< Timer compare 3 interrupt enable */ 2541 #define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /*!< Timer compare 4 interrupt enable */ 2542 #define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /*!< Timer repetition interrupt enable */ 2543 #define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /*!< Timer update interrupt enable */ 2544 #define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /*!< Timer capture 1 interrupt enable */ 2545 #define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /*!< Timer capture 2 interrupt enable */ 2546 #define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /*!< Timer output 1 set interrupt enable */ 2547 #define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /*!< Timer output 1 reset interrupt enable */ 2548 #define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /*!< Timer output 2 set interrupt enable */ 2549 #define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /*!< Timer output 2 reset interrupt enable */ 2550 #define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt enable */ 2551 #define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE /*!< Timer delay protection interrupt enable */ 2552 /** 2553 * @} 2554 */ 2555 2556 /** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag 2557 * @{ 2558 */ 2559 #define HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1 /*!< Fault 1 interrupt flag */ 2560 #define HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2 /*!< Fault 2 interrupt flag */ 2561 #define HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3 /*!< Fault 3 interrupt flag */ 2562 #define HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4 /*!< Fault 4 interrupt flag */ 2563 #define HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5 /*!< Fault 5 interrupt flag */ 2564 #define HRTIM_FLAG_FLT6 HRTIM_ISR_FLT6 /*!< Fault 6 interrupt flag */ 2565 #define HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT /*!< System Fault interrupt flag */ 2566 #define HRTIM_FLAG_DLLRDY HRTIM_ISR_DLLRDY /*!< DLL ready interrupt flag */ 2567 #define HRTIM_FLAG_BMPER HRTIM_ISR_BMPER /*!< Burst mode period interrupt flag */ 2568 /** 2569 * @} 2570 */ 2571 2572 /** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag 2573 * @{ 2574 */ 2575 #define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /*!< Master compare 1 interrupt flag */ 2576 #define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /*!< Master compare 2 interrupt flag */ 2577 #define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /*!< Master compare 3 interrupt flag */ 2578 #define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /*!< Master compare 4 interrupt flag */ 2579 #define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /*!< Master Repetition interrupt flag */ 2580 #define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /*!< Synchronization input interrupt flag */ 2581 #define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /*!< Master update interrupt flag */ 2582 /** 2583 * @} 2584 */ 2585 2586 /** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag 2587 * @{ 2588 */ 2589 #define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /*!< Timer compare 1 interrupt flag */ 2590 #define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /*!< Timer compare 2 interrupt flag */ 2591 #define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /*!< Timer compare 3 interrupt flag */ 2592 #define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /*!< Timer compare 4 interrupt flag */ 2593 #define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /*!< Timer repetition interrupt flag */ 2594 #define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /*!< Timer update interrupt flag */ 2595 #define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /*!< Timer capture 1 interrupt flag */ 2596 #define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /*!< Timer capture 2 interrupt flag */ 2597 #define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /*!< Timer output 1 set interrupt flag */ 2598 #define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /*!< Timer output 1 reset interrupt flag */ 2599 #define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /*!< Timer output 2 set interrupt flag */ 2600 #define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /*!< Timer output 2 reset interrupt flag */ 2601 #define HRTIM_TIM_FLAG_RST HRTIM_TIMISR_RST /*!< Timer reset interrupt flag */ 2602 #define HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT /*!< Timer delay protection interrupt flag */ 2603 /** 2604 * @} 2605 */ 2606 2607 /** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable 2608 * @{ 2609 */ 2610 #define HRTIM_MASTER_DMA_NONE 0x00000000U /*!< No DMA request enable */ 2611 #define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /*!< Master compare 1 DMA request enable */ 2612 #define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /*!< Master compare 2 DMA request enable */ 2613 #define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /*!< Master compare 3 DMA request enable */ 2614 #define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /*!< Master compare 4 DMA request enable */ 2615 #define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /*!< Master Repetition DMA request enable */ 2616 #define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /*!< Synchronization input DMA request enable */ 2617 #define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /*!< Master update DMA request enable */ 2618 /** 2619 * @} 2620 */ 2621 2622 /** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable 2623 * @{ 2624 */ 2625 #define HRTIM_TIM_DMA_NONE 0x00000000U /*!< No DMA request enable */ 2626 #define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /*!< Timer compare 1 DMA request enable */ 2627 #define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /*!< Timer compare 2 DMA request enable */ 2628 #define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /*!< Timer compare 3 DMA request enable */ 2629 #define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /*!< Timer compare 4 DMA request enable */ 2630 #define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /*!< Timer repetition DMA request enable */ 2631 #define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /*!< Timer update DMA request enable */ 2632 #define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /*!< Timer capture 1 DMA request enable */ 2633 #define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /*!< Timer capture 2 DMA request enable */ 2634 #define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /*!< Timer output 1 set DMA request enable */ 2635 #define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /*!< Timer output 1 reset DMA request enable */ 2636 #define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /*!< Timer output 2 set DMA request enable */ 2637 #define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /*!< Timer output 2 reset DMA request enable */ 2638 #define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /*!< Timer reset DMA request enable */ 2639 #define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /*!< Timer delay protection DMA request enable */ 2640 /** 2641 * @} 2642 */ 2643 2644 /** 2645 * @} 2646 */ 2647 2648 /* Private Constants --------------------------------------------------------*/ 2649 /** @addtogroup HRTIM_Private_Constants 2650 * @{ 2651 */ 2652 #define HRTIM_CAPTUREFTRIGGER_NONE 0x00000000U /*!< 32bit value Capture trigger is disabled */ 2653 #define HRTIM_CAPTUREFTRIGGER_TF1_SET (HRTIM_CPT1CR_TF1SET) /*!< 32bit value Capture is triggered by TF1 output inactive to active transition */ 2654 #define HRTIM_CAPTUREFTRIGGER_TF1_RESET (HRTIM_CPT1CR_TF1RST) /*!< 32bit value Capture is triggered by TF1 output active to inactive transition */ 2655 #define HRTIM_CAPTUREFTRIGGER_TIMERF_CMP1 (HRTIM_CPT1CR_TIMFCMP1) /*!< 32bit value Timer F Compare 1 triggers Capture */ 2656 #define HRTIM_CAPTUREFTRIGGER_TIMERF_CMP2 (HRTIM_CPT1CR_TIMFCMP2) /*!< 32bit value Timer F Compare 2 triggers Capture */ 2657 /** 2658 * @} 2659 */ 2660 2661 /* Private macros --------------------------------------------------------*/ 2662 /** @addtogroup HRTIM_Private_Macros 2663 * @{ 2664 */ 2665 #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\ 2666 (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ 2667 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ 2668 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ 2669 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ 2670 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ 2671 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E) || \ 2672 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_F)) 2673 2674 #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\ 2675 (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ 2676 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ 2677 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ 2678 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ 2679 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E) || \ 2680 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_F)) 2681 2682 #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFF80FFFFU) == 0x00000000U) 2683 2684 #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\ 2685 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \ 2686 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \ 2687 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \ 2688 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4)) 2689 2690 #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\ 2691 (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ 2692 ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) 2693 2694 #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFF000U) == 0x00000000U) 2695 2696 #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\ 2697 ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ 2698 (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ 2699 ((OUTPUT) == HRTIM_OUTPUT_TA2))) \ 2700 || \ 2701 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ 2702 (((OUTPUT) == HRTIM_OUTPUT_TB1) || \ 2703 ((OUTPUT) == HRTIM_OUTPUT_TB2))) \ 2704 || \ 2705 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ 2706 (((OUTPUT) == HRTIM_OUTPUT_TC1) || \ 2707 ((OUTPUT) == HRTIM_OUTPUT_TC2))) \ 2708 || \ 2709 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ 2710 (((OUTPUT) == HRTIM_OUTPUT_TD1) || \ 2711 ((OUTPUT) == HRTIM_OUTPUT_TD2))) \ 2712 || \ 2713 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ 2714 (((OUTPUT) == HRTIM_OUTPUT_TE1) || \ 2715 ((OUTPUT) == HRTIM_OUTPUT_TE2))) \ 2716 || \ 2717 (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && \ 2718 (((OUTPUT) == HRTIM_OUTPUT_TF1) || \ 2719 ((OUTPUT) == HRTIM_OUTPUT_TF2)))) 2720 2721 #define IS_HRTIM_TIMEEVENT(EVENT)\ 2722 (((EVENT) == HRTIM_EVENTCOUNTER_A) || \ 2723 ((EVENT) == HRTIM_EVENTCOUNTER_B)) 2724 2725 #define IS_HRTIM_TIMEEVENT_RESETMODE(EVENT)\ 2726 (((EVENT) == HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL) || \ 2727 ((EVENT) == HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL)) 2728 2729 #define IS_HRTIM_TIMSYNCUPDATE(EVENT)\ 2730 (((EVENT) == HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL) || \ 2731 ((EVENT) == HRTIM_TIMERESYNC_UPDATE_CONDITIONAL)) 2732 2733 #define IS_HRTIM_TIMEEVENT_COUNTER(COUNTER)\ 2734 ((((COUNTER) > (uint32_t)0x00U) && ((COUNTER) <= (uint32_t)0x3FU)) ||\ 2735 ((COUNTER) == (uint32_t)0x00U)) 2736 2737 #define IS_HRTIM_TIMEEVENT_SOURCE(SOURCE)\ 2738 (((SOURCE) >= (uint32_t)0x00U) && ((SOURCE) <= (uint32_t)0x9U)) 2739 2740 #define IS_HRTIM_EVENT(EVENT)\ 2741 (((EVENT) == HRTIM_EVENT_NONE)|| \ 2742 ((EVENT) == HRTIM_EVENT_1) || \ 2743 ((EVENT) == HRTIM_EVENT_2) || \ 2744 ((EVENT) == HRTIM_EVENT_3) || \ 2745 ((EVENT) == HRTIM_EVENT_4) || \ 2746 ((EVENT) == HRTIM_EVENT_5) || \ 2747 ((EVENT) == HRTIM_EVENT_6) || \ 2748 ((EVENT) == HRTIM_EVENT_7) || \ 2749 ((EVENT) == HRTIM_EVENT_8) || \ 2750 ((EVENT) == HRTIM_EVENT_9) || \ 2751 ((EVENT) == HRTIM_EVENT_10)) 2752 2753 #define IS_HRTIM_FAULT(FAULT)\ 2754 (((FAULT) == HRTIM_FAULT_1) || \ 2755 ((FAULT) == HRTIM_FAULT_2) || \ 2756 ((FAULT) == HRTIM_FAULT_3) || \ 2757 ((FAULT) == HRTIM_FAULT_4) || \ 2758 ((FAULT) == HRTIM_FAULT_5) || \ 2759 ((FAULT) == HRTIM_FAULT_6)) 2760 2761 #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\ 2762 (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \ 2763 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \ 2764 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \ 2765 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \ 2766 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \ 2767 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ 2768 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ 2769 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) 2770 2771 #define IS_HRTIM_MODE(MODE)\ 2772 (((MODE) == HRTIM_MODE_CONTINUOUS) || \ 2773 ((MODE) == HRTIM_MODE_SINGLESHOT) || \ 2774 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) 2775 2776 #define IS_HRTIM_MODE_ONEPULSE(MODE)\ 2777 (((MODE) == HRTIM_MODE_SINGLESHOT) || \ 2778 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) 2779 2780 2781 #define IS_HRTIM_HALFMODE(HALFMODE)\ 2782 (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \ 2783 ((HALFMODE) == HRTIM_HALFMODE_ENABLED)) 2784 2785 #define IS_HRTIM_INTERLEAVEDMODE(INTLVDMODE)\ 2786 (((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED) || \ 2787 ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DUAL) || \ 2788 ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED) || \ 2789 ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_TRIPLE) || \ 2790 ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED) || \ 2791 ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_QUAD)) 2792 2793 #define IS_HRTIM_SYNCSTART(SYNCSTART)\ 2794 (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ 2795 ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) 2796 2797 #define IS_HRTIM_SYNCRESET(SYNCRESET)\ 2798 (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ 2799 ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) 2800 2801 #define IS_HRTIM_DACSYNC(DACSYNC)\ 2802 (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ 2803 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ 2804 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ 2805 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3)) 2806 2807 #define IS_HRTIM_PRELOAD(PRELOAD)\ 2808 (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \ 2809 ((PRELOAD) == HRTIM_PRELOAD_ENABLED)) 2810 2811 #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\ 2812 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ 2813 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ 2814 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)) 2815 2816 #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\ 2817 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ 2818 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ 2819 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \ 2820 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \ 2821 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \ 2822 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \ 2823 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \ 2824 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ 2825 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) 2826 2827 #define IS_HRTIM_TIMERBURSTMODE(MODE) \ 2828 (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ 2829 ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) 2830 #define IS_HRTIM_TIMERUPDOWNMODE(MODE) \ 2831 (((MODE) == HRTIM_TIMERUPDOWNMODE_UP) || \ 2832 ((MODE) == HRTIM_TIMERUPDOWNMODE_UPDOWN)) 2833 2834 #define IS_HRTIM_TIMERTRGHLFMODE(MODE) \ 2835 (((MODE) == HRTIM_TIMERTRIGHALF_DISABLED) || \ 2836 ((MODE) == HRTIM_TIMERTRIGHALF_ENABLED)) 2837 2838 #define IS_HRTIM_TIMERGTCMP3(MODE) \ 2839 (((MODE) == HRTIM_TIMERGTCMP3_EQUAL) || \ 2840 ((MODE) == HRTIM_TIMERGTCMP3_GREATER)) 2841 2842 #define IS_HRTIM_TIMERGTCMP1(MODE) \ 2843 (((MODE) == HRTIM_TIMERGTCMP1_EQUAL) || \ 2844 ((MODE) == HRTIM_TIMERGTCMP1_GREATER)) 2845 2846 #define IS_HRTIM_DUALDAC_RESET(DUALCHANNELDAC) \ 2847 (((DUALCHANNELDAC) == HRTIM_TIMER_DCDR_COUNTER) || \ 2848 ((DUALCHANNELDAC) == HRTIM_TIMER_DCDR_OUT1SET)) 2849 2850 #define IS_HRTIM_DUALDAC_STEP(DUALCHANNELDAC) \ 2851 (((DUALCHANNELDAC) == HRTIM_TIMER_DCDS_CMP2) || \ 2852 ((DUALCHANNELDAC) == HRTIM_TIMER_DCDS_OUT1RST)) 2853 2854 #define IS_HRTIM_DUALDAC_ENABLE(DUALCHANNELDAC) \ 2855 (((DUALCHANNELDAC) == HRTIM_TIMER_DCDE_DISABLED) || \ 2856 ((DUALCHANNELDAC) == HRTIM_TIMER_DCDE_ENABLED )) 2857 2858 #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \ 2859 (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ 2860 ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) 2861 2862 #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\ 2863 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ 2864 ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) 2865 #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFC0U) == 0x00000000U) 2866 2867 #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\ 2868 (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ 2869 ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) 2870 2871 #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\ 2872 (((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \ 2873 ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)) 2874 2875 #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\ 2876 ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \ 2877 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \ 2878 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \ 2879 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \ 2880 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \ 2881 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \ 2882 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \ 2883 || \ 2884 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ 2885 (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ 2886 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))) 2887 2888 #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE06FFFFU) == 0x00000000U) 2889 2890 #define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x00000000U) == 0x00000000U) 2891 2892 2893 #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \ 2894 (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \ 2895 ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED)) 2896 2897 #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\ 2898 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ 2899 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ 2900 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ 2901 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)) 2902 2903 /* Auto delayed mode is only available for compare units 2 and 4U */ 2904 #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \ 2905 ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \ 2906 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ 2907 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ 2908 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ 2909 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \ 2910 || \ 2911 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \ 2912 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ 2913 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ 2914 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ 2915 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))) 2916 2917 #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\ 2918 (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \ 2919 ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW)) 2920 2921 #define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU) 2922 2923 #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\ 2924 (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ 2925 ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ 2926 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ 2927 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ 2928 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ 2929 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ 2930 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ 2931 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ 2932 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ 2933 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ 2934 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ 2935 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ 2936 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1) || \ 2937 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2) || \ 2938 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2) || \ 2939 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3) || \ 2940 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1) || \ 2941 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2) || \ 2942 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3) || \ 2943 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4) || \ 2944 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4) || \ 2945 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ 2946 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ 2947 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ 2948 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ 2949 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ 2950 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ 2951 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ 2952 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ 2953 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ 2954 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ 2955 ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) 2956 2957 #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\ 2958 (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ 2959 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ 2960 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ 2961 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ 2962 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ 2963 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ 2964 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ 2965 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ 2966 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ 2967 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ 2968 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ 2969 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ 2970 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1) || \ 2971 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2) || \ 2972 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2) || \ 2973 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3) || \ 2974 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1) || \ 2975 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2) || \ 2976 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3) || \ 2977 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4) || \ 2978 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4) || \ 2979 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ 2980 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ 2981 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ 2982 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ 2983 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ 2984 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ 2985 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ 2986 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ 2987 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ 2988 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ 2989 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) 2990 2991 #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\ 2992 (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \ 2993 ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE)) 2994 2995 #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\ 2996 (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \ 2997 ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE)) 2998 2999 #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\ 3000 (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \ 3001 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \ 3002 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \ 3003 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ)) 3004 3005 #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\ 3006 (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \ 3007 ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED)) 3008 3009 #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\ 3010 (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ 3011 ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) 3012 3013 #define IS_HRTIM_OUTPUTBALANCEDIDLE(OUTPUTBIAR)\ 3014 (((OUTPUTBIAR) == HRTIM_OUTPUTBIAR_DISABLED) || \ 3015 ((OUTPUTBIAR) == HRTIM_OUTPUTBIAR_ENABLED)) 3016 3017 #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \ 3018 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ 3019 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \ 3020 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \ 3021 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \ 3022 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) || \ 3023 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) || \ 3024 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) || \ 3025 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) || \ 3026 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) || \ 3027 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) || \ 3028 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) || \ 3029 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \ 3030 || \ 3031 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ 3032 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 3033 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 3034 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 3035 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 3036 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 3037 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 3038 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 3039 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 3040 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 3041 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 3042 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 3043 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ 3044 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 3045 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 3046 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 3047 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 3048 || \ 3049 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ 3050 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 3051 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 3052 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 3053 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 3054 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 3055 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 3056 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 3057 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 3058 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 3059 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 3060 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 3061 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ 3062 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 3063 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 3064 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 3065 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 3066 || \ 3067 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ 3068 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 3069 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 3070 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 3071 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 3072 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 3073 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 3074 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 3075 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 3076 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 3077 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 3078 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 3079 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ 3080 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 3081 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 3082 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 3083 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 3084 || \ 3085 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ 3086 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 3087 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 3088 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 3089 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 3090 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 3091 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 3092 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 3093 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 3094 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 3095 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 3096 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 3097 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 3098 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 3099 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 3100 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 3101 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 3102 || \ 3103 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ 3104 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 3105 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 3106 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 3107 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 3108 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 3109 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 3110 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 3111 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 3112 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 3113 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 3114 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 3115 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 3116 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 3117 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 3118 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 3119 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))) \ 3120 || \ 3121 (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && \ 3122 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 3123 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 3124 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 3125 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 3126 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 3127 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 3128 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 3129 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 3130 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 3131 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 3132 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 3133 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 3134 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 3135 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 3136 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 3137 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ 3138 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 3139 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 3140 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 3141 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))) 3142 3143 #define IS_HRTIM_TIMER_CAPTUREFTRIGGER(TIMER, CAPTUREFTRIGGER) \ 3144 ( ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_NONE) || \ 3145 ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TF1_SET) || \ 3146 ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TF1_RESET) || \ 3147 ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TIMERF_CMP1) || \ 3148 ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TIMERF_CMP2)) 3149 3150 #define IS_HRTIM_TIMEVENTFILTER(TIMER,TIMEVENTFILTER)\ 3151 (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_NONE) || \ 3152 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP1) || \ 3153 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP2) || \ 3154 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP3) || \ 3155 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP4) || \ 3156 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGCMP2) || \ 3157 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGCMP3) || \ 3158 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGTIM) \ 3159 || \ 3160 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ 3161 (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF1_TIMBCMP1) || \ 3162 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF2_TIMBCMP4) || \ 3163 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF3_TIMBOUT2) || \ 3164 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF4_TIMCCMP1) || \ 3165 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF5_TIMCCMP4) || \ 3166 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF6_TIMFCMP1) || \ 3167 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF7_TIMDCMP1) || \ 3168 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF8_TIMECMP2))) \ 3169 || \ 3170 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ 3171 (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF1_TIMACMP1) || \ 3172 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF2_TIMACMP4) || \ 3173 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF3_TIMAOUT2) || \ 3174 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF4_TIMCCMP1) || \ 3175 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF5_TIMCCMP2) || \ 3176 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF6_TIMFCMP2) || \ 3177 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF7_TIMDCMP2) || \ 3178 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF8_TIMECMP1))) \ 3179 || \ 3180 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ 3181 (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF1_TIMACMP2) || \ 3182 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF2_TIMBCMP1) || \ 3183 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF3_TIMBCMP4) || \ 3184 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF4_TIMFCMP1) || \ 3185 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF5_TIMDCMP1) || \ 3186 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF6_TIMDCMP4) || \ 3187 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF7_TIMDOUT2) || \ 3188 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF8_TIMECMP4))) \ 3189 || \ 3190 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ 3191 (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF1_TIMACMP1) || \ 3192 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF2_TIMBCMP2) || \ 3193 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF3_TIMCCMP1) || \ 3194 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF4_TIMCCMP2) || \ 3195 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF5_TIMCOUT2) || \ 3196 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF6_TIMECMP1) || \ 3197 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF7_TIMECMP4) || \ 3198 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF8_TIMFCMP4))) \ 3199 || \ 3200 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ 3201 (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF1_TIMACMP2) || \ 3202 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF2_TIMBCMP1) || \ 3203 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF3_TIMCCMP1) || \ 3204 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF4_TIMFCMP4) || \ 3205 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF5_TIMFOUT2) || \ 3206 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF6_TIMDCMP1) || \ 3207 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF7_TIMDCMP4) || \ 3208 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF8_TIMDOUT2))) \ 3209 || \ 3210 (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && \ 3211 (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF1_TIMACMP4) || \ 3212 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF2_TIMBCMP2) || \ 3213 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF3_TIMCCMP4) || \ 3214 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF4_TIMDCMP2) || \ 3215 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF5_TIMDCMP4) || \ 3216 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF6_TIMECMP1) || \ 3217 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF7_TIMECMP4) || \ 3218 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF8_TIMEOUT2)))) 3219 3220 #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\ 3221 (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ 3222 ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) 3223 3224 #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\ 3225 (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \ 3226 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \ 3227 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \ 3228 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ 3229 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \ 3230 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ 3231 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ 3232 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16)) 3233 3234 #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\ 3235 (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ 3236 ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) 3237 3238 #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\ 3239 (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ 3240 ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) 3241 3242 #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\ 3243 (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \ 3244 ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY)) 3245 3246 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\ 3247 (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \ 3248 ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE)) 3249 3250 #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\ 3251 (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \ 3252 ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY)) 3253 3254 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\ 3255 (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \ 3256 ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY)) 3257 3258 #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\ 3259 (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \ 3260 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \ 3261 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \ 3262 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \ 3263 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \ 3264 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \ 3265 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \ 3266 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \ 3267 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \ 3268 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \ 3269 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \ 3270 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \ 3271 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \ 3272 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \ 3273 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \ 3274 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256)) 3275 3276 #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\ 3277 (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \ 3278 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \ 3279 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \ 3280 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \ 3281 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \ 3282 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \ 3283 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \ 3284 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875)) 3285 3286 #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\ 3287 (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \ 3288 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \ 3289 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \ 3290 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \ 3291 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \ 3292 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \ 3293 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \ 3294 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \ 3295 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \ 3296 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \ 3297 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \ 3298 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \ 3299 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \ 3300 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \ 3301 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \ 3302 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256)) 3303 3304 #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\ 3305 (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \ 3306 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \ 3307 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT)) 3308 3309 #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\ 3310 (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \ 3311 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \ 3312 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \ 3313 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1)) 3314 3315 #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\ 3316 (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \ 3317 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ 3318 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) 3319 3320 #define IS_HRTIM_EVENTSRC(EVENT, EVENTSRC) \ 3321 ((((EVENT) == HRTIM_EVENT_1) && \ 3322 (((EVENTSRC) == HRTIM_EEV1SRC_GPIO ) || \ 3323 ((EVENTSRC) == HRTIM_EEV1SRC_COMP2_OUT ) || \ 3324 ((EVENTSRC) == HRTIM_EEV1SRC_TIM1_TRGO ) || \ 3325 ((EVENTSRC) == HRTIM_EEV1SRC_ADC1_AWD1 ))) \ 3326 || \ 3327 (((EVENT) == HRTIM_EVENT_2) && \ 3328 (((EVENTSRC) == HRTIM_EEV2SRC_GPIO ) || \ 3329 ((EVENTSRC) == HRTIM_EEV2SRC_COMP4_OUT ) || \ 3330 ((EVENTSRC) == HRTIM_EEV2SRC_TIM2_TRGO ) || \ 3331 ((EVENTSRC) == HRTIM_EEV2SRC_ADC1_AWD2 ))) \ 3332 || \ 3333 (((EVENT) == HRTIM_EVENT_3) && \ 3334 (((EVENTSRC) == HRTIM_EEV3SRC_GPIO ) || \ 3335 ((EVENTSRC) == HRTIM_EEV3SRC_COMP6_OUT ) || \ 3336 ((EVENTSRC) == HRTIM_EEV3SRC_TIM3_TRGO ) || \ 3337 ((EVENTSRC) == HRTIM_EEV3SRC_ADC1_AWD3 ))) \ 3338 || \ 3339 (((EVENT) == HRTIM_EVENT_4) && \ 3340 (((EVENTSRC) == HRTIM_EEV4SRC_GPIO ) || \ 3341 ((EVENTSRC) == HRTIM_EEV4SRC_COMP1_OUT ) || \ 3342 ((EVENTSRC) == HRTIM_EEV4SRC_COMP5_OUT ) || \ 3343 ((EVENTSRC) == HRTIM_EEV4SRC_ADC2_AWD1 ))) \ 3344 || \ 3345 (((EVENT) == HRTIM_EVENT_5) && \ 3346 (((EVENTSRC) == HRTIM_EEV5SRC_GPIO ) || \ 3347 ((EVENTSRC) == HRTIM_EEV5SRC_COMP3_OUT ) || \ 3348 ((EVENTSRC) == HRTIM_EEV5SRC_COMP7_OUT ) || \ 3349 ((EVENTSRC) == HRTIM_EEV5SRC_ADC2_AWD2 ))) \ 3350 || \ 3351 (((EVENT) == HRTIM_EVENT_6) && \ 3352 (((EVENTSRC) == HRTIM_EEV6SRC_GPIO ) || \ 3353 ((EVENTSRC) == HRTIM_EEV6SRC_COMP2_OUT ) || \ 3354 ((EVENTSRC) == HRTIM_EEV6SRC_COMP1_OUT ) || \ 3355 ((EVENTSRC) == HRTIM_EEV6SRC_ADC2_AWD3 ))) \ 3356 || \ 3357 (((EVENT) == HRTIM_EVENT_7) && \ 3358 (((EVENTSRC) == HRTIM_EEV7SRC_GPIO ) || \ 3359 ((EVENTSRC) == HRTIM_EEV7SRC_COMP4_OUT ) || \ 3360 ((EVENTSRC) == HRTIM_EEV7SRC_TIM7_TRGO ) || \ 3361 ((EVENTSRC) == HRTIM_EEV7SRC_ADC3_AWD1 ))) \ 3362 || \ 3363 (((EVENT) == HRTIM_EVENT_8) && \ 3364 (((EVENTSRC) == HRTIM_EEV8SRC_GPIO ) || \ 3365 ((EVENTSRC) == HRTIM_EEV8SRC_COMP6_OUT ) || \ 3366 ((EVENTSRC) == HRTIM_EEV8SRC_COMP3_OUT ) || \ 3367 ((EVENTSRC) == HRTIM_EEV8SRC_ADC4_AWD1 ))) \ 3368 || \ 3369 (((EVENT) == HRTIM_EVENT_9) && \ 3370 (((EVENTSRC) == HRTIM_EEV9SRC_GPIO ) || \ 3371 ((EVENTSRC) == HRTIM_EEV9SRC_COMP5_OUT ) || \ 3372 ((EVENTSRC) == HRTIM_EEV9SRC_TIM15_TRGO) || \ 3373 ((EVENTSRC) == HRTIM_EEV9SRC_COMP4_OUT ))) \ 3374 || \ 3375 (((EVENT) == HRTIM_EVENT_10) && \ 3376 (((EVENTSRC) == HRTIM_EEV10SRC_GPIO ) || \ 3377 ((EVENTSRC) == HRTIM_EEV10SRC_COMP7_OUT) || \ 3378 ((EVENTSRC) == HRTIM_EEV10SRC_TIM6_TRGO) || \ 3379 ((EVENTSRC) == HRTIM_EEV10SRC_ADC5_AWD1)))) 3380 3381 #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\ 3382 ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \ 3383 (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \ 3384 ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \ 3385 || \ 3386 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ 3387 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \ 3388 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))) 3389 3390 #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\ 3391 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \ 3392 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ 3393 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \ 3394 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)) 3395 3396 #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\ 3397 (((((EVENT) == HRTIM_EVENT_1) || \ 3398 ((EVENT) == HRTIM_EVENT_2) || \ 3399 ((EVENT) == HRTIM_EVENT_3) || \ 3400 ((EVENT) == HRTIM_EVENT_4) || \ 3401 ((EVENT) == HRTIM_EVENT_5)) && \ 3402 (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \ 3403 ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \ 3404 || \ 3405 (((EVENT) == HRTIM_EVENT_6) || \ 3406 ((EVENT) == HRTIM_EVENT_7) || \ 3407 ((EVENT) == HRTIM_EVENT_8) || \ 3408 ((EVENT) == HRTIM_EVENT_9) || \ 3409 ((EVENT) == HRTIM_EVENT_10))) 3410 3411 3412 #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\ 3413 ((((EVENT) == HRTIM_EVENT_1) || \ 3414 ((EVENT) == HRTIM_EVENT_2) || \ 3415 ((EVENT) == HRTIM_EVENT_3) || \ 3416 ((EVENT) == HRTIM_EVENT_4) || \ 3417 ((EVENT) == HRTIM_EVENT_5)) \ 3418 || \ 3419 ((((EVENT) == HRTIM_EVENT_6) || \ 3420 ((EVENT) == HRTIM_EVENT_7) || \ 3421 ((EVENT) == HRTIM_EVENT_8) || \ 3422 ((EVENT) == HRTIM_EVENT_9) || \ 3423 ((EVENT) == HRTIM_EVENT_10)) && \ 3424 (((FILTER) == HRTIM_EVENTFILTER_NONE) || \ 3425 ((FILTER) == HRTIM_EVENTFILTER_1) || \ 3426 ((FILTER) == HRTIM_EVENTFILTER_2) || \ 3427 ((FILTER) == HRTIM_EVENTFILTER_3) || \ 3428 ((FILTER) == HRTIM_EVENTFILTER_4) || \ 3429 ((FILTER) == HRTIM_EVENTFILTER_5) || \ 3430 ((FILTER) == HRTIM_EVENTFILTER_6) || \ 3431 ((FILTER) == HRTIM_EVENTFILTER_7) || \ 3432 ((FILTER) == HRTIM_EVENTFILTER_8) || \ 3433 ((FILTER) == HRTIM_EVENTFILTER_9) || \ 3434 ((FILTER) == HRTIM_EVENTFILTER_10) || \ 3435 ((FILTER) == HRTIM_EVENTFILTER_11) || \ 3436 ((FILTER) == HRTIM_EVENTFILTER_12) || \ 3437 ((FILTER) == HRTIM_EVENTFILTER_13) || \ 3438 ((FILTER) == HRTIM_EVENTFILTER_14) || \ 3439 ((FILTER) == HRTIM_EVENTFILTER_15)))) 3440 3441 #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\ 3442 (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ 3443 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ 3444 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ 3445 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) 3446 3447 #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\ 3448 (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ 3449 ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL) || \ 3450 ((FAULTSOURCE) == HRTIM_FAULTSOURCE_EEVINPUT)) 3451 3452 #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\ 3453 (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ 3454 ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) 3455 3456 #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\ 3457 (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ 3458 ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) 3459 3460 #define IS_HRTIM_FAULTBLANKNGMODE(FAULTBLANKINGMODE)\ 3461 (((FAULTBLANKINGMODE) == HRTIM_FAULTBLANKINGMODE_RSTALIGNED) || \ 3462 ((FAULTBLANKINGMODE) == HRTIM_FAULTBLANKINGMODE_MOVING)) 3463 3464 #define IS_HRTIM_FAULTBLANKING(FAULTBLANKINGCTL)\ 3465 (((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKING_DISABLED) || \ 3466 ((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKING_ENABLED)) 3467 3468 #define IS_HRTIM_FAULTCOUNTERRST(HRTIM_FAULTCOUNTERRST)\ 3469 (((HRTIM_FAULTCOUNTERRST) == HRTIM_FAULTCOUNTERRST_UNCONDITIONAL) || \ 3470 ((HRTIM_FAULTCOUNTERRST) == HRTIM_FAULTCOUNTERRST_CONDITIONAL)) 3471 3472 #define IS_HRTIM_FAULTBLANKINGCTL(FAULTBLANKINGCTL)\ 3473 (((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKINGCTL_DISABLED) || \ 3474 ((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKINGCTL_ENABLED)) 3475 3476 #define IS_HRTIM_FAULTCOUNTER(FAULTCOUNTER)\ 3477 (((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_NONE) || \ 3478 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_1) || \ 3479 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_2) || \ 3480 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_3) || \ 3481 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_4) || \ 3482 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_5) || \ 3483 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_6) || \ 3484 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_7) || \ 3485 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_8) || \ 3486 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_9) || \ 3487 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_10) || \ 3488 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_11) || \ 3489 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_12) || \ 3490 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_13) || \ 3491 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_14) || \ 3492 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_15)) 3493 3494 #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\ 3495 (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ 3496 ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ 3497 ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \ 3498 ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \ 3499 ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \ 3500 ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \ 3501 ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \ 3502 ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \ 3503 ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \ 3504 ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \ 3505 ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \ 3506 ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \ 3507 ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \ 3508 ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \ 3509 ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \ 3510 ((FAULTFILTER) == HRTIM_FAULTFILTER_15)) 3511 3512 #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\ 3513 (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \ 3514 ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY)) 3515 3516 #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\ 3517 (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \ 3518 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \ 3519 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \ 3520 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8)) 3521 3522 #define IS_HRTIM_BURSTMODE(BURSTMODE)\ 3523 (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \ 3524 ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS)) 3525 3526 #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\ 3527 (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \ 3528 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \ 3529 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \ 3530 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \ 3531 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \ 3532 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \ 3533 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_F) || \ 3534 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \ 3535 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \ 3536 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \ 3537 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM)) 3538 3539 #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\ 3540 (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \ 3541 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \ 3542 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \ 3543 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \ 3544 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \ 3545 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \ 3546 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \ 3547 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \ 3548 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \ 3549 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \ 3550 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \ 3551 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \ 3552 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \ 3553 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \ 3554 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \ 3555 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768)) 3556 3557 #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\ 3558 (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \ 3559 ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED)) 3560 3561 #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\ 3562 (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \ 3563 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \ 3564 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \ 3565 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \ 3566 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \ 3567 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \ 3568 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \ 3569 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \ 3570 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \ 3571 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \ 3572 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \ 3573 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \ 3574 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \ 3575 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \ 3576 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \ 3577 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \ 3578 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \ 3579 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \ 3580 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERF_RESET) || \ 3581 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \ 3582 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \ 3583 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERF_REPETITION) || \ 3584 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \ 3585 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERF_CMP1) || \ 3586 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \ 3587 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \ 3588 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \ 3589 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \ 3590 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \ 3591 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \ 3592 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \ 3593 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP)) 3594 3595 #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\ 3596 (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \ 3597 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \ 3598 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ 3599 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ 3600 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ 3601 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E) || \ 3602 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_F)) 3603 3604 #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\ 3605 (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ 3606 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_0) || \ 3607 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_1) || \ 3608 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_2) || \ 3609 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_3)) 3610 3611 #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \ 3612 ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \ 3613 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ 3614 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ 3615 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ 3616 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ 3617 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ 3618 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U))) 3619 3620 #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\ 3621 (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ 3622 ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) 3623 3624 #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFF80U) == 0x00000000U) 3625 3626 #define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFF80FFU) == 0x00000000U) 3627 3628 #define IS_HRTIM_TIMERSWAP(TIMERSWAP) (((TIMERSWAP) & 0xFFC0FFFFU) == 0x00000000U) 3629 3630 #define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFF80U) == 0x00000000U) 3631 3632 #define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U) 3633 3634 3635 #define IS_HRTIM_TIM_IT(TIM_IT) (((TIM_IT) & 0xFFFF8020U) == 0x00000000U) 3636 3637 3638 #define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U) 3639 3640 #define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U) 3641 /** 3642 * @} 3643 */ 3644 3645 /* Exported macros -----------------------------------------------------------*/ 3646 /** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros 3647 * @{ 3648 */ 3649 3650 /** 3651 * @brief configures the actual direction of the counter to UP counting mode 3652 * @param __HANDLE__ : HRTIM handle. 3653 * @param __TIMER__ : Timer index 3654 * This parameter can be a combination of the following values: 3655 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A 3656 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B 3657 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C 3658 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D 3659 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E 3660 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F 3661 * @retval none 3662 */ 3663 #define __HAL_HRTIM_COUNTER_MODE_UP(__HANDLE__, __TIMERS__)\ 3664 do {\ 3665 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\ 3666 {\ 3667 CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_A)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3668 }\ 3669 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ 3670 {\ 3671 CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_B)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3672 }\ 3673 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\ 3674 {\ 3675 CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_C)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3676 }\ 3677 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\ 3678 {\ 3679 CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_D)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3680 }\ 3681 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\ 3682 {\ 3683 CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_E)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3684 }\ 3685 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\ 3686 {\ 3687 CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_F)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3688 }\ 3689 } while(0U) 3690 3691 /** 3692 * @brief configures the actual direction of the counter to UP-DOWN counting mode 3693 * @param __HANDLE__ : HRTIM handle. 3694 * @param __TIMER__ : Timer index 3695 * This parameter can be a combination of the following values: 3696 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A 3697 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B 3698 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C 3699 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D 3700 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E 3701 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F 3702 * @retval none 3703 */ 3704 #define __HAL_HRTIM_COUNTER_MODE_UPDOWN(__HANDLE__, __TIMERS__)\ 3705 do {\ 3706 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\ 3707 {\ 3708 SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_A)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3709 }\ 3710 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ 3711 {\ 3712 SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_B)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3713 }\ 3714 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\ 3715 {\ 3716 SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_C)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3717 }\ 3718 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\ 3719 {\ 3720 SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_D)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3721 }\ 3722 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\ 3723 {\ 3724 SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_E)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3725 }\ 3726 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\ 3727 {\ 3728 SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_F)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3729 }\ 3730 } while(0U) 3731 3732 /** 3733 * @brief swap the output of the timer 3734 * HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2, 3735 * HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1 3736 * @param __HANDLE__ : HRTIM handle. 3737 * @param __TIMER__ : Timer index 3738 * This parameter can be a combination of the following values: 3739 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A 3740 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B 3741 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C 3742 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D 3743 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E 3744 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F 3745 * @retval none 3746 */ 3747 #define __HAL_HRTIM_TIMER_OUTPUT_SWAP(__HANDLE__, __TIMERS__)\ 3748 do {\ 3749 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\ 3750 {\ 3751 SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPA)); \ 3752 }\ 3753 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\ 3754 {\ 3755 SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPB)); \ 3756 }\ 3757 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\ 3758 {\ 3759 SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPC)); \ 3760 }\ 3761 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\ 3762 {\ 3763 SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPD)); \ 3764 }\ 3765 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\ 3766 {\ 3767 SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPE)); \ 3768 }\ 3769 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_F) == HRTIM_TIMERID_TIMER_F)\ 3770 {\ 3771 SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPF)); \ 3772 }\ 3773 } while(0U) 3774 3775 /** 3776 * @brief Un-swap the output of the timer 3777 * HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1, 3778 * HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2 3779 * @param __HANDLE__ : HRTIM handle. 3780 * @param __TIMER__ : Timer index 3781 * This parameter can be a combination of the following values: 3782 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A 3783 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B 3784 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C 3785 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D 3786 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E 3787 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F 3788 * @retval none 3789 3790 */ 3791 #define __HAL_HRTIM_TIMER_OUTPUT_NOSWAP(__HANDLE__, __TIMERS__)\ 3792 do {\ 3793 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\ 3794 {\ 3795 CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPA)); \ 3796 }\ 3797 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\ 3798 {\ 3799 CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPB)); \ 3800 }\ 3801 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\ 3802 {\ 3803 CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPC)); \ 3804 }\ 3805 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\ 3806 {\ 3807 CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPD)); \ 3808 }\ 3809 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\ 3810 {\ 3811 CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPE)); \ 3812 }\ 3813 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_F) == HRTIM_TIMERID_TIMER_F)\ 3814 {\ 3815 CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPF)); \ 3816 }\ 3817 } while(0U) 3818 3819 /** @brief Reset HRTIM handle state 3820 * @param __HANDLE__ HRTIM handle. 3821 * @retval None 3822 */ 3823 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 3824 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) do{ \ 3825 (__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \ 3826 (__HANDLE__)->MspInitCallback = NULL; \ 3827 (__HANDLE__)->MspDeInitCallback = NULL; \ 3828 } while(0) 3829 #else 3830 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET) 3831 #endif 3832 3833 /** @brief Enables or disables the timer counter(s) 3834 * @param __HANDLE__ specifies the HRTIM Handle. 3835 * @param __TIMERS__ timers to enable/disable 3836 * This parameter can be any combinations of the following values: 3837 * @arg HRTIM_TIMERID_MASTER: Master timer identifier 3838 * @arg HRTIM_TIMERID_TIMER_A: Timer A identifier 3839 * @arg HRTIM_TIMERID_TIMER_B: Timer B identifier 3840 * @arg HRTIM_TIMERID_TIMER_C: Timer C identifier 3841 * @arg HRTIM_TIMERID_TIMER_D: Timer D identifier 3842 * @arg HRTIM_TIMERID_TIMER_E: Timer E identifier 3843 * @arg HRTIM_TIMERID_TIMER_F: Timer F identifier 3844 * @retval None 3845 */ 3846 #define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__)) 3847 3848 /* The counter of a timing unit is disabled only if all the timer outputs */ 3849 /* are disabled and no capture is configured */ 3850 #define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN) 3851 #define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN) 3852 #define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN) 3853 #define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN) 3854 #define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN) 3855 #define HRTIM_TFOEN_MASK (HRTIM_OENR_TF2OEN | HRTIM_OENR_TF1OEN) 3856 #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\ 3857 do {\ 3858 if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\ 3859 {\ 3860 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\ 3861 }\ 3862 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\ 3863 {\ 3864 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\ 3865 {\ 3866 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\ 3867 }\ 3868 }\ 3869 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\ 3870 {\ 3871 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\ 3872 {\ 3873 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\ 3874 }\ 3875 }\ 3876 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\ 3877 {\ 3878 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\ 3879 {\ 3880 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\ 3881 }\ 3882 }\ 3883 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\ 3884 {\ 3885 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\ 3886 {\ 3887 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\ 3888 }\ 3889 }\ 3890 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\ 3891 {\ 3892 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\ 3893 {\ 3894 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\ 3895 }\ 3896 }\ 3897 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_F) == HRTIM_TIMERID_TIMER_F)\ 3898 {\ 3899 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TFOEN_MASK) == (uint32_t)RESET)\ 3900 {\ 3901 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_F);\ 3902 }\ 3903 }\ 3904 } while(0U) 3905 3906 /** @brief Enables the External Event counter 3907 * @param __HANDLE__ specifies the HRTIM Handle. 3908 * @param __TIMERS__ timers to enable/disable 3909 * This parameter can be one of the following values: 3910 * @arg HRTIM_TIMERINDEX_TIMER_A: Timer A identifier 3911 * @arg HRTIM_TIMERINDEX_TIMER_B: Timer B identifier 3912 * @arg HRTIM_TIMERINDEX_TIMER_C: Timer C identifier 3913 * @arg HRTIM_TIMERINDEX_TIMER_D: Timer D identifier 3914 * @arg HRTIM_TIMERINDEX_TIMER_E: Timer E identifier 3915 * @arg HRTIM_TIMERINDEX_TIMER_F: Timer F identifier 3916 * @param Event external event Counter A or B for which timer event must be enabled 3917 * This parameter can be one of the following values: 3918 * @arg HRTIM_EVENTCOUNTER_A 3919 * @arg HRTIM_EVENTCOUNTER_B 3920 * @retval None 3921 */ 3922 #define __HAL_HRTIM_EXTERNAL_EVENT_COUNTER_ENABLE(__HANDLE__, __TIMER__, __EVENT__)\ 3923 do {\ 3924 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\ 3925 {\ 3926 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 3927 {\ 3928 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ 3929 }\ 3930 if (((__EVENT__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ 3931 {\ 3932 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ 3933 }\ 3934 }\ 3935 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ 3936 {\ 3937 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 3938 {\ 3939 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ 3940 }\ 3941 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 3942 {\ 3943 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ 3944 }\ 3945 }\ 3946 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\ 3947 {\ 3948 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 3949 {\ 3950 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ 3951 }\ 3952 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 3953 {\ 3954 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ 3955 }\ 3956 }\ 3957 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\ 3958 {\ 3959 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 3960 {\ 3961 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ 3962 }\ 3963 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 3964 {\ 3965 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ 3966 }\ 3967 }\ 3968 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\ 3969 {\ 3970 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 3971 {\ 3972 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ 3973 }\ 3974 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 3975 {\ 3976 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ 3977 }\ 3978 }\ 3979 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\ 3980 {\ 3981 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 3982 {\ 3983 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ 3984 }\ 3985 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 3986 {\ 3987 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ 3988 }\ 3989 }\ 3990 } while(0U) 3991 3992 /** @brief Disables the External Event counter 3993 * @param __HANDLE__ specifies the HRTIM Handle. 3994 * @param __TIMERS__ timers to enable/disable 3995 * This parameter can be one of the following values: 3996 * @arg HRTIM_TIMERINDEX_TIMER_A: Timer A identifier 3997 * @arg HRTIM_TIMERINDEX_TIMER_B: Timer B identifier 3998 * @arg HRTIM_TIMERINDEX_TIMER_C: Timer C identifier 3999 * @arg HRTIM_TIMERINDEX_TIMER_D: Timer D identifier 4000 * @arg HRTIM_TIMERINDEX_TIMER_E: Timer E identifier 4001 * @arg HRTIM_TIMERINDEX_TIMER_F: Timer F identifier 4002 * @param Event external event A or B for which timer event must be disabled 4003 * This parameter can be one of the following values: 4004 * @arg HRTIM_EVENTCOUNTER_A 4005 * @arg HRTIM_EVENTCOUNTER_B 4006 * @retval None 4007 */ 4008 #define __HAL_HRTIM_EXTERNAL_EVENT_COUNTER_DISABLE(__HANDLE__, __TIMER__, __EVENT__)\ 4009 do {\ 4010 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\ 4011 {\ 4012 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4013 {\ 4014 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ 4015 }\ 4016 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4017 {\ 4018 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ 4019 }\ 4020 }\ 4021 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ 4022 {\ 4023 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4024 {\ 4025 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ 4026 }\ 4027 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4028 {\ 4029 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ 4030 }\ 4031 }\ 4032 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\ 4033 {\ 4034 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4035 {\ 4036 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ 4037 }\ 4038 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4039 {\ 4040 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ 4041 }\ 4042 }\ 4043 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\ 4044 {\ 4045 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4046 {\ 4047 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ 4048 }\ 4049 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4050 {\ 4051 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ 4052 }\ 4053 }\ 4054 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\ 4055 {\ 4056 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4057 {\ 4058 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ 4059 }\ 4060 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4061 {\ 4062 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ 4063 }\ 4064 }\ 4065 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\ 4066 {\ 4067 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4068 {\ 4069 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ 4070 }\ 4071 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4072 {\ 4073 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ 4074 }\ 4075 }\ 4076 } while(0U) 4077 4078 /** @brief Resets the External Event counter 4079 * @param __HANDLE__ specifies the HRTIM Handle. 4080 * @param __TIMERS__ timers to enable/disable 4081 * This parameter can be one of the following values: 4082 * @arg HRTIM_TIMERINDEX_TIMER_A: Timer A identifier 4083 * @arg HRTIM_TIMERINDEX_TIMER_B: Timer B identifier 4084 * @arg HRTIM_TIMERINDEX_TIMER_C: Timer C identifier 4085 * @arg HRTIM_TIMERINDEX_TIMER_D: Timer D identifier 4086 * @arg HRTIM_TIMERINDEX_TIMER_E: Timer E identifier 4087 * @arg HRTIM_TIMERINDEX_TIMER_F: Timer F identifier 4088 * @param Event external event A or B for which timer event must be reset 4089 * This parameter can be one of the following values: 4090 * @arg HRTIM_EVENTCOUNTER_A 4091 * @arg HRTIM_EVENTCOUNTER_B 4092 * @retval None 4093 */ 4094 #define __HAL_HRTIM_EXTERNAL_EVENT_COUNTER_RESET(__HANDLE__, __TIMER__, __EVENT__)\ 4095 do {\ 4096 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\ 4097 {\ 4098 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4099 {\ 4100 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ 4101 }\ 4102 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4103 {\ 4104 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ 4105 }\ 4106 }\ 4107 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ 4108 {\ 4109 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4110 {\ 4111 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ 4112 }\ 4113 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4114 {\ 4115 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ 4116 }\ 4117 }\ 4118 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\ 4119 {\ 4120 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4121 {\ 4122 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ 4123 }\ 4124 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4125 {\ 4126 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ 4127 }\ 4128 }\ 4129 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\ 4130 {\ 4131 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4132 {\ 4133 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ 4134 }\ 4135 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4136 {\ 4137 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ 4138 }\ 4139 }\ 4140 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\ 4141 {\ 4142 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4143 {\ 4144 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ 4145 }\ 4146 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4147 {\ 4148 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ 4149 }\ 4150 }\ 4151 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\ 4152 {\ 4153 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4154 {\ 4155 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ 4156 }\ 4157 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4158 {\ 4159 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ 4160 }\ 4161 }\ 4162 } while(0U) 4163 4164 4165 /** @brief Enables or disables the specified HRTIM common interrupts. 4166 * @param __HANDLE__ specifies the HRTIM Handle. 4167 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 4168 * This parameter can be one of the following values: 4169 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable 4170 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable 4171 * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable 4172 * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable 4173 * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable 4174 * @arg HRTIM_IT_FLT6: Fault 6 interrupt enable 4175 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable 4176 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable 4177 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable 4178 * @retval None 4179 */ 4180 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__)) 4181 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__)) 4182 4183 /** @brief Enables or disables the specified HRTIM Master timer interrupts. 4184 * @param __HANDLE__ specifies the HRTIM Handle. 4185 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 4186 * This parameter can be one of the following values: 4187 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable 4188 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable 4189 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable 4190 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable 4191 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable 4192 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable 4193 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable 4194 * @retval None 4195 */ 4196 #define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__)) 4197 #define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__)) 4198 4199 /** @brief Enables or disables the specified HRTIM Timerx interrupts. 4200 * @param __HANDLE__ specifies the HRTIM Handle. 4201 * @param __TIMER__ specified the timing unit (Timer A to F) 4202 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 4203 * This parameter can be one of the following values: 4204 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable 4205 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable 4206 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable 4207 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable 4208 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable 4209 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable 4210 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable 4211 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable 4212 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable 4213 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable 4214 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable 4215 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable 4216 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable 4217 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable 4218 * @retval None 4219 */ 4220 #define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__)) 4221 #define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__)) 4222 4223 /** @brief Checks if the specified HRTIM common interrupt source is enabled or disabled. 4224 * @param __HANDLE__ specifies the HRTIM Handle. 4225 * @param __INTERRUPT__ specifies the interrupt source to check. 4226 * This parameter can be one of the following values: 4227 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable 4228 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable 4229 * @arg HRTIM_IT_FLT3: Fault 3 enable 4230 * @arg HRTIM_IT_FLT4: Fault 4 enable 4231 * @arg HRTIM_IT_FLT5: Fault 5 enable 4232 * @arg HRTIM_IT_FLT6: Fault 6 enable 4233 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable 4234 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable 4235 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable 4236 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 4237 */ 4238 #define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 4239 4240 /** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled. 4241 * @param __HANDLE__ specifies the HRTIM Handle. 4242 * @param __INTERRUPT__ specifies the interrupt source to check. 4243 * This parameter can be one of the following values: 4244 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable 4245 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable 4246 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable 4247 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable 4248 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable 4249 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable 4250 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable 4251 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 4252 */ 4253 #define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 4254 4255 /** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled. 4256 * @param __HANDLE__ specifies the HRTIM Handle. 4257 * @param __TIMER__ specified the timing unit (Timer A to F) 4258 * @param __INTERRUPT__ specifies the interrupt source to check. 4259 * This parameter can be one of the following values: 4260 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable 4261 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable 4262 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable 4263 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable 4264 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable 4265 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable 4266 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable 4267 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable 4268 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable 4269 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable 4270 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable 4271 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable 4272 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable 4273 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable 4274 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable 4275 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable 4276 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable 4277 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable 4278 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable 4279 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable 4280 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable 4281 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 4282 */ 4283 #define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 4284 4285 /** @brief Clears the specified HRTIM common pending flag. 4286 * @param __HANDLE__ specifies the HRTIM Handle. 4287 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 4288 * This parameter can be one of the following values: 4289 * @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag 4290 * @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag 4291 * @arg HRTIM_IT_FLT3: Fault 3 clear flag 4292 * @arg HRTIM_IT_FLT4: Fault 4 clear flag 4293 * @arg HRTIM_IT_FLT5: Fault 5 clear flag 4294 * @arg HRTIM_IT_FLT6: Fault 6 clear flag 4295 * @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag 4296 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt clear flag 4297 * @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag 4298 * @retval None 4299 */ 4300 #define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__)) 4301 4302 /** @brief Clears the specified HRTIM Master pending flag. 4303 * @param __HANDLE__ specifies the HRTIM Handle. 4304 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 4305 * This parameter can be one of the following values: 4306 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag 4307 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag 4308 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag 4309 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag 4310 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag 4311 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag 4312 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag 4313 * @retval None 4314 */ 4315 #define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__)) 4316 4317 /** @brief Clears the specified HRTIM Timerx pending flag. 4318 * @param __HANDLE__ specifies the HRTIM Handle. 4319 * @param __TIMER__ specified the timing unit (Timer A to F) 4320 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 4321 * This parameter can be one of the following values: 4322 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag 4323 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag 4324 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag 4325 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag 4326 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag 4327 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag 4328 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag 4329 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag 4330 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag 4331 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag 4332 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag 4333 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag 4334 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag 4335 * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag 4336 * @retval None 4337 */ 4338 #define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__)) 4339 4340 /* DMA HANDLING */ 4341 /** @brief Enables or disables the specified HRTIM Master timer DMA requests. 4342 * @param __HANDLE__ specifies the HRTIM Handle. 4343 * @param __DMA__ specifies the DMA request to enable or disable. 4344 * This parameter can be one of the following values: 4345 * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request enable 4346 * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request enable 4347 * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request enable 4348 * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request enable 4349 * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request enable 4350 * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request enable 4351 * @arg HRTIM_MASTER_DMA_MUPD: Master update DMA request enable 4352 * @retval None 4353 */ 4354 #define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__)) 4355 #define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__)) 4356 4357 /** @brief Enables or disables the specified HRTIM Timerx DMA requests. 4358 * @param __HANDLE__ specifies the HRTIM Handle. 4359 * @param __TIMER__ specified the timing unit (Timer A to F) 4360 * @param __DMA__ specifies the DMA request to enable or disable. 4361 * This parameter can be one of the following values: 4362 * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request enable 4363 * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request enable 4364 * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request enable 4365 * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request enable 4366 * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request enable 4367 * @arg HRTIM_TIM_DMA_UPD: Timer update DMA request enable 4368 * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request enable 4369 * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request enable 4370 * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request enable 4371 * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request enable 4372 * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request enable 4373 * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request enable 4374 * @arg HRTIM_TIM_DMA_RST: Timer reset DMA request enable 4375 * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request enable 4376 * @retval None 4377 */ 4378 #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__)) 4379 #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__)) 4380 4381 #define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__)) 4382 #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__)) 4383 4384 #define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__)) 4385 #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__)) 4386 4387 #define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__)) 4388 #define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__)) 4389 4390 /** @brief Sets the HRTIM timer Counter Register value on runtime 4391 * @param __HANDLE__ HRTIM Handle. 4392 * @param __TIMER__ HRTIM timer 4393 * This parameter can be one of the following values: 4394 * @arg 0x6 for master timer 4395 * @arg 0x0 to 0x5 for timers A to F 4396 * @param __COUNTER__ specifies the Counter Register new value. 4397 * @retval None 4398 */ 4399 #define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \ 4400 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\ 4401 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__))) 4402 4403 /** @brief Gets the HRTIM timer Counter Register value on runtime 4404 * @param __HANDLE__ HRTIM Handle. 4405 * @param __TIMER__ HRTIM timer 4406 * This parameter can be one of the following values: 4407 * @arg 0x6 for master timer 4408 * @arg 0x0 to 0x5 for timers A to F 4409 * @retval HRTIM timer Counter Register value 4410 */ 4411 #define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \ 4412 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\ 4413 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR)) 4414 4415 /** @brief Sets the HRTIM timer Period value on runtime 4416 * @param __HANDLE__ HRTIM Handle. 4417 * @param __TIMER__ HRTIM timer 4418 * This parameter can be one of the following values: 4419 * @arg 0x6 for master timer 4420 * @arg 0x0 to 0x5 for timers A to F 4421 * @param __PERIOD__ specifies the Period Register new value. 4422 * @retval None 4423 */ 4424 #define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \ 4425 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\ 4426 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__))) 4427 4428 /** @brief Gets the HRTIM timer Period Register value on runtime 4429 * @param __HANDLE__ HRTIM Handle. 4430 * @param __TIMER__ HRTIM timer 4431 * This parameter can be one of the following values: 4432 * @arg 0x6 for master timer 4433 * @arg 0x0 to 0x5 for timers A to F 4434 * @retval timer Period Register 4435 */ 4436 #define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \ 4437 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\ 4438 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR)) 4439 4440 /** @brief Sets the HRTIM timer clock prescaler value on runtime 4441 * @param __HANDLE__ HRTIM Handle. 4442 * @param __TIMER__ HRTIM timer 4443 * This parameter can be one of the following values: 4444 * @arg 0x6 for master timer 4445 * @arg 0x0 to 0x5 for timers A to F 4446 * @param __PRESCALER__ specifies the clock prescaler new value. 4447 * This parameter can be one of the following values: 4448 * @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) 4449 * @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) 4450 * @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) 4451 * @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) 4452 * @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) 4453 * @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) 4454 * @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) 4455 * @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) 4456 * @retval None 4457 */ 4458 #define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \ 4459 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? (MODIFY_REG((__HANDLE__)->Instance->sMasterRegs.MCR, HRTIM_MCR_CK_PSC, (__PRESCALER__))) :\ 4460 (MODIFY_REG((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR, HRTIM_TIMCR_CK_PSC, (__PRESCALER__)))) 4461 4462 /** @brief Gets the HRTIM timer clock prescaler value on runtime 4463 * @param __HANDLE__ HRTIM Handle. 4464 * @param __TIMER__ HRTIM timer 4465 * This parameter can be one of the following values: 4466 * @arg 0x6 for master timer 4467 * @arg 0x0 to 0x5 for timers A to F 4468 * @retval timer clock prescaler value 4469 */ 4470 #define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \ 4471 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\ 4472 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR & HRTIM_TIMCR_CK_PSC)) 4473 4474 /** @brief Sets the HRTIM timer Compare Register value on runtime 4475 * @param __HANDLE__ HRTIM Handle. 4476 * @param __TIMER__ HRTIM timer 4477 * This parameter can be one of the following values: 4478 * @arg 0x0 to 0x5 for timers A to F 4479 * @param __COMPAREUNIT__ timer compare unit 4480 * This parameter can be one of the following values: 4481 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1 4482 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2 4483 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3 4484 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4 4485 * @param __COMPARE__ specifies the Compare new value. 4486 * @retval None 4487 */ 4488 #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \ 4489 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ 4490 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\ 4491 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\ 4492 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\ 4493 ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \ 4494 : \ 4495 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\ 4496 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\ 4497 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\ 4498 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__)))) 4499 4500 /** @brief Gets the HRTIM timer Compare Register value on runtime 4501 * @param __HANDLE__ HRTIM Handle. 4502 * @param __TIMER__ HRTIM timer 4503 * This parameter can be one of the following values: 4504 * @arg 0x0 to 0x5 for timers A to F 4505 * @param __COMPAREUNIT__ timer compare unit 4506 * This parameter can be one of the following values: 4507 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1 4508 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2 4509 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3 4510 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4 4511 * @retval Compare value 4512 */ 4513 #define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \ 4514 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ 4515 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\ 4516 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\ 4517 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\ 4518 ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \ 4519 : \ 4520 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\ 4521 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\ 4522 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\ 4523 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR))) 4524 4525 /** 4526 * @brief Enables the Fault Counter 4527 * @param hhrtim pointer to HAL HRTIM handle 4528 * @param Fault fault input to enable 4529 * This parameter can be one of the following values: 4530 * @arg HRTIM_FAULT_1: Fault input 1 4531 * @arg HRTIM_FAULT_2: Fault input 2 4532 * @arg HRTIM_FAULT_3: Fault input 3 4533 * @arg HRTIM_FAULT_4: Fault input 4 4534 * @arg HRTIM_FAULT_5: Fault input 5 4535 * @arg HRTIM_FAULT_6: Fault input 6 4536 * @note This function must be called when fault is not enabled 4537 * @retval HAL status 4538 */ 4539 #define __HAL_HRTIM_FAULT_BLANKING_ENABLE(__HANDLE__, __FAULT__)\ 4540 do {\ 4541 if (((__FAULT__) & HRTIM_FAULT_1) == HRTIM_FAULT_1)\ 4542 {\ 4543 ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT1BLKE;\ 4544 }\ 4545 if (((__FAULT__) & HRTIM_FAULT_2) == HRTIM_FAULT_2)\ 4546 {\ 4547 ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT2BLKE;\ 4548 }\ 4549 if (((__FAULT__) & HRTIM_FAULT_3) == HRTIM_FAULT_3)\ 4550 {\ 4551 ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT3BLKE;\ 4552 }\ 4553 if (((__FAULT__) & HRTIM_FAULT_4) == HRTIM_FAULT_4)\ 4554 {\ 4555 ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT4BLKE;\ 4556 }\ 4557 if (((__FAULT__) & HRTIM_FAULT_5) == HRTIM_FAULT_5)\ 4558 {\ 4559 ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) |= HRTIM_FLTINR4_FLT5BLKE;\ 4560 }\ 4561 if (((__FAULT__) & HRTIM_FAULT_6) == HRTIM_FAULT_6)\ 4562 {\ 4563 ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) |= HRTIM_FLTINR4_FLT6BLKE;\ 4564 }\ 4565 } while(0U) 4566 4567 /** 4568 * @brief Disables the Fault Counter 4569 * @param hhrtim pointer to HAL HRTIM handle 4570 * @param Fault fault input to disable 4571 * This parameter can be one of the following values: 4572 * @arg HRTIM_FAULT_1: Fault input 1 4573 * @arg HRTIM_FAULT_2: Fault input 2 4574 * @arg HRTIM_FAULT_3: Fault input 3 4575 * @arg HRTIM_FAULT_4: Fault input 4 4576 * @arg HRTIM_FAULT_5: Fault input 5 4577 * @arg HRTIM_FAULT_6: Fault input 6 4578 * @retval HAL status 4579 */ 4580 #define __HAL_HRTIM_FAULT_BLANKING_DISABLE(__HANDLE__, __FAULT__)\ 4581 do {\ 4582 if (((__FAULT__) & HRTIM_FAULT_1) == HRTIM_FAULT_1)\ 4583 {\ 4584 ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT1BLKE;\ 4585 }\ 4586 if (((__FAULT__) & HRTIM_FAULT_2) == HRTIM_FAULT_2)\ 4587 {\ 4588 ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT2BLKE;\ 4589 }\ 4590 if (((__FAULT__) & HRTIM_FAULT_3) == HRTIM_FAULT_3)\ 4591 {\ 4592 ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT3BLKE;\ 4593 }\ 4594 if (((__FAULT__) & HRTIM_FAULT_4) == HRTIM_FAULT_4)\ 4595 {\ 4596 ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT4BLKE;\ 4597 }\ 4598 if (((__FAULT__) & HRTIM_FAULT_5) == HRTIM_FAULT_5)\ 4599 {\ 4600 ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) &= ~HRTIM_FLTINR4_FLT5BLKE;\ 4601 }\ 4602 if (((__FAULT__) & HRTIM_FAULT_6) == HRTIM_FAULT_6)\ 4603 {\ 4604 ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) &= ~HRTIM_FLTINR4_FLT6BLKE;\ 4605 }\ 4606 } while(0U) 4607 4608 /** 4609 * @} 4610 */ 4611 4612 /* Exported functions --------------------------------------------------------*/ 4613 /** @addtogroup HRTIM_Exported_Functions 4614 * @{ 4615 */ 4616 4617 /** @addtogroup HRTIM_Exported_Functions_Group1 4618 * @{ 4619 */ 4620 4621 /* Initialization and Configuration functions ********************************/ 4622 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim); 4623 4624 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim); 4625 4626 void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim); 4627 4628 void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim); 4629 4630 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, 4631 uint32_t TimerIdx, 4632 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); 4633 4634 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim, 4635 uint32_t CalibrationRate); 4636 4637 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim, 4638 uint32_t CalibrationRate); 4639 4640 HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim, 4641 uint32_t Timeout); 4642 4643 /** 4644 * @} 4645 */ 4646 4647 /** @addtogroup HRTIM_Exported_Functions_Group2 4648 * @{ 4649 */ 4650 4651 /* Simple time base related functions *****************************************/ 4652 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim, 4653 uint32_t TimerIdx); 4654 4655 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim, 4656 uint32_t TimerIdx); 4657 4658 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim, 4659 uint32_t TimerIdx); 4660 4661 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim, 4662 uint32_t TimerIdx); 4663 4664 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim, 4665 uint32_t TimerIdx, 4666 uint32_t SrcAddr, 4667 uint32_t DestAddr, 4668 uint32_t Length); 4669 4670 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim, 4671 uint32_t TimerIdx); 4672 4673 /** 4674 * @} 4675 */ 4676 4677 /** @addtogroup HRTIM_Exported_Functions_Group3 4678 * @{ 4679 */ 4680 /* Simple output compare related functions ************************************/ 4681 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim, 4682 uint32_t TimerIdx, 4683 uint32_t OCChannel, 4684 HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg); 4685 4686 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim, 4687 uint32_t TimerIdx, 4688 uint32_t OCChannel); 4689 4690 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim, 4691 uint32_t TimerIdx, 4692 uint32_t OCChannel); 4693 4694 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim, 4695 uint32_t TimerIdx, 4696 uint32_t OCChannel); 4697 4698 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim, 4699 uint32_t TimerIdx, 4700 uint32_t OCChannel); 4701 4702 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim, 4703 uint32_t TimerIdx, 4704 uint32_t OCChannel, 4705 uint32_t SrcAddr, 4706 uint32_t DestAddr, 4707 uint32_t Length); 4708 4709 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim, 4710 uint32_t TimerIdx, 4711 uint32_t OCChannel); 4712 4713 /** 4714 * @} 4715 */ 4716 4717 /** @addtogroup HRTIM_Exported_Functions_Group4 4718 * @{ 4719 */ 4720 /* Simple PWM output related functions ****************************************/ 4721 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim, 4722 uint32_t TimerIdx, 4723 uint32_t PWMChannel, 4724 HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg); 4725 4726 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim, 4727 uint32_t TimerIdx, 4728 uint32_t PWMChannel); 4729 4730 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim, 4731 uint32_t TimerIdx, 4732 uint32_t PWMChannel); 4733 4734 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim, 4735 uint32_t TimerIdx, 4736 uint32_t PWMChannel); 4737 4738 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim, 4739 uint32_t TimerIdx, 4740 uint32_t PWMChannel); 4741 4742 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim, 4743 uint32_t TimerIdx, 4744 uint32_t PWMChannel, 4745 uint32_t SrcAddr, 4746 uint32_t DestAddr, 4747 uint32_t Length); 4748 4749 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim, 4750 uint32_t TimerIdx, 4751 uint32_t PWMChannel); 4752 4753 /** 4754 * @} 4755 */ 4756 4757 /** @addtogroup HRTIM_Exported_Functions_Group5 4758 * @{ 4759 */ 4760 /* Simple capture related functions *******************************************/ 4761 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim, 4762 uint32_t TimerIdx, 4763 uint32_t CaptureChannel, 4764 HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg); 4765 4766 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim, 4767 uint32_t TimerIdx, 4768 uint32_t CaptureChannel); 4769 4770 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim, 4771 uint32_t TimerIdx, 4772 uint32_t CaptureChannel); 4773 4774 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim, 4775 uint32_t TimerIdx, 4776 uint32_t CaptureChannel); 4777 4778 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim, 4779 uint32_t TimerIdx, 4780 uint32_t CaptureChannel); 4781 4782 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim, 4783 uint32_t TimerIdx, 4784 uint32_t CaptureChannel, 4785 uint32_t SrcAddr, 4786 uint32_t DestAddr, 4787 uint32_t Length); 4788 4789 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim, 4790 uint32_t TimerIdx, 4791 uint32_t CaptureChannel); 4792 4793 /** 4794 * @} 4795 */ 4796 4797 /** @addtogroup HRTIM_Exported_Functions_Group6 4798 * @{ 4799 */ 4800 /* Simple one pulse related functions *****************************************/ 4801 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim, 4802 uint32_t TimerIdx, 4803 uint32_t OnePulseChannel, 4804 HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg); 4805 4806 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim, 4807 uint32_t TimerIdx, 4808 uint32_t OnePulseChannel); 4809 4810 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim, 4811 uint32_t TimerIdx, 4812 uint32_t OnePulseChannel); 4813 4814 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim, 4815 uint32_t TimerIdx, 4816 uint32_t OnePulseChannel); 4817 4818 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim, 4819 uint32_t TimerIdx, 4820 uint32_t OnePulseChannel); 4821 4822 /** 4823 * @} 4824 */ 4825 4826 /** @addtogroup HRTIM_Exported_Functions_Group7 4827 * @{ 4828 */ 4829 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim, 4830 HRTIM_BurstModeCfgTypeDef* pBurstModeCfg); 4831 4832 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, 4833 uint32_t Event, 4834 HRTIM_EventCfgTypeDef* pEventCfg); 4835 4836 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, 4837 uint32_t Prescaler); 4838 4839 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim, 4840 uint32_t Fault, 4841 HRTIM_FaultCfgTypeDef* pFaultCfg); 4842 4843 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, 4844 uint32_t Prescaler); 4845 4846 HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef * hhrtim, 4847 uint32_t Fault, 4848 HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg); 4849 4850 HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef * hhrtim, 4851 uint32_t Fault, 4852 HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg); 4853 4854 HAL_StatusTypeDef HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef * hhrtim, 4855 uint32_t Fault); 4856 4857 HAL_StatusTypeDef HAL_HRTIM_SwapTimerOutput(HRTIM_HandleTypeDef * hhrtim, 4858 uint32_t Timers); 4859 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, 4860 uint32_t Faults, 4861 uint32_t Enable); 4862 4863 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, 4864 uint32_t ADCTrigger, 4865 HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg); 4866 4867 HAL_StatusTypeDef HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef * hhrtim, 4868 uint32_t ADCTrigger, 4869 uint32_t Postscaler); 4870 4871 HAL_StatusTypeDef HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef * hhrtim, 4872 uint32_t TimerIdx, 4873 uint32_t RollOverCfg); 4874 4875 HAL_StatusTypeDef HAL_HRTIM_OutputSwapEnable(HRTIM_HandleTypeDef * hhrtim, 4876 uint32_t Timers); 4877 4878 HAL_StatusTypeDef HAL_HRTIM_OutputSwapDisable(HRTIM_HandleTypeDef * hhrtim, 4879 uint32_t Timers); 4880 /** 4881 * @} 4882 */ 4883 4884 /** @addtogroup HRTIM_Exported_Functions_Group8 4885 * @{ 4886 */ 4887 /* Waveform related functions *************************************************/ 4888 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, 4889 uint32_t TimerIdx, 4890 HRTIM_TimerCfgTypeDef * pTimerCfg); 4891 4892 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef * hhrtim, 4893 uint32_t TimerIdx, 4894 HRTIM_TimerCtlTypeDef * pTimerCtl); 4895 4896 HAL_StatusTypeDef HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef * hhrtim, 4897 uint32_t TimerIdx, 4898 HRTIM_TimerCtlTypeDef * pTimerCtl); 4899 4900 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, 4901 uint32_t TimerIdx, 4902 uint32_t CompareUnit, 4903 HRTIM_CompareCfgTypeDef* pCompareCfg); 4904 4905 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim, 4906 uint32_t TimerIdx, 4907 uint32_t CaptureUnit, 4908 HRTIM_CaptureCfgTypeDef* pCaptureCfg); 4909 4910 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, 4911 uint32_t TimerIdx, 4912 uint32_t Output, 4913 HRTIM_OutputCfgTypeDef * pOutputCfg); 4914 4915 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, 4916 uint32_t TimerIdx, 4917 uint32_t Output, 4918 uint32_t OutputLevel); 4919 4920 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim, 4921 uint32_t TimerIdx, 4922 uint32_t Event, 4923 HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg); 4924 4925 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef * hhrtim, 4926 uint32_t TimerIdx, 4927 uint32_t EventCounter, 4928 HRTIM_ExternalEventCfgTypeDef* pTimerExternalEventCfg); 4929 4930 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef * hhrtim, 4931 uint32_t TimerIdx, 4932 uint32_t EventCounter); 4933 4934 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef * hhrtim, 4935 uint32_t TimerIdx, 4936 uint32_t EventCounter); 4937 4938 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef * hhrtim, 4939 uint32_t TimerIdx, 4940 uint32_t EventCounter); 4941 4942 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim, 4943 uint32_t TimerIdx, 4944 HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg); 4945 4946 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim, 4947 uint32_t TimerIdx, 4948 HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg); 4949 4950 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, 4951 uint32_t TimerIdx, 4952 uint32_t RegistersToUpdate); 4953 4954 4955 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim, 4956 uint32_t Timers); 4957 4958 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim, 4959 uint32_t Timers); 4960 4961 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim, 4962 uint32_t Timers); 4963 4964 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim, 4965 uint32_t Timers); 4966 4967 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim, 4968 uint32_t Timers); 4969 4970 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim, 4971 uint32_t Timers); 4972 4973 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim, 4974 uint32_t OutputsToStart); 4975 4976 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim, 4977 uint32_t OutputsToStop); 4978 4979 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim, 4980 uint32_t Enable); 4981 4982 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim); 4983 4984 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim, 4985 uint32_t TimerIdx, 4986 uint32_t CaptureUnit); 4987 4988 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim, 4989 uint32_t Timers); 4990 4991 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim, 4992 uint32_t Timers); 4993 4994 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, 4995 uint32_t TimerIdx, 4996 uint32_t BurstBufferAddress, 4997 uint32_t BurstBufferLength); 4998 4999 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, 5000 uint32_t Timers); 5001 5002 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, 5003 uint32_t Timers); 5004 5005 /** 5006 * @} 5007 */ 5008 5009 /** @addtogroup HRTIM_Exported_Functions_Group9 5010 * @{ 5011 */ 5012 /* HRTIM peripheral state functions */ 5013 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim); 5014 5015 uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim, 5016 uint32_t TimerIdx, 5017 uint32_t CaptureUnit); 5018 5019 uint32_t HAL_HRTIM_GetCapturedDir(HRTIM_HandleTypeDef * hhrtim, 5020 uint32_t TimerIdx, 5021 uint32_t CaptureUnit); 5022 5023 HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(HRTIM_HandleTypeDef * hhrtim, 5024 uint32_t TimerIdx, 5025 uint32_t CaptureUnit); 5026 5027 uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim, 5028 uint32_t TimerIdx, 5029 uint32_t Output); 5030 5031 uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim, 5032 uint32_t TimerIdx, 5033 uint32_t Output); 5034 5035 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim, 5036 uint32_t TimerIdx, 5037 uint32_t Output); 5038 5039 uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim); 5040 5041 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim, 5042 uint32_t TimerIdx); 5043 5044 uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim, 5045 uint32_t TimerIdx); 5046 5047 /** 5048 * @} 5049 */ 5050 5051 /** @addtogroup HRTIM_Exported_Functions_Group10 5052 * @{ 5053 */ 5054 /* IRQ handler */ 5055 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim, 5056 uint32_t TimerIdx); 5057 5058 /* HRTIM events related callback functions */ 5059 void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim); 5060 void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim); 5061 void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim); 5062 void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim); 5063 void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim); 5064 void HAL_HRTIM_Fault6Callback(HRTIM_HandleTypeDef *hhrtim); 5065 void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim); 5066 void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef *hhrtim); 5067 void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim); 5068 void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim); 5069 5070 /* Timer events related callback functions */ 5071 void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim, 5072 uint32_t TimerIdx); 5073 void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim, 5074 uint32_t TimerIdx); 5075 void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim, 5076 uint32_t TimerIdx); 5077 void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim, 5078 uint32_t TimerIdx); 5079 void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim, 5080 uint32_t TimerIdx); 5081 void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim, 5082 uint32_t TimerIdx); 5083 void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim, 5084 uint32_t TimerIdx); 5085 void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim, 5086 uint32_t TimerIdx); 5087 void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim, 5088 uint32_t TimerIdx); 5089 void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim, 5090 uint32_t TimerIdx); 5091 void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim, 5092 uint32_t TimerIdx); 5093 void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim, 5094 uint32_t TimerIdx); 5095 void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim, 5096 uint32_t TimerIdx); 5097 void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim, 5098 uint32_t TimerIdx); 5099 void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim, 5100 uint32_t TimerIdx); 5101 void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim); 5102 5103 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 5104 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, 5105 HAL_HRTIM_CallbackIDTypeDef CallbackID, 5106 pHRTIM_CallbackTypeDef pCallback); 5107 5108 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, 5109 HAL_HRTIM_CallbackIDTypeDef CallbackID); 5110 5111 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, 5112 HAL_HRTIM_CallbackIDTypeDef CallbackID, 5113 pHRTIM_TIMxCallbackTypeDef pCallback); 5114 5115 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, 5116 HAL_HRTIM_CallbackIDTypeDef CallbackID); 5117 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 5118 5119 /** 5120 * @} 5121 */ 5122 5123 /** 5124 * @} 5125 */ 5126 5127 /** 5128 * @} 5129 */ 5130 5131 /** 5132 * @} 5133 */ 5134 5135 #endif /* HRTIM1 */ 5136 5137 #ifdef __cplusplus 5138 } 5139 #endif 5140 5141 #endif /* STM32G4xx_HAL_HRTIM_H */ 5142
