1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_hal_flash.h 4 * @author MCD Application Team 5 * @brief Header file of FLASH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32G4xx_HAL_FLASH_H 20 #define STM32G4xx_HAL_FLASH_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32g4xx_hal_def.h" 28 29 /** @addtogroup STM32G4xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup FLASH 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 /** @defgroup FLASH_Exported_Types FLASH Exported Types 39 * @{ 40 */ 41 42 /** 43 * @brief FLASH Erase structure definition 44 */ 45 typedef struct 46 { 47 uint32_t TypeErase; /*!< Mass erase or page erase. 48 This parameter can be a value of @ref FLASH_Type_Erase */ 49 uint32_t Banks; /*!< Select bank to erase. 50 This parameter must be a value of @ref FLASH_Banks 51 (FLASH_BANK_BOTH should be used only for mass erase) */ 52 uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled. 53 This parameter must be a value between 0 and (max number of pages in the bank - 1) 54 (eg : 127 for 512KB dual bank) */ 55 uint32_t NbPages; /*!< Number of pages to be erased. 56 This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/ 57 } FLASH_EraseInitTypeDef; 58 59 /** 60 * @brief FLASH Option Bytes Program structure definition 61 */ 62 typedef struct 63 { 64 uint32_t OptionType; /*!< Option byte to be configured. 65 This parameter can be a combination of the values of @ref FLASH_OB_Type */ 66 uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). 67 Only one WRP area could be programmed at the same time. 68 This parameter can be value of @ref FLASH_OB_WRP_Area */ 69 uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). 70 This parameter must be a value between 0 and (max number of pages in the bank - 1) */ 71 uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). 72 This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */ 73 uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP). 74 This parameter can be a value of @ref FLASH_OB_Read_Protection */ 75 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). 76 This parameter can be a combination of @ref FLASH_OB_USER_Type */ 77 uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). 78 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, 79 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, 80 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, 81 @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, 82 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2 (*), 83 @ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM_PE, 84 @ref FLASH_OB_USER_CCMSRAM_RST 85 @note (*) availability depends on devices */ 86 uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). 87 This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) 88 and @ref FLASH_OB_PCROP_RDP */ 89 uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). 90 This parameter must be a value between begin and end of bank 91 => Be careful of the bank swapping for the address */ 92 uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). 93 This parameter must be a value between PCROP Start address and end of bank */ 94 uint32_t BootEntryPoint; /*!< Set the Boot Lock (used for OPTIONBYTE_BOOT_LOCK). 95 This parameter can be a value of @ref FLASH_OB_Boot_Lock */ 96 uint32_t SecBank; /*!< Bank of securable memory area to be programmed (used for OPTIONBYTE_SEC). 97 Only one securable memory area could be programmed at the same time. 98 This parameter can be one of the following values: 99 FLASH_BANK_1: Securable memory area to be programmed in bank 1 100 FLASH_BANK_2: Securable memory area to be programmed in bank 2 (*) 101 @note (*) availability depends on devices */ 102 uint32_t SecSize; /*!< Size of securable memory area to be programmed (used for OPTIONBYTE_SEC), 103 in number of pages. Securable memory area is starting from first page of the bank. 104 Only one securable memory could be programmed at the same time. 105 This parameter must be a value between 0 and (max number of pages in the bank - 1) */ 106 } FLASH_OBProgramInitTypeDef; 107 108 /** 109 * @brief FLASH Procedure structure definition 110 */ 111 typedef enum 112 { 113 FLASH_PROC_NONE = 0, 114 FLASH_PROC_PAGE_ERASE, 115 FLASH_PROC_MASS_ERASE, 116 FLASH_PROC_PROGRAM, 117 FLASH_PROC_PROGRAM_LAST 118 } FLASH_ProcedureTypeDef; 119 120 /** 121 * @brief FLASH Cache structure definition 122 */ 123 typedef enum 124 { 125 FLASH_CACHE_DISABLED = 0, 126 FLASH_CACHE_ICACHE_ENABLED, 127 FLASH_CACHE_DCACHE_ENABLED, 128 FLASH_CACHE_ICACHE_DCACHE_ENABLED 129 } FLASH_CacheTypeDef; 130 131 /** 132 * @brief FLASH handle Structure definition 133 */ 134 typedef struct 135 { 136 HAL_LockTypeDef Lock; /* FLASH locking object */ 137 __IO uint32_t ErrorCode; /* FLASH error code */ 138 __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ 139 __IO uint32_t Address; /* Internal variable to save address selected for program in IT context */ 140 __IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */ 141 __IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ 142 __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ 143 __IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */ 144 } FLASH_ProcessTypeDef; 145 146 /** 147 * @} 148 */ 149 150 /* Exported constants --------------------------------------------------------*/ 151 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 152 * @{ 153 */ 154 155 /** @defgroup FLASH_Error FLASH Error 156 * @{ 157 */ 158 #define HAL_FLASH_ERROR_NONE 0x00000000U 159 #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR 160 #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR 161 #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR 162 #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR 163 #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR 164 #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR 165 #define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR 166 #define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR 167 #define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR 168 #define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR 169 #define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC 170 #define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD 171 #if defined (FLASH_OPTR_DBANK) 172 #define HAL_FLASH_ERROR_ECCC2 FLASH_FLAG_ECCC2 173 #define HAL_FLASH_ERROR_ECCD2 FLASH_FLAG_ECCD2 174 #endif 175 /** 176 * @} 177 */ 178 179 /** @defgroup FLASH_Type_Erase FLASH Erase Type 180 * @{ 181 */ 182 #define FLASH_TYPEERASE_PAGES 0x00U /*!<Pages erase only*/ 183 #define FLASH_TYPEERASE_MASSERASE 0x01U /*!<Flash mass erase activation*/ 184 /** 185 * @} 186 */ 187 188 /** @defgroup FLASH_Banks FLASH Banks 189 * @{ 190 */ 191 #define FLASH_BANK_1 0x00000001U /*!< Bank 1 */ 192 #if defined (FLASH_OPTR_DBANK) 193 #define FLASH_BANK_2 0x00000002U /*!< Bank 2 */ 194 #define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ 195 #else 196 #define FLASH_BANK_BOTH FLASH_BANK_1 /*!< Bank 1 */ 197 #endif 198 /** 199 * @} 200 */ 201 202 203 /** @defgroup FLASH_Type_Program FLASH Program Type 204 * @{ 205 */ 206 #define FLASH_TYPEPROGRAM_DOUBLEWORD 0x00U /*!< Program a double-word (64-bit) at a specified address.*/ 207 #define FLASH_TYPEPROGRAM_FAST 0x01U /*!< Fast program a 32 row double-word (64-bit) at a specified address. 208 And another 32 row double-word (64-bit) will be programmed */ 209 #define FLASH_TYPEPROGRAM_FAST_AND_LAST 0x02U /*!< Fast program a 32 row double-word (64-bit) at a specified address. 210 And this is the last 32 row double-word (64-bit) programmed */ 211 /** 212 * @} 213 */ 214 215 /** @defgroup FLASH_OB_Type FLASH Option Bytes Type 216 * @{ 217 */ 218 #define OPTIONBYTE_WRP 0x01U /*!< WRP option byte configuration */ 219 #define OPTIONBYTE_RDP 0x02U /*!< RDP option byte configuration */ 220 #define OPTIONBYTE_USER 0x04U /*!< USER option byte configuration */ 221 #define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */ 222 #define OPTIONBYTE_BOOT_LOCK 0x10U /*!< Boot lock option byte configuration */ 223 #define OPTIONBYTE_SEC 0x20U /*!< Securable memory option byte configuration */ 224 /** 225 * @} 226 */ 227 228 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area 229 * @{ 230 */ 231 #define OB_WRPAREA_BANK1_AREAA 0x00U /*!< Flash Bank 1 Area A */ 232 #define OB_WRPAREA_BANK1_AREAB 0x01U /*!< Flash Bank 1 Area B */ 233 #if defined (FLASH_OPTR_DBANK) 234 #define OB_WRPAREA_BANK2_AREAA 0x02U /*!< Flash Bank 2 Area A */ 235 #define OB_WRPAREA_BANK2_AREAB 0x04U /*!< Flash Bank 2 Area B */ 236 #endif 237 /** 238 * @} 239 */ 240 241 /** @defgroup FLASH_OB_Boot_Lock FLASH Boot Lock 242 * @{ 243 */ 244 #define OB_BOOT_LOCK_DISABLE 0x00000000U /*!< Boot Lock Disable */ 245 #define OB_BOOT_LOCK_ENABLE FLASH_SEC1R_BOOT_LOCK /*!< Boot Lock Enable */ 246 /** 247 * @} 248 */ 249 250 /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection 251 * @{ 252 */ 253 #define OB_RDP_LEVEL_0 0xAAU 254 #define OB_RDP_LEVEL_1 0xBBU 255 #define OB_RDP_LEVEL_2 0xCCU /*!< Warning: When enabling read protection level 2 256 it's no more possible to go back to level 1 or 0 */ 257 /** 258 * @} 259 */ 260 261 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type 262 * @{ 263 */ 264 #define OB_USER_BOR_LEV 0x00000001U /*!< BOR reset Level */ 265 #define OB_USER_nRST_STOP 0x00000002U /*!< Reset generated when entering the stop mode */ 266 #define OB_USER_nRST_STDBY 0x00000004U /*!< Reset generated when entering the standby mode */ 267 #define OB_USER_IWDG_SW 0x00000008U /*!< Independent watchdog selection */ 268 #define OB_USER_IWDG_STOP 0x00000010U /*!< Independent watchdog counter freeze in stop mode */ 269 #define OB_USER_IWDG_STDBY 0x00000020U /*!< Independent watchdog counter freeze in standby mode */ 270 #define OB_USER_WWDG_SW 0x00000040U /*!< Window watchdog selection */ 271 #if defined (FLASH_OPTR_DBANK) 272 #define OB_USER_BFB2 0x00000080U /*!< Dual-bank boot */ 273 #define OB_USER_DBANK 0x00000100U /*!< Single bank with 128-bits data or two banks with 64-bits data */ 274 #endif 275 #if defined (FLASH_OPTR_PB4_PUPEN) 276 #define OB_USER_PB4_PUPEN 0x00000100U /*!< USB power delivery dead-battery/TDI pull-up */ 277 #endif 278 #define OB_USER_nBOOT1 0x00000200U /*!< Boot configuration */ 279 #define OB_USER_SRAM_PE 0x00000400U /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) */ 280 #define OB_USER_CCMSRAM_RST 0x00000800U /*!< CCMSRAM Erase when system reset */ 281 #define OB_USER_nRST_SHDW 0x00001000U /*!< Reset generated when entering the shutdown mode */ 282 #define OB_USER_nSWBOOT0 0x00002000U /*!< Software BOOT0 */ 283 #define OB_USER_nBOOT0 0x00004000U /*!< nBOOT0 option bit */ 284 #define OB_USER_NRST_MODE 0x00008000U /*!< Reset pin configuration */ 285 #define OB_USER_IRHEN 0x00010000U /*!< Internal Reset Holder enable */ 286 /** 287 * @} 288 */ 289 290 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level 291 * @{ 292 */ 293 #define OB_BOR_LEVEL_0 FLASH_OPTR_BOR_LEV_0 /*!< Reset level threshold is around 1.7V */ 294 #define OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_1 /*!< Reset level threshold is around 2.0V */ 295 #define OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_2 /*!< Reset level threshold is around 2.2V */ 296 #define OB_BOR_LEVEL_3 FLASH_OPTR_BOR_LEV_3 /*!< Reset level threshold is around 2.5V */ 297 #define OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_4 /*!< Reset level threshold is around 2.8V */ 298 /** 299 * @} 300 */ 301 302 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop 303 * @{ 304 */ 305 #define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */ 306 #define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */ 307 /** 308 * @} 309 */ 310 311 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby 312 * @{ 313 */ 314 #define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */ 315 #define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */ 316 /** 317 * @} 318 */ 319 320 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown 321 * @{ 322 */ 323 #define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */ 324 #define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode */ 325 /** 326 * @} 327 */ 328 329 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type 330 * @{ 331 */ 332 #define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ 333 #define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */ 334 /** 335 * @} 336 */ 337 338 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop 339 * @{ 340 */ 341 #define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */ 342 #define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop mode */ 343 /** 344 * @} 345 */ 346 347 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby 348 * @{ 349 */ 350 #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */ 351 #define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */ 352 /** 353 * @} 354 */ 355 356 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type 357 * @{ 358 */ 359 #define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ 360 #define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */ 361 /** 362 * @} 363 */ 364 365 #if defined (FLASH_OPTR_DBANK) 366 /** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode 367 * @{ 368 */ 369 #define OB_BFB2_DISABLE 0x00000000U /*!< Dual-bank boot disable */ 370 #define OB_BFB2_ENABLE FLASH_OPTR_BFB2 /*!< Dual-bank boot enable */ 371 /** 372 * @} 373 */ 374 375 /** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type 376 * @{ 377 */ 378 #define OB_DBANK_128_BITS 0x00000000U /*!< Single-bank with 128-bits data */ 379 #define OB_DBANK_64_BITS FLASH_OPTR_DBANK /*!< Dual-bank with 64-bits data */ 380 /** 381 * @} 382 */ 383 #endif 384 385 #if defined (FLASH_OPTR_PB4_PUPEN) 386 /** @defgroup FLASH_OB_USER_PB4_PUPEN FLASH Option Bytes User PB4 PUPEN bit 387 * @{ 388 */ 389 #define OB_PB4_PUPEN_DISABLE 0x00000000U /*!< USB power delivery dead-battery enabled/ TDI pull-up deactivated */ 390 #define OB_PB4_PUPEN_ENABLE FLASH_OPTR_PB4_PUPEN /*!< USB power delivery dead-battery disabled/ TDI pull-up activated */ 391 /** 392 * @} 393 */ 394 #endif 395 396 /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type 397 * @{ 398 */ 399 #define OB_BOOT1_SRAM 0x00000000U /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */ 400 #define OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1 /*!< System memory is selected as boot space (if BOOT0=1) */ 401 /** 402 * @} 403 */ 404 405 /** @defgroup FLASH_OB_USER_SRAM_PE FLASH Option Bytes User SRAM Parity Check Type 406 * @{ 407 */ 408 #define OB_SRAM_PARITY_ENABLE 0x00000000U /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) */ 409 #define OB_SRAM_PARITY_DISABLE FLASH_OPTR_SRAM_PE /*!< SRAM parity check disable (first 32kB of SRAM1 + CCM SRAM) */ 410 /** 411 * @} 412 */ 413 414 /** @defgroup FLASH_OB_USER_CCMSRAM_RST FLASH Option Bytes User CCMSRAM Erase On Reset Type 415 * @{ 416 */ 417 #define OB_CCMSRAM_RST_ERASE 0x00000000U /*!< CCMSRAM erased when a system reset occurs */ 418 #define OB_CCMSRAM_RST_NOT_ERASE FLASH_OPTR_CCMSRAM_RST /*!< CCMSRAM is not erased when a system reset occurs */ 419 /** 420 * @} 421 */ 422 423 /** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 424 * @{ 425 */ 426 #define OB_BOOT0_FROM_OB 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */ 427 #define OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0 /*!< BOOT0 taken from PB8/BOOT0 pin */ 428 /** 429 * @} 430 */ 431 432 /** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit 433 * @{ 434 */ 435 #define OB_nBOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */ 436 #define OB_nBOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */ 437 /** 438 * @} 439 */ 440 441 /** @defgroup FLASH_OB_USER_NRST_MODE FLASH Option Bytes User NRST mode bit 442 * @{ 443 */ 444 #define OB_NRST_MODE_INPUT_ONLY FLASH_OPTR_NRST_MODE_0 /*!< Reset pin is in Reset input mode only */ 445 #define OB_NRST_MODE_GPIO FLASH_OPTR_NRST_MODE_1 /*!< Reset pin is in GPIO mode only */ 446 #define OB_NRST_MODE_INPUT_OUTPUT FLASH_OPTR_NRST_MODE /*!< Reset pin is in reset input and output mode */ 447 /** 448 * @} 449 */ 450 451 /** @defgroup FLASH_OB_USER_INTERNAL_RESET_HOLDER FLASH Option Bytes User internal reset holder bit 452 * @{ 453 */ 454 #define OB_IRH_DISABLE 0x00000000U /*!< Internal Reset holder disable */ 455 #define OB_IRH_ENABLE FLASH_OPTR_IRHEN /*!< Internal Reset holder enable */ 456 /** 457 * @} 458 */ 459 460 /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type 461 * @{ 462 */ 463 #define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level 464 is decreased from Level 1 to Level 0 */ 465 #define OB_PCROP_RDP_ERASE FLASH_PCROP1ER_PCROP_RDP /*!< PCROP area is erased when the RDP level is 466 decreased from Level 1 to Level 0 (full mass erase) */ 467 /** 468 * @} 469 */ 470 471 /** @defgroup FLASH_Latency FLASH Latency 472 * @{ 473 */ 474 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ 475 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ 476 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ 477 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ 478 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ 479 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait state */ 480 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait state */ 481 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */ 482 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */ 483 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait states */ 484 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait state */ 485 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait state */ 486 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait states */ 487 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait states */ 488 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait states */ 489 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait states */ 490 /** 491 * @} 492 */ 493 494 /** @defgroup FLASH_Keys FLASH Keys 495 * @{ 496 */ 497 #define FLASH_KEY1 0x45670123U /*!< Flash key1 */ 498 #define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 499 to unlock the FLASH registers access */ 500 501 #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ 502 #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 503 to unlock the RUN_PD bit in FLASH_ACR */ 504 505 #define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ 506 #define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 507 to allow option bytes operations */ 508 /** 509 * @} 510 */ 511 512 /** @defgroup FLASH_Flags FLASH Flags Definition 513 * @{ 514 */ 515 #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */ 516 #define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */ 517 #define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */ 518 #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */ 519 #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */ 520 #define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ 521 #define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */ 522 #define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */ 523 #define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */ 524 #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */ 525 #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */ 526 #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ 527 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction in 64 LSB bits */ 528 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection in 64 LSB bits */ 529 #if defined (FLASH_OPTR_DBANK) 530 #define FLASH_FLAG_ECCC2 FLASH_ECCR_ECCC2 /*!< FLASH ECC correction in 64 MSB bits (mode 128 bits only) */ 531 #define FLASH_FLAG_ECCD2 FLASH_ECCR_ECCD2 /*!< FLASH ECC detection in 64 MSB bits (mode 128 bits only) */ 532 #endif 533 534 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 535 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 536 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 537 FLASH_FLAG_OPTVERR) 538 #if defined (FLASH_OPTR_DBANK) 539 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD | FLASH_FLAG_ECCC2 | FLASH_FLAG_ECCD2) 540 #else 541 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD) 542 #endif 543 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS) 544 /** 545 * @} 546 */ 547 548 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition 549 * @brief FLASH Interrupt definition 550 * @{ 551 */ 552 #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ 553 #define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */ 554 #define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source*/ 555 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24U) /*!< ECC Correction Interrupt source */ 556 /** 557 * @} 558 */ 559 560 /** 561 * @} 562 */ 563 564 /* Exported macros -----------------------------------------------------------*/ 565 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros 566 * @brief macros to control FLASH features 567 * @{ 568 */ 569 570 /** 571 * @brief Set the FLASH Latency. 572 * @param __LATENCY__ FLASH Latency. 573 * This parameter can be one of the following values : 574 * @arg FLASH_LATENCY_0: FLASH Zero wait state 575 * @arg FLASH_LATENCY_1: FLASH One wait state 576 * @arg FLASH_LATENCY_2: FLASH Two wait states 577 * @arg FLASH_LATENCY_3: FLASH Three wait states 578 * @arg FLASH_LATENCY_4: FLASH Four wait states 579 * @arg FLASH_LATENCY_5: FLASH Five wait states 580 * @arg FLASH_LATENCY_6: FLASH Six wait states 581 * @arg FLASH_LATENCY_7: FLASH Seven wait states 582 * @arg FLASH_LATENCY_8: FLASH Eight wait states 583 * @arg FLASH_LATENCY_9: FLASH Nine wait states 584 * @arg FLASH_LATENCY_10: FLASH Ten wait state 585 * @arg FLASH_LATENCY_11: FLASH Eleven wait state 586 * @arg FLASH_LATENCY_12: FLASH Twelve wait states 587 * @arg FLASH_LATENCY_13: FLASH Thirteen wait states 588 * @arg FLASH_LATENCY_14: FLASH Fourteen wait states 589 * @arg FLASH_LATENCY_15: FLASH Fifteen wait states 590 * @retval None 591 */ 592 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)) 593 594 /** 595 * @brief Get the FLASH Latency. 596 * @retval FLASH_Latency. 597 * This parameter can be one of the following values : 598 * @arg FLASH_LATENCY_0: FLASH Zero wait state 599 * @arg FLASH_LATENCY_1: FLASH One wait state 600 * @arg FLASH_LATENCY_2: FLASH Two wait states 601 * @arg FLASH_LATENCY_3: FLASH Three wait states 602 * @arg FLASH_LATENCY_4: FLASH Four wait states 603 * @arg FLASH_LATENCY_5: FLASH Five wait states 604 * @arg FLASH_LATENCY_6: FLASH Six wait states 605 * @arg FLASH_LATENCY_7: FLASH Seven wait states 606 * @arg FLASH_LATENCY_8: FLASH Eight wait states 607 * @arg FLASH_LATENCY_9: FLASH Nine wait states 608 * @arg FLASH_LATENCY_10: FLASH Ten wait state 609 * @arg FLASH_LATENCY_11: FLASH Eleven wait state 610 * @arg FLASH_LATENCY_12: FLASH Twelve wait states 611 * @arg FLASH_LATENCY_13: FLASH Thirteen wait states 612 * @arg FLASH_LATENCY_14: FLASH Fourteen wait states 613 * @arg FLASH_LATENCY_15: FLASH Fifteen wait states 614 */ 615 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) 616 617 /** 618 * @brief Enable the FLASH prefetch buffer. 619 * @retval None 620 */ 621 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 622 623 /** 624 * @brief Disable the FLASH prefetch buffer. 625 * @retval None 626 */ 627 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 628 629 /** 630 * @brief Enable the FLASH instruction cache. 631 * @retval none 632 */ 633 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) 634 635 /** 636 * @brief Disable the FLASH instruction cache. 637 * @retval none 638 */ 639 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) 640 641 /** 642 * @brief Enable the FLASH data cache. 643 * @retval none 644 */ 645 #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN) 646 647 /** 648 * @brief Disable the FLASH data cache. 649 * @retval none 650 */ 651 #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN) 652 653 /** 654 * @brief Reset the FLASH instruction Cache. 655 * @note This function must be used only when the Instruction Cache is disabled. 656 * @retval None 657 */ 658 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ 659 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ 660 } while (0) 661 662 /** 663 * @brief Reset the FLASH data Cache. 664 * @note This function must be used only when the data Cache is disabled. 665 * @retval None 666 */ 667 #define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ 668 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ 669 } while (0) 670 671 /** 672 * @brief Enable the FLASH power down during Low-power run mode. 673 * @note Writing this bit to 1, automatically the keys are 674 * lost and a new unlock sequence is necessary to re-write it to 0. 675 */ 676 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ 677 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ 678 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ 679 } while (0) 680 681 /** 682 * @brief Disable the FLASH power down during Low-power run mode. 683 * @note Writing this bit to 0, automatically the keys are 684 * lost and a new unlock sequence is necessary to re-write it to 1. 685 */ 686 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ 687 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ 688 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ 689 } while (0) 690 691 /** 692 * @brief Enable the FLASH power down during Low-Power sleep mode 693 * @retval none 694 */ 695 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 696 697 /** 698 * @brief Disable the FLASH power down during Low-Power sleep mode 699 * @retval none 700 */ 701 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 702 703 /** 704 * @} 705 */ 706 707 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros 708 * @brief macros to handle FLASH interrupts 709 * @{ 710 */ 711 712 /** 713 * @brief Enable the specified FLASH interrupt. 714 * @param __INTERRUPT__ FLASH interrupt 715 * This parameter can be any combination of the following values: 716 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 717 * @arg FLASH_IT_OPERR: Error Interrupt 718 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt 719 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 720 * @retval none 721 */ 722 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 723 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 724 } while (0) 725 726 /** 727 * @brief Disable the specified FLASH interrupt. 728 * @param __INTERRUPT__ FLASH interrupt 729 * This parameter can be any combination of the following values: 730 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 731 * @arg FLASH_IT_OPERR: Error Interrupt 732 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt 733 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 734 * @retval none 735 */ 736 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 737 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 738 } while (0) 739 740 /** 741 * @brief Check whether the specified FLASH flag is set or not. 742 * @param __FLAG__ specifies the FLASH flag to check. 743 * This parameter can be one of the following values: 744 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 745 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 746 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 747 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 748 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 749 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 750 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 751 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag 752 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag 753 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag 754 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag 755 * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 756 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits 757 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits 758 * @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only) 759 * @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only) 760 * @note (*) availability depends on devices 761 * @retval The new state of FLASH_FLAG (SET or RESET). 762 */ 763 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ 764 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 765 (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) 766 767 /** 768 * @brief Clear the FLASH's pending flags. 769 * @param __FLAG__ specifies the FLASH flags to clear. 770 * This parameter can be any combination of the following values: 771 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 772 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 773 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 774 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 775 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 776 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 777 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 778 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag 779 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag 780 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag 781 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag 782 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits 783 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits 784 * @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only) 785 * @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only) 786 * @arg FLASH_FLAG_SR_ERRORS: FLASH All SR errors flags 787 * @arg FLASH_FLAG_ECCR_ERRORS: FLASH All ECCR errors flags 788 * @note (*) availability depends on devices 789 * @retval None 790 */ 791 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 792 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ 793 } while (0) 794 /** 795 * @} 796 */ 797 798 /* Include FLASH HAL Extended module */ 799 #include "stm32g4xx_hal_flash_ex.h" 800 #include "stm32g4xx_hal_flash_ramfunc.h" 801 802 /* Exported variables --------------------------------------------------------*/ 803 /** @defgroup FLASH_Exported_Variables FLASH Exported Variables 804 * @{ 805 */ 806 extern FLASH_ProcessTypeDef pFlash; 807 /** 808 * @} 809 */ 810 811 /* Exported functions --------------------------------------------------------*/ 812 /** @addtogroup FLASH_Exported_Functions 813 * @{ 814 */ 815 816 /* Program operation functions ***********************************************/ 817 /** @addtogroup FLASH_Exported_Functions_Group1 818 * @{ 819 */ 820 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 821 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 822 /* FLASH IRQ handler method */ 823 void HAL_FLASH_IRQHandler(void); 824 /* Callbacks in non blocking modes */ 825 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 826 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 827 /** 828 * @} 829 */ 830 831 /* Peripheral Control functions **********************************************/ 832 /** @addtogroup FLASH_Exported_Functions_Group2 833 * @{ 834 */ 835 HAL_StatusTypeDef HAL_FLASH_Unlock(void); 836 HAL_StatusTypeDef HAL_FLASH_Lock(void); 837 /* Option bytes control */ 838 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 839 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 840 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); 841 /** 842 * @} 843 */ 844 845 /* Peripheral State functions ************************************************/ 846 /** @addtogroup FLASH_Exported_Functions_Group3 847 * @{ 848 */ 849 uint32_t HAL_FLASH_GetError(void); 850 /** 851 * @} 852 */ 853 854 /** 855 * @} 856 */ 857 858 /** @addtogroup FLASH_Private_Functions 859 * @{ 860 */ 861 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 862 /** 863 * @} 864 */ 865 866 /* Private constants --------------------------------------------------------*/ 867 /** @defgroup FLASH_Private_Constants FLASH Private Constants 868 * @{ 869 */ 870 #define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE 871 872 #if defined (FLASH_OPTR_DBANK) 873 #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x200UL << 10U) : \ 874 (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U)) 875 #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) 876 #define FLASH_PAGE_NB 128U 877 #define FLASH_PAGE_SIZE_128_BITS 0x1000U /* 4 KB */ 878 #else 879 #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x80UL << 10U) : \ 880 (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U)) 881 #define FLASH_BANK_SIZE (FLASH_SIZE) 882 #define FLASH_PAGE_NB ((FLASH_SIZE == 0x00080000U) ? 256U : \ 883 ((FLASH_SIZE == 0x00040000U) ? 128U : 64U)) 884 #endif 885 886 #define FLASH_PAGE_SIZE 0x800U /* 2 KB */ 887 888 #define FLASH_TIMEOUT_VALUE 1000U /* 1 s */ 889 890 /** 891 * @} 892 */ 893 894 /* Private macros ------------------------------------------------------------*/ 895 /** @defgroup FLASH_Private_Macros FLASH Private Macros 896 * @{ 897 */ 898 899 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ 900 ((VALUE) == FLASH_TYPEERASE_MASSERASE)) 901 902 #if defined (FLASH_OPTR_DBANK) 903 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ 904 ((BANK) == FLASH_BANK_2) || \ 905 ((BANK) == FLASH_BANK_BOTH)) 906 907 #define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ 908 ((BANK) == FLASH_BANK_2)) 909 #else 910 #define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) 911 912 #define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) 913 #endif 914 915 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ 916 ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \ 917 ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) 918 919 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) 920 921 #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU)) 922 923 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS)) 924 925 #define IS_FLASH_PAGE(PAGE) ((PAGE) < FLASH_PAGE_NB) 926 927 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \ 928 OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_SEC))) 929 930 #if defined (FLASH_OPTR_DBANK) 931 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ 932 ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) 933 #else 934 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB)) 935 #endif 936 937 #define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_ENABLE) || ((VALUE) == OB_BOOT_LOCK_DISABLE)) 938 939 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ 940 ((LEVEL) == OB_RDP_LEVEL_1) ||\ 941 ((LEVEL) == OB_RDP_LEVEL_2)) 942 943 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFFU) && ((TYPE) != 0U)) 944 945 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ 946 ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ 947 ((LEVEL) == OB_BOR_LEVEL_4)) 948 949 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) 950 951 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) 952 953 #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) 954 955 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) 956 957 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) 958 959 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) 960 961 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) 962 963 #if defined (FLASH_OPTR_DBANK) 964 #define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE)) 965 966 #define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) 967 #endif 968 969 #if defined (FLASH_OPTR_PB4_PUPEN) 970 #define IS_OB_USER_PB4_PUPEN(VALUE) (((VALUE) == OB_PB4_PUPEN_DISABLE) || ((VALUE) == OB_PB4_PUPEN_ENABLE)) 971 #endif 972 973 #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM)) 974 975 #define IS_OB_USER_SRAM_PARITY(VALUE) (((VALUE) == OB_SRAM_PARITY_ENABLE) || ((VALUE) == OB_SRAM_PARITY_DISABLE)) 976 977 #define IS_OB_USER_CCMSRAM_RST(VALUE) (((VALUE) == OB_CCMSRAM_RST_ERASE) || ((VALUE) == OB_CCMSRAM_RST_NOT_ERASE)) 978 979 #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) 980 981 #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET)) 982 983 #define IS_OB_USER_NRST_MODE(VALUE) (((VALUE) == OB_NRST_MODE_GPIO) || ((VALUE) == OB_NRST_MODE_INPUT_ONLY) || \ 984 ((VALUE) == OB_NRST_MODE_INPUT_OUTPUT)) 985 986 #define IS_OB_USER_IRHEN(VALUE) (((VALUE) == OB_IRH_ENABLE) || ((VALUE) == OB_IRH_DISABLE)) 987 988 #define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE)) 989 990 #define IS_OB_SECMEM_SIZE(VALUE) ((VALUE) <= FLASH_PAGE_NB) 991 992 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ 993 ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ 994 ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ 995 ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ 996 ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ 997 ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ 998 ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ 999 ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) 1000 /** 1001 * @} 1002 */ 1003 1004 /** 1005 * @} 1006 */ 1007 1008 /** 1009 * @} 1010 */ 1011 1012 #ifdef __cplusplus 1013 } 1014 #endif 1015 1016 #endif /* STM32G4xx_HAL_FLASH_H */ 1017 1018
