1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32G4xx_HAL_ADC_H 21 #define STM32G4xx_HAL_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32g4xx_hal_def.h" 29 30 /* Include low level driver */ 31 #include "stm32g4xx_ll_adc.h" 32 33 /** @addtogroup STM32G4xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup ADC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup ADC_Exported_Types ADC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief ADC group regular oversampling structure definition 48 */ 49 typedef struct 50 { 51 uint32_t Ratio; /*!< Configures the oversampling ratio. 52 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 53 54 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 55 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 56 57 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 58 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 59 60 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. 61 The oversampling is either temporary stopped or reset upon an injected 62 sequence interruption. 63 If oversampling is enabled on both regular and injected groups, this parameter 64 is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" 65 (the oversampling buffer is zeroed during injection sequence). 66 This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ 67 68 } ADC_OversamplingTypeDef; 69 70 /** 71 * @brief Structure definition of ADC instance and ADC group regular. 72 * @note Parameters of this structure are shared within 2 scopes: 73 * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, 74 * GainCompensation, ScanConvMode, EOCSelection, LowPowerAutoWait. 75 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, 76 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling, SamplingMode. 77 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 78 * ADC state can be either: 79 * - For all parameters: ADC disabled 80 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular. 81 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected. 82 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 83 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter 84 * (which fulfills the ADC state condition) on the fly). 85 */ 86 typedef struct 87 { 88 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. 89 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. 90 Note: The ADC clock configuration is common to all ADC instances. 91 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 92 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. 93 Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only 94 if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC 95 must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. 96 Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. 97 Note: This parameter can be modified only if all ADC instances are disabled. */ 98 99 uint32_t Resolution; /*!< Configure the ADC resolution. 100 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 101 102 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). 103 Refer to reference manual for alignments formats versus resolutions. 104 This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ 105 106 uint32_t GainCompensation; /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw conversion data, based on following formula: 107 DATA = DATA(raw) * (gain compensation coef) / 4096 108 2.12 bit format, unsigned: 2 bits exponents / 12 bits mantissa 109 Gain step is 1/4096 = 0.000244 110 Gain range is 0.0000 to 3.999756 111 This parameter value can be 112 0 Gain compensation will be disabled and coefficient set to 0 113 1 -> 0x3FFF Gain compensation will be enabled and coefficient set to specified value 114 115 Note: Gain compensation when enabled is applied to all channels. */ 116 117 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. 118 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 119 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 120 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 121 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer). 122 Scan direction is upward: from rank 1 to rank 'n'. 123 This parameter can be a value of @ref ADC_Scan_mode */ 124 125 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. 126 This parameter can be a value of @ref ADC_EOCSelection. */ 127 128 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous 129 conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, 130 using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). 131 This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun 132 for low frequency applications. 133 This parameter can be set to ENABLE or DISABLE. 134 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). 135 Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). 136 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: 137 use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. 138 (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ 139 140 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, 141 after the first ADC conversion start trigger occurred (software start or external trigger). 142 This parameter can be set to ENABLE or DISABLE. */ 143 144 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. 145 To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 146 This parameter must be a number between Min_Data = 1 and Max_Data = 16. 147 Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without 148 continuous mode or external trigger that could launch a conversion). */ 149 150 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence 151 (main sequence subdivided in successive parts). 152 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 153 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 154 This parameter can be set to ENABLE or DISABLE. */ 155 156 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. 157 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 158 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 159 160 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. 161 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 162 This parameter can be a value of @ref ADC_regular_external_trigger_source. 163 Caution: external trigger source is common to all ADC instances. */ 164 165 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. 166 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 167 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 168 169 uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion. 170 This parameter can be a value of @ref ADC_regular_sampling_mode */ 171 172 FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) 173 or in continuous mode (DMA transfer unlimited, whatever number of conversions). 174 This parameter can be set to ENABLE or DISABLE. 175 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ 176 177 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 178 This parameter applies to ADC group regular only. 179 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 180 Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear 181 end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function 182 HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). 183 Note: Error reporting with respect to the conversion mode: 184 - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data 185 overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. 186 - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ 187 188 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 189 This parameter can be set to ENABLE or DISABLE. 190 Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */ 191 192 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 193 Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ 194 195 } ADC_InitTypeDef; 196 197 /** 198 * @brief Structure definition of ADC channel for regular group 199 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 200 * ADC state can be either: 201 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') 202 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group. 203 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. 204 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 205 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) 206 * on the fly). 207 */ 208 typedef struct 209 { 210 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 211 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 212 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 213 214 uint32_t Rank; /*!< Specify the rank in the regular group sequencer. 215 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS 216 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 217 the new channel setting (or parameter number of conversions adjusted) */ 218 219 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 220 Unit: ADC clock cycles 221 Conversion time is the addition of sampling time and processing time 222 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 223 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 224 Caution: This parameter applies to a channel that can be used into regular and/or injected group. 225 It overwrites the last setting. 226 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 227 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 228 Refer to device datasheet for timings values. */ 229 230 uint32_t SingleDiff; /*!< Select single-ended or differential input. 231 In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 232 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 233 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING 234 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 235 It overwrites the last setting. 236 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 237 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 238 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 239 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 240 of another parameter update on the fly) */ 241 242 uint32_t OffsetNumber; /*!< Select the offset number 243 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB 244 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 245 246 uint32_t Offset; /*!< Define the offset to be applied on the raw converted data. 247 Offset value must be a positive number. 248 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 249 0x3FF, 0xFF or 0x3F respectively. 250 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 251 without continuous mode or external trigger that could launch a conversion). */ 252 253 uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. 254 This parameter can be a value of @ref ADCEx_OffsetSign. 255 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 256 without continuous mode or external trigger that could launch a conversion). */ 257 FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. 258 This parameter value can be ENABLE or DISABLE. 259 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 260 without continuous mode or external trigger that could launch a conversion). */ 261 262 } ADC_ChannelConfTypeDef; 263 264 /** 265 * @brief Structure definition of ADC analog watchdog 266 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 267 * ADC state can be either: 268 * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected. 269 * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and injected groups. 270 */ 271 typedef struct 272 { 273 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 274 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') 275 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) 276 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 277 278 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 279 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. 280 For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. 281 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 282 283 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 284 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). 285 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). 286 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 287 288 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 289 This parameter can be set to ENABLE or DISABLE */ 290 291 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 292 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 293 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 294 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 295 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 296 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 297 impacted: the comparison of analog watchdog thresholds is done on 298 oversampling final computation (after ratio and shift application): 299 ADC data register bitfield [15:4] (12 most significant bits). */ 300 301 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 302 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 303 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 304 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 305 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 306 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 307 impacted: the comparison of analog watchdog thresholds is done on 308 oversampling final computation (after ratio and shift application): 309 ADC data register bitfield [15:4] (12 most significant bits). */ 310 311 uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider. 312 Before setting flag or raising interrupt, analog watchdog can wait to have several 313 consecutive out-of-window samples. This parameter allows to configure this number. 314 This parameter only applies to Analog watchdog 1. For others, use value ADC_AWD_FILTERING_NONE. 315 This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */ 316 } ADC_AnalogWDGConfTypeDef; 317 318 /** 319 * @brief ADC group injected contexts queue configuration 320 * @note Structure intended to be used only through structure "ADC_HandleTypeDef" 321 */ 322 typedef struct 323 { 324 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each 325 HAL_ADCEx_InjectedConfigChannel() call to finally initialize 326 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ 327 328 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ 329 } ADC_InjectionConfigTypeDef; 330 331 /** @defgroup ADC_States ADC States 332 * @{ 333 */ 334 335 /** 336 * @brief HAL ADC state machine: ADC states definition (bitfields) 337 * @note ADC state machine is managed by bitfields, state must be compared 338 * with bit by bit. 339 * For example: 340 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " 341 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " 342 */ 343 /* States of ADC global scope */ 344 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ 345 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ 346 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */ 347 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ 348 349 /* States of ADC errors */ 350 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ 351 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ 352 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ 353 354 /* States of ADC group regular */ 355 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, 356 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 357 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ 358 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ 359 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ 360 361 /* States of ADC group injected */ 362 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, 363 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 364 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ 365 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ 366 367 /* States of ADC analog watchdogs */ 368 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 369 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ 370 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ 371 372 /* States of ADC multi-mode */ 373 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ 374 375 /** 376 * @} 377 */ 378 379 /** 380 * @brief ADC handle Structure definition 381 */ 382 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 383 typedef struct __ADC_HandleTypeDef 384 #else 385 typedef struct 386 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 387 { 388 ADC_TypeDef *Instance; /*!< Register base address */ 389 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ 390 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 391 HAL_LockTypeDef Lock; /*!< ADC locking object */ 392 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 393 __IO uint32_t ErrorCode; /*!< ADC Error code */ 394 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ 395 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 396 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 397 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 398 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 399 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 400 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ 401 void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */ 402 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 403 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 404 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 405 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 406 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 407 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 408 } ADC_HandleTypeDef; 409 410 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 411 /** 412 * @brief HAL ADC Callback ID enumeration definition 413 */ 414 typedef enum 415 { 416 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 417 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 418 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 419 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 420 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 421 HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ 422 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 423 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 424 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 425 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 426 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 427 } HAL_ADC_CallbackIDTypeDef; 428 429 /** 430 * @brief HAL ADC Callback pointer definition 431 */ 432 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 433 434 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 435 436 /** 437 * @} 438 */ 439 440 441 /* Exported constants --------------------------------------------------------*/ 442 443 /** @defgroup ADC_Exported_Constants ADC Exported Constants 444 * @{ 445 */ 446 447 /** @defgroup ADC_Error_Code ADC Error Code 448 * @{ 449 */ 450 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 451 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, 452 enable/disable, erroneous state, ...) */ 453 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 454 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 455 #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ 456 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 457 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 458 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 459 /** 460 * @} 461 */ 462 463 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 464 * @{ 465 */ 466 #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */ 467 #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ 468 #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ 469 470 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ 471 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ 472 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ 473 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ 474 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ 475 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ 476 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ 477 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ 478 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ 479 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ 480 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ 481 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ 482 /** 483 * @} 484 */ 485 486 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 487 * @{ 488 */ 489 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 490 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 491 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 492 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ 493 /** 494 * @} 495 */ 496 497 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment 498 * @{ 499 */ 500 #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ 501 #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ 502 /** 503 * @} 504 */ 505 506 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 507 * @{ 508 */ 509 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ 510 #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ 511 /** 512 * @} 513 */ 514 515 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 516 * @{ 517 */ 518 /* ADC group regular trigger sources for all ADC instances */ 519 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ 520 #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 521 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ 522 #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 523 #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 524 #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 525 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 526 #define ADC_EXTERNALTRIG_T2_CC1 (LL_ADC_REG_TRIG_EXT_TIM2_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 527 #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 528 #define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 529 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 530 #define ADC_EXTERNALTRIG_T3_CC1 (LL_ADC_REG_TRIG_EXT_TIM3_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 531 #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 532 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 533 #define ADC_EXTERNALTRIG_T4_CC1 (LL_ADC_REG_TRIG_EXT_TIM4_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 534 #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 535 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ 536 #define ADC_EXTERNALTRIG_T7_TRGO (LL_ADC_REG_TRIG_EXT_TIM7_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */ 537 #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 538 #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ 539 #define ADC_EXTERNALTRIG_T8_CC1 (LL_ADC_REG_TRIG_EXT_TIM8_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 540 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ 541 #define ADC_EXTERNALTRIG_T20_TRGO (LL_ADC_REG_TRIG_EXT_TIM20_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). */ 542 #define ADC_EXTERNALTRIG_T20_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */ 543 #define ADC_EXTERNALTRIG_T20_CC1 (LL_ADC_REG_TRIG_EXT_TIM20_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 544 #define ADC_EXTERNALTRIG_T20_CC2 (LL_ADC_REG_TRIG_EXT_TIM20_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 545 #define ADC_EXTERNALTRIG_T20_CC3 (LL_ADC_REG_TRIG_EXT_TIM20_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 546 #define ADC_EXTERNALTRIG_HRTIM_TRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). */ 547 #define ADC_EXTERNALTRIG_HRTIM_TRG2 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). */ 548 #define ADC_EXTERNALTRIG_HRTIM_TRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). */ 549 #define ADC_EXTERNALTRIG_HRTIM_TRG4 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG4) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). */ 550 #define ADC_EXTERNALTRIG_HRTIM_TRG5 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). */ 551 #define ADC_EXTERNALTRIG_HRTIM_TRG6 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). */ 552 #define ADC_EXTERNALTRIG_HRTIM_TRG7 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). */ 553 #define ADC_EXTERNALTRIG_HRTIM_TRG8 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). */ 554 #define ADC_EXTERNALTRIG_HRTIM_TRG9 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). */ 555 #define ADC_EXTERNALTRIG_HRTIM_TRG10 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). */ 556 #define ADC_EXTERNALTRIG_EXT_IT2 (LL_ADC_REG_TRIG_EXT_EXTI_LINE2) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 2. Trigger edge set to rising edge (default setting). */ 557 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ 558 #define ADC_EXTERNALTRIG_LPTIM_OUT (LL_ADC_REG_TRIG_EXT_LPTIM_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ 559 /** 560 * @} 561 */ 562 563 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 564 * @{ 565 */ 566 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */ 567 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ 568 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ 569 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ 570 /** 571 * @} 572 */ 573 574 /** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode 575 * @{ 576 */ 577 #define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */ 578 #define ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event. 579 Note: First conversion is using minimal sampling time (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */ 580 #define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events: 581 Trigger rising edge = start sampling 582 Trigger falling edge = stop sampling and start conversion */ 583 /** 584 * @} 585 */ 586 587 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 588 * @{ 589 */ 590 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 591 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 592 /** 593 * @} 594 */ 595 596 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 597 * @{ 598 */ 599 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ 600 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ 601 /** 602 * @} 603 */ 604 605 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 606 * @{ 607 */ 608 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 609 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 610 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 611 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 612 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 613 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 614 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 615 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 616 #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ 617 #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ 618 #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ 619 #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ 620 #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ 621 #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ 622 #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ 623 #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ 624 /** 625 * @} 626 */ 627 628 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 629 * @{ 630 */ 631 #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ 632 #define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */ 633 #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ 634 #define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */ 635 #define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */ 636 #define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */ 637 #define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */ 638 #define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */ 639 #define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */ 640 /** 641 * @} 642 */ 643 644 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 645 * @{ 646 */ 647 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ 648 /* all ADC instances (refer to Reference Manual). */ 649 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 650 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 651 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 652 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 653 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 654 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 655 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 656 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 657 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 658 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 659 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 660 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 661 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 662 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 663 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 664 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 665 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 666 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 667 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ 668 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2. */ 669 #define ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance. */ 670 #define ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */ 671 #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 series, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */ 672 #define ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_VOPAMP1) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance. */ 673 #define ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_VOPAMP2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance. */ 674 #define ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_VOPAMP3_ADC2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance. */ 675 #define ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_VOPAMP3_ADC3) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */ 676 #define ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_VOPAMP4) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ 677 #define ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_VOPAMP5) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ 678 #define ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_VOPAMP6) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 availability */ 679 /** 680 * @} 681 */ 682 683 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 684 * @{ 685 */ 686 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 687 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 688 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 689 /** 690 * @} 691 */ 692 693 /** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration 694 * @{ 695 */ 696 #define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */ 697 #define ADC_AWD_FILTERING_2SAMPLES ((ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */ 698 #define ADC_AWD_FILTERING_3SAMPLES ((ADC_TR1_AWDFILT_1)) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */ 699 #define ADC_AWD_FILTERING_4SAMPLES ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */ 700 #define ADC_AWD_FILTERING_5SAMPLES ((ADC_TR1_AWDFILT_2)) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */ 701 #define ADC_AWD_FILTERING_6SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */ 702 #define ADC_AWD_FILTERING_7SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */ 703 #define ADC_AWD_FILTERING_8SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */ 704 /** 705 * @} 706 */ 707 708 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode 709 * @{ 710 */ 711 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ 712 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ 713 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */ 714 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */ 715 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ 716 #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ 717 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */ 718 /** 719 * @} 720 */ 721 722 /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio 723 * @{ 724 */ 725 #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 726 #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 727 #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 728 #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 729 #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 730 #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 731 #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 732 #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 733 /** 734 * @} 735 */ 736 737 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 738 * @{ 739 */ 740 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ 741 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ 742 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ 743 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ 744 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ 745 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ 746 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ 747 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ 748 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ 749 /** 750 * @} 751 */ 752 753 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 754 * @{ 755 */ 756 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ 757 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ 758 /** 759 * @} 760 */ 761 762 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular 763 * @{ 764 */ 765 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */ 766 #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */ 767 /** 768 * @} 769 */ 770 771 /** @defgroup ADC_Event_type ADC Event type 772 * @{ 773 */ 774 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 775 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ 776 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ 777 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ 778 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 779 #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ 780 /** 781 * @} 782 */ 783 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ 784 785 /** @defgroup ADC_interrupts_definition ADC interrupts definition 786 * @{ 787 */ 788 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 789 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 790 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 791 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 792 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 793 #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ 794 #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ 795 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 796 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ 797 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ 798 #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ 799 800 #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ 801 802 /** 803 * @} 804 */ 805 806 /** @defgroup ADC_flags_definition ADC flags definition 807 * @{ 808 */ 809 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 810 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 811 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 812 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 813 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 814 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ 815 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ 816 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ 817 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ 818 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ 819 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ 820 821 /** 822 * @} 823 */ 824 825 /** 826 * @} 827 */ 828 829 /* Private macro -------------------------------------------------------------*/ 830 831 /** @defgroup ADC_Private_Macros ADC Private Macros 832 * @{ 833 */ 834 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 835 /* code of final user. */ 836 837 /** 838 * @brief Return resolution bits in CFGR register RES[1:0] field. 839 * @param __HANDLE__ ADC handle 840 * @retval Value of bitfield RES in CFGR register. 841 */ 842 #define ADC_GET_RESOLUTION(__HANDLE__) \ 843 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 844 845 /** 846 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 847 * @param __HANDLE__ ADC handle 848 * @retval None 849 */ 850 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 851 852 /** 853 * @brief Simultaneously clear and set specific bits of the handle State. 854 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 855 * the first parameter is the ADC handle State, the second parameter is the 856 * bit field to clear, the third and last parameter is the bit field to set. 857 * @retval None 858 */ 859 #define ADC_STATE_CLR_SET MODIFY_REG 860 861 /** 862 * @brief Verify that a given value is aligned with the ADC resolution range. 863 * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). 864 * @param __ADC_VALUE__ value checked against the resolution. 865 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 866 */ 867 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 868 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) 869 870 /** 871 * @brief Verify the length of the scheduled regular conversions group. 872 * @param __LENGTH__ number of programmed conversions. 873 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) 874 */ 875 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) 876 877 878 /** 879 * @brief Verify the number of scheduled regular conversions in discontinuous mode. 880 * @param NUMBER number of scheduled regular conversions in discontinuous mode. 881 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large) 882 */ 883 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) 884 885 886 /** 887 * @brief Verify the ADC clock setting. 888 * @param __ADC_CLOCK__ programmed ADC clock. 889 * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) 890 */ 891 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ 892 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 893 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 894 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ 895 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ 896 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ 897 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ 898 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ 899 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ 900 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ 901 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ 902 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ 903 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ 904 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ 905 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) 906 907 /** 908 * @brief Verify the ADC resolution setting. 909 * @param __RESOLUTION__ programmed ADC resolution. 910 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 911 */ 912 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 913 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 914 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 915 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 916 917 /** 918 * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. 919 * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. 920 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 921 */ 922 #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 923 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 924 925 /** 926 * @brief Verify the ADC converted data alignment. 927 * @param __ALIGN__ programmed ADC converted data alignment. 928 * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) 929 */ 930 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ 931 ((__ALIGN__) == ADC_DATAALIGN_LEFT) ) 932 933 /** 934 * @brief Verify the ADC gain compensation. 935 * @param __GAIN_COMPENSATION__ programmed ADC gain compensation coefficient. 936 * @retval SET (__GAIN_COMPENSATION__ is a valid value) or RESET (__GAIN_COMPENSATION__ is invalid) 937 */ 938 #define IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) ((__GAIN_COMPENSATION__) <= 16393UL) 939 940 /** 941 * @brief Verify the ADC scan mode. 942 * @param __SCAN_MODE__ programmed ADC scan mode. 943 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) 944 */ 945 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ 946 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) 947 948 /** 949 * @brief Verify the ADC edge trigger setting for regular group. 950 * @param __EDGE__ programmed ADC edge trigger setting. 951 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 952 */ 953 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 954 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 955 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 956 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 957 958 /** 959 * @brief Verify the ADC regular conversions external trigger. 960 * @param __HANDLE__ ADC handle 961 * @param __REGTRIG__ programmed ADC regular conversions external trigger. 962 * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) 963 */ 964 #if defined(STM32G474xx) || defined(STM32G484xx) 965 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 966 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 967 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 968 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 969 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 970 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 971 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 972 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ 973 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 974 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 975 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 976 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \ 977 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ 978 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ 979 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG1) || \ 980 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG3) || \ 981 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG5) || \ 982 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG6) || \ 983 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG7) || \ 984 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG8) || \ 985 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG9) || \ 986 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG10) || \ 987 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ 988 ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ 989 (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 990 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 991 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 992 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 993 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 994 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ 995 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ 996 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ 997 ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ 998 (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ 999 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ 1000 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ 1001 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ 1002 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ 1003 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG2) || \ 1004 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG4) || \ 1005 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ 1006 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1007 #elif defined(STM32G473xx) || defined(STM32G483xx) 1008 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 1009 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1010 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 1011 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1012 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 1013 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 1014 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 1015 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ 1016 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 1017 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 1018 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 1019 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \ 1020 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ 1021 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ 1022 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ 1023 ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ 1024 (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 1025 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 1026 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 1027 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 1028 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 1029 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ 1030 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ 1031 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ 1032 ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ 1033 (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ 1034 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ 1035 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ 1036 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ 1037 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ 1038 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ 1039 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1040 #elif defined(STM32G471xx) 1041 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 1042 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1043 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 1044 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1045 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 1046 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 1047 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 1048 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ 1049 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 1050 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 1051 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 1052 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ 1053 ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ 1054 (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 1055 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 1056 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 1057 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 1058 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 1059 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ 1060 ((((__HANDLE__)->Instance == ADC3)) && \ 1061 (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ 1062 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ 1063 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ 1064 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ 1065 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ 1066 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ 1067 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1068 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) 1069 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 1070 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1071 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 1072 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 1073 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 1074 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1075 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 1076 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 1077 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 1078 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 1079 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 1080 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 1081 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ 1082 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 1083 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 1084 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 1085 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ 1086 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 1087 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1088 #elif defined(STM32G491xx) || defined(STM32G4A1xx) 1089 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 1090 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1091 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 1092 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1093 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 1094 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 1095 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 1096 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ 1097 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 1098 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 1099 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 1100 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \ 1101 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ 1102 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ 1103 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ 1104 ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ 1105 (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 1106 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 1107 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 1108 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 1109 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 1110 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ 1111 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ 1112 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ 1113 (((__HANDLE__)->Instance == ADC3) && \ 1114 (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ 1115 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ 1116 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ 1117 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ 1118 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ 1119 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ 1120 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1121 #endif 1122 1123 /** 1124 * @brief Verify the ADC regular conversions external trigger. 1125 * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger. 1126 * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid) 1127 */ 1128 #define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \ 1129 ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \ 1130 ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED) ) 1131 1132 /** 1133 * @brief Verify the ADC regular conversions check for converted data availability. 1134 * @param __EOC_SELECTION__ converted data availability check. 1135 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) 1136 */ 1137 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ 1138 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) 1139 1140 /** 1141 * @brief Verify the ADC regular conversions overrun handling. 1142 * @param __OVR__ ADC regular conversions overrun handling. 1143 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) 1144 */ 1145 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ 1146 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) 1147 1148 /** 1149 * @brief Verify the ADC conversions sampling time. 1150 * @param __TIME__ ADC conversions sampling time. 1151 * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) 1152 */ 1153 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 1154 ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \ 1155 ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ 1156 ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ 1157 ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ 1158 ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ 1159 ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ 1160 ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ 1161 ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) 1162 1163 /** 1164 * @brief Verify the ADC regular channel setting. 1165 * @param __CHANNEL__ programmed ADC regular channel. 1166 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 1167 */ 1168 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ 1169 ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ 1170 ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ 1171 ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ 1172 ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ 1173 ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ 1174 ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ 1175 ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ 1176 ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ 1177 ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ 1178 ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ 1179 ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ 1180 ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ 1181 ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ 1182 ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ 1183 ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) 1184 1185 /** 1186 * @} 1187 */ 1188 1189 1190 /* Private constants ---------------------------------------------------------*/ 1191 1192 /** @defgroup ADC_Private_Constants ADC Private Constants 1193 * @{ 1194 */ 1195 1196 /* Fixed timeout values for ADC conversion (including sampling time) */ 1197 /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */ 1198 /* Maximum conversion time is 12.5 + Maximum sampling time */ 1199 /* or 12.5 + 640.5 = 653 ADC clock cycles */ 1200 /* Minimum ADC Clock frequency is 0.14 MHz */ 1201 /* Maximum conversion time is */ 1202 /* 653 / 0.14 MHz = 4.66 ms */ 1203 #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ 1204 1205 /* Delay for temperature sensor stabilization time. */ 1206 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ 1207 /* Unit: us */ 1208 #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) 1209 1210 /** 1211 * @} 1212 */ 1213 1214 /* Exported macro ------------------------------------------------------------*/ 1215 1216 /** @defgroup ADC_Exported_Macros ADC Exported Macros 1217 * @{ 1218 */ 1219 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 1220 /* final user. */ 1221 1222 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 1223 * @{ 1224 */ 1225 1226 /** @brief Reset ADC handle state. 1227 * @param __HANDLE__ ADC handle 1228 * @retval None 1229 */ 1230 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1231 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1232 do{ \ 1233 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 1234 (__HANDLE__)->MspInitCallback = NULL; \ 1235 (__HANDLE__)->MspDeInitCallback = NULL; \ 1236 } while(0) 1237 #else 1238 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1239 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 1240 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1241 1242 /** 1243 * @brief Enable ADC interrupt. 1244 * @param __HANDLE__ ADC handle 1245 * @param __INTERRUPT__ ADC Interrupt 1246 * This parameter can be one of the following values: 1247 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1248 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1249 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1250 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1251 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1252 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1253 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1254 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1255 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1256 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1257 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1258 * @retval None 1259 */ 1260 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1261 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 1262 1263 /** 1264 * @brief Disable ADC interrupt. 1265 * @param __HANDLE__ ADC handle 1266 * @param __INTERRUPT__ ADC Interrupt 1267 * This parameter can be one of the following values: 1268 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1269 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1270 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1271 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1272 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1273 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1274 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1275 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1276 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1277 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1278 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1279 * @retval None 1280 */ 1281 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1282 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 1283 1284 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 1285 * @param __HANDLE__ ADC handle 1286 * @param __INTERRUPT__ ADC interrupt source to check 1287 * This parameter can be one of the following values: 1288 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1289 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1290 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1291 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1292 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1293 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1294 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1295 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1296 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1297 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1298 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1299 * @retval State of interruption (SET or RESET) 1300 */ 1301 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 1302 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 1303 1304 /** 1305 * @brief Check whether the specified ADC flag is set or not. 1306 * @param __HANDLE__ ADC handle 1307 * @param __FLAG__ ADC flag 1308 * This parameter can be one of the following values: 1309 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1310 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1311 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1312 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1313 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1314 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1315 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1316 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1317 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1318 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1319 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1320 * @retval State of flag (TRUE or FALSE). 1321 */ 1322 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 1323 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 1324 1325 /** 1326 * @brief Clear the specified ADC flag. 1327 * @param __HANDLE__ ADC handle 1328 * @param __FLAG__ ADC flag 1329 * This parameter can be one of the following values: 1330 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1331 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1332 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1333 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1334 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1335 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1336 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1337 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1338 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1339 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1340 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1341 * @retval None 1342 */ 1343 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 1344 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1345 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 1346 1347 /** 1348 * @} 1349 */ 1350 1351 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 1352 * @{ 1353 */ 1354 1355 /** 1356 * @brief Helper macro to get ADC channel number in decimal format 1357 * from literals ADC_CHANNEL_x. 1358 * @note Example: 1359 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 1360 * will return decimal number "4". 1361 * @note The input can be a value from functions where a channel 1362 * number is returned, either defined with number 1363 * or with bitfield (only one bit must be set). 1364 * @param __CHANNEL__ This parameter can be one of the following values: 1365 * @arg @ref ADC_CHANNEL_0 1366 * @arg @ref ADC_CHANNEL_1 (8) 1367 * @arg @ref ADC_CHANNEL_2 (8) 1368 * @arg @ref ADC_CHANNEL_3 (8) 1369 * @arg @ref ADC_CHANNEL_4 (8) 1370 * @arg @ref ADC_CHANNEL_5 (8) 1371 * @arg @ref ADC_CHANNEL_6 1372 * @arg @ref ADC_CHANNEL_7 1373 * @arg @ref ADC_CHANNEL_8 1374 * @arg @ref ADC_CHANNEL_9 1375 * @arg @ref ADC_CHANNEL_10 1376 * @arg @ref ADC_CHANNEL_11 1377 * @arg @ref ADC_CHANNEL_12 1378 * @arg @ref ADC_CHANNEL_13 1379 * @arg @ref ADC_CHANNEL_14 1380 * @arg @ref ADC_CHANNEL_15 1381 * @arg @ref ADC_CHANNEL_16 1382 * @arg @ref ADC_CHANNEL_17 1383 * @arg @ref ADC_CHANNEL_18 1384 * @arg @ref ADC_CHANNEL_VREFINT (7) 1385 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) 1386 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) 1387 * @arg @ref ADC_CHANNEL_VBAT (6) 1388 * @arg @ref ADC_CHANNEL_VOPAMP1 (1) 1389 * @arg @ref ADC_CHANNEL_VOPAMP2 (2) 1390 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) 1391 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) 1392 * @arg @ref ADC_CHANNEL_VOPAMP4 (5) 1393 * @arg @ref ADC_CHANNEL_VOPAMP5 (5) 1394 * @arg @ref ADC_CHANNEL_VOPAMP6 (4) 1395 * 1396 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n 1397 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n 1398 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n 1399 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n 1400 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n 1401 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n 1402 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n 1403 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. 1404 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. 1405 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n 1406 * @retval Value between Min_Data=0 and Max_Data=18 1407 */ 1408 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 1409 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 1410 1411 /** 1412 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 1413 * from number in decimal format. 1414 * @note Example: 1415 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 1416 * will return a data equivalent to "ADC_CHANNEL_4". 1417 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 1418 * @retval Returned value can be one of the following values: 1419 * @arg @ref ADC_CHANNEL_0 1420 * @arg @ref ADC_CHANNEL_1 (8) 1421 * @arg @ref ADC_CHANNEL_2 (8) 1422 * @arg @ref ADC_CHANNEL_3 (8) 1423 * @arg @ref ADC_CHANNEL_4 (8) 1424 * @arg @ref ADC_CHANNEL_5 (8) 1425 * @arg @ref ADC_CHANNEL_6 1426 * @arg @ref ADC_CHANNEL_7 1427 * @arg @ref ADC_CHANNEL_8 1428 * @arg @ref ADC_CHANNEL_9 1429 * @arg @ref ADC_CHANNEL_10 1430 * @arg @ref ADC_CHANNEL_11 1431 * @arg @ref ADC_CHANNEL_12 1432 * @arg @ref ADC_CHANNEL_13 1433 * @arg @ref ADC_CHANNEL_14 1434 * @arg @ref ADC_CHANNEL_15 1435 * @arg @ref ADC_CHANNEL_16 1436 * @arg @ref ADC_CHANNEL_17 1437 * @arg @ref ADC_CHANNEL_18 1438 * @arg @ref ADC_CHANNEL_VREFINT (7) 1439 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) 1440 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) 1441 * @arg @ref ADC_CHANNEL_VBAT (6) 1442 * @arg @ref ADC_CHANNEL_VOPAMP1 (1) 1443 * @arg @ref ADC_CHANNEL_VOPAMP2 (2) 1444 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) 1445 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) 1446 * @arg @ref ADC_CHANNEL_VOPAMP4 (5) 1447 * @arg @ref ADC_CHANNEL_VOPAMP5 (5) 1448 * @arg @ref ADC_CHANNEL_VOPAMP6 (4) 1449 * 1450 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n 1451 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n 1452 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n 1453 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n 1454 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n 1455 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n 1456 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n 1457 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. 1458 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. 1459 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n 1460 * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, 1461 * comparison with internal channel parameter to be done 1462 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1463 */ 1464 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 1465 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 1466 1467 /** 1468 * @brief Helper macro to determine whether the selected channel 1469 * corresponds to literal definitions of driver. 1470 * @note The different literal definitions of ADC channels are: 1471 * - ADC internal channel: 1472 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... 1473 * - ADC external channel (channel connected to a GPIO pin): 1474 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 1475 * @note The channel parameter must be a value defined from literal 1476 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1477 * ADC_CHANNEL_TEMPSENSOR, ...), 1478 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 1479 * must not be a value from functions where a channel number is 1480 * returned from ADC registers, 1481 * because internal and external channels share the same channel 1482 * number in ADC registers. The differentiation is made only with 1483 * parameters definitions of driver. 1484 * @param __CHANNEL__ This parameter can be one of the following values: 1485 * @arg @ref ADC_CHANNEL_0 1486 * @arg @ref ADC_CHANNEL_1 (8) 1487 * @arg @ref ADC_CHANNEL_2 (8) 1488 * @arg @ref ADC_CHANNEL_3 (8) 1489 * @arg @ref ADC_CHANNEL_4 (8) 1490 * @arg @ref ADC_CHANNEL_5 (8) 1491 * @arg @ref ADC_CHANNEL_6 1492 * @arg @ref ADC_CHANNEL_7 1493 * @arg @ref ADC_CHANNEL_8 1494 * @arg @ref ADC_CHANNEL_9 1495 * @arg @ref ADC_CHANNEL_10 1496 * @arg @ref ADC_CHANNEL_11 1497 * @arg @ref ADC_CHANNEL_12 1498 * @arg @ref ADC_CHANNEL_13 1499 * @arg @ref ADC_CHANNEL_14 1500 * @arg @ref ADC_CHANNEL_15 1501 * @arg @ref ADC_CHANNEL_16 1502 * @arg @ref ADC_CHANNEL_17 1503 * @arg @ref ADC_CHANNEL_18 1504 * @arg @ref ADC_CHANNEL_VREFINT (7) 1505 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) 1506 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) 1507 * @arg @ref ADC_CHANNEL_VBAT (6) 1508 * @arg @ref ADC_CHANNEL_VOPAMP1 (1) 1509 * @arg @ref ADC_CHANNEL_VOPAMP2 (2) 1510 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) 1511 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) 1512 * @arg @ref ADC_CHANNEL_VOPAMP4 (5) 1513 * @arg @ref ADC_CHANNEL_VOPAMP5 (5) 1514 * @arg @ref ADC_CHANNEL_VOPAMP6 (4) 1515 * 1516 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n 1517 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n 1518 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n 1519 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n 1520 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n 1521 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n 1522 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n 1523 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. 1524 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. 1525 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n 1526 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). 1527 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 1528 */ 1529 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 1530 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 1531 1532 /** 1533 * @brief Helper macro to convert a channel defined from parameter 1534 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1535 * ADC_CHANNEL_TEMPSENSOR, ...), 1536 * to its equivalent parameter definition of a ADC external channel 1537 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 1538 * @note The channel parameter can be, additionally to a value 1539 * defined from parameter definition of a ADC internal channel 1540 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), 1541 * a value defined from parameter definition of 1542 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1543 * or a value from functions where a channel number is returned 1544 * from ADC registers. 1545 * @param __CHANNEL__ This parameter can be one of the following values: 1546 * @arg @ref ADC_CHANNEL_0 1547 * @arg @ref ADC_CHANNEL_1 (8) 1548 * @arg @ref ADC_CHANNEL_2 (8) 1549 * @arg @ref ADC_CHANNEL_3 (8) 1550 * @arg @ref ADC_CHANNEL_4 (8) 1551 * @arg @ref ADC_CHANNEL_5 (8) 1552 * @arg @ref ADC_CHANNEL_6 1553 * @arg @ref ADC_CHANNEL_7 1554 * @arg @ref ADC_CHANNEL_8 1555 * @arg @ref ADC_CHANNEL_9 1556 * @arg @ref ADC_CHANNEL_10 1557 * @arg @ref ADC_CHANNEL_11 1558 * @arg @ref ADC_CHANNEL_12 1559 * @arg @ref ADC_CHANNEL_13 1560 * @arg @ref ADC_CHANNEL_14 1561 * @arg @ref ADC_CHANNEL_15 1562 * @arg @ref ADC_CHANNEL_16 1563 * @arg @ref ADC_CHANNEL_17 1564 * @arg @ref ADC_CHANNEL_18 1565 * @arg @ref ADC_CHANNEL_VREFINT (7) 1566 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) 1567 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) 1568 * @arg @ref ADC_CHANNEL_VBAT (6) 1569 * @arg @ref ADC_CHANNEL_VOPAMP1 (1) 1570 * @arg @ref ADC_CHANNEL_VOPAMP2 (2) 1571 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) 1572 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) 1573 * @arg @ref ADC_CHANNEL_VOPAMP4 (5) 1574 * @arg @ref ADC_CHANNEL_VOPAMP5 (5) 1575 * @arg @ref ADC_CHANNEL_VOPAMP6 (4) 1576 * 1577 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n 1578 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n 1579 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n 1580 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n 1581 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n 1582 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n 1583 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n 1584 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. 1585 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. 1586 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n 1587 * @retval Returned value can be one of the following values: 1588 * @arg @ref ADC_CHANNEL_0 1589 * @arg @ref ADC_CHANNEL_1 1590 * @arg @ref ADC_CHANNEL_2 1591 * @arg @ref ADC_CHANNEL_3 1592 * @arg @ref ADC_CHANNEL_4 1593 * @arg @ref ADC_CHANNEL_5 1594 * @arg @ref ADC_CHANNEL_6 1595 * @arg @ref ADC_CHANNEL_7 1596 * @arg @ref ADC_CHANNEL_8 1597 * @arg @ref ADC_CHANNEL_9 1598 * @arg @ref ADC_CHANNEL_10 1599 * @arg @ref ADC_CHANNEL_11 1600 * @arg @ref ADC_CHANNEL_12 1601 * @arg @ref ADC_CHANNEL_13 1602 * @arg @ref ADC_CHANNEL_14 1603 * @arg @ref ADC_CHANNEL_15 1604 * @arg @ref ADC_CHANNEL_16 1605 * @arg @ref ADC_CHANNEL_17 1606 * @arg @ref ADC_CHANNEL_18 1607 */ 1608 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 1609 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 1610 1611 /** 1612 * @brief Helper macro to determine whether the internal channel 1613 * selected is available on the ADC instance selected. 1614 * @note The channel parameter must be a value defined from parameter 1615 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1616 * ADC_CHANNEL_TEMPSENSOR, ...), 1617 * must not be a value defined from parameter definition of 1618 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1619 * or a value from functions where a channel number is 1620 * returned from ADC registers, 1621 * because internal and external channels share the same channel 1622 * number in ADC registers. The differentiation is made only with 1623 * parameters definitions of driver. 1624 * @param __ADC_INSTANCE__ ADC instance 1625 * @param __CHANNEL__ This parameter can be one of the following values: 1626 * @arg @ref ADC_CHANNEL_VREFINT (7) 1627 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) 1628 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) 1629 * @arg @ref ADC_CHANNEL_VBAT (6) 1630 * @arg @ref ADC_CHANNEL_VOPAMP1 (1) 1631 * @arg @ref ADC_CHANNEL_VOPAMP2 (2) 1632 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) 1633 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) 1634 * @arg @ref ADC_CHANNEL_VOPAMP4 (5) 1635 * @arg @ref ADC_CHANNEL_VOPAMP5 (5) 1636 * @arg @ref ADC_CHANNEL_VOPAMP6 (4) 1637 * 1638 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n 1639 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n 1640 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n 1641 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n 1642 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n 1643 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n 1644 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n 1645 * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. 1646 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 1647 * Value "1" if the internal channel selected is available on the ADC instance selected. 1648 */ 1649 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 1650 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 1651 1652 #if defined(ADC_MULTIMODE_SUPPORT) 1653 /** 1654 * @brief Helper macro to get the ADC multimode conversion data of ADC master 1655 * or ADC slave from raw value with both ADC conversion data concatenated. 1656 * @note This macro is intended to be used when multimode transfer by DMA 1657 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 1658 * In this case the transferred data need to processed with this macro 1659 * to separate the conversion data of ADC master and ADC slave. 1660 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 1661 * @arg @ref LL_ADC_MULTI_MASTER 1662 * @arg @ref LL_ADC_MULTI_SLAVE 1663 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 1664 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 1665 */ 1666 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 1667 __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) 1668 #endif /* ADC_MULTIMODE_SUPPORT */ 1669 1670 /** 1671 * @brief Helper macro to select the ADC common instance 1672 * to which is belonging the selected ADC instance. 1673 * @note ADC common register instance can be used for: 1674 * - Set parameters common to several ADC instances 1675 * - Multimode (for devices with several ADC instances) 1676 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1677 * @param __ADCx__ ADC instance 1678 * @retval ADC common register instance 1679 */ 1680 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 1681 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 1682 1683 /** 1684 * @brief Helper macro to check if all ADC instances sharing the same 1685 * ADC common instance are disabled. 1686 * @note This check is required by functions with setting conditioned to 1687 * ADC state: 1688 * All ADC instances of the ADC common group must be disabled. 1689 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1690 * @note On devices with only 1 ADC common instance, parameter of this macro 1691 * is useless and can be ignored (parameter kept for compatibility 1692 * with devices featuring several ADC common instances). 1693 * @param __ADCXY_COMMON__ ADC common instance 1694 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1695 * @retval Value "0" if all ADC instances sharing the same ADC common instance 1696 * are disabled. 1697 * Value "1" if at least one ADC instance sharing the same ADC common instance 1698 * is enabled. 1699 */ 1700 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1701 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 1702 1703 /** 1704 * @brief Helper macro to define the ADC conversion data full-scale digital 1705 * value corresponding to the selected ADC resolution. 1706 * @note ADC conversion data full-scale corresponds to voltage range 1707 * determined by analog voltage references Vref+ and Vref- 1708 * (refer to reference manual). 1709 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1710 * @arg @ref ADC_RESOLUTION_12B 1711 * @arg @ref ADC_RESOLUTION_10B 1712 * @arg @ref ADC_RESOLUTION_8B 1713 * @arg @ref ADC_RESOLUTION_6B 1714 * @retval ADC conversion data full-scale digital value 1715 */ 1716 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1717 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 1718 1719 /** 1720 * @brief Helper macro to convert the ADC conversion data from 1721 * a resolution to another resolution. 1722 * @param __DATA__ ADC conversion data to be converted 1723 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 1724 * This parameter can be one of the following values: 1725 * @arg @ref ADC_RESOLUTION_12B 1726 * @arg @ref ADC_RESOLUTION_10B 1727 * @arg @ref ADC_RESOLUTION_8B 1728 * @arg @ref ADC_RESOLUTION_6B 1729 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 1730 * This parameter can be one of the following values: 1731 * @arg @ref ADC_RESOLUTION_12B 1732 * @arg @ref ADC_RESOLUTION_10B 1733 * @arg @ref ADC_RESOLUTION_8B 1734 * @arg @ref ADC_RESOLUTION_6B 1735 * @retval ADC conversion data to the requested resolution 1736 */ 1737 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 1738 __ADC_RESOLUTION_CURRENT__,\ 1739 __ADC_RESOLUTION_TARGET__) \ 1740 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ 1741 (__ADC_RESOLUTION_CURRENT__),\ 1742 (__ADC_RESOLUTION_TARGET__)) 1743 1744 /** 1745 * @brief Helper macro to calculate the voltage (unit: mVolt) 1746 * corresponding to a ADC conversion data (unit: digital value). 1747 * @note Analog reference voltage (Vref+) must be either known from 1748 * user board environment or can be calculated using ADC measurement 1749 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1750 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1751 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 1752 * (unit: digital value). 1753 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1754 * @arg @ref ADC_RESOLUTION_12B 1755 * @arg @ref ADC_RESOLUTION_10B 1756 * @arg @ref ADC_RESOLUTION_8B 1757 * @arg @ref ADC_RESOLUTION_6B 1758 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1759 */ 1760 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 1761 __ADC_DATA__,\ 1762 __ADC_RESOLUTION__) \ 1763 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 1764 (__ADC_DATA__),\ 1765 (__ADC_RESOLUTION__)) 1766 1767 /** 1768 * @brief Helper macro to calculate analog reference voltage (Vref+) 1769 * (unit: mVolt) from ADC conversion data of internal voltage 1770 * reference VrefInt. 1771 * @note Computation is using VrefInt calibration value 1772 * stored in system memory for each device during production. 1773 * @note This voltage depends on user board environment: voltage level 1774 * connected to pin Vref+. 1775 * On devices with small package, the pin Vref+ is not present 1776 * and internally bonded to pin Vdda. 1777 * @note On this STM32 series, calibration data of internal voltage reference 1778 * VrefInt corresponds to a resolution of 12 bits, 1779 * this is the recommended ADC resolution to convert voltage of 1780 * internal voltage reference VrefInt. 1781 * Otherwise, this macro performs the processing to scale 1782 * ADC conversion data to 12 bits. 1783 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 1784 * of internal voltage reference VrefInt (unit: digital value). 1785 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1786 * @arg @ref ADC_RESOLUTION_12B 1787 * @arg @ref ADC_RESOLUTION_10B 1788 * @arg @ref ADC_RESOLUTION_8B 1789 * @arg @ref ADC_RESOLUTION_6B 1790 * @retval Analog reference voltage (unit: mV) 1791 */ 1792 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 1793 __ADC_RESOLUTION__) \ 1794 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ 1795 (__ADC_RESOLUTION__)) 1796 1797 /** 1798 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1799 * from ADC conversion data of internal temperature sensor. 1800 * @note Computation is using temperature sensor calibration values 1801 * stored in system memory for each device during production. 1802 * @note Calculation formula: 1803 * Temperature = ((TS_ADC_DATA - TS_CAL1) 1804 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 1805 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 1806 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1807 * Avg_Slope = (TS_CAL2 - TS_CAL1) 1808 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 1809 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 1810 * TEMP_DEGC_CAL1 (calibrated in factory) 1811 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 1812 * TEMP_DEGC_CAL2 (calibrated in factory) 1813 * Caution: Calculation relevancy under reserve that calibration 1814 * parameters are correct (address and data). 1815 * To calculate temperature using temperature sensor 1816 * datasheet typical values (generic values less, therefore 1817 * less accurate than calibrated values), 1818 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 1819 * @note As calculation input, the analog reference voltage (Vref+) must be 1820 * defined as it impacts the ADC LSB equivalent voltage. 1821 * @note Analog reference voltage (Vref+) must be either known from 1822 * user board environment or can be calculated using ADC measurement 1823 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1824 * @note On this STM32 series, calibration data of temperature sensor 1825 * corresponds to a resolution of 12 bits, 1826 * this is the recommended ADC resolution to convert voltage of 1827 * temperature sensor. 1828 * Otherwise, this macro performs the processing to scale 1829 * ADC conversion data to 12 bits. 1830 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1831 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 1832 * temperature sensor (unit: digital value). 1833 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 1834 * sensor voltage has been measured. 1835 * This parameter can be one of the following values: 1836 * @arg @ref ADC_RESOLUTION_12B 1837 * @arg @ref ADC_RESOLUTION_10B 1838 * @arg @ref ADC_RESOLUTION_8B 1839 * @arg @ref ADC_RESOLUTION_6B 1840 * @retval Temperature (unit: degree Celsius) 1841 */ 1842 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 1843 __TEMPSENSOR_ADC_DATA__,\ 1844 __ADC_RESOLUTION__) \ 1845 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ 1846 (__TEMPSENSOR_ADC_DATA__),\ 1847 (__ADC_RESOLUTION__)) 1848 1849 /** 1850 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1851 * from ADC conversion data of internal temperature sensor. 1852 * @note Computation is using temperature sensor typical values 1853 * (refer to device datasheet). 1854 * @note Calculation formula: 1855 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 1856 * / Avg_Slope + CALx_TEMP 1857 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1858 * (unit: digital value) 1859 * Avg_Slope = temperature sensor slope 1860 * (unit: uV/Degree Celsius) 1861 * TS_TYP_CALx_VOLT = temperature sensor digital value at 1862 * temperature CALx_TEMP (unit: mV) 1863 * Caution: Calculation relevancy under reserve the temperature sensor 1864 * of the current device has characteristics in line with 1865 * datasheet typical values. 1866 * If temperature sensor calibration values are available on 1867 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 1868 * temperature calculation will be more accurate using 1869 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 1870 * @note As calculation input, the analog reference voltage (Vref+) must be 1871 * defined as it impacts the ADC LSB equivalent voltage. 1872 * @note Analog reference voltage (Vref+) must be either known from 1873 * user board environment or can be calculated using ADC measurement 1874 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1875 * @note ADC measurement data must correspond to a resolution of 12bits 1876 * (full scale digital value 4095). If not the case, the data must be 1877 * preliminarily rescaled to an equivalent resolution of 12 bits. 1878 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). 1879 * On STM32G4, refer to device datasheet parameter "Avg_Slope". 1880 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). 1881 * On STM32G4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). 1882 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) 1883 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 1884 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 1885 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 1886 * This parameter can be one of the following values: 1887 * @arg @ref ADC_RESOLUTION_12B 1888 * @arg @ref ADC_RESOLUTION_10B 1889 * @arg @ref ADC_RESOLUTION_8B 1890 * @arg @ref ADC_RESOLUTION_6B 1891 * @retval Temperature (unit: degree Celsius) 1892 */ 1893 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 1894 __TEMPSENSOR_TYP_CALX_V__,\ 1895 __TEMPSENSOR_CALX_TEMP__,\ 1896 __VREFANALOG_VOLTAGE__,\ 1897 __TEMPSENSOR_ADC_DATA__,\ 1898 __ADC_RESOLUTION__) \ 1899 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ 1900 (__TEMPSENSOR_TYP_CALX_V__),\ 1901 (__TEMPSENSOR_CALX_TEMP__),\ 1902 (__VREFANALOG_VOLTAGE__),\ 1903 (__TEMPSENSOR_ADC_DATA__),\ 1904 (__ADC_RESOLUTION__)) 1905 1906 /** 1907 * @} 1908 */ 1909 1910 /** 1911 * @} 1912 */ 1913 1914 /* Include ADC HAL Extended module */ 1915 #include "stm32g4xx_hal_adc_ex.h" 1916 1917 /* Exported functions --------------------------------------------------------*/ 1918 /** @addtogroup ADC_Exported_Functions 1919 * @{ 1920 */ 1921 1922 /** @addtogroup ADC_Exported_Functions_Group1 1923 * @brief Initialization and Configuration functions 1924 * @{ 1925 */ 1926 /* Initialization and de-initialization functions ****************************/ 1927 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); 1928 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1929 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); 1930 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); 1931 1932 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1933 /* Callbacks Register/UnRegister functions ***********************************/ 1934 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, 1935 pADC_CallbackTypeDef pCallback); 1936 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 1937 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1938 /** 1939 * @} 1940 */ 1941 1942 /** @addtogroup ADC_Exported_Functions_Group2 1943 * @brief IO operation functions 1944 * @{ 1945 */ 1946 /* IO operation functions *****************************************************/ 1947 1948 /* Blocking mode: Polling */ 1949 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); 1950 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); 1951 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1952 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); 1953 1954 /* Non-blocking mode: Interruption */ 1955 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); 1956 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); 1957 1958 /* Non-blocking mode: DMA */ 1959 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1960 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); 1961 1962 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1963 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); 1964 1965 /* ADC sampling control */ 1966 HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc); 1967 HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc); 1968 1969 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 1970 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); 1971 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); 1972 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); 1973 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); 1974 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 1975 /** 1976 * @} 1977 */ 1978 1979 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 1980 * @brief Peripheral Control functions 1981 * @{ 1982 */ 1983 /* Peripheral Control functions ***********************************************/ 1984 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); 1985 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); 1986 1987 /** 1988 * @} 1989 */ 1990 1991 /* Peripheral State functions *************************************************/ 1992 /** @addtogroup ADC_Exported_Functions_Group4 1993 * @{ 1994 */ 1995 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); 1996 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 1997 1998 /** 1999 * @} 2000 */ 2001 2002 /** 2003 * @} 2004 */ 2005 2006 /* Private functions -----------------------------------------------------------*/ 2007 /** @addtogroup ADC_Private_Functions ADC Private Functions 2008 * @{ 2009 */ 2010 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); 2011 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); 2012 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); 2013 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 2014 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 2015 void ADC_DMAError(DMA_HandleTypeDef *hdma); 2016 2017 /** 2018 * @} 2019 */ 2020 2021 /** 2022 * @} 2023 */ 2024 2025 /** 2026 * @} 2027 */ 2028 2029 #ifdef __cplusplus 2030 } 2031 #endif 2032 2033 2034 #endif /* STM32G4xx_HAL_ADC_H */ 2035
