1 /** 2 ****************************************************************************** 3 * @file stm32_hal_legacy.h 4 * @author MCD Application Team 5 * @brief This file contains aliases definition for the STM32Cube HAL constants 6 * macros and functions maintained for legacy purpose. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32_HAL_LEGACY 22 #define STM32_HAL_LEGACY 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 /* Exported types ------------------------------------------------------------*/ 30 /* Exported constants --------------------------------------------------------*/ 31 32 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose 33 * @{ 34 */ 35 #define AES_FLAG_RDERR CRYP_FLAG_RDERR 36 #define AES_FLAG_WRERR CRYP_FLAG_WRERR 37 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF 38 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR 39 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR 40 #if defined(STM32U5) 41 #define CRYP_DATATYPE_32B CRYP_NO_SWAP 42 #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP 43 #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP 44 #define CRYP_DATATYPE_1B CRYP_BIT_SWAP 45 #define CRYP_CCF_CLEAR CRYP_CLEAR_CCF 46 #define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF 47 #endif /* STM32U5 */ 48 /** 49 * @} 50 */ 51 52 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose 53 * @{ 54 */ 55 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B 56 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B 57 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B 58 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B 59 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN 60 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED 61 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV 62 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV 63 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV 64 #define REGULAR_GROUP ADC_REGULAR_GROUP 65 #define INJECTED_GROUP ADC_INJECTED_GROUP 66 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP 67 #define AWD_EVENT ADC_AWD_EVENT 68 #define AWD1_EVENT ADC_AWD1_EVENT 69 #define AWD2_EVENT ADC_AWD2_EVENT 70 #define AWD3_EVENT ADC_AWD3_EVENT 71 #define OVR_EVENT ADC_OVR_EVENT 72 #define JQOVF_EVENT ADC_JQOVF_EVENT 73 #define ALL_CHANNELS ADC_ALL_CHANNELS 74 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS 75 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS 76 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR 77 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT 78 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 79 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 80 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 81 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 82 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 83 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO 84 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 85 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO 86 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 87 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO 88 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 89 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 90 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE 91 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING 92 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING 93 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING 94 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 95 96 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY 97 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY 98 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC 99 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC 100 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL 101 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL 102 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 103 104 #if defined(STM32H7) 105 #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT 106 #endif /* STM32H7 */ 107 /** 108 * @} 109 */ 110 111 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose 112 * @{ 113 */ 114 115 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 116 117 /** 118 * @} 119 */ 120 121 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose 122 * @{ 123 */ 124 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE 125 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE 126 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 127 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 128 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 129 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 130 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 131 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 132 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 133 #if defined(STM32L0) 134 #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ 135 #endif 136 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR 137 #if defined(STM32F373xC) || defined(STM32F378xx) 138 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 139 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR 140 #endif /* STM32F373xC || STM32F378xx */ 141 142 #if defined(STM32L0) || defined(STM32L4) 143 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON 144 145 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 146 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 147 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 148 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 149 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 150 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 151 152 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT 153 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT 154 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT 155 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT 156 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 157 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 158 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 159 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 160 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 161 #if defined(STM32L0) 162 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ 163 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ 164 /* to the second dedicated IO (only for COMP2). */ 165 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 166 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 167 #else 168 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 169 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 170 #endif 171 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 172 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 173 174 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW 175 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH 176 177 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ 178 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ 179 #if defined(COMP_CSR_LOCK) 180 #define COMP_FLAG_LOCK COMP_CSR_LOCK 181 #elif defined(COMP_CSR_COMP1LOCK) 182 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK 183 #elif defined(COMP_CSR_COMPxLOCK) 184 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK 185 #endif 186 187 #if defined(STM32L4) 188 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 189 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 190 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 191 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 192 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 193 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 194 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE 195 #endif 196 197 #if defined(STM32L0) 198 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED 199 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER 200 #else 201 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED 202 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED 203 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER 204 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER 205 #endif 206 207 #endif 208 /** 209 * @} 210 */ 211 212 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose 213 * @{ 214 */ 215 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig 216 #if defined(STM32U5) 217 #define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE 218 #define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE 219 #define MPU_DEVICE_nGRE MPU_DEVICE_NGRE 220 #endif /* STM32U5 */ 221 /** 222 * @} 223 */ 224 225 /** @defgroup CRC_Aliases CRC API aliases 226 * @{ 227 */ 228 #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ 229 #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ 230 /** 231 * @} 232 */ 233 234 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose 235 * @{ 236 */ 237 238 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE 239 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE 240 241 /** 242 * @} 243 */ 244 245 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose 246 * @{ 247 */ 248 249 #define DAC1_CHANNEL_1 DAC_CHANNEL_1 250 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 251 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 252 #define DAC_WAVE_NONE 0x00000000U 253 #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 254 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 255 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE 256 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE 257 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE 258 259 #if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) 260 #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL 261 #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL 262 #endif 263 264 #if defined(STM32U5) 265 #define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 266 #define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 267 #define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 268 #define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 269 #endif 270 271 #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) 272 #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID 273 #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID 274 #endif 275 276 /** 277 * @} 278 */ 279 280 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose 281 * @{ 282 */ 283 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 284 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 285 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 286 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 287 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 288 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 289 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 290 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 291 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 292 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 293 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 294 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 295 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 296 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 297 298 #define IS_HAL_REMAPDMA IS_DMA_REMAP 299 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE 300 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE 301 302 #if defined(STM32L4) 303 304 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 305 #define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 306 #define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 307 #define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 308 #define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 309 #define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 310 #define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 311 #define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 312 #define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 313 #define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 314 #define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 315 #define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 316 #define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 317 #define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 318 #define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 319 #define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 320 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 321 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 322 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 323 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 324 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 325 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 326 #define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE 327 #define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT 328 #define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 329 #define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT 330 331 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 332 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 333 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 334 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 335 336 #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 337 #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI 338 #endif 339 340 #endif /* STM32L4 */ 341 342 #if defined(STM32G0) 343 #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 344 #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 345 #define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM 346 #define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM 347 348 #define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM 349 #define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM 350 #endif 351 352 #if defined(STM32H7) 353 354 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 355 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 356 357 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX 358 #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX 359 360 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 361 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 362 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 363 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 364 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 365 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 366 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 367 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 368 369 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 370 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 371 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 372 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 373 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 374 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 375 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 376 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 377 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 378 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 379 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 380 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 381 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 382 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 383 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 384 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 385 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 386 #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT 387 #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT 388 #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP 389 #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 390 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 391 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 392 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT 393 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 394 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 395 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT 396 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 397 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 398 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 399 400 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 401 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 402 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 403 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 404 405 #define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT 406 #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT 407 #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT 408 409 #define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT 410 #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT 411 412 #endif /* STM32H7 */ 413 /** 414 * @} 415 */ 416 417 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose 418 * @{ 419 */ 420 421 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE 422 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD 423 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD 424 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD 425 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS 426 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES 427 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES 428 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE 429 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE 430 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE 431 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE 432 #define OBEX_PCROP OPTIONBYTE_PCROP 433 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG 434 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE 435 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE 436 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE 437 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD 438 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD 439 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE 440 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD 441 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD 442 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE 443 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD 444 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD 445 #define PAGESIZE FLASH_PAGE_SIZE 446 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE 447 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD 448 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD 449 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 450 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 451 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 452 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 453 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST 454 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST 455 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA 456 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB 457 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA 458 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB 459 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE 460 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN 461 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE 462 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN 463 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE 464 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD 465 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG 466 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS 467 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP 468 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV 469 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR 470 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG 471 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION 472 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA 473 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE 474 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE 475 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS 476 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS 477 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST 478 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR 479 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO 480 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION 481 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS 482 #define OB_WDG_SW OB_IWDG_SW 483 #define OB_WDG_HW OB_IWDG_HW 484 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET 485 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET 486 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET 487 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET 488 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR 489 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 490 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 491 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 492 #if defined(STM32G0) 493 #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE 494 #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH 495 #else 496 #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE 497 #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE 498 #endif 499 #if defined(STM32H7) 500 #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 501 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 502 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 503 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 504 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 505 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 506 #define FLASH_FLAG_WDW FLASH_FLAG_WBNE 507 #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL 508 #endif /* STM32H7 */ 509 #if defined(STM32U5) 510 #define OB_USER_nRST_STOP OB_USER_NRST_STOP 511 #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY 512 #define OB_USER_nRST_SHDW OB_USER_NRST_SHDW 513 #define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 514 #define OB_USER_nBOOT0 OB_USER_NBOOT0 515 #define OB_nBOOT0_RESET OB_NBOOT0_RESET 516 #define OB_nBOOT0_SET OB_NBOOT0_SET 517 #endif /* STM32U5 */ 518 519 /** 520 * @} 521 */ 522 523 /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose 524 * @{ 525 */ 526 527 #if defined(STM32H7) 528 #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE 529 #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE 530 #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET 531 #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET 532 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE 533 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE 534 #endif /* STM32H7 */ 535 536 /** 537 * @} 538 */ 539 540 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose 541 * @{ 542 */ 543 544 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 545 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 546 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 547 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 548 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 549 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 550 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 551 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 552 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 553 #if defined(STM32G4) 554 555 #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster 556 #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster 557 #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD 558 #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD 559 #endif /* STM32G4 */ 560 561 /** 562 * @} 563 */ 564 565 566 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose 567 * @{ 568 */ 569 #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) 570 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE 571 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE 572 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 573 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 574 #elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) 575 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE 576 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE 577 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 578 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 579 #endif 580 /** 581 * @} 582 */ 583 584 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose 585 * @{ 586 */ 587 588 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef 589 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef 590 /** 591 * @} 592 */ 593 594 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose 595 * @{ 596 */ 597 #define GET_GPIO_SOURCE GPIO_GET_INDEX 598 #define GET_GPIO_INDEX GPIO_GET_INDEX 599 600 #if defined(STM32F4) 601 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO 602 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO 603 #endif 604 605 #if defined(STM32F7) 606 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 607 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 608 #endif 609 610 #if defined(STM32L4) 611 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 612 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 613 #endif 614 615 #if defined(STM32H7) 616 #define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 617 #define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 618 #define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 619 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 620 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 621 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 622 623 #if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ 624 defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) 625 #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS 626 #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS 627 #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS 628 #endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ 629 #endif /* STM32H7 */ 630 631 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 632 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 633 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 634 635 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) 636 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 637 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 638 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH 639 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 640 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ 641 642 #if defined(STM32L1) 643 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW 644 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM 645 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH 646 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 647 #endif /* STM32L1 */ 648 649 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) 650 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 651 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 652 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH 653 #endif /* STM32F0 || STM32F3 || STM32F1 */ 654 655 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 656 657 #if defined(STM32U5) 658 #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ 659 #endif /* STM32U5 */ 660 /** 661 * @} 662 */ 663 664 /** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose 665 * @{ 666 */ 667 #if defined(STM32U5) 668 #define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI 669 #endif /* STM32U5 */ 670 /** 671 * @} 672 */ 673 674 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose 675 * @{ 676 */ 677 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED 678 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 679 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 680 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 681 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 682 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 683 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 684 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 685 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 686 687 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER 688 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER 689 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD 690 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD 691 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER 692 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER 693 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE 694 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE 695 696 #if defined(STM32G4) 697 #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig 698 #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable 699 #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable 700 #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset 701 #define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A 702 #define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B 703 #define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL 704 #define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL 705 #endif /* STM32G4 */ 706 707 #if defined(STM32H7) 708 #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 709 #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 710 #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 711 #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 712 #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 713 #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 714 #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 715 #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 716 #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 717 #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 718 #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 719 #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 720 #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 721 #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 722 #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 723 #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 724 #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 725 #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 726 #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 727 #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 728 #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 729 #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 730 #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 731 #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 732 #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 733 #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 734 #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 735 #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 736 #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 737 #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 738 #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 739 #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 740 #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 741 #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 742 #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 743 #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 744 #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 745 #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 746 #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 747 #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 748 #define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 749 #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 750 #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 751 #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 752 #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 753 #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 754 #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 755 #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 756 #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 757 #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 758 #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 759 #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 760 #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 761 #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 762 763 #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 764 #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 765 #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 766 #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 767 #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 768 #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 769 #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 770 #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 771 #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 772 #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 773 #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 774 #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 775 #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 776 #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 777 #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 778 #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 779 #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 780 #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 781 #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 782 #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 783 #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 784 #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 785 #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 786 #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 787 #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 788 #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 789 #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 790 #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 791 #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 792 #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 793 #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 794 #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 795 #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 796 #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 797 #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 798 #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 799 #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 800 #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 801 #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 802 #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 803 #define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 804 #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 805 #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 806 #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 807 #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 808 #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 809 #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 810 #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 811 #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 812 #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 813 #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 814 #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 815 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 816 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 817 #endif /* STM32H7 */ 818 819 #if defined(STM32F3) 820 /** @brief Constants defining available sources associated to external events. 821 */ 822 #define HRTIM_EVENTSRC_1 (0x00000000U) 823 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) 824 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) 825 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) 826 827 /** @brief Constants defining the DLL calibration periods (in micro seconds) 828 */ 829 #define HRTIM_CALIBRATIONRATE_7300 0x00000000U 830 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) 831 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) 832 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) 833 834 #endif /* STM32F3 */ 835 /** 836 * @} 837 */ 838 839 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose 840 * @{ 841 */ 842 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE 843 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE 844 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE 845 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE 846 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE 847 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE 848 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE 849 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE 850 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) 851 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX 852 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX 853 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX 854 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX 855 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX 856 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX 857 #endif 858 /** 859 * @} 860 */ 861 862 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose 863 * @{ 864 */ 865 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE 866 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE 867 868 /** 869 * @} 870 */ 871 872 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose 873 * @{ 874 */ 875 #define KR_KEY_RELOAD IWDG_KEY_RELOAD 876 #define KR_KEY_ENABLE IWDG_KEY_ENABLE 877 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE 878 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE 879 /** 880 * @} 881 */ 882 883 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 884 * @{ 885 */ 886 887 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 888 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS 889 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS 890 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS 891 892 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING 893 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING 894 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING 895 896 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 897 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS 898 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS 899 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS 900 901 /* The following 3 definition have also been present in a temporary version of lptim.h */ 902 /* They need to be renamed also to the right name, just in case */ 903 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS 904 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS 905 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS 906 907 908 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 909 * @{ 910 */ 911 #define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue 912 /** 913 * @} 914 */ 915 916 /** @defgroup HAL_LPTIM_Aliased_Defines LL LPTIM Aliased Defines maintained for legacy purpose 917 * @{ 918 */ 919 #define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1 920 #define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2 921 #define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1 922 #define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2 923 /** 924 * @} 925 */ 926 927 #if defined(STM32U5) 928 #define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF 929 #define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF 930 #define LPTIM_CHANNEL_ALL 0x00000000U 931 #endif /* STM32U5 */ 932 /** 933 * @} 934 */ 935 936 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose 937 * @{ 938 */ 939 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b 940 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b 941 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b 942 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b 943 944 #define NAND_AddressTypedef NAND_AddressTypeDef 945 946 #define __ARRAY_ADDRESS ARRAY_ADDRESS 947 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE 948 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE 949 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE 950 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE 951 /** 952 * @} 953 */ 954 955 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose 956 * @{ 957 */ 958 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef 959 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS 960 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING 961 #define NOR_ERROR HAL_NOR_STATUS_ERROR 962 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT 963 964 #define __NOR_WRITE NOR_WRITE 965 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT 966 /** 967 * @} 968 */ 969 970 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose 971 * @{ 972 */ 973 974 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 975 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 976 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 977 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 978 979 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 980 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 981 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 982 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 983 984 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 985 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 986 987 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 988 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 989 990 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 991 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 992 993 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 994 995 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO 996 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 997 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 998 999 #if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) 1000 #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID 1001 #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID 1002 #endif 1003 1004 #if defined(STM32L4) || defined(STM32L5) 1005 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER 1006 #elif defined(STM32G4) 1007 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED 1008 #endif 1009 1010 /** 1011 * @} 1012 */ 1013 1014 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose 1015 * @{ 1016 */ 1017 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS 1018 1019 #if defined(STM32H7) 1020 #define I2S_IT_TXE I2S_IT_TXP 1021 #define I2S_IT_RXNE I2S_IT_RXP 1022 1023 #define I2S_FLAG_TXE I2S_FLAG_TXP 1024 #define I2S_FLAG_RXNE I2S_FLAG_RXP 1025 #endif 1026 1027 #if defined(STM32F7) 1028 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL 1029 #endif 1030 /** 1031 * @} 1032 */ 1033 1034 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose 1035 * @{ 1036 */ 1037 1038 /* Compact Flash-ATA registers description */ 1039 #define CF_DATA ATA_DATA 1040 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT 1041 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER 1042 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW 1043 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH 1044 #define CF_CARD_HEAD ATA_CARD_HEAD 1045 #define CF_STATUS_CMD ATA_STATUS_CMD 1046 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE 1047 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA 1048 1049 /* Compact Flash-ATA commands */ 1050 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD 1051 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD 1052 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD 1053 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD 1054 1055 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef 1056 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS 1057 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING 1058 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR 1059 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT 1060 /** 1061 * @} 1062 */ 1063 1064 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose 1065 * @{ 1066 */ 1067 1068 #define FORMAT_BIN RTC_FORMAT_BIN 1069 #define FORMAT_BCD RTC_FORMAT_BCD 1070 1071 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE 1072 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE 1073 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1074 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1075 1076 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1077 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1078 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE 1079 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1080 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1081 1082 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT 1083 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 1084 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 1085 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 1086 1087 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE 1088 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 1089 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 1090 1091 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 1092 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 1093 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 1094 1095 #if defined(STM32H7) 1096 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X 1097 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT 1098 1099 #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 1100 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 1101 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 1102 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL 1103 #endif /* STM32H7 */ 1104 1105 /** 1106 * @} 1107 */ 1108 1109 1110 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose 1111 * @{ 1112 */ 1113 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE 1114 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE 1115 1116 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1117 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1118 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1119 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1120 1121 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE 1122 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE 1123 1124 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE 1125 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE 1126 /** 1127 * @} 1128 */ 1129 1130 1131 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose 1132 * @{ 1133 */ 1134 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE 1135 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE 1136 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE 1137 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE 1138 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE 1139 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE 1140 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE 1141 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE 1142 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE 1143 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE 1144 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN 1145 /** 1146 * @} 1147 */ 1148 1149 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose 1150 * @{ 1151 */ 1152 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE 1153 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE 1154 1155 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE 1156 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE 1157 1158 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE 1159 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE 1160 1161 #if defined(STM32H7) 1162 1163 #define SPI_FLAG_TXE SPI_FLAG_TXP 1164 #define SPI_FLAG_RXNE SPI_FLAG_RXP 1165 1166 #define SPI_IT_TXE SPI_IT_TXP 1167 #define SPI_IT_RXNE SPI_IT_RXP 1168 1169 #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET 1170 #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET 1171 #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET 1172 #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET 1173 1174 #endif /* STM32H7 */ 1175 1176 /** 1177 * @} 1178 */ 1179 1180 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose 1181 * @{ 1182 */ 1183 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK 1184 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK 1185 1186 #define TIM_DMABase_CR1 TIM_DMABASE_CR1 1187 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 1188 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR 1189 #define TIM_DMABase_DIER TIM_DMABASE_DIER 1190 #define TIM_DMABase_SR TIM_DMABASE_SR 1191 #define TIM_DMABase_EGR TIM_DMABASE_EGR 1192 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 1193 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 1194 #define TIM_DMABase_CCER TIM_DMABASE_CCER 1195 #define TIM_DMABase_CNT TIM_DMABASE_CNT 1196 #define TIM_DMABase_PSC TIM_DMABASE_PSC 1197 #define TIM_DMABase_ARR TIM_DMABASE_ARR 1198 #define TIM_DMABase_RCR TIM_DMABASE_RCR 1199 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 1200 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 1201 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 1202 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 1203 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR 1204 #define TIM_DMABase_DCR TIM_DMABASE_DCR 1205 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR 1206 #define TIM_DMABase_OR1 TIM_DMABASE_OR1 1207 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 1208 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 1209 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 1210 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 1211 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 1212 #define TIM_DMABase_OR TIM_DMABASE_OR 1213 1214 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE 1215 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 1216 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 1217 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 1218 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 1219 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM 1220 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER 1221 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK 1222 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 1223 1224 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER 1225 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS 1226 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS 1227 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS 1228 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS 1229 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS 1230 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS 1231 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS 1232 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS 1233 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS 1234 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS 1235 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS 1236 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS 1237 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS 1238 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS 1239 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS 1240 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS 1241 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS 1242 1243 #if defined(STM32L0) 1244 #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO 1245 #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO 1246 #endif 1247 1248 #if defined(STM32F3) 1249 #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE 1250 #endif 1251 1252 #if defined(STM32H7) 1253 #define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 1254 #define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 1255 #define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 1256 #define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 1257 #define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 1258 #define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 1259 #define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 1260 #define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 1261 #define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 1262 #define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 1263 #define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 1264 #define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 1265 #define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 1266 #define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 1267 #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 1268 #endif 1269 1270 /** 1271 * @} 1272 */ 1273 1274 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose 1275 * @{ 1276 */ 1277 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING 1278 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING 1279 /** 1280 * @} 1281 */ 1282 1283 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose 1284 * @{ 1285 */ 1286 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1287 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1288 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1289 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1290 1291 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE 1292 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE 1293 1294 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 1295 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 1296 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 1297 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 1298 1299 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 1300 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 1301 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 1302 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 1303 1304 #define __DIV_LPUART UART_DIV_LPUART 1305 1306 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE 1307 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK 1308 1309 /** 1310 * @} 1311 */ 1312 1313 1314 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose 1315 * @{ 1316 */ 1317 1318 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE 1319 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE 1320 1321 #define USARTNACK_ENABLED USART_NACK_ENABLE 1322 #define USARTNACK_DISABLED USART_NACK_DISABLE 1323 /** 1324 * @} 1325 */ 1326 1327 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose 1328 * @{ 1329 */ 1330 #define CFR_BASE WWDG_CFR_BASE 1331 1332 /** 1333 * @} 1334 */ 1335 1336 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose 1337 * @{ 1338 */ 1339 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 1340 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 1341 #define CAN_IT_RQCP0 CAN_IT_TME 1342 #define CAN_IT_RQCP1 CAN_IT_TME 1343 #define CAN_IT_RQCP2 CAN_IT_TME 1344 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE 1345 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE 1346 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) 1347 #define CAN_TXSTATUS_OK ((uint8_t)0x01U) 1348 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) 1349 1350 /** 1351 * @} 1352 */ 1353 1354 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose 1355 * @{ 1356 */ 1357 1358 #define VLAN_TAG ETH_VLAN_TAG 1359 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD 1360 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD 1361 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD 1362 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK 1363 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK 1364 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK 1365 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK 1366 1367 #define ETH_MMCCR 0x00000100U 1368 #define ETH_MMCRIR 0x00000104U 1369 #define ETH_MMCTIR 0x00000108U 1370 #define ETH_MMCRIMR 0x0000010CU 1371 #define ETH_MMCTIMR 0x00000110U 1372 #define ETH_MMCTGFSCCR 0x0000014CU 1373 #define ETH_MMCTGFMSCCR 0x00000150U 1374 #define ETH_MMCTGFCR 0x00000168U 1375 #define ETH_MMCRFCECR 0x00000194U 1376 #define ETH_MMCRFAECR 0x00000198U 1377 #define ETH_MMCRGUFCR 0x000001C4U 1378 1379 #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ 1380 #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ 1381 #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ 1382 #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ 1383 #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ 1384 #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ 1385 #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ 1386 #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ 1387 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ 1388 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ 1389 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ 1390 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ 1391 #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ 1392 #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ 1393 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ 1394 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ 1395 #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ 1396 #if defined(STM32F1) 1397 #else 1398 #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ 1399 #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ 1400 #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ 1401 #endif 1402 #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ 1403 #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ 1404 #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ 1405 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ 1406 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ 1407 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ 1408 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ 1409 1410 /** 1411 * @} 1412 */ 1413 1414 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose 1415 * @{ 1416 */ 1417 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR 1418 #define DCMI_IT_OVF DCMI_IT_OVR 1419 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI 1420 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI 1421 1422 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop 1423 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop 1424 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop 1425 1426 /** 1427 * @} 1428 */ 1429 1430 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1431 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1432 || defined(STM32H7) 1433 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose 1434 * @{ 1435 */ 1436 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 1437 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 1438 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 1439 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 1440 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 1441 1442 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 1443 #define CM_RGB888 DMA2D_INPUT_RGB888 1444 #define CM_RGB565 DMA2D_INPUT_RGB565 1445 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 1446 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 1447 #define CM_L8 DMA2D_INPUT_L8 1448 #define CM_AL44 DMA2D_INPUT_AL44 1449 #define CM_AL88 DMA2D_INPUT_AL88 1450 #define CM_L4 DMA2D_INPUT_L4 1451 #define CM_A8 DMA2D_INPUT_A8 1452 #define CM_A4 DMA2D_INPUT_A4 1453 /** 1454 * @} 1455 */ 1456 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ 1457 1458 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1459 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1460 || defined(STM32H7) || defined(STM32U5) 1461 /** @defgroup DMA2D_Aliases DMA2D API Aliases 1462 * @{ 1463 */ 1464 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort 1465 for compatibility with legacy code */ 1466 /** 1467 * @} 1468 */ 1469 1470 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ 1471 1472 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose 1473 * @{ 1474 */ 1475 1476 /** 1477 * @} 1478 */ 1479 1480 /* Exported functions --------------------------------------------------------*/ 1481 1482 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose 1483 * @{ 1484 */ 1485 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback 1486 /** 1487 * @} 1488 */ 1489 1490 /** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose 1491 * @{ 1492 */ 1493 1494 #if defined(STM32U5) 1495 #define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr 1496 #define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT 1497 #endif /* STM32U5 */ 1498 1499 /** 1500 * @} 1501 */ 1502 1503 #if !defined(STM32F2) 1504 /** @defgroup HASH_alias HASH API alias 1505 * @{ 1506 */ 1507 #define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ 1508 /** 1509 * 1510 * @} 1511 */ 1512 #endif /* STM32F2 */ 1513 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose 1514 * @{ 1515 */ 1516 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef 1517 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef 1518 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish 1519 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish 1520 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish 1521 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish 1522 1523 /*HASH Algorithm Selection*/ 1524 1525 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 1526 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 1527 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 1528 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 1529 1530 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH 1531 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC 1532 1533 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY 1534 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY 1535 1536 #if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) 1537 1538 #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt 1539 #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End 1540 #define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT 1541 #define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT 1542 1543 #define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt 1544 #define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End 1545 #define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT 1546 #define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT 1547 1548 #define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt 1549 #define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End 1550 #define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT 1551 #define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT 1552 1553 #define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt 1554 #define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End 1555 #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT 1556 #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT 1557 1558 #endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ 1559 /** 1560 * @} 1561 */ 1562 1563 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose 1564 * @{ 1565 */ 1566 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode 1567 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode 1568 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode 1569 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode 1570 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode 1571 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode 1572 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ 1573 )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) 1574 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect 1575 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) 1576 #if defined(STM32L0) 1577 #else 1578 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) 1579 #endif 1580 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) 1581 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ 1582 )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) 1583 #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) 1584 #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode 1585 #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode 1586 #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode 1587 #define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode 1588 #endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ 1589 1590 /** 1591 * @} 1592 */ 1593 1594 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose 1595 * @{ 1596 */ 1597 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram 1598 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown 1599 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown 1600 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock 1601 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock 1602 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase 1603 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program 1604 1605 /** 1606 * @} 1607 */ 1608 1609 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose 1610 * @{ 1611 */ 1612 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter 1613 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter 1614 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter 1615 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter 1616 1617 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ 1618 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) 1619 1620 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) 1621 #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT 1622 #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT 1623 #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT 1624 #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT 1625 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1626 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) 1627 #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA 1628 #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA 1629 #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA 1630 #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA 1631 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1632 1633 #if defined(STM32F4) 1634 #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT 1635 #define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT 1636 #define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT 1637 #define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT 1638 #define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA 1639 #define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA 1640 #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA 1641 #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA 1642 #endif /* STM32F4 */ 1643 /** 1644 * @} 1645 */ 1646 1647 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose 1648 * @{ 1649 */ 1650 1651 #if defined(STM32G0) 1652 #define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD 1653 #define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD 1654 #define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD 1655 #define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler 1656 #endif 1657 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD 1658 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg 1659 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown 1660 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor 1661 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg 1662 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown 1663 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor 1664 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler 1665 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD 1666 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler 1667 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback 1668 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive 1669 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive 1670 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC 1671 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC 1672 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM 1673 1674 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL 1675 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING 1676 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING 1677 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING 1678 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING 1679 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING 1680 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING 1681 1682 #define CR_OFFSET_BB PWR_CR_OFFSET_BB 1683 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB 1684 #define PMODE_BIT_NUMBER VOS_BIT_NUMBER 1685 #define CR_PMODE_BB CR_VOS_BB 1686 1687 #define DBP_BitNumber DBP_BIT_NUMBER 1688 #define PVDE_BitNumber PVDE_BIT_NUMBER 1689 #define PMODE_BitNumber PMODE_BIT_NUMBER 1690 #define EWUP_BitNumber EWUP_BIT_NUMBER 1691 #define FPDS_BitNumber FPDS_BIT_NUMBER 1692 #define ODEN_BitNumber ODEN_BIT_NUMBER 1693 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER 1694 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER 1695 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER 1696 #define BRE_BitNumber BRE_BIT_NUMBER 1697 1698 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL 1699 1700 /** 1701 * @} 1702 */ 1703 1704 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose 1705 * @{ 1706 */ 1707 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT 1708 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback 1709 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback 1710 /** 1711 * @} 1712 */ 1713 1714 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose 1715 * @{ 1716 */ 1717 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo 1718 /** 1719 * @} 1720 */ 1721 1722 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose 1723 * @{ 1724 */ 1725 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt 1726 #define HAL_TIM_DMAError TIM_DMAError 1727 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt 1728 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt 1729 #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) 1730 #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro 1731 #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT 1732 #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback 1733 #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent 1734 #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT 1735 #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA 1736 #endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ 1737 /** 1738 * @} 1739 */ 1740 1741 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose 1742 * @{ 1743 */ 1744 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback 1745 /** 1746 * @} 1747 */ 1748 1749 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose 1750 * @{ 1751 */ 1752 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback 1753 #define HAL_LTDC_Relaod HAL_LTDC_Reload 1754 #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig 1755 #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig 1756 /** 1757 * @} 1758 */ 1759 1760 1761 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose 1762 * @{ 1763 */ 1764 1765 /** 1766 * @} 1767 */ 1768 1769 /* Exported macros ------------------------------------------------------------*/ 1770 1771 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose 1772 * @{ 1773 */ 1774 #define AES_IT_CC CRYP_IT_CC 1775 #define AES_IT_ERR CRYP_IT_ERR 1776 #define AES_FLAG_CCF CRYP_FLAG_CCF 1777 /** 1778 * @} 1779 */ 1780 1781 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 1782 * @{ 1783 */ 1784 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE 1785 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH 1786 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH 1787 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM 1788 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC 1789 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 1790 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC 1791 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI 1792 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK 1793 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG 1794 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG 1795 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE 1796 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE 1797 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE 1798 1799 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY 1800 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 1801 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS 1802 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER 1803 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER 1804 1805 /** 1806 * @} 1807 */ 1808 1809 1810 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose 1811 * @{ 1812 */ 1813 #define __ADC_ENABLE __HAL_ADC_ENABLE 1814 #define __ADC_DISABLE __HAL_ADC_DISABLE 1815 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS 1816 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS 1817 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE 1818 #define __ADC_IS_ENABLED ADC_IS_ENABLE 1819 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR 1820 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED 1821 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED 1822 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR 1823 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED 1824 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING 1825 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE 1826 1827 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION 1828 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK 1829 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT 1830 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR 1831 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION 1832 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE 1833 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS 1834 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS 1835 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM 1836 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT 1837 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS 1838 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN 1839 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ 1840 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET 1841 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET 1842 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL 1843 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL 1844 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET 1845 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET 1846 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD 1847 1848 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION 1849 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION 1850 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION 1851 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER 1852 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI 1853 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 1854 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 1855 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER 1856 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER 1857 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE 1858 1859 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT 1860 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT 1861 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL 1862 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM 1863 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET 1864 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE 1865 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE 1866 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER 1867 1868 #define __HAL_ADC_SQR1 ADC_SQR1 1869 #define __HAL_ADC_SMPR1 ADC_SMPR1 1870 #define __HAL_ADC_SMPR2 ADC_SMPR2 1871 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK 1872 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK 1873 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK 1874 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS 1875 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS 1876 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV 1877 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection 1878 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq 1879 #define __HAL_ADC_JSQR ADC_JSQR 1880 1881 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL 1882 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS 1883 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF 1884 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT 1885 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS 1886 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN 1887 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR 1888 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ 1889 1890 /** 1891 * @} 1892 */ 1893 1894 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 1895 * @{ 1896 */ 1897 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT 1898 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT 1899 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT 1900 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE 1901 1902 /** 1903 * @} 1904 */ 1905 1906 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose 1907 * @{ 1908 */ 1909 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 1910 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 1911 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 1912 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 1913 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 1914 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 1915 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 1916 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 1917 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 1918 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 1919 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 1920 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 1921 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 1922 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 1923 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 1924 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 1925 1926 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 1927 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 1928 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 1929 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 1930 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 1931 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 1932 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 1933 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 1934 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 1935 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 1936 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 1937 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 1938 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 1939 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 1940 1941 1942 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 1943 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 1944 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 1945 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 1946 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 1947 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 1948 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC 1949 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC 1950 #if defined(STM32H7) 1951 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 1952 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 1953 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 1954 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 1955 #else 1956 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG 1957 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG 1958 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG 1959 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG 1960 #endif /* STM32H7 */ 1961 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT 1962 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT 1963 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT 1964 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT 1965 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT 1966 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT 1967 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 1968 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 1969 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 1970 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 1971 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 1972 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 1973 1974 /** 1975 * @} 1976 */ 1977 1978 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose 1979 * @{ 1980 */ 1981 #if defined(STM32F3) 1982 #define COMP_START __HAL_COMP_ENABLE 1983 #define COMP_STOP __HAL_COMP_DISABLE 1984 #define COMP_LOCK __HAL_COMP_LOCK 1985 1986 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 1987 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 1988 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 1989 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 1990 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 1991 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 1992 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 1993 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 1994 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 1995 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 1996 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 1997 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 1998 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 1999 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2000 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2001 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 2002 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2003 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2004 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 2005 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2006 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2007 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 2008 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2009 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2010 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 2011 # endif 2012 # if defined(STM32F302xE) || defined(STM32F302xC) 2013 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2014 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2015 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2016 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 2017 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2018 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2019 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2020 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 2021 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2022 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2023 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2024 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 2025 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2026 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2027 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2028 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 2029 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2030 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2031 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2032 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 2033 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2034 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2035 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2036 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 2037 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2038 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2039 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2040 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 2041 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2042 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2043 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2044 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 2045 # endif 2046 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) 2047 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2048 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2049 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ 2050 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2051 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ 2052 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ 2053 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) 2054 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2055 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2056 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ 2057 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2058 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ 2059 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ 2060 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) 2061 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2062 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2063 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ 2064 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2065 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ 2066 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ 2067 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) 2068 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2069 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2070 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ 2071 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2072 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ 2073 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ 2074 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) 2075 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2076 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2077 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ 2078 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2079 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ 2080 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ 2081 __HAL_COMP_COMP7_EXTI_ENABLE_IT()) 2082 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2083 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2084 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ 2085 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2086 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ 2087 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ 2088 __HAL_COMP_COMP7_EXTI_DISABLE_IT()) 2089 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2090 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2091 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ 2092 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2093 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ 2094 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ 2095 __HAL_COMP_COMP7_EXTI_GET_FLAG()) 2096 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2097 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2098 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ 2099 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2100 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ 2101 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ 2102 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) 2103 # endif 2104 # if defined(STM32F373xC) ||defined(STM32F378xx) 2105 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2106 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2107 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2108 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2109 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2110 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2111 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2112 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2113 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2114 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2115 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2116 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2117 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2118 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2119 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2120 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2121 # endif 2122 #else 2123 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2124 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2125 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2126 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2127 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2128 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2129 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2130 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2131 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2132 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2133 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2134 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2135 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2136 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2137 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2138 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2139 #endif 2140 2141 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE 2142 2143 #if defined(STM32L0) || defined(STM32L4) 2144 /* Note: On these STM32 families, the only argument of this macro */ 2145 /* is COMP_FLAG_LOCK. */ 2146 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ 2147 /* argument. */ 2148 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) 2149 #endif 2150 /** 2151 * @} 2152 */ 2153 2154 #if defined(STM32L0) || defined(STM32L4) 2155 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose 2156 * @{ 2157 */ 2158 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ 2159 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ 2160 /** 2161 * @} 2162 */ 2163 #endif 2164 2165 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 2166 * @{ 2167 */ 2168 2169 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ 2170 ((WAVE) == DAC_WAVE_NOISE)|| \ 2171 ((WAVE) == DAC_WAVE_TRIANGLE)) 2172 2173 /** 2174 * @} 2175 */ 2176 2177 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose 2178 * @{ 2179 */ 2180 2181 #define IS_WRPAREA IS_OB_WRPAREA 2182 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM 2183 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM 2184 #define IS_TYPEERASE IS_FLASH_TYPEERASE 2185 #define IS_NBSECTORS IS_FLASH_NBSECTORS 2186 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE 2187 2188 /** 2189 * @} 2190 */ 2191 2192 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose 2193 * @{ 2194 */ 2195 2196 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 2197 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START 2198 #if defined(STM32F1) 2199 #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE 2200 #else 2201 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE 2202 #endif /* STM32F1 */ 2203 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME 2204 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD 2205 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST 2206 #define __HAL_I2C_SPEED I2C_SPEED 2207 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE 2208 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ 2209 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS 2210 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE 2211 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ 2212 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB 2213 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB 2214 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE 2215 /** 2216 * @} 2217 */ 2218 2219 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose 2220 * @{ 2221 */ 2222 2223 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE 2224 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT 2225 2226 #if defined(STM32H7) 2227 #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG 2228 #endif 2229 2230 /** 2231 * @} 2232 */ 2233 2234 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose 2235 * @{ 2236 */ 2237 2238 #define __IRDA_DISABLE __HAL_IRDA_DISABLE 2239 #define __IRDA_ENABLE __HAL_IRDA_ENABLE 2240 2241 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2242 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2243 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2244 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2245 2246 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE 2247 2248 2249 /** 2250 * @} 2251 */ 2252 2253 2254 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose 2255 * @{ 2256 */ 2257 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS 2258 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS 2259 /** 2260 * @} 2261 */ 2262 2263 2264 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose 2265 * @{ 2266 */ 2267 2268 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT 2269 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT 2270 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE 2271 2272 /** 2273 * @} 2274 */ 2275 2276 2277 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose 2278 * @{ 2279 */ 2280 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD 2281 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX 2282 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX 2283 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX 2284 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX 2285 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L 2286 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H 2287 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM 2288 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES 2289 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX 2290 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT 2291 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION 2292 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET 2293 2294 /** 2295 * @} 2296 */ 2297 2298 2299 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose 2300 * @{ 2301 */ 2302 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2303 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2304 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2305 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2306 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2307 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2308 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE 2309 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE 2310 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE 2311 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE 2312 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE 2313 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE 2314 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine 2315 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine 2316 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig 2317 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig 2318 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) 2319 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2320 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2321 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2322 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2323 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2324 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2325 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2326 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2327 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) 2328 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) 2329 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention 2330 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention 2331 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 2332 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 2333 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE 2334 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE 2335 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB 2336 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB 2337 2338 #if defined (STM32F4) 2339 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() 2340 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() 2341 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() 2342 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() 2343 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() 2344 #else 2345 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG 2346 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT 2347 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT 2348 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT 2349 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG 2350 #endif /* STM32F4 */ 2351 /** 2352 * @} 2353 */ 2354 2355 2356 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose 2357 * @{ 2358 */ 2359 2360 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI 2361 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI 2362 2363 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback 2364 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ 2365 )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) 2366 2367 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE 2368 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE 2369 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE 2370 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE 2371 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET 2372 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET 2373 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE 2374 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE 2375 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET 2376 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET 2377 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE 2378 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE 2379 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE 2380 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE 2381 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET 2382 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET 2383 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE 2384 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE 2385 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET 2386 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET 2387 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 2388 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 2389 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 2390 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 2391 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 2392 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 2393 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE 2394 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE 2395 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE 2396 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE 2397 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET 2398 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET 2399 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 2400 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 2401 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 2402 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 2403 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET 2404 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET 2405 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET 2406 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET 2407 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET 2408 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET 2409 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET 2410 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET 2411 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET 2412 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET 2413 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET 2414 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET 2415 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE 2416 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE 2417 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET 2418 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET 2419 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2420 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2421 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE 2422 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE 2423 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2424 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2425 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2426 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2427 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2428 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2429 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE 2430 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE 2431 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET 2432 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET 2433 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE 2434 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE 2435 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE 2436 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE 2437 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET 2438 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET 2439 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE 2440 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE 2441 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET 2442 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET 2443 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE 2444 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE 2445 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE 2446 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE 2447 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET 2448 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET 2449 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE 2450 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE 2451 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET 2452 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET 2453 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE 2454 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE 2455 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE 2456 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE 2457 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET 2458 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET 2459 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE 2460 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE 2461 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET 2462 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET 2463 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE 2464 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE 2465 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE 2466 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE 2467 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET 2468 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET 2469 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE 2470 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE 2471 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE 2472 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE 2473 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET 2474 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET 2475 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE 2476 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE 2477 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE 2478 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE 2479 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET 2480 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET 2481 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE 2482 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE 2483 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET 2484 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET 2485 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE 2486 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE 2487 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE 2488 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE 2489 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE 2490 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE 2491 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE 2492 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE 2493 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE 2494 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE 2495 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET 2496 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET 2497 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE 2498 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE 2499 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET 2500 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET 2501 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE 2502 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE 2503 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE 2504 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE 2505 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE 2506 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE 2507 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET 2508 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET 2509 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE 2510 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE 2511 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE 2512 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE 2513 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE 2514 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE 2515 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET 2516 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET 2517 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE 2518 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE 2519 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE 2520 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE 2521 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET 2522 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET 2523 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE 2524 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE 2525 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE 2526 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE 2527 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET 2528 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET 2529 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE 2530 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE 2531 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE 2532 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE 2533 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET 2534 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET 2535 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE 2536 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE 2537 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE 2538 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE 2539 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET 2540 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET 2541 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE 2542 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE 2543 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE 2544 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE 2545 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET 2546 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET 2547 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE 2548 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE 2549 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE 2550 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE 2551 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET 2552 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET 2553 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE 2554 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE 2555 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE 2556 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE 2557 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET 2558 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET 2559 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE 2560 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE 2561 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE 2562 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE 2563 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET 2564 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET 2565 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE 2566 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE 2567 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE 2568 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE 2569 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET 2570 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET 2571 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE 2572 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE 2573 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE 2574 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE 2575 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET 2576 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET 2577 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE 2578 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE 2579 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE 2580 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE 2581 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET 2582 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET 2583 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE 2584 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE 2585 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE 2586 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE 2587 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET 2588 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET 2589 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE 2590 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE 2591 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE 2592 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE 2593 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET 2594 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET 2595 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE 2596 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE 2597 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE 2598 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE 2599 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET 2600 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET 2601 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE 2602 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE 2603 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE 2604 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE 2605 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET 2606 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET 2607 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE 2608 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE 2609 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE 2610 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE 2611 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET 2612 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET 2613 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE 2614 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE 2615 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE 2616 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE 2617 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET 2618 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET 2619 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE 2620 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE 2621 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE 2622 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE 2623 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET 2624 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET 2625 2626 #if defined(STM32WB) 2627 #define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE 2628 #define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE 2629 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE 2630 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE 2631 #define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET 2632 #define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET 2633 #define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED 2634 #define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED 2635 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED 2636 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED 2637 #define QSPI_IRQHandler QUADSPI_IRQHandler 2638 #endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ 2639 2640 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE 2641 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE 2642 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE 2643 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE 2644 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET 2645 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET 2646 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE 2647 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE 2648 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE 2649 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE 2650 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET 2651 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET 2652 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE 2653 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE 2654 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE 2655 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE 2656 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET 2657 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET 2658 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 2659 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 2660 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE 2661 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE 2662 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE 2663 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE 2664 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET 2665 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET 2666 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE 2667 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE 2668 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE 2669 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE 2670 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET 2671 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET 2672 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE 2673 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE 2674 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE 2675 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE 2676 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET 2677 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET 2678 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE 2679 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE 2680 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE 2681 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE 2682 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET 2683 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET 2684 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE 2685 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE 2686 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE 2687 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE 2688 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE 2689 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE 2690 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE 2691 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE 2692 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE 2693 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE 2694 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET 2695 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET 2696 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE 2697 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE 2698 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE 2699 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE 2700 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET 2701 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET 2702 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE 2703 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE 2704 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE 2705 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE 2706 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET 2707 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET 2708 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE 2709 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE 2710 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET 2711 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET 2712 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE 2713 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE 2714 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET 2715 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET 2716 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE 2717 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE 2718 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET 2719 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET 2720 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE 2721 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE 2722 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET 2723 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET 2724 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE 2725 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE 2726 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET 2727 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET 2728 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE 2729 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE 2730 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE 2731 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE 2732 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET 2733 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET 2734 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE 2735 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE 2736 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE 2737 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE 2738 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET 2739 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET 2740 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE 2741 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE 2742 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE 2743 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE 2744 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET 2745 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET 2746 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE 2747 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE 2748 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE 2749 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE 2750 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET 2751 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET 2752 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE 2753 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE 2754 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE 2755 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE 2756 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET 2757 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET 2758 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE 2759 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE 2760 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE 2761 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE 2762 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET 2763 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET 2764 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE 2765 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE 2766 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE 2767 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE 2768 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET 2769 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET 2770 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE 2771 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE 2772 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE 2773 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE 2774 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET 2775 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET 2776 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE 2777 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE 2778 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE 2779 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE 2780 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET 2781 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET 2782 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE 2783 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE 2784 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE 2785 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE 2786 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET 2787 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET 2788 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE 2789 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE 2790 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET 2791 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET 2792 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE 2793 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE 2794 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE 2795 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE 2796 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET 2797 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET 2798 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 2799 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 2800 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 2801 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 2802 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 2803 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 2804 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 2805 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 2806 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 2807 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 2808 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 2809 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 2810 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE 2811 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE 2812 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE 2813 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE 2814 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET 2815 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET 2816 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE 2817 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE 2818 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE 2819 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE 2820 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET 2821 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET 2822 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE 2823 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE 2824 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE 2825 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE 2826 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET 2827 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET 2828 #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 2829 #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 2830 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 2831 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 2832 #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 2833 #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 2834 #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 2835 #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 2836 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 2837 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 2838 #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 2839 #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 2840 #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 2841 #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 2842 #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 2843 #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 2844 #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 2845 #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 2846 #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 2847 #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 2848 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE 2849 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE 2850 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET 2851 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE 2852 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE 2853 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE 2854 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE 2855 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET 2856 2857 #if defined(STM32H7) 2858 #define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE 2859 #define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE 2860 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE 2861 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE 2862 2863 #define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ 2864 #define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ 2865 2866 2867 #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED 2868 #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED 2869 #endif 2870 2871 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE 2872 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE 2873 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE 2874 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE 2875 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET 2876 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET 2877 2878 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE 2879 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE 2880 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET 2881 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET 2882 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE 2883 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE 2884 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE 2885 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE 2886 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET 2887 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET 2888 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE 2889 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE 2890 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE 2891 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE 2892 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE 2893 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE 2894 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET 2895 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET 2896 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE 2897 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE 2898 2899 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 2900 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 2901 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE 2902 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE 2903 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE 2904 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE 2905 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE 2906 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE 2907 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE 2908 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE 2909 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE 2910 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE 2911 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE 2912 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE 2913 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE 2914 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE 2915 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE 2916 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE 2917 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE 2918 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET 2919 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET 2920 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE 2921 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE 2922 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE 2923 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE 2924 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE 2925 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET 2926 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET 2927 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE 2928 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE 2929 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE 2930 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE 2931 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET 2932 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET 2933 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE 2934 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE 2935 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE 2936 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE 2937 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET 2938 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET 2939 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE 2940 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE 2941 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE 2942 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE 2943 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE 2944 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE 2945 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE 2946 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE 2947 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE 2948 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE 2949 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE 2950 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE 2951 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE 2952 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE 2953 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE 2954 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE 2955 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE 2956 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE 2957 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE 2958 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE 2959 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE 2960 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET 2961 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET 2962 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE 2963 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE 2964 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE 2965 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE 2966 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET 2967 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET 2968 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE 2969 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE 2970 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE 2971 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE 2972 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET 2973 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET 2974 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE 2975 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE 2976 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE 2977 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE 2978 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET 2979 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET 2980 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE 2981 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE 2982 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE 2983 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE 2984 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET 2985 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE 2986 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE 2987 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE 2988 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE 2989 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE 2990 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE 2991 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET 2992 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET 2993 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE 2994 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE 2995 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 2996 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 2997 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 2998 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 2999 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE 3000 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE 3001 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 3002 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 3003 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 3004 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 3005 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE 3006 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE 3007 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 3008 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 3009 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 3010 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 3011 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 3012 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 3013 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 3014 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 3015 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED 3016 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED 3017 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 3018 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 3019 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 3020 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 3021 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED 3022 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED 3023 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE 3024 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE 3025 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE 3026 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE 3027 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE 3028 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE 3029 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE 3030 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE 3031 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE 3032 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET 3033 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET 3034 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE 3035 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE 3036 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3037 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3038 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3039 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3040 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE 3041 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE 3042 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET 3043 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET 3044 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE 3045 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE 3046 3047 /* alias define maintained for legacy */ 3048 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 3049 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 3050 3051 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 3052 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 3053 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE 3054 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE 3055 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE 3056 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE 3057 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE 3058 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE 3059 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE 3060 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE 3061 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE 3062 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE 3063 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE 3064 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE 3065 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE 3066 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE 3067 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE 3068 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE 3069 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE 3070 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE 3071 3072 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 3073 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 3074 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET 3075 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET 3076 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET 3077 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET 3078 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET 3079 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET 3080 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET 3081 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET 3082 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET 3083 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET 3084 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET 3085 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET 3086 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET 3087 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET 3088 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET 3089 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET 3090 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET 3091 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET 3092 3093 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED 3094 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED 3095 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3096 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3097 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED 3098 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED 3099 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED 3100 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED 3101 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED 3102 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED 3103 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED 3104 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED 3105 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED 3106 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED 3107 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED 3108 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED 3109 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED 3110 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED 3111 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED 3112 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED 3113 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED 3114 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED 3115 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED 3116 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED 3117 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED 3118 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED 3119 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED 3120 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED 3121 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED 3122 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED 3123 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED 3124 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED 3125 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED 3126 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED 3127 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED 3128 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED 3129 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED 3130 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED 3131 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED 3132 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED 3133 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED 3134 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED 3135 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED 3136 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED 3137 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED 3138 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED 3139 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED 3140 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED 3141 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED 3142 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED 3143 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED 3144 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED 3145 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED 3146 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED 3147 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED 3148 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED 3149 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED 3150 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED 3151 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED 3152 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED 3153 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED 3154 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED 3155 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED 3156 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED 3157 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED 3158 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED 3159 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED 3160 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED 3161 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED 3162 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED 3163 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED 3164 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED 3165 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED 3166 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED 3167 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED 3168 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED 3169 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED 3170 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED 3171 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED 3172 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED 3173 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED 3174 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED 3175 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED 3176 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED 3177 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED 3178 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED 3179 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED 3180 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED 3181 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED 3182 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED 3183 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED 3184 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED 3185 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED 3186 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED 3187 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED 3188 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED 3189 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED 3190 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED 3191 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED 3192 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED 3193 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED 3194 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED 3195 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED 3196 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED 3197 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED 3198 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED 3199 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED 3200 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED 3201 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED 3202 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED 3203 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED 3204 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED 3205 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED 3206 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED 3207 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED 3208 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED 3209 3210 #if defined(STM32L1) 3211 #define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 3212 #define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 3213 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 3214 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 3215 #define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 3216 #define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 3217 #endif /* STM32L1 */ 3218 3219 #if defined(STM32F4) 3220 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3221 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3222 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3223 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3224 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 3225 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 3226 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED 3227 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED 3228 #define Sdmmc1ClockSelection SdioClockSelection 3229 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO 3230 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 3231 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK 3232 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG 3233 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE 3234 #endif 3235 3236 #if defined(STM32F7) || defined(STM32L4) 3237 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET 3238 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET 3239 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE 3240 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE 3241 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE 3242 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE 3243 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED 3244 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED 3245 #define SdioClockSelection Sdmmc1ClockSelection 3246 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 3247 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG 3248 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE 3249 #endif 3250 3251 #if defined(STM32F7) 3252 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 3253 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK 3254 #endif 3255 3256 #if defined(STM32H7) 3257 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() 3258 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() 3259 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() 3260 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() 3261 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() 3262 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() 3263 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() 3264 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() 3265 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() 3266 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() 3267 3268 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() 3269 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() 3270 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() 3271 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() 3272 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() 3273 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() 3274 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() 3275 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() 3276 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() 3277 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() 3278 #endif 3279 3280 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG 3281 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG 3282 3283 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE 3284 3285 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE 3286 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE 3287 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK 3288 #define IS_RCC_HCLK_DIV IS_RCC_PCLK 3289 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK 3290 3291 #define RCC_IT_HSI14 RCC_IT_HSI14RDY 3292 3293 #define RCC_IT_CSSLSE RCC_IT_LSECSS 3294 #define RCC_IT_CSSHSE RCC_IT_CSS 3295 3296 #define RCC_PLLMUL_3 RCC_PLL_MUL3 3297 #define RCC_PLLMUL_4 RCC_PLL_MUL4 3298 #define RCC_PLLMUL_6 RCC_PLL_MUL6 3299 #define RCC_PLLMUL_8 RCC_PLL_MUL8 3300 #define RCC_PLLMUL_12 RCC_PLL_MUL12 3301 #define RCC_PLLMUL_16 RCC_PLL_MUL16 3302 #define RCC_PLLMUL_24 RCC_PLL_MUL24 3303 #define RCC_PLLMUL_32 RCC_PLL_MUL32 3304 #define RCC_PLLMUL_48 RCC_PLL_MUL48 3305 3306 #define RCC_PLLDIV_2 RCC_PLL_DIV2 3307 #define RCC_PLLDIV_3 RCC_PLL_DIV3 3308 #define RCC_PLLDIV_4 RCC_PLL_DIV4 3309 3310 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE 3311 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG 3312 #define RCC_MCO_NODIV RCC_MCODIV_1 3313 #define RCC_MCO_DIV1 RCC_MCODIV_1 3314 #define RCC_MCO_DIV2 RCC_MCODIV_2 3315 #define RCC_MCO_DIV4 RCC_MCODIV_4 3316 #define RCC_MCO_DIV8 RCC_MCODIV_8 3317 #define RCC_MCO_DIV16 RCC_MCODIV_16 3318 #define RCC_MCO_DIV32 RCC_MCODIV_32 3319 #define RCC_MCO_DIV64 RCC_MCODIV_64 3320 #define RCC_MCO_DIV128 RCC_MCODIV_128 3321 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK 3322 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI 3323 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE 3324 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK 3325 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI 3326 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 3327 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 3328 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE 3329 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK 3330 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK 3331 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 3332 3333 #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) 3334 #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE 3335 #else 3336 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK 3337 #endif 3338 3339 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 3340 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL 3341 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI 3342 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL 3343 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL 3344 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 3345 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 3346 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 3347 3348 #define HSION_BitNumber RCC_HSION_BIT_NUMBER 3349 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER 3350 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER 3351 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER 3352 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER 3353 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER 3354 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER 3355 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER 3356 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER 3357 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER 3358 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER 3359 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER 3360 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER 3361 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER 3362 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER 3363 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER 3364 #define LSION_BitNumber RCC_LSION_BIT_NUMBER 3365 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER 3366 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER 3367 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER 3368 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER 3369 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER 3370 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER 3371 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER 3372 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER 3373 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER 3374 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS 3375 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS 3376 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS 3377 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS 3378 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE 3379 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE 3380 3381 #define CR_HSION_BB RCC_CR_HSION_BB 3382 #define CR_CSSON_BB RCC_CR_CSSON_BB 3383 #define CR_PLLON_BB RCC_CR_PLLON_BB 3384 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB 3385 #define CR_MSION_BB RCC_CR_MSION_BB 3386 #define CSR_LSION_BB RCC_CSR_LSION_BB 3387 #define CSR_LSEON_BB RCC_CSR_LSEON_BB 3388 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB 3389 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB 3390 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB 3391 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB 3392 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB 3393 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB 3394 #define CR_HSEON_BB RCC_CR_HSEON_BB 3395 #define CSR_RMVF_BB RCC_CSR_RMVF_BB 3396 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB 3397 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB 3398 3399 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE 3400 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE 3401 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE 3402 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE 3403 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE 3404 3405 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT 3406 3407 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN 3408 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF 3409 3410 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 3411 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ 3412 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP 3413 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ 3414 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE 3415 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 3416 3417 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE 3418 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE 3419 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED 3420 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED 3421 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET 3422 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET 3423 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE 3424 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE 3425 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED 3426 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED 3427 #define DfsdmClockSelection Dfsdm1ClockSelection 3428 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 3429 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3430 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK 3431 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG 3432 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE 3433 #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3434 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 3435 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 3436 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 3437 3438 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 3439 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 3440 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 3441 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 3442 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 3443 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 3444 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 3445 #if defined(STM32U5) 3446 #define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL 3447 #define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL 3448 #define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE 3449 #define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE 3450 #define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE 3451 #define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE 3452 #define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE 3453 #define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE 3454 #define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE 3455 #define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE 3456 #define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE 3457 #define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT 3458 #define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK 3459 #define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 3460 #define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 3461 #define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 3462 #define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK 3463 #define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 3464 #define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 3465 #define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3466 #define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3467 #define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 3468 #define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 3469 #endif 3470 3471 /** 3472 * @} 3473 */ 3474 3475 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose 3476 * @{ 3477 */ 3478 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) 3479 3480 /** 3481 * @} 3482 */ 3483 3484 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose 3485 * @{ 3486 */ 3487 #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) 3488 #else 3489 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG 3490 #endif 3491 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT 3492 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT 3493 3494 #if defined (STM32F1) 3495 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() 3496 3497 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() 3498 3499 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() 3500 3501 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() 3502 3503 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() 3504 #else 3505 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ 3506 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ 3507 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) 3508 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ 3509 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ 3510 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) 3511 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ 3512 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ 3513 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) 3514 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ 3515 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ 3516 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) 3517 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ 3518 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ 3519 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) 3520 #endif /* STM32F1 */ 3521 3522 #define IS_ALARM IS_RTC_ALARM 3523 #define IS_ALARM_MASK IS_RTC_ALARM_MASK 3524 #define IS_TAMPER IS_RTC_TAMPER 3525 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE 3526 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER 3527 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT 3528 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE 3529 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION 3530 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE 3531 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ 3532 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION 3533 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER 3534 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK 3535 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER 3536 3537 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE 3538 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE 3539 3540 /** 3541 * @} 3542 */ 3543 3544 /** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose 3545 * @{ 3546 */ 3547 3548 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE 3549 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS 3550 3551 #if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1) 3552 #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE 3553 #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE 3554 #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE 3555 3556 #define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV 3557 #define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV 3558 #endif 3559 3560 #if defined(STM32F4) || defined(STM32F2) 3561 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED 3562 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY 3563 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED 3564 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION 3565 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND 3566 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT 3567 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED 3568 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE 3569 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE 3570 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE 3571 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL 3572 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT 3573 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT 3574 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG 3575 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG 3576 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT 3577 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT 3578 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS 3579 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT 3580 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND 3581 /* alias CMSIS */ 3582 #define SDMMC1_IRQn SDIO_IRQn 3583 #define SDMMC1_IRQHandler SDIO_IRQHandler 3584 #endif 3585 3586 #if defined(STM32F7) || defined(STM32L4) 3587 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED 3588 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY 3589 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED 3590 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION 3591 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND 3592 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT 3593 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED 3594 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE 3595 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE 3596 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE 3597 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE 3598 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT 3599 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT 3600 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG 3601 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG 3602 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT 3603 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT 3604 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS 3605 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT 3606 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND 3607 /* alias CMSIS for compatibilities */ 3608 #define SDIO_IRQn SDMMC1_IRQn 3609 #define SDIO_IRQHandler SDMMC1_IRQHandler 3610 #endif 3611 3612 #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) 3613 #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef 3614 #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef 3615 #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef 3616 #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef 3617 #endif 3618 3619 #if defined(STM32H7) || defined(STM32L5) 3620 #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback 3621 #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback 3622 #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback 3623 #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback 3624 #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback 3625 #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback 3626 #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback 3627 #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback 3628 #define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback 3629 #endif 3630 /** 3631 * @} 3632 */ 3633 3634 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose 3635 * @{ 3636 */ 3637 3638 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT 3639 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT 3640 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE 3641 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE 3642 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE 3643 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE 3644 3645 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3646 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3647 3648 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE 3649 3650 /** 3651 * @} 3652 */ 3653 3654 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose 3655 * @{ 3656 */ 3657 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 3658 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 3659 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START 3660 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH 3661 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR 3662 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE 3663 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE 3664 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED 3665 /** 3666 * @} 3667 */ 3668 3669 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose 3670 * @{ 3671 */ 3672 3673 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX 3674 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX 3675 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC 3676 3677 /** 3678 * @} 3679 */ 3680 3681 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose 3682 * @{ 3683 */ 3684 3685 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 3686 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION 3687 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 3688 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION 3689 3690 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD 3691 3692 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE 3693 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE 3694 3695 /** 3696 * @} 3697 */ 3698 3699 3700 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose 3701 * @{ 3702 */ 3703 3704 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT 3705 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT 3706 #define __USART_ENABLE __HAL_USART_ENABLE 3707 #define __USART_DISABLE __HAL_USART_DISABLE 3708 3709 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 3710 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 3711 3712 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) 3713 #define USART_OVERSAMPLING_16 0x00000000U 3714 #define USART_OVERSAMPLING_8 USART_CR1_OVER8 3715 3716 #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ 3717 ((__SAMPLING__) == USART_OVERSAMPLING_8)) 3718 #endif /* STM32F0 || STM32F3 || STM32F7 */ 3719 /** 3720 * @} 3721 */ 3722 3723 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose 3724 * @{ 3725 */ 3726 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE 3727 3728 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 3729 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 3730 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 3731 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE 3732 3733 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 3734 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 3735 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 3736 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE 3737 3738 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT 3739 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT 3740 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG 3741 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG 3742 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE 3743 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3744 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3745 3746 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT 3747 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT 3748 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG 3749 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG 3750 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE 3751 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3752 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3753 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT 3754 3755 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT 3756 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT 3757 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG 3758 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG 3759 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE 3760 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3761 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3762 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT 3763 3764 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup 3765 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup 3766 3767 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo 3768 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo 3769 /** 3770 * @} 3771 */ 3772 3773 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose 3774 * @{ 3775 */ 3776 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE 3777 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE 3778 3779 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 3780 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT 3781 3782 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 3783 3784 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN 3785 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER 3786 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER 3787 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER 3788 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD 3789 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD 3790 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION 3791 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION 3792 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER 3793 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER 3794 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE 3795 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE 3796 3797 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 3798 /** 3799 * @} 3800 */ 3801 3802 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose 3803 * @{ 3804 */ 3805 3806 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT 3807 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT 3808 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG 3809 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG 3810 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER 3811 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER 3812 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER 3813 3814 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE 3815 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE 3816 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE 3817 /** 3818 * @} 3819 */ 3820 3821 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose 3822 * @{ 3823 */ 3824 #define __HAL_LTDC_LAYER LTDC_LAYER 3825 #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG 3826 /** 3827 * @} 3828 */ 3829 3830 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose 3831 * @{ 3832 */ 3833 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE 3834 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE 3835 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE 3836 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE 3837 #define SAI_STREOMODE SAI_STEREOMODE 3838 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY 3839 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL 3840 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL 3841 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL 3842 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL 3843 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL 3844 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE 3845 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 3846 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE 3847 /** 3848 * @} 3849 */ 3850 3851 /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose 3852 * @{ 3853 */ 3854 #if defined(STM32H7) 3855 #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow 3856 #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT 3857 #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA 3858 #endif 3859 /** 3860 * @} 3861 */ 3862 3863 /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose 3864 * @{ 3865 */ 3866 #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) 3867 #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT 3868 #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA 3869 #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart 3870 #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT 3871 #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA 3872 #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop 3873 #endif 3874 /** 3875 * @} 3876 */ 3877 3878 /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose 3879 * @{ 3880 */ 3881 #if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) 3882 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE 3883 #endif /* STM32L4 || STM32F4 || STM32F7 */ 3884 /** 3885 * @} 3886 */ 3887 3888 /** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 3889 * @{ 3890 */ 3891 #if defined (STM32F7) 3892 #define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE 3893 #endif /* STM32F7 */ 3894 /** 3895 * @} 3896 */ 3897 3898 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose 3899 * @{ 3900 */ 3901 3902 /** 3903 * @} 3904 */ 3905 3906 #ifdef __cplusplus 3907 } 3908 #endif 3909 3910 #endif /* STM32_HAL_LEGACY */ 3911 3912 3913
