1 /**
2 ******************************************************************************
3 * @file stm32g0xx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32g0xx_ll_dma.h"
22 #include "stm32g0xx_ll_bus.h"
23 #ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25 #else
26 #define assert_param(expr) ((void)0U)
27 #endif /* USE_FULL_ASSERT */
28
29 /** @addtogroup STM32G0xx_LL_Driver
30 * @{
31 */
32
33 #if defined (DMA1) || defined (DMA2)
34
35 /** @defgroup DMA_LL DMA
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43 /** @addtogroup DMA_LL_Private_Macros
44 * @{
45 */
46 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
47 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
48 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
49
50 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
51 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
52
53 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
54 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
55
56 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
57 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
58
59 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
60 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
61 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
62
63 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
64 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
65 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
66
67 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
68
69 #define IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX_MAX_REQ)
70
71 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
72 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
73 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
74 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
75
76 #if defined(DMA2)
77 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
78 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
79 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
80 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
81 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
82 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
83 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
84 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
85 (((INSTANCE) == DMA2) && \
86 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
87 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
88 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
89 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
90 ((CHANNEL) == LL_DMA_CHANNEL_5))))
91 #else /* DMA1 */
92 #if defined(DMA1_Channel7)
93 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
94 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
95 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
96 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
97 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
98 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
99 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
100 ((CHANNEL) == LL_DMA_CHANNEL_7))))
101 #else
102 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
103 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
104 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
105 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
106 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
107 ((CHANNEL) == LL_DMA_CHANNEL_5))))
108 #endif /* DMA1_Channel8 */
109 #endif /* DMA2 */
110 /**
111 * @}
112 */
113
114 /* Private function prototypes -----------------------------------------------*/
115
116 /* Exported functions --------------------------------------------------------*/
117 /** @addtogroup DMA_LL_Exported_Functions
118 * @{
119 */
120
121 /** @addtogroup DMA_LL_EF_Init
122 * @{
123 */
124
125 /**
126 * @brief De-initialize the DMA registers to their default reset values.
127 * @param DMAx DMAx Instance
128 * @param Channel This parameter can be one of the following values:
129 * @arg @ref LL_DMA_CHANNEL_1
130 * @arg @ref LL_DMA_CHANNEL_2
131 * @arg @ref LL_DMA_CHANNEL_3
132 * @arg @ref LL_DMA_CHANNEL_4
133 * @arg @ref LL_DMA_CHANNEL_5
134 * @arg @ref LL_DMA_CHANNEL_6
135 * @arg @ref LL_DMA_CHANNEL_7
136 * @arg @ref LL_DMA_CHANNEL_ALL
137 * @retval An ErrorStatus enumeration value:
138 * - SUCCESS: DMA registers are de-initialized
139 * - ERROR: DMA registers are not de-initialized
140 */
LL_DMA_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)141 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
142 {
143 ErrorStatus status = SUCCESS;
144
145 /* Check the DMA Instance DMAx and Channel parameters*/
146 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
147
148 if (Channel == LL_DMA_CHANNEL_ALL)
149 {
150 if (DMAx == DMA1)
151 {
152 /* Force reset of DMA clock */
153 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
154
155 /* Release reset of DMA clock */
156 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
157 }
158 #if defined(DMA2)
159 else if (DMAx == DMA2)
160 {
161 /* Force reset of DMA clock */
162 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
163
164 /* Release reset of DMA clock */
165 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
166 }
167 #endif /* DMA2 */
168 else
169 {
170 status = ERROR;
171 }
172 }
173 else
174 {
175 DMA_Channel_TypeDef *tmp;
176
177 tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
178
179 /* Disable the selected DMAx_Channely */
180 CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
181
182 /* Reset DMAx_Channely control register */
183 WRITE_REG(tmp->CCR, 0U);
184
185 /* Reset DMAx_Channely remaining bytes register */
186 WRITE_REG(tmp->CNDTR, 0U);
187
188 /* Reset DMAx_Channely peripheral address register */
189 WRITE_REG(tmp->CPAR, 0U);
190
191 /* Reset DMAx_Channely memory address register */
192 WRITE_REG(tmp->CMAR, 0U);
193
194 /* Reset Request register field for DMAx Channel */
195 LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQ_MEM2MEM);
196
197 if (Channel == LL_DMA_CHANNEL_1)
198 {
199 /* Reset interrupt pending bits for DMAx Channel1 */
200 LL_DMA_ClearFlag_GI1(DMAx);
201 }
202 else if (Channel == LL_DMA_CHANNEL_2)
203 {
204 /* Reset interrupt pending bits for DMAx Channel2 */
205 LL_DMA_ClearFlag_GI2(DMAx);
206 }
207 else if (Channel == LL_DMA_CHANNEL_3)
208 {
209 /* Reset interrupt pending bits for DMAx Channel3 */
210 LL_DMA_ClearFlag_GI3(DMAx);
211 }
212 else if (Channel == LL_DMA_CHANNEL_4)
213 {
214 /* Reset interrupt pending bits for DMAx Channel4 */
215 LL_DMA_ClearFlag_GI4(DMAx);
216 }
217 else if (Channel == LL_DMA_CHANNEL_5)
218 {
219 /* Reset interrupt pending bits for DMAx Channel5 */
220 LL_DMA_ClearFlag_GI5(DMAx);
221 }
222 #if defined(DMA1_Channel6)
223 else if (Channel == LL_DMA_CHANNEL_6)
224 {
225 /* Reset interrupt pending bits for DMAx Channel6 */
226 LL_DMA_ClearFlag_GI6(DMAx);
227 }
228 #endif /* DMA1_Channel6 */
229 #if defined(DMA1_Channel7)
230 else if (Channel == LL_DMA_CHANNEL_7)
231 {
232 /* Reset interrupt pending bits for DMAx Channel7 */
233 LL_DMA_ClearFlag_GI7(DMAx);
234 }
235 #endif /* DMA1_Channel7 */
236 else
237 {
238 status = ERROR;
239 }
240 }
241
242 return status;
243 }
244
245 /**
246 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
247 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
248 * @arg @ref __LL_DMA_GET_INSTANCE
249 * @arg @ref __LL_DMA_GET_CHANNEL
250 * @param DMAx DMAx Instance
251 * @param Channel This parameter can be one of the following values:
252 * @arg @ref LL_DMA_CHANNEL_1
253 * @arg @ref LL_DMA_CHANNEL_2
254 * @arg @ref LL_DMA_CHANNEL_3
255 * @arg @ref LL_DMA_CHANNEL_4
256 * @arg @ref LL_DMA_CHANNEL_5
257 * @arg @ref LL_DMA_CHANNEL_6
258 * @arg @ref LL_DMA_CHANNEL_7
259 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
260 * @retval An ErrorStatus enumeration value:
261 * - SUCCESS: DMA registers are initialized
262 * - ERROR: Not applicable
263 */
LL_DMA_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitTypeDef * DMA_InitStruct)264 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
265 {
266 /* Check the DMA Instance DMAx and Channel parameters*/
267 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
268
269 /* Check the DMA parameters from DMA_InitStruct */
270 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
271 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
272 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
273 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
274 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
275 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
276 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
277 assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
278 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
279
280 /*---------------------------- DMAx CCR Configuration ------------------------
281 * Configure DMAx_Channely: data transfer direction, data transfer mode,
282 * peripheral and memory increment mode,
283 * data size alignment and priority level with parameters :
284 * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
285 * - Mode: DMA_CCR_CIRC bit
286 * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
287 * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
288 * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
289 * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
290 * - Priority: DMA_CCR_PL[1:0] bits
291 */
292 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
293 DMA_InitStruct->Mode | \
294 DMA_InitStruct->PeriphOrM2MSrcIncMode | \
295 DMA_InitStruct->MemoryOrM2MDstIncMode | \
296 DMA_InitStruct->PeriphOrM2MSrcDataSize | \
297 DMA_InitStruct->MemoryOrM2MDstDataSize | \
298 DMA_InitStruct->Priority);
299
300 /*-------------------------- DMAx CMAR Configuration -------------------------
301 * Configure the memory or destination base address with parameter :
302 * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
303 */
304 LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
305
306 /*-------------------------- DMAx CPAR Configuration -------------------------
307 * Configure the peripheral or source base address with parameter :
308 * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
309 */
310 LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
311
312 /*--------------------------- DMAx CNDTR Configuration -----------------------
313 * Configure the peripheral base address with parameter :
314 * - NbData: DMA_CNDTR_NDT[15:0] bits
315 */
316 LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
317
318 /*--------------------------- DMAMUXx CCR Configuration ----------------------
319 * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter :
320 * - PeriphRequest: DMA_CxCR[7:0] bits
321 */
322 LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
323
324 return SUCCESS;
325 }
326
327 /**
328 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
329 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
330 * @retval None
331 */
LL_DMA_StructInit(LL_DMA_InitTypeDef * DMA_InitStruct)332 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
333 {
334 /* Set DMA_InitStruct fields to default values */
335 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
336 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
337 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
338 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
339 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
340 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
341 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
342 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
343 DMA_InitStruct->NbData = 0x00000000U;
344 DMA_InitStruct->PeriphRequest = LL_DMAMUX_REQ_MEM2MEM;
345 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
346 }
347
348 /**
349 * @}
350 */
351
352 /**
353 * @}
354 */
355
356 /**
357 * @}
358 */
359
360 #endif /* DMA1 || DMA2 */
361
362 /**
363 * @}
364 */
365
366 #endif /* USE_FULL_LL_DRIVER */
367
368
